Re: [PATCH v9 06/11] arm64: dts: renesas: add support for solidrun rzg2lc som and hb-iiot evb

[Josua Mayer <josua@solid-run.com>]

Am 28.09.26 um 16:56 schrieb sashiko-bot@kernel.org:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [High] dts: missing output-enable property for ET0_TXC pin
> --
>
> commit f7d1836ef2ca9d47ba42e92fcf7b8155deac999a
> Author: Josua Mayer <josua@solid-run.com>
>
> arm64: dts: renesas: add support for solidrun rzg2lc som and hb-iiot evb
>
> Adds device tree support for the SolidRun RZ/G2LC SoM on the HummingBoard
> IIoT carrier board. The SoM features Ethernet, eMMC, DDR, and WiFi/BT,
> while the carrier provides additional I/O like USB, RS232/RS485, and DSI.
> Descriptions for eMMC, microSD, and RS485 are shared with the G2L variant.
>
> [1] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-g2lc-som/
> [2] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hummingboard-rz-series-sbcs/hummingboard-rz-g2l-iot-sbc/
>
>> diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi
>> new file mode 100644
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi
> [ ... ]
>
>> +&pinctrl {
>> +	eth0_pins: eth0 {
>> +		pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
>> +			 <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
>> +			 <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
>> +			 <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
> [Severity: High]
> Does this configuration omit the output-enable property needed to drive the
> Ethernet MAC-to-PHY TX clock?
>
> The eth0_pins node lumps all Ethernet pins into a single pinmux without
> declaring output-enable. When the pinctrl driver processes this, it leaves
> the PIN_CFG_OEN bit disabled, meaning the PHY will not receive a transmit
> clock and Ethernet transmission could fail.
>
> Would it be better to isolate ET0_TXC into a subnode with output-enable
> declared to ensure the clock is driven out by the SoC?
>
>> +			 <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
>> +			 <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
> [ ... ]
>
This is a false positive in that it is uncommon to set output-enable on
RZ/G2 platforms, it is a default at boot-time.

LLM pattern-matching was likely fed from patch 2 in this series,
which adds output-disable and input-disable to allowed properties|
for the pincontroller.