* [PATCH 13/16] arm: dts: rename mt7623-evb.dts to arch/arm/boot/dts/mt7623n-rfb.dtsi
From: John Crispin @ 2017-01-23 11:29 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Andreas Färber, John Crispin
In-Reply-To: <1485170975-51813-1-git-send-email-john-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
There are 2 versions of the SoC. MT7623N is almost identical to MT7623A
but has some additional multimedia features. The reference boards are
available as NAND or MMC and might have a different ethernet setup. In
order to reduce the duplication of devicetree code we add an intermediate
dtsi file for these reference boards. Additionally MTK/WCN pointed out,
that the EVB is yet another board and the board in question is infact the
RFB. Take this into account while renaming the files.
Signed-off-by: John Crispin <john-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
---
Documentation/devicetree/bindings/arm/mediatek.txt | 4 +--
arch/arm/boot/dts/Makefile | 2 +-
arch/arm/boot/dts/mt7623-evb.dts | 33 --------------------
arch/arm/boot/dts/mt7623n-rfb-nand.dts | 21 +++++++++++++
arch/arm/boot/dts/mt7623n-rfb.dtsi | 29 +++++++++++++++++
5 files changed, 53 insertions(+), 36 deletions(-)
delete mode 100644 arch/arm/boot/dts/mt7623-evb.dts
create mode 100644 arch/arm/boot/dts/mt7623n-rfb-nand.dts
create mode 100644 arch/arm/boot/dts/mt7623n-rfb.dtsi
diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt
index c860b24..71149cb 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -38,9 +38,9 @@ Supported boards:
- Evaluation board for MT6795(Helio X10):
Required root node properties:
- compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
-- Evaluation board for MT7623:
+- Reference board for MT7623N with NAND:
Required root node properties:
- - compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
+ - compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
- MTK mt8127 tablet moose EVB:
Required root node properties:
- compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index cccdbcb..9735c2c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -976,7 +976,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt6580-evbp1.dtb \
mt6589-aquaris5.dtb \
mt6592-evb.dtb \
- mt7623-evb.dtb \
+ mt7623n-rfb-nand.dtb \
mt8127-moose.dtb \
mt8135-evbp1.dtb
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
diff --git a/arch/arm/boot/dts/mt7623-evb.dts b/arch/arm/boot/dts/mt7623-evb.dts
deleted file mode 100644
index 58ed038..0000000
--- a/arch/arm/boot/dts/mt7623-evb.dts
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (c) 2016 MediaTek Inc.
- * Author: John Crispin <blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/dts-v1/;
-#include "mt7623-mt6323.dtsi"
-
-/ {
- model = "MediaTek MT7623 evaluation board";
- compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
-
- chosen {
- stdout-path = &uart2;
- };
-
- memory {
- reg = <0 0x80000000 0 0x40000000>;
- };
-};
-
-&uart2 {
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/mt7623n-rfb-nand.dts b/arch/arm/boot/dts/mt7623n-rfb-nand.dts
new file mode 100644
index 0000000..436d51c
--- /dev/null
+++ b/arch/arm/boot/dts/mt7623n-rfb-nand.dts
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ * Author: John Crispin <blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "mt7623n-rfb.dtsi"
+
+/ {
+ model = "MediaTek MT7623N NAND reference board";
+ compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
+};
diff --git a/arch/arm/boot/dts/mt7623n-rfb.dtsi b/arch/arm/boot/dts/mt7623n-rfb.dtsi
new file mode 100644
index 0000000..d46390e
--- /dev/null
+++ b/arch/arm/boot/dts/mt7623n-rfb.dtsi
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ * Author: John Crispin <blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "mt7623-mt6323.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ memory {
+ reg = <0 0x80000000 0 0x40000000>;
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
--
1.7.10.4
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* [PATCH 14/16] arm: dts: cleanup the mt7623n rfb uart nodes
From: John Crispin @ 2017-01-23 11:29 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Andreas Färber, John Crispin
In-Reply-To: <1485170975-51813-1-git-send-email-john-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
This patch does a cleanup of the uart nodes in the dts file of the RFB. It
adds aliases, enables 2 more uarts and explicitly sets the uart mode of the
console.
Signed-off-by: John Crispin <john-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
---
arch/arm/boot/dts/mt7623n-rfb.dtsi | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/mt7623n-rfb.dtsi b/arch/arm/boot/dts/mt7623n-rfb.dtsi
index d46390e..df9e564 100644
--- a/arch/arm/boot/dts/mt7623n-rfb.dtsi
+++ b/arch/arm/boot/dts/mt7623n-rfb.dtsi
@@ -16,12 +16,26 @@
/ {
chosen {
- stdout-path = &uart2;
+ stdout-path = "serial2:115200n8";
};
memory {
reg = <0 0x80000000 0 0x40000000>;
};
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
};
&uart2 {
--
1.7.10.4
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* [PATCH 15/16] arm: dts: enable the usb device on the mt7623n rfb
From: John Crispin @ 2017-01-23 11:29 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Andreas Färber, John Crispin
In-Reply-To: <1485170975-51813-1-git-send-email-john-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
All versions of the mt7623n RFB have an USB port so enable the device.
There is a gpio that gets used to power up the port supply. Add support
for this gpio using the fixed-regulator driver.
Signed-off-by: John Crispin <john-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
---
arch/arm/boot/dts/mt7623.dtsi | 1 +
arch/arm/boot/dts/mt7623n-rfb.dtsi | 18 ++++++++++++++++++
2 files changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index b256ff51..388ba7f 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -15,6 +15,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt2701-clk.h>
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
#include <dt-bindings/power/mt2701-power.h>
diff --git a/arch/arm/boot/dts/mt7623n-rfb.dtsi b/arch/arm/boot/dts/mt7623n-rfb.dtsi
index df9e564..777334a 100644
--- a/arch/arm/boot/dts/mt7623n-rfb.dtsi
+++ b/arch/arm/boot/dts/mt7623n-rfb.dtsi
@@ -28,6 +28,15 @@
serial1 = &uart1;
serial2 = &uart2;
};
+
+ usb_p1_vbus: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pio 135 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
};
&uart0 {
@@ -41,3 +50,12 @@
&uart2 {
status = "okay";
};
+
+&usb1 {
+ vbus-supply = <&usb_p1_vbus>;
+ status = "okay";
+};
+
+&u3phy1 {
+ status = "okay";
+};
--
1.7.10.4
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* [PATCH 16/16] arm: dts: enable the nand device on the mt7623n nand rfb
From: John Crispin @ 2017-01-23 11:29 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Andreas Färber, John Crispin
In-Reply-To: <1485170975-51813-1-git-send-email-john-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
Enable the nand device and setup pinmux on the mt7632m rfb with nand
support.
Signed-off-by: John Crispin <john-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
---
arch/arm/boot/dts/mt7623n-rfb-nand.dts | 88 ++++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/arch/arm/boot/dts/mt7623n-rfb-nand.dts b/arch/arm/boot/dts/mt7623n-rfb-nand.dts
index 436d51c..9356095 100644
--- a/arch/arm/boot/dts/mt7623n-rfb-nand.dts
+++ b/arch/arm/boot/dts/mt7623n-rfb-nand.dts
@@ -19,3 +19,91 @@
model = "MediaTek MT7623N NAND reference board";
compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
};
+
+&pio {
+ nand_pins_default: nanddefault {
+ pins_dat {
+ pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,
+ <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,
+ <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
+ <MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>,
+ <MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>,
+ <MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>,
+ <MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>,
+ <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>,
+ <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>;
+ input-enable;
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-up;
+ };
+
+ pins_we {
+ pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins_ale {
+ pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+ };
+};
+
+&nandc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_pins_default>;
+ nand@0 {
+ reg = <0>;
+ spare_per_sector = <64>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <12>;
+ nand-ecc-step-size = <1024>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "preloader";
+ reg = <0x0 0x40000>;
+ };
+
+ partition@40000 {
+ label = "uboot";
+ reg = <0x40000 0x80000>;
+ };
+
+ partition@C0000 {
+ label = "uboot-env";
+ reg = <0xC0000 0x40000>;
+ };
+
+ partition@140000 {
+ label = "bootimg";
+ reg = <0x140000 0x2000000>;
+ };
+
+ partition@2140000 {
+ label = "recovery";
+ reg = <0x2140000 0x2000000>;
+ };
+
+ partition@4140000 {
+ label = "rootfs";
+ reg = <0x4140000 0x1000000>;
+ };
+
+ partition@5140000 {
+ label = "usrdata";
+ reg = <0x5140000 0x1000000>;
+ };
+ };
+ };
+};
+
+&bch {
+ status = "okay";
+};
--
1.7.10.4
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^ permalink raw reply related
* Re: [PATCH 00/16] arm: dts: extend mt7623 support
From: John Crispin @ 2017-01-23 11:32 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Andreas Färber
In-Reply-To: <1485170975-51813-1-git-send-email-john-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
On 23/01/2017 12:29, John Crispin wrote:
> This series extends the dts files used for booting mt7623 base boards.
> Since support for mt7623 was added around v4.6, many new drivers have
> been accepted upstream. The contained patches add several of these to
> the devicetree.
>
> Additionally the series does a bit of refactoring. MTK/WCN pointed out
> that the evaluation board is infact a reference design and asked the the
> evb files be renamed to rfb.
>
> As with all of the current ARM bases MTK silicon, these boards also have
> a PMIC. Instead of adding the nodes to all of the dts files, we add an
> intermediate dtsi file that contains the required nodes. This allows us
> to reduce the size of the top most dts files.
>
> The RFB comes in various versions and asiarf has even done a crowdfunder
> to sell them. We should try to reduce the duplication. This series adds
> a common dtsi file for these boards. This results in the topmost dts files
> only needing to specify the compatible string, MTD nodes and ethernet setup.
>
Hi,
i have a 2nd series in the making which makes the following things work,
just in case anyone else is also working on this, let me know so that we
don't duplicate any of the work.
* pcie
* cpufreq
* mt7623a RFB
* ethernet
* spi-nor
* PWM
John
> John Crispin (16):
> arm: dts: add clock controller device nodes
> arm: dts: add subsystem clock controller device nodes
> arm: dts: add power domain controller device node
> arm: dts: add clock-frequency to the a7 timer node to mt7623.dtsi
> arm: dts: add pinctrl nodes to the mt7623 dtsi file
> arm: dts: add pmic nodes to the mt7623 dtsi file
> arm: dts: add i2c nodes to the mt7623.dtsi file
> arm: dts: add spi nodes to the mt7623.dtsi file
> arm: dts: add nand nodes to the mt7623.dtsi file
> arm: dts: add mmc nodes to the mt7623.dtsi file
> arm: dts: add usb nodes to the mt7623.dtsi file
> arm: dts: add mt7623-mt6323.dtsi file
> arm: dts: rename mt7623-evb.dts to arch/arm/boot/dts/mt7623n-rfb.dtsi
> arm: dts: cleanup the mt7623n rfb uart nodes
> arm: dts: enable the usb device on the mt7623n rfb
> arm: dts: enable the nand device on the mt7623n nand rfb
>
> Documentation/devicetree/bindings/arm/mediatek.txt | 4 +-
> arch/arm/boot/dts/Makefile | 2 +-
> arch/arm/boot/dts/mt7623-evb.dts | 33 ---
> arch/arm/boot/dts/mt7623-mt6323.dtsi | 273 ++++++++++++++++++
> arch/arm/boot/dts/mt7623.dtsi | 297 +++++++++++++++++++-
> arch/arm/boot/dts/mt7623n-rfb-nand.dts | 109 +++++++
> arch/arm/boot/dts/mt7623n-rfb.dtsi | 61 ++++
> 7 files changed, 730 insertions(+), 49 deletions(-)
> delete mode 100644 arch/arm/boot/dts/mt7623-evb.dts
> create mode 100644 arch/arm/boot/dts/mt7623-mt6323.dtsi
> create mode 100644 arch/arm/boot/dts/mt7623n-rfb-nand.dts
> create mode 100644 arch/arm/boot/dts/mt7623n-rfb.dtsi
>
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* Re: [PATCH 2/4] sdio: mediatek: Support sdio feature
From: Wei-Ning Huang @ 2017-01-23 11:34 UTC (permalink / raw)
To: Yong Mao
Cc: Ulf Hansson, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon, Matthias Brugger, YH Huang, Mathias Nyman,
Chunfeng Yun, Eddie Huang, Philipp Zabel, Chaotian Jing,
Nicolas Boichat, Douglas Anderson, Geert Uytterhoeven, devicetree,
linux-arm-kernel, LKML, linux-mmc, linux-mediatek
In-Reply-To: <CABicQ-W103YX8OR+20Kjjg1yKFzw1Bu1aZuQNAsd3DSVVHcxJQ@mail.gmail.com>
On Mon, Jan 23, 2017 at 7:24 PM, Wei-Ning Huang <wnhuang@google.com> wrote:
> On Tue, Nov 8, 2016 at 2:08 PM, Yong Mao <yong.mao@mediatek.com> wrote:
>> From: yong mao <yong.mao@mediatek.com>
>>
>> 1. Add irqlock to protect accessing the shared register
>> 2. Modify the implementation of msdc_card_busy due to SDIO
>> 3. Implement enable_sdio_irq
>> 4. Add msdc_recheck_sdio_irq mechanism to make sure all
>> interrupts can be processed immediately
>>
>> Signed-off-by: Yong Mao <yong.mao@mediatek.com>
>> Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
>> ---
>> drivers/mmc/host/mtk-sd.c | 167 ++++++++++++++++++++++++++++++++++-----------
>> 1 file changed, 129 insertions(+), 38 deletions(-)
>>
>> diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
>> index b29683b..37edf30 100644
>> --- a/drivers/mmc/host/mtk-sd.c
>> +++ b/drivers/mmc/host/mtk-sd.c
>> @@ -117,6 +117,7 @@
>> #define MSDC_PS_CDSTS (0x1 << 1) /* R */
>> #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
>> #define MSDC_PS_DAT (0xff << 16) /* R */
>> +#define MSDC_PS_DATA1 (0x1 << 17) /* R */
>> #define MSDC_PS_CMD (0x1 << 24) /* R */
>> #define MSDC_PS_WP (0x1 << 31) /* R */
>>
>> @@ -304,6 +305,7 @@ struct msdc_host {
>> int cmd_rsp;
>>
>> spinlock_t lock;
>> + spinlock_t irqlock; /* sdio irq lock */
>> struct mmc_request *mrq;
>> struct mmc_command *cmd;
>> struct mmc_data *data;
>> @@ -322,12 +324,14 @@ struct msdc_host {
>> struct pinctrl_state *pins_uhs;
>> struct delayed_work req_timeout;
>> int irq; /* host interrupt */
>> + bool irq_thread_alive;
>>
>> struct clk *src_clk; /* msdc source clock */
>> struct clk *h_clk; /* msdc h_clk */
>> u32 mclk; /* mmc subsystem clock frequency */
>> u32 src_clk_freq; /* source clock frequency */
>> u32 sclk; /* SD/MS bus clock frequency */
>> + bool clock_on;
>> unsigned char timing;
>> bool vqmmc_enabled;
>> u32 hs400_ds_delay;
>> @@ -387,6 +391,7 @@ static void msdc_reset_hw(struct msdc_host *host)
>>
>> static void msdc_cmd_next(struct msdc_host *host,
>> struct mmc_request *mrq, struct mmc_command *cmd);
>> +static void msdc_recheck_sdio_irq(struct msdc_host *host);
>>
>> static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
>> MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
>> @@ -513,6 +518,7 @@ static void msdc_gate_clock(struct msdc_host *host)
>> {
>> clk_disable_unprepare(host->src_clk);
>> clk_disable_unprepare(host->h_clk);
>> + host->clock_on = false;
>> }
>>
>> static void msdc_ungate_clock(struct msdc_host *host)
>> @@ -521,6 +527,7 @@ static void msdc_ungate_clock(struct msdc_host *host)
>> clk_prepare_enable(host->src_clk);
>> while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
>> cpu_relax();
>> + host->clock_on = true;
>> }
>>
>> static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
>> @@ -529,6 +536,7 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
>> u32 flags;
>> u32 div;
>> u32 sclk;
>> + unsigned long irq_flags;
>>
>> if (!hz) {
>> dev_dbg(host->dev, "set mclk to 0\n");
>> @@ -537,8 +545,11 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
>> return;
>> }
>>
>> + spin_lock_irqsave(&host->irqlock, irq_flags);
>> flags = readl(host->base + MSDC_INTEN);
>> sdr_clr_bits(host->base + MSDC_INTEN, flags);
>> + spin_unlock_irqrestore(&host->irqlock, irq_flags);
>> +
>> sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
>> if (timing == MMC_TIMING_UHS_DDR50 ||
>> timing == MMC_TIMING_MMC_DDR52 ||
>> @@ -588,7 +599,10 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
>> host->timing = timing;
>> /* need because clk changed. */
>> msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
>> +
>> + spin_lock_irqsave(&host->irqlock, irq_flags);
>> sdr_set_bits(host->base + MSDC_INTEN, flags);
>> + spin_unlock_irqrestore(&host->irqlock, irq_flags);
>>
>> /*
>> * mmc_select_hs400() will drop to 50Mhz and High speed mode,
>> @@ -690,6 +704,7 @@ static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
>> static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq,
>> struct mmc_command *cmd, struct mmc_data *data)
>> {
>> + unsigned long flags;
>> bool read;
>>
>> WARN_ON(host->data);
>> @@ -698,8 +713,12 @@ static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq,
>>
>> mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
>> msdc_dma_setup(host, &host->dma, data);
>> +
>> + spin_lock_irqsave(&host->irqlock, flags);
>> sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
>> sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
>> + spin_unlock_irqrestore(&host->irqlock, flags);
>> +
>> dev_dbg(host->dev, "DMA start\n");
>> dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
>> __func__, cmd->opcode, data->blocks, read);
>> @@ -756,6 +775,7 @@ static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
>> if (mrq->data)
>> msdc_unprepare_data(host, mrq);
>> mmc_request_done(host->mmc, mrq);
>> + msdc_recheck_sdio_irq(host);
>> }
>>
>> /* returns true if command is fully handled; returns false otherwise */
>> @@ -779,15 +799,17 @@ static bool msdc_cmd_done(struct msdc_host *host, int events,
>> | MSDC_INT_CMDTMO)))
>> return done;
>>
>> - spin_lock_irqsave(&host->lock, flags);
>> done = !host->cmd;
>> + spin_lock_irqsave(&host->lock, flags);
>> host->cmd = NULL;
>> spin_unlock_irqrestore(&host->lock, flags);
>>
>> if (done)
>> return true;
>>
>> + spin_lock_irqsave(&host->irqlock, flags);
>> sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
>> + spin_unlock_irqrestore(&host->irqlock, flags);
>>
>> if (cmd->flags & MMC_RSP_PRESENT) {
>> if (cmd->flags & MMC_RSP_136) {
>> @@ -902,6 +924,7 @@ static inline bool msdc_cmd_is_ready(struct msdc_host *host,
>> static void msdc_start_command(struct msdc_host *host,
>> struct mmc_request *mrq, struct mmc_command *cmd)
>> {
>> + unsigned long flags;
>> u32 rawcmd;
>>
>> WARN_ON(host->cmd);
>> @@ -920,7 +943,10 @@ static void msdc_start_command(struct msdc_host *host,
>> rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
>> mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
>>
>> + spin_lock_irqsave(&host->irqlock, flags);
>> sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
>> + spin_unlock_irqrestore(&host->irqlock, flags);
>> +
>> writel(cmd->arg, host->base + SDC_ARG);
>> writel(rawcmd, host->base + SDC_CMD);
>> }
>> @@ -1013,8 +1039,8 @@ static bool msdc_data_xfer_done(struct msdc_host *host, u32 events,
>> | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
>> | MSDC_INT_DMA_PROTECT);
>>
>> - spin_lock_irqsave(&host->lock, flags);
>> done = !host->data;
>> + spin_lock_irqsave(&host->lock, flags);
>> if (check_data)
>> host->data = NULL;
>> spin_unlock_irqrestore(&host->lock, flags);
>> @@ -1029,7 +1055,11 @@ static bool msdc_data_xfer_done(struct msdc_host *host, u32 events,
>> 1);
>> while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS)
>> cpu_relax();
>> +
>> + spin_lock_irqsave(&host->irqlock, flags);
>> sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
>> + spin_unlock_irqrestore(&host->irqlock, flags);
>> +
>> dev_dbg(host->dev, "DMA stop\n");
>>
>> if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
>> @@ -1134,44 +1164,47 @@ static void msdc_request_timeout(struct work_struct *work)
>>
>> static irqreturn_t msdc_irq(int irq, void *dev_id)
>> {
>> + unsigned long flags;
>> struct msdc_host *host = (struct msdc_host *) dev_id;
>> + struct mmc_request *mrq;
>> + struct mmc_command *cmd;
>> + struct mmc_data *data;
>> + u32 events, event_mask;
>> +
>> + spin_lock_irqsave(&host->irqlock, flags);
>> + events = readl(host->base + MSDC_INT);
>> + event_mask = readl(host->base + MSDC_INTEN);
>> + /* clear interrupts */
>> + writel(events & event_mask, host->base + MSDC_INT);
>> +
>> + mrq = host->mrq;
>> + cmd = host->cmd;
>> + data = host->data;
>> + spin_unlock_irqrestore(&host->irqlock, flags);
>> +
>> + if ((events & event_mask) & MSDC_INT_SDIOIRQ) {
>> + mmc_signal_sdio_irq(host->mmc);
>> + if (!mrq)
>> + return IRQ_HANDLED;
>> + }
>>
>> - while (true) {
>> - unsigned long flags;
>> - struct mmc_request *mrq;
>> - struct mmc_command *cmd;
>> - struct mmc_data *data;
>> - u32 events, event_mask;
>> -
>> - spin_lock_irqsave(&host->lock, flags);
>> - events = readl(host->base + MSDC_INT);
>> - event_mask = readl(host->base + MSDC_INTEN);
>> - /* clear interrupts */
>> - writel(events & event_mask, host->base + MSDC_INT);
>> -
>> - mrq = host->mrq;
>> - cmd = host->cmd;
>> - data = host->data;
>> - spin_unlock_irqrestore(&host->lock, flags);
>> -
>> - if (!(events & event_mask))
>> - break;
>> + if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ)))
>> + return IRQ_HANDLED;
>>
>> - if (!mrq) {
>> - dev_err(host->dev,
>> - "%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
>> - __func__, events, event_mask);
>> - WARN_ON(1);
>> - break;
>> - }
>> + if (!mrq) {
>> + dev_err(host->dev,
>> + "%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
>> + __func__, events, event_mask);
>> + WARN_ON(1);
>> + return IRQ_HANDLED;
>> + }
>>
>> - dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
>> + dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
>>
>> - if (cmd)
>> - msdc_cmd_done(host, events, mrq, cmd);
>> - else if (data)
>> - msdc_data_xfer_done(host, events, mrq, data);
>> - }
>> + if (cmd)
>> + msdc_cmd_done(host, events, mrq, cmd);
>> + else if (data)
>> + msdc_data_xfer_done(host, events, mrq, data);
>>
>> return IRQ_HANDLED;
>> }
>> @@ -1179,6 +1212,7 @@ static irqreturn_t msdc_irq(int irq, void *dev_id)
>> static void msdc_init_hw(struct msdc_host *host)
>> {
>> u32 val;
>> + unsigned long flags;
>>
>> /* Configure to MMC/SD mode, clock free running */
>> sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
>> @@ -1190,9 +1224,11 @@ static void msdc_init_hw(struct msdc_host *host)
>> sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
>>
>> /* Disable and clear all interrupts */
>> + spin_lock_irqsave(&host->irqlock, flags);
>> writel(0, host->base + MSDC_INTEN);
>> val = readl(host->base + MSDC_INT);
>> writel(val, host->base + MSDC_INT);
>> + spin_unlock_irqrestore(&host->irqlock, flags);
>>
>> writel(0, host->base + MSDC_PAD_TUNE);
>> writel(0, host->base + MSDC_IOCON);
>> @@ -1207,9 +1243,11 @@ static void msdc_init_hw(struct msdc_host *host)
>> */
>> sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
>>
>> - /* disable detect SDIO device interrupt function */
>> - sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
>> -
>> + if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
>> + sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
>> + else
>> + /* disable detect SDIO device interrupt function */
>> + sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
>> /* Configure to default data timeout */
>> sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
>>
>> @@ -1221,11 +1259,15 @@ static void msdc_init_hw(struct msdc_host *host)
>> static void msdc_deinit_hw(struct msdc_host *host)
>> {
>> u32 val;
>> + unsigned long flags;
>> +
>> /* Disable and clear all interrupts */
>> + spin_lock_irqsave(&host->irqlock, flags);
>> writel(0, host->base + MSDC_INTEN);
>>
>> val = readl(host->base + MSDC_INT);
>> writel(val, host->base + MSDC_INT);
>> + spin_unlock_irqrestore(&host->irqlock, flags);
>> }
>>
>> /* init gpd and bd list in msdc_drv_probe */
>> @@ -1493,6 +1535,52 @@ static void msdc_hw_reset(struct mmc_host *mmc)
>> sdr_clr_bits(host->base + EMMC_IOCON, 1);
>> }
>>
>> +/**
>> + * msdc_recheck_sdio_irq - recheck whether the SDIO IRQ is lost
>> + * @host: The host to check.
>> + *
>> + * Host controller may lost interrupt in some special case.
>> + * Add sdio IRQ recheck mechanism to make sure all interrupts
>> + * can be processed immediately
>> + *
>> + */
>> +static void msdc_recheck_sdio_irq(struct msdc_host *host)
>> +{
>> + u32 reg_int, reg_ps;
>> +
>> + if (host->clock_on &&
>> + (host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
>> + host->irq_thread_alive) {
>> + reg_int = readl(host->base + MSDC_INT);
>> + reg_ps = readl(host->base + MSDC_PS);
>> + if (!((reg_int & MSDC_INT_SDIOIRQ) ||
>> + (reg_ps & MSDC_PS_DATA1))) {
>> + mmc_signal_sdio_irq(host->mmc);
>> + }
>> + }
>> +}
>> +
>> +static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enable)
>> +{
>> + unsigned long flags;
>> + struct msdc_host *host = mmc_priv(mmc);
>> +
>> + host->irq_thread_alive = true;
>> + if (enable) {
>> + pm_runtime_get_sync(host->dev);\
> This cause problems in kernel >= 3.19. Since pm_runtime_get_sync calls
> __might_sleep, and you are not suppose to sleep in a IRQ handler.
Ignore above, apparently I don't know what I'm talking about ...
It's actually because the sdio_irq_thread set task state to
TASK_INTERRUPTABLE before calling enable_sdio_irq:
set_current_state(TASK_INTERRUPTIBLE);
if (host->caps & MMC_CAP_SDIO_IRQ)
host->ops->enable_sdio_irq(host, 1);
if (!kthread_should_stop())
schedule_timeout(period);
set_current_state(TASK_RUNNING);
so we are not suppose to call __might_sleep in the enable_sdio_irq callback.
>
> 2017-01-20T00:32:49.855603-08:00 WARNING kernel: [ 11.068860] do not
> call blocking ops when !TASK_RUNNING; state=1 set at
> [<ffffffc0007a350c>] sdio_irq_thread+0x11c/0x1dc
> ...
> 2017-01-20T00:32:49.856042-08:00 EMERG kernel: [ 12.136156] Call
> trace:
> 2017-01-20T00:32:49.856044-08:00 WARNING kernel: [ 12.138584]
> [<ffffffc000249d84>] __might_sleep+0x64/0x90
> 2017-01-20T00:32:49.856047-08:00 WARNING kernel: [ 12.143855]
> [<ffffffc000630f54>] __pm_runtime_resume+0x40/0x9c
> 2017-01-20T00:32:49.856049-08:00 WARNING kernel: [ 12.149644]
> [<ffffffc0007ae994>] msdc_enable_sdio_irq+0x44/0xd0
> 2017-01-20T00:32:49.856051-08:00 WARNING kernel: [ 12.155516]
> [<ffffffc0007a3544>] sdio_irq_thread+0x154/0x1dc
> 2017-01-20T00:32:49.856053-08:00 WARNING kernel: [ 12.161131]
> [<ffffffc00023f30c>] kthread+0x10c/0x114
> 2017-01-20T00:32:49.856055-08:00 WARNING kernel: [ 12.166056]
> [<ffffffc000203dd0>] ret_from_fork+0x10/0x40
> 2017-01-20T00:32:49.856057-08:00 WARNING kernel: [ 12.171368] sched:
> RT throttling activated for rt_rq ffffffc0fff5a5c0 (cpu 1)
> 2017-01-20T00:32:49.856059-08:00 WARNING kernel: [ 12.171368]
> potential CPU hogs:
> 2017-01-20T00:32:49.856061-08:00 WARNING kernel: [ 12.171368]
> ksdioirqd/mmc2 (1772)
>
> dw_mmc also enables autosuspend but it didn't call any pm_runtime_get*
> function in it's enable_sdio_irq function, I don't really know how it
> worked around this.
> Ulf, any suggestions on how we can do this?
>
> Wei-Ning
>
>> + msdc_recheck_sdio_irq(host);
>> +
>> + spin_lock_irqsave(&host->irqlock, flags);
>> + sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
>> + sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
>> + spin_unlock_irqrestore(&host->irqlock, flags);
>> + } else {
>> + spin_lock_irqsave(&host->irqlock, flags);
>> + sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
>> + spin_unlock_irqrestore(&host->irqlock, flags);
>> + }
>> +}
>> +
>> static struct mmc_host_ops mt_msdc_ops = {
>> .post_req = msdc_post_req,
>> .pre_req = msdc_pre_req,
>> @@ -1504,6 +1592,7 @@ static void msdc_hw_reset(struct mmc_host *mmc)
>> .execute_tuning = msdc_execute_tuning,
>> .prepare_hs400_tuning = msdc_prepare_hs400_tuning,
>> .hw_reset = msdc_hw_reset,
>> + .enable_sdio_irq = msdc_enable_sdio_irq,
>> };
>>
>> static int msdc_drv_probe(struct platform_device *pdev)
>> @@ -1600,6 +1689,7 @@ static int msdc_drv_probe(struct platform_device *pdev)
>> mmc_dev(mmc)->dma_mask = &host->dma_mask;
>>
>> host->timeout_clks = 3 * 1048576;
>> + host->irq_thread_alive = false;
>> host->dma.gpd = dma_alloc_coherent(&pdev->dev,
>> 2 * sizeof(struct mt_gpdma_desc),
>> &host->dma.gpd_addr, GFP_KERNEL);
>> @@ -1613,6 +1703,7 @@ static int msdc_drv_probe(struct platform_device *pdev)
>> msdc_init_gpd_bd(host, &host->dma);
>> INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
>> spin_lock_init(&host->lock);
>> + spin_lock_init(&host->irqlock);
>>
>> platform_set_drvdata(pdev, mmc);
>> msdc_ungate_clock(host);
>> --
>> 1.7.9.5
>>
>
>
>
> --
> Wei-Ning Huang, 黃偉寧 | Software Engineer, Google Inc., Taiwan |
> wnhuang@google.com | Cell: +886 910-380678
--
Wei-Ning Huang, 黃偉寧 | Software Engineer, Google Inc., Taiwan |
wnhuang@google.com | Cell: +886 910-380678
^ permalink raw reply
* Re: [PATCH 1/2] hwmon: (lm70) Utilize dev_warn instead of pr_warn
From: Julia Lawall @ 2017-01-23 12:00 UTC (permalink / raw)
To: Joe Perches
Cc: Florian Fainelli, linux-kernel, Julia Lawall, Rob Herring,
Mark Rutland, Jean Delvare, Guenter Roeck, Jonathan Corbet,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:HARDWARE MONITORING, open list:DOCUMENTATION
In-Reply-To: <1485154594.12563.27.camel@perches.com>
On Sun, 22 Jan 2017, Joe Perches wrote:
> On Sun, 2017-01-22 at 22:43 -0800, Joe Perches wrote:
> > Two questions for Julia Lawall:
> >
> > o is there a better way to do this than repeat the blocks
> > one for each replacement
> > o can struct device * dev be made an arbitrary identifier
> >
> > $ cat dev_printk.cocci
> > @@
> > identifier fn;
> > type T;
> > @@
> >
> > T fn ( ..., struct device * dev, ... ) {
> > <...
> > - pr_emerg(
> > + dev_emerg(dev,
> > ...);
> > ...>
> > }
>
> Well, the second question is simple if I would just
> think a little before asking...
>
> @@
> identifier fn;
> identifier dev;
Yes :)
julia
> type T;
> @@
>
> T fn ( ..., struct device * dev, ... ) {
> <...
> - pr_emerg(
> + dev_emerg(dev,
> ...);
> ...>
> }
>
> etc...
>
>
^ permalink raw reply
* [GIT PULL] Immutable branch between MFD, ARM, IIO and PWM due for the v4.10 merge window
From: Lee Jones @ 2017-01-23 12:12 UTC (permalink / raw)
To: Benjamin Gaignard
Cc: arm-DgEjT+Ai2ygdnm+yROfE0A, Arnd Bergmann,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
alexandre.torgue-qxv4g6HH51o, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
linux-pwm-u79uwXL29TY76Z2rM5mHXA, jic23-DgEjT+Ai2ygdnm+yROfE0A,
knaack.h-Mmb7MZpHnFY, lars-Qo5EllUWu/uELgA04lAiVw,
pmeerw-jW+XmwGofnusTnJN9+BGXg, linux-iio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
fabrice.gasnier-qxv4g6HH51o, gerald.baeza-qxv4g6HH51o,
arnaud.pouliquen-qxv4g6HH51o,
linaro-kernel-cunTk1MwBs8s++Sfvej+rw, Benjamin Gaignard
In-Reply-To: <1484903709-11650-1-git-send-email-benjamin.gaignard-qxv4g6HH51o@public.gmane.org>
Arm, IIO and PWM Maintainers,
Enjoy!
The following changes since commit 7ce7d89f48834cefece7804d38fc5d85382edf77:
Linux 4.10-rc1 (2016-12-25 16:13:08 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git ib-mfd-arm-iio-pwm-v4.10
for you to fetch changes up to 94df449273475980a39f1bf47f1e3d2b07ce6577:
ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco (2017-01-23 12:06:28 +0000)
----------------------------------------------------------------
Immutable branch between MFD, ARM, IIO and PWM due for the v4.10 merge window
----------------------------------------------------------------
Benjamin Gaignard (8):
dt-bindings: mfd: Add bindings for STM32 Timers driver
mfd: Add STM32 Timers driver
dt-bindings: pwm: Add STM32 bindings
pwm: Add driver for STM32 plaftorm
iio: Add bindings for STM32 timer trigger driver
iio: Add STM32 timer trigger driver
ARM: dts: stm32: add Timers driver for stm32f429 MCU
ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco
.../ABI/testing/sysfs-bus-iio-timer-stm32 | 29 ++
.../bindings/iio/timer/stm32-timer-trigger.txt | 23 ++
.../devicetree/bindings/mfd/stm32-timers.txt | 46 +++
.../devicetree/bindings/pwm/pwm-stm32.txt | 35 ++
arch/arm/boot/dts/stm32f429.dtsi | 275 ++++++++++++++
arch/arm/boot/dts/stm32f469-disco.dts | 28 ++
drivers/iio/trigger/Kconfig | 9 +
drivers/iio/trigger/Makefile | 1 +
drivers/iio/trigger/stm32-timer-trigger.c | 342 ++++++++++++++++++
drivers/mfd/Kconfig | 11 +
drivers/mfd/Makefile | 2 +
drivers/mfd/stm32-timers.c | 80 +++++
drivers/pwm/Kconfig | 9 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-stm32.c | 398 +++++++++++++++++++++
include/linux/iio/timer/stm32-timer-trigger.h | 62 ++++
include/linux/mfd/stm32-timers.h | 71 ++++
17 files changed, 1422 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timers.txt
create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt
create mode 100644 drivers/iio/trigger/stm32-timer-trigger.c
create mode 100644 drivers/mfd/stm32-timers.c
create mode 100644 drivers/pwm/pwm-stm32.c
create mode 100644 include/linux/iio/timer/stm32-timer-trigger.h
create mode 100644 include/linux/mfd/stm32-timers.h
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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^ permalink raw reply
* Re: [PATCH 2/4] Documentation: devicetree: Add LED subnode binding for MT6323 PMIC
From: Lee Jones @ 2017-01-23 12:15 UTC (permalink / raw)
To: sean.wang-NuS5LvNUpcJWk0Htik3J/w
Cc: rpurdie-Fm38FmjxZ/leoWH0uzbU5w,
jacek.anaszewski-Re5JQEeQqe8AvxtiuMwx3w,
matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w, pavel-+ZI9xUNit7I,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-leds-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
keyhaede-Re5JQEeQqe8AvxtiuMwx3w
In-Reply-To: <1485143685-11808-3-git-send-email-sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
On Mon, 23 Jan 2017, sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org wrote:
> From: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
>
> This patch adds documentation for devicetree bindings
> for LED support as the subnode of MT6323 PMIC
>
> Signed-off-by: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
> Documentation/devicetree/bindings/mfd/mt6397.txt | 4 ++++
> 1 file changed, 4 insertions(+)
Applied, thanks.
> diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentation/devicetree/bindings/mfd/mt6397.txt
> index 949c85f..c568d52 100644
> --- a/Documentation/devicetree/bindings/mfd/mt6397.txt
> +++ b/Documentation/devicetree/bindings/mfd/mt6397.txt
> @@ -34,6 +34,10 @@ Optional subnodes:
> - clk
> Required properties:
> - compatible: "mediatek,mt6397-clk"
> +- led
> + Required properties:
> + - compatible: "mediatek,mt6323-led"
> + see Documentation/devicetree/bindings/leds/leds-mt6323.txt
>
> Example:
> pwrap: pwrap@1000f000 {
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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^ permalink raw reply
* Re: [PATCH 4/4] mfd: mt6397: Add MT6323 LED support into MT6397 driver
From: Lee Jones @ 2017-01-23 12:16 UTC (permalink / raw)
To: sean.wang-NuS5LvNUpcJWk0Htik3J/w
Cc: rpurdie-Fm38FmjxZ/leoWH0uzbU5w,
jacek.anaszewski-Re5JQEeQqe8AvxtiuMwx3w,
matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w, pavel-+ZI9xUNit7I,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-leds-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
keyhaede-Re5JQEeQqe8AvxtiuMwx3w
In-Reply-To: <1485143685-11808-5-git-send-email-sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
On Mon, 23 Jan 2017, sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org wrote:
> From: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
>
> Add compatible string as "mt6323-led" that will make
> the OF core spawn child devices for the LED subnode
> of that MT6323 MFD device.
>
> Signed-off-by: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
> drivers/mfd/mt6397-core.c | 4 ++++
> 1 file changed, 4 insertions(+)
Applied, thanks.
> diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
> index e14d8b0..8e601c8 100644
> --- a/drivers/mfd/mt6397-core.c
> +++ b/drivers/mfd/mt6397-core.c
> @@ -48,6 +48,10 @@
> .name = "mt6323-regulator",
> .of_compatible = "mediatek,mt6323-regulator"
> },
> + {
> + .name = "mt6323-led",
> + .of_compatible = "mediatek,mt6323-led"
> + },
> };
>
> static const struct mfd_cell mt6397_devs[] = {
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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^ permalink raw reply
* [PATCH] of/platform: Ignore disabled devices in of_platform_populate()
From: Alexander Sverdlin @ 2017-01-23 12:21 UTC (permalink / raw)
Cc: Alexander Sverdlin, Rob Herring, Frank Rowand,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <CAL_JsqKb8KUgit-q_cOON8VgZBsrXEQd2EcC0iF=ou_271Vg_w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
Check the status property and give up early enough. Otherwise
OF_POPULATED_BUS might be set for disabled bus which will prevent
it from being populated later (if enabled).
Signed-off-by: Alexander Sverdlin <alexander.sverdlin-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Frank Rowand <frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
drivers/of/platform.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index 35de1fc59fa6..5ad8c13f754a 100644
--- a/drivers/of/platform.c
+++ b/drivers/of/platform.c
@@ -473,9 +473,13 @@ int of_platform_populate(struct device_node *root,
struct device_node *child;
int rc = 0;
- root = root ? of_node_get(root) : of_find_node_by_path("/");
+ if (!root)
+ root = of_find_node_by_path("/");
if (!root)
return -EINVAL;
+ if (!of_device_is_available(root))
+ return 0;
+ of_node_get(root);
pr_debug("%s()\n", __func__);
pr_debug(" starting at: %s\n", root->full_name);
--
2.11.0
--
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^ permalink raw reply related
* Re: [PATCH v4 3/4] dt-bindings: phy: Add support for QMP phy
From: Vivek Gautam @ 2017-01-23 12:22 UTC (permalink / raw)
To: Stephen Boyd, Kishon Vijay Abraham I
Cc: Bjorn Andersson, robh+dt, linux-kernel, devicetree, mark.rutland,
srinivas.kandagatla, linux-arm-msm
In-Reply-To: <20170119214258.GD7829@codeaurora.org>
On 01/20/2017 03:12 AM, Stephen Boyd wrote:
> On 01/19, Vivek Gautam wrote:
>> On 01/19/2017 06:10 AM, Stephen Boyd wrote:
>>> Didn't we already move away from subnodes for lanes in an earlier
>>> revision of these patches? I seem to recall we did that because
>>> lanes are not devices and the whole "phy as a bus" concept not
>>> making sense.
>> Yea, we started out without having any sub-nodes and we
>> argued that we don't require them since the qmp device is
>> represented by the qmp node itself.
>> The lanes otoh are representative of gen_phys and related properties.
>>
>> In the driver -
>> "struct qmp_phy " represents the lanes and holds "struct phy",
>> "struct qcom_qmp" represents the qmp block as a whole and holds
>> "struct device"
>> Does this make lanes qualify to be childs of qmp ?
> Hmm... maybe I was recalling the DSI phy binding. I think there
> are lanes there too but we decided to just have one node.
>
>> "phy as a bus" (just trying to understand here) -
>> let's say a usb phy controller has one HSIC phy port and one USB2 phy port.
>> So, should this phy controller be a bus providing two ports (and so
>> we will have
>> couple of child nodes to the phy controller) ?
>>
> Typically in DT a subnode or collection of subnodes means there's
> some sort of bus involved. Usually each node corresponds to a
> struct device, and the parent node corresponds to the bus or
> controller for the logical bus.
>
> In this case (only PCIe though? not UFS or USB?) it seems like we
> have multiple phys that share a common register space, but
> otherwise they have their own register space and power
> management. Would you have each PCIe controller point to a
> different subnode for their associated phy? I'm trying to
> understand the benefit of the subnodes if they aren't treated as
> struct devices.
AFAIU, It's not straight that forward to point each controller to
different subnodes and not associate a 'struct device' with subnodes.
The phy translation (of_phy_simple_xlate, in case we point each controller
to subnodes) will not be able to associate a correct phy_provider device
to the phy consumer.
Kishon,
Is my understanding correct here? Please correct me if i am missing things.
Regards
Vivek
>
> At the least, please get DT reviewers to ack the new binding
> before rewriting the code.
>
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* Re: [PATCH] of/platform: Ignore disabled devices in of_platform_populate()
From: Alexander Sverdlin @ 2017-01-23 12:24 UTC (permalink / raw)
Cc: Rob Herring, Frank Rowand, devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170123122151.21908-1-alexander.sverdlin-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
Hello all,
On 23/01/17 13:21, Alexander Sverdlin wrote:
> Check the status property and give up early enough. Otherwise
> OF_POPULATED_BUS might be set for disabled bus which will prevent
> it from being populated later (if enabled).
>
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Frank Rowand <frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
> drivers/of/platform.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/of/platform.c b/drivers/of/platform.c
> index 35de1fc59fa6..5ad8c13f754a 100644
> --- a/drivers/of/platform.c
> +++ b/drivers/of/platform.c
> @@ -473,9 +473,13 @@ int of_platform_populate(struct device_node *root,
> struct device_node *child;
> int rc = 0;
>
> - root = root ? of_node_get(root) : of_find_node_by_path("/");
> + if (!root)
> + root = of_find_node_by_path("/");
> if (!root)
> return -EINVAL;
> + if (!of_device_is_available(root))
> + return 0;
> + of_node_get(root);
Auch, I see unbalanced reference counting here, please ignore this patch...
> pr_debug("%s()\n", __func__);
> pr_debug(" starting at: %s\n", root->full_name);
--
Best regards,
Alexander Sverdlin.
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^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: gpu: Add Mali Utgard bindings
From: Maxime Ripard @ 2017-01-23 12:34 UTC (permalink / raw)
To: Rob Herring
Cc: John Stultz, Mark Rutland, Thomas Petazzoni,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Heiko Stuebner, Javier Martinez Canillas, Kevin Hilman,
Linus Walleij, Krzysztof Kozlowski, Matthias Brugger,
Chen-Yu Tsai, Kukjin Kim, Alexandre Belloni, Boris Brezillon,
Carlo Caione, Antoine Ténart, linux-arm-kernel
In-Reply-To: <CAL_JsqL5fYVvCRgui9NQVEM+=gkGUnf7-D9KHK9YTtJyfGy3Ew-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 1457 bytes --]
Hi Rob,
On Fri, Jan 20, 2017 at 08:15:21AM -0600, Rob Herring wrote:
> > The only thing that might be vendor specific would be the (optional)
> > declaration of the mali_gpu_device_data structure. As far as I know,
> > there's two things of importance there:
> > - the list of the valid OPPs in order to do DVFS, but that could be
> > made generic too using the operating-points binding
> >
> > - And the valid area for the buffers for the fbdev blobs (fb_start,
> > fb_size and shared_mem_size). I'm not entirely happy with this one
> > so far (which is also why I've not pushed it). We'd need to come
> > up with a way to get the base address and size of the CMA region
> > backing the framebuffer allocation, but I haven't find any trivial
> > way to do so, so for now I just hardcoded it. Worst case scenario,
> > we can hardcode values based on the compatible.
>
> memory-region property?
That might do it, however those buffers usually are allocated by the
display engine, and not the GPU device. Even if we declare a reserved
memory region and use memory-region in the GPU node, chances are that
buffers allocated for the display may not be in that region (for
example if it's using the default CMA pool).
Unless we create a memory region for the default CMA pool?
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 801 bytes --]
^ permalink raw reply
* [PATCH v2] of/platform: Ignore disabled devices in of_platform_populate()
From: Alexander Sverdlin @ 2017-01-23 12:52 UTC (permalink / raw)
Cc: Alexander Sverdlin, Rob Herring, Frank Rowand,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <CAL_JsqKb8KUgit-q_cOON8VgZBsrXEQd2EcC0iF=ou_271Vg_w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
Check the status property and give up early enough. Otherwise
OF_POPULATED_BUS might be set for disabled bus which will prevent
it from being populated later (if enabled).
Signed-off-by: Alexander Sverdlin <alexander.sverdlin-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Frank Rowand <frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
drivers/of/platform.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index 35de1fc59fa6..060621d94f1a 100644
--- a/drivers/of/platform.c
+++ b/drivers/of/platform.c
@@ -476,6 +476,10 @@ int of_platform_populate(struct device_node *root,
root = root ? of_node_get(root) : of_find_node_by_path("/");
if (!root)
return -EINVAL;
+ if (!of_device_is_available(root)) {
+ of_node_put(root);
+ return 0;
+ }
pr_debug("%s()\n", __func__);
pr_debug(" starting at: %s\n", root->full_name);
--
2.11.0
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^ permalink raw reply related
* Re: [RFC v2 1/5] UDC: Split the driver into amd (pci) and Synopsys core driver
From: Raviteja Garimella @ 2017-01-23 13:05 UTC (permalink / raw)
To: Florian Fainelli
Cc: Rob Herring, Mark Rutland, Greg Kroah-Hartman, Felipe Balbi,
devicetree, linux-kernel, BCM Kernel Feedback, linux-usb
In-Reply-To: <db1037e7-33f2-95ce-2f7a-60fe98d75e0c@gmail.com>
Hi Florian,
On Fri, Jan 20, 2017 at 12:58 AM, Florian Fainelli <f.fainelli@gmail.com> wrote:
> On 01/19/2017 02:44 AM, Raviteja Garimella wrote:
>> Hi,
>>
>> On Thu, Jan 19, 2017 at 12:15 AM, Florian Fainelli <f.fainelli@gmail.com> wrote:
>>> On 01/17/2017 12:05 AM, Raviteja Garimella wrote:
>>>> This patch splits the amd5536udc driver into two -- one that does
>>>> pci device registration and the other file that does the rest of
>>>> the driver tasks like the gadget/ep ops etc for Synopsys UDC.
>>>>
>>>> This way of splitting helps in exporting core driver symbols which
>>>> can be used by any other platform/pci driver that is written for
>>>> the same Synopsys USB device controller.
>>>>
>>>> The current patch also includes a change in the Kconfig and Makefile.
>>>> A new config option USB_SNP_CORE will be selected automatically when
>>>> any one of the platform or pci driver for the same UDC is selected.
>>>>
>>>> Signed-off-by: Raviteja Garimella <raviteja.garimella@broadcom.com>
>>>
>>> Although the changes you have done make sense and it is most certainly a
>>> good idea to split udc core from bus specific glue logic, it is really
>>> hard to review the changes per-se because of the file rename, could that
>>> happen at a later time?
>>
>> If you start looking at this specific patch from the header file (amd5536udc.h),
>> the additions in there comprise of:
>> - 9 function declarations
>> - some module parameter variable declarations that's moved out from the older
>> common file amd5536udc.c
>> - 2 #includes that are needed by all files.
>
> Well, I don't really question the changes themselves, rather how this is
> presented as a patch series to reviewers.
>
> What I would do, to help introduce both the rename, and the splitting of
> core vs. bus-glue specific changes is:
>
> - have an initial patch which extracts the core functionality of the
> driver and the PCI bus glue logic into adm5536udc_pci.c and left
> adm5536udc.c intact (that would be a small delta to review)
>
> - have a second patch that performs the file rename from adm5536udc.c
> into snps_udc_core.c and updates adm5536udc_pci.c eventually as a result
> of that, then again, a reviewer can ignore the rename part (don't format
> to generate your patches with git format-patch -M in that case) and just
> focus on the conversion part for adm5536udc_pci.c
>
Just waited for any more comments coming in. I will submit the next version
as PATCH like the way you suggested.
>>
>> So, basically what's done for this split is that:
>> 1. the static keyword is removed from those 9 functions in the new file
>> snps_udc_core.c and are exported.
>> 2. The module parameters declarations (since they are used in both core
>> and pci file) are moved to the header file now.
>
> These should really be part of the commit messages for each commit doing
> the changes, this is meant to help a reviewer understand what you are
> doing, and to some degree, will help him/her make an educated decision
> as to what part of the code the focus should be put on.
>
Will do.
Thanks,
Ravi
> Thanks
> --
> Florian
^ permalink raw reply
* Re: [V2 2/2] arm64: dts: Add dts files for Hisilicon Hi3660 SoC
From: Mark Rutland @ 2017-01-23 13:46 UTC (permalink / raw)
To: Chen Feng
Cc: xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
catalin.marinas-5wv7dgnIgG8, will.deacon-5wv7dgnIgG8,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
puck.chen-H32Fclmsjq1BDgjK7y7TUQ, dan.zhao-C8/M+/jPZTeaMJb+Lgu22Q,
suzhuangluan-C8/M+/jPZTeaMJb+Lgu22Q,
saberlily.xia-C8/M+/jPZTeaMJb+Lgu22Q,
xuyiping-C8/M+/jPZTeaMJb+Lgu22Q, qijiwen-C8/M+/jPZTeaMJb+Lgu22Q
In-Reply-To: <1484034915-48879-2-git-send-email-puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
On Tue, Jan 10, 2017 at 03:55:15PM +0800, Chen Feng wrote:
> + memory@0 {
> + device_type = "memory";
> + reg = <0x0 0x00400000 0x0 0xbfe00000>;
> + };
The unit-address here is incorrect. The base address of this memory is
not zero.
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> + clock-frequency = <1920000>;
> + };
This clock-frequency property should not be required; please remove it.
Your FW should program CNTFRQ_EL0 with the timer frequency.
Thanks,
Mark.
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^ permalink raw reply
* [PATCH v2 0/3] Add support for es8323 and hdmi audio to the firefly-rk3288
From: Romain Perier @ 2017-01-23 13:47 UTC (permalink / raw)
To: Heiko Stuebner, devicetree, Rob Herring, Ian Campbell, Pawel Moll,
Mark Rutland, Kumar Gala, Jaroslav Kysela, Takashi Iwai,
alsa-devel
Cc: Romain Perier, linux-rockchip, Sjoerd Simons, linux-arm-kernel
This set of patches enables support for the es8323 codecs on the
firefly-rk3288. It adds the required DT definitions to link rockchip-i2s
to the es8388 analog output. As the support for HDMI audio is also
built-in in the corresponding ASoC machine driver, HDMI audio output is
also enabled.
Changes in v2:
- Adapted DT for the firefly-rk3288 to the ASoC machine driver
rk3288-hdmi-analog
- Added patch 02/03 to this series
- Re-wrote this cover letter
Romain Perier (3):
SoC: es8328-i2c: Add compatible for ES8323
arm: dts: rockchip: Don't set otp-gpio pinctrl by default in
rk3288.dtsi
arm: dts: Add support for ES8323 to the Firefly-RK3288
Documentation/devicetree/bindings/sound/es8328.txt | 5 +++-
arch/arm/boot/dts/rk3288-evb.dtsi | 4 +++
arch/arm/boot/dts/rk3288-firefly.dtsi | 34 ++++++++++++++++++++++
arch/arm/boot/dts/rk3288-veyron.dtsi | 4 +++
arch/arm/boot/dts/rk3288.dtsi | 4 ---
sound/soc/codecs/es8328-i2c.c | 2 ++
6 files changed, 48 insertions(+), 5 deletions(-)
--
2.9.3
^ permalink raw reply
* [PATCH v2 1/3] SoC: es8328-i2c: Add compatible for ES8323
From: Romain Perier @ 2017-01-23 13:47 UTC (permalink / raw)
To: Heiko Stuebner, devicetree, Rob Herring, Ian Campbell, Pawel Moll,
Mark Rutland, Kumar Gala, Jaroslav Kysela, Takashi Iwai,
alsa-devel
Cc: Romain Perier, linux-rockchip, Sjoerd Simons, linux-arm-kernel
In-Reply-To: <20170123134747.1385-1-romain.perier@collabora.com>
This commit adds a compatible string for everest,es8323. This is an
audio codec that is compatible with es8328 and can be found for example
on the Firefly-RK3288 board.
Signed-off-by: Romain Perier <romain.perier@collabora.com>
---
Changes in v2: None
Documentation/devicetree/bindings/sound/es8328.txt | 5 ++++-
sound/soc/codecs/es8328-i2c.c | 2 ++
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/sound/es8328.txt b/Documentation/devicetree/bindings/sound/es8328.txt
index 33fbf05..86b6d6e 100644
--- a/Documentation/devicetree/bindings/sound/es8328.txt
+++ b/Documentation/devicetree/bindings/sound/es8328.txt
@@ -4,7 +4,10 @@ This device supports both I2C and SPI.
Required properties:
- - compatible : Should be "everest,es8328" or "everest,es8388"
+ - compatible : Should be one of the following:
+ - "everest,es8323"
+ - "everest,es8328"
+ - "everest,es8388"
- DVDD-supply : Regulator providing digital core supply voltage 1.8 - 3.6V
- AVDD-supply : Regulator providing analog supply voltage 3.3V
- PVDD-supply : Regulator providing digital IO supply voltage 1.8 - 3.6V
diff --git a/sound/soc/codecs/es8328-i2c.c b/sound/soc/codecs/es8328-i2c.c
index 318ab28..be3f03c 100644
--- a/sound/soc/codecs/es8328-i2c.c
+++ b/sound/soc/codecs/es8328-i2c.c
@@ -19,6 +19,7 @@
#include "es8328.h"
static const struct i2c_device_id es8328_id[] = {
+ { "es8323", 0 },
{ "es8328", 0 },
{ "es8388", 0 },
{ }
@@ -26,6 +27,7 @@ static const struct i2c_device_id es8328_id[] = {
MODULE_DEVICE_TABLE(i2c, es8328_id);
static const struct of_device_id es8328_of_match[] = {
+ { .compatible = "everest,es8323", },
{ .compatible = "everest,es8328", },
{ .compatible = "everest,es8388", },
{ }
--
2.9.3
^ permalink raw reply related
* [PATCH v2 2/3] arm: dts: rockchip: Don't set otp-gpio pinctrl by default in rk3288.dtsi
From: Romain Perier @ 2017-01-23 13:47 UTC (permalink / raw)
To: Heiko Stuebner, devicetree, Rob Herring, Ian Campbell, Pawel Moll,
Mark Rutland, Kumar Gala, Jaroslav Kysela, Takashi Iwai,
alsa-devel
Cc: Romain Perier, linux-rockchip, Sjoerd Simons, linux-arm-kernel
In-Reply-To: <20170123134747.1385-1-romain.perier@collabora.com>
The tsadc supports two reset methods: the cru and the otp_gpio. All
boards except veyron and the evb simply use the cru-method and reuse the
pin for something else. On the Firefly-RK3288 this is for example the
case with the headphone. To prevent pinctrl-conflicts with these don't
set the otp-gpio pinctrl by default but only in the boards using it.
Signed-off-by: Romain Perier <romain.perier@collabora.com>
---
Changes in v2:
- Added this patch
arch/arm/boot/dts/rk3288-evb.dtsi | 4 ++++
arch/arm/boot/dts/rk3288-veyron.dtsi | 4 ++++
arch/arm/boot/dts/rk3288.dtsi | 4 ----
3 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
index bf7ccfa..7160d07 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -290,6 +290,10 @@
};
&tsadc {
+ pinctrl-names = "init", "default", "sleep";
+ pinctrl-0 = <&otp_gpio>;
+ pinctrl-1 = <&otp_out>;
+ pinctrl-2 = <&otp_gpio>;
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
status = "okay";
diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
index 2251d28..e7801d8 100644
--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
@@ -393,6 +393,10 @@
&tsadc {
status = "okay";
+ pinctrl-names = "init", "default", "sleep";
+ pinctrl-0 = <&otp_gpio>;
+ pinctrl-1 = <&otp_out>;
+ pinctrl-2 = <&otp_gpio>;
rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
};
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 4fad133..f419e4d 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -532,10 +532,6 @@
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
- pinctrl-names = "init", "default", "sleep";
- pinctrl-0 = <&otp_gpio>;
- pinctrl-1 = <&otp_out>;
- pinctrl-2 = <&otp_gpio>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
status = "disabled";
--
2.9.3
^ permalink raw reply related
* [PATCH v2 3/3] arm: dts: Add support for ES8323 to the Firefly-RK3288
From: Romain Perier @ 2017-01-23 13:47 UTC (permalink / raw)
To: Heiko Stuebner, devicetree, Rob Herring, Ian Campbell, Pawel Moll,
Mark Rutland, Kumar Gala, Jaroslav Kysela, Takashi Iwai,
alsa-devel
Cc: Romain Perier, linux-rockchip, Sjoerd Simons, linux-arm-kernel
In-Reply-To: <20170123134747.1385-1-romain.perier@collabora.com>
This commit adds the DT definition of the es8323 i2c device found at
address 0x10. It also adds the definition for connecting the Rockchip
I2S to the es8323 analog output.
Signed-off-by: Romain Perier <romain.perier@collabora.com>
---
Changes in v2:
- Add the pinctrl headphone, that was previously in conflict with otp pins
- Renamed sound_es8323 to sound_i2s
- Added the property rockchip,routing
arch/arm/boot/dts/rk3288-firefly.dtsi | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi
index 44935af..ddb0beb 100644
--- a/arch/arm/boot/dts/rk3288-firefly.dtsi
+++ b/arch/arm/boot/dts/rk3288-firefly.dtsi
@@ -103,6 +103,19 @@
};
};
+ sound_i2s {
+ compatible = "rockchip,rk3288-hdmi-analog";
+ rockchip,model = "I2S";
+ rockchip,i2s-controller = <&i2s>;
+ rockchip,audio-codec = <&es8323>;
+ rockchip,routing = "Analog", "LOUT2",
+ "Analog", "ROUT2";
+ rockchip,hp-en-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
+ rockchip,hp-det-gpios = <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&headphone>;
+ };
+
vbat_wl: vcc_sys: vsys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
@@ -371,6 +384,17 @@
&i2c2 {
status = "okay";
+
+ es8323: es8323@10 {
+ compatible = "everest,es8323", "everest,es8328";
+ reg = <0x10>;
+ AVDD-supply = <&vcca_33>;
+ DVDD-supply = <&vcca_33>;
+ HPVDD-supply = <&vcca_33>;
+ PVDD-supply = <&vcca_33>;
+ clocks = <&cru SCLK_I2S0_OUT>;
+ clock-names = "i2s_clk_out";
+ };
};
&i2c4 {
@@ -381,6 +405,10 @@
status = "okay";
};
+&i2s {
+ status = "okay";
+};
+
&io_domains {
status = "okay";
@@ -483,6 +511,12 @@
};
};
+ sound {
+ headphone: headphone {
+ rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
usb_host {
host_vbus_drv: host-vbus-drv {
rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
--
2.9.3
^ permalink raw reply related
* Urgent Please,,
From: Joyes Dadi @ 2017-01-23 13:53 UTC (permalink / raw)
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Email: joyesdadi767-xnxYRYGmInRAgIPG3DZhQQ@public.gmane.org
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^ permalink raw reply
* [PATCH v3 0/2] clocksource: Add renesas-ostm timer driver
From: Chris Brandt @ 2017-01-23 13:54 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Simon Horman, Magnus Damm,
Russell King, Daniel Lezcano, Thomas Gleixner, Geert Uytterhoeven
Cc: devicetree, linux-renesas-soc, Chris Brandt
This patch set adds a new clocksource driver that uses the OS Timer
(OSTM) that exists in the R7S72100 (RZ/A1) SoC.
The operation of the driver was tested with a simple user application
that does multiple calls to nanosleep() and gettimeofday().
The purpose of adding this driver is to get better time keeping
accuracy over the default MTU2 clocksource timer.
v3:
* Changed ostm@fcfec000 to timer@fcfec000
* Added power-domains to nodes
v2:
* The biggest change was now the channels are independent of each
other and have separate nodes in the DT. The first probed will
be set up as a clock source, and any additional channels probed
will become a clock event.
Chris Brandt (2):
dt-bindings: document renesas-ostm timer
clocksource: Add renesas-ostm timer driver
.../devicetree/bindings/timer/renesas,ostm.txt | 30 ++
arch/arm/mach-shmobile/Kconfig | 1 +
drivers/clocksource/Kconfig | 12 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/renesas-ostm.c | 349 +++++++++++++++++++++
5 files changed, 393 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/renesas,ostm.txt
create mode 100644 drivers/clocksource/renesas-ostm.c
--
2.10.1
^ permalink raw reply
* [PATCH v3 1/2] dt-bindings: document renesas-ostm timer
From: Chris Brandt @ 2017-01-23 13:54 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Simon Horman, Magnus Damm,
Russell King, Daniel Lezcano, Thomas Gleixner, Geert Uytterhoeven
Cc: devicetree, linux-renesas-soc, Chris Brandt
In-Reply-To: <20170123135423.28780-1-chris.brandt@renesas.com>
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
* changed ostm@fcfec000 to timer@fcfec000 in example
* added power-domains in example
v2:
* remove sw implementation specific portions
---
.../devicetree/bindings/timer/renesas,ostm.txt | 30 ++++++++++++++++++++++
1 file changed, 30 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/renesas,ostm.txt
diff --git a/Documentation/devicetree/bindings/timer/renesas,ostm.txt b/Documentation/devicetree/bindings/timer/renesas,ostm.txt
new file mode 100644
index 0000000..be3ae0f
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/renesas,ostm.txt
@@ -0,0 +1,30 @@
+* Renesas OS Timer (OSTM)
+
+The OSTM is a multi-channel 32-bit timer/counter with fixed clock
+source that can operate in either interval count down timer or free-running
+compare match mode.
+
+Channels are independent from each other.
+
+Required Properties:
+
+ - compatible: must be one or more of the following:
+ - "renesas,r7s72100-ostm" for the r7s72100 OSTM
+ - "renesas,ostm" for any OSTM
+ This is a fallback for the above renesas,*-ostm entries
+
+ - reg: base address and length of the register block for a timer channel.
+
+ - interrupts: interrupt specifier for the timer channel.
+
+ - clocks: clock specifier for the timer channel.
+
+Example: R7S72100 (RZ/A1H) OSTM node
+
+ ostm0: timer@fcfec000 {
+ compatible = "renesas,r7s72100-ostm", "renesas,ostm";
+ reg = <0xfcfec000 0x30>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
+ power-domains = <&cpg_clocks>;
+ };
--
2.10.1
^ permalink raw reply related
* [PATCH v3 2/2] clocksource: Add renesas-ostm timer driver
From: Chris Brandt @ 2017-01-23 13:54 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Simon Horman, Magnus Damm,
Russell King, Daniel Lezcano, Thomas Gleixner, Geert Uytterhoeven
Cc: devicetree, linux-renesas-soc, Chris Brandt
In-Reply-To: <20170123135423.28780-1-chris.brandt@renesas.com>
This patch adds a OSTM driver for the Renesas architecture.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
---
v2:
* changed implementation to be independent channel nodes
---
arch/arm/mach-shmobile/Kconfig | 1 +
drivers/clocksource/Kconfig | 12 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/renesas-ostm.c | 349 +++++++++++++++++++++++++++++++++++++
4 files changed, 363 insertions(+)
create mode 100644 drivers/clocksource/renesas-ostm.c
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 2bb4b09..b928634 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -57,6 +57,7 @@ config ARCH_R7S72100
select PM
select PM_GENERIC_DOMAINS
select SYS_SUPPORTS_SH_MTU2
+ select SYS_SUPPORTS_RENESAS_OSTM
config ARCH_R8A73A4
bool "R-Mobile APE6 (R8A73A40)"
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 4866f7a..95c8d56 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -431,6 +431,9 @@ config MTK_TIMER
config SYS_SUPPORTS_SH_MTU2
bool
+config SYS_SUPPORTS_RENESAS_OSTM
+ bool
+
config SYS_SUPPORTS_SH_TMU
bool
@@ -467,6 +470,15 @@ config SH_TIMER_MTU2
Timer Pulse Unit 2 (MTU2) hardware available on SoCs from Renesas.
This hardware comes with 16 bit-timer registers.
+config RENESAS_OSTM
+ bool "Renesas OSTM timer driver" if COMPILE_TEST
+ depends on GENERIC_CLOCKEVENTS
+ select CLKSRC_MMIO
+ default SYS_SUPPORTS_RENESAS_OSTM
+ help
+ This enables the build of the OSTM timer driver.
+ It creates a clock source and clock event device.
+
config SH_TIMER_TMU
bool "Renesas TMU timer driver" if COMPILE_TEST
depends on GENERIC_CLOCKEVENTS
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index a14111e..bbd163b 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += cs5535-clockevt.o
obj-$(CONFIG_CLKSRC_JCORE_PIT) += jcore-pit.o
obj-$(CONFIG_SH_TIMER_CMT) += sh_cmt.o
obj-$(CONFIG_SH_TIMER_MTU2) += sh_mtu2.o
+obj-$(CONFIG_RENESAS_OSTM) += renesas-ostm.o
obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o
obj-$(CONFIG_EM_TIMER_STI) += em_sti.o
obj-$(CONFIG_CLKBLD_I8253) += i8253.o
diff --git a/drivers/clocksource/renesas-ostm.c b/drivers/clocksource/renesas-ostm.c
new file mode 100644
index 0000000..37f2461
--- /dev/null
+++ b/drivers/clocksource/renesas-ostm.c
@@ -0,0 +1,349 @@
+/*
+ * Renesas Timer Support - OSTM
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <linux/sched_clock.h>
+
+/*
+ * The OSTM contains independent channels.
+ * The first OSTM channel probed will be set up as a free running
+ * clocksource. Additionally we will use this clocksource for the system
+ * schedule timer sched_clock().
+ *
+ * The second (or more) channel probed will be set up as an interrupt
+ * driven clock event.
+ */
+
+struct ostm_device {
+ struct platform_device *pdev;
+
+ int irq;
+ struct clk *clk;
+ unsigned long rate;
+ void __iomem *base;
+ unsigned long ticks_per_jiffy;
+ struct clock_event_device ced;
+};
+
+static void __iomem *system_clock; /* For sched_clock() */
+
+/* OSTM REGISTERS */
+#define OSTM_CMP 0x000 /* RW,32 */
+#define OSTM_CNT 0x004 /* R,32 */
+#define OSTM_TE 0x010 /* R,8 */
+#define OSTM_TS 0x014 /* W,8 */
+#define OSTM_TT 0x018 /* W,8 */
+#define OSTM_CTL 0x020 /* RW,8 */
+
+#define TE 0x01
+#define TS 0x01
+#define TT 0x01
+#define CTL_PERIODIC 0x00
+#define CTL_ONESHOT 0x02
+#define CTL_FREERUN 0x02
+
+static struct ostm_device *ced_to_ostm(struct clock_event_device *ced)
+{
+ return container_of(ced, struct ostm_device, ced);
+}
+
+static int __init ostm_init_clksrc(struct ostm_device *ostm)
+{
+ int ret;
+
+ /* irq not used (clock sources don't use interrupts) */
+
+ /* stop counter */
+ iowrite8(TT, ostm->base + OSTM_TT);
+ while (ioread8(ostm->base + OSTM_TE) & TE)
+ ;
+
+ /* setup as freerun */
+ iowrite32(0, ostm->base + OSTM_CMP);
+ iowrite8(CTL_FREERUN, ostm->base + OSTM_CTL);
+ iowrite8(TS, ostm->base + OSTM_TS);
+
+ /* register */
+ ret = clocksource_mmio_init(ostm->base + OSTM_CNT,
+ "ostm", ostm->rate,
+ 300, 32, clocksource_mmio_readl_up);
+
+ return ret;
+}
+
+static u64 notrace ostm_read_sched_clock(void)
+{
+ return ioread32(system_clock);
+}
+
+static int __init ostm_init_sched_clock(struct ostm_device *ostm)
+{
+ unsigned long flags;
+
+ system_clock = ostm->base + OSTM_CNT;
+ local_irq_save(flags);
+ local_irq_disable();
+ sched_clock_register(ostm_read_sched_clock, 32, ostm->rate);
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+static void ostm_clkevt_timer_stop(struct ostm_device *ostm)
+{
+ if (ioread8(ostm->base + OSTM_TE) & TE) {
+ iowrite8(TT, ostm->base + OSTM_TT);
+ while (ioread8(ostm->base + OSTM_TE) & TE)
+ ;
+ }
+}
+
+static int ostm_clock_event_next(unsigned long delta,
+ struct clock_event_device *ced)
+{
+ struct ostm_device *ostm = ced_to_ostm(ced);
+
+ WARN_ON(!clockevent_state_oneshot(ced));
+
+ ostm_clkevt_timer_stop(ostm);
+
+ iowrite32(delta, ostm->base + OSTM_CMP);
+ iowrite8(CTL_ONESHOT, ostm->base + OSTM_CTL);
+ iowrite8(TS, ostm->base + OSTM_TS);
+
+ return 0;
+}
+
+static int ostm_shutdown(struct clock_event_device *ced)
+{
+ struct ostm_device *ostm = ced_to_ostm(ced);
+
+ ostm_clkevt_timer_stop(ostm);
+
+ return 0;
+}
+static int ostm_set_periodic(struct clock_event_device *ced)
+{
+ struct ostm_device *ostm = ced_to_ostm(ced);
+
+ if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
+ ostm_clkevt_timer_stop(ostm);
+
+ iowrite32(ostm->ticks_per_jiffy - 1, ostm->base + OSTM_CMP);
+ iowrite8(CTL_PERIODIC, ostm->base + OSTM_CTL);
+ iowrite8(TS, ostm->base + OSTM_TS);
+
+ return 0;
+}
+
+static int ostm_set_oneshot(struct clock_event_device *ced)
+{
+ struct ostm_device *ostm = ced_to_ostm(ced);
+
+ ostm_clkevt_timer_stop(ostm);
+
+ return 0;
+}
+
+static irqreturn_t ostm_timer_interrupt(int irq, void *dev_id)
+{
+ struct ostm_device *ostm = dev_id;
+
+ if (clockevent_state_oneshot(&ostm->ced))
+ ostm_clkevt_timer_stop(ostm);
+
+ /* notify clockevent layer */
+ if (ostm->ced.event_handler)
+ ostm->ced.event_handler(&ostm->ced);
+
+ return IRQ_HANDLED;
+}
+
+static int __init ostm_init_clkevt(struct ostm_device *ostm)
+{
+ struct clock_event_device *ced = &ostm->ced;
+ int ret = -ENXIO;
+
+ ret = request_irq(ostm->irq, ostm_timer_interrupt,
+ IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
+ dev_name(&ostm->pdev->dev), ostm);
+ if (ret) {
+ dev_err(&ostm->pdev->dev, "failed to request irq\n");
+ return ret;
+ }
+
+ ced->name = "ostm";
+ ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC;
+ ced->set_state_shutdown = ostm_shutdown;
+ ced->set_state_periodic = ostm_set_periodic;
+ ced->set_state_oneshot = ostm_set_oneshot;
+ ced->set_next_event = ostm_clock_event_next;
+ ced->shift = 32;
+ ced->rating = 300;
+ ced->cpumask = cpumask_of(0);
+ clockevents_config_and_register(ced, ostm->rate, 0xf, 0xffffffff);
+
+ return 0;
+}
+
+static int __init ostm_probe(struct platform_device *pdev)
+{
+ struct ostm_device *ostm;
+ struct resource *res;
+ int ret = -EFAULT;
+
+ if (!is_early_platform_device(pdev)) {
+ pm_runtime_set_active(&pdev->dev);
+ pm_runtime_enable(&pdev->dev);
+ }
+
+ ostm = platform_get_drvdata(pdev);
+ if (ostm) {
+ dev_info(&pdev->dev, "kept as earlytimer\n");
+ ret = 0;
+ goto out;
+ }
+
+ ostm = kzalloc(sizeof(*ostm), GFP_KERNEL);
+ if (!ostm) {
+ dev_err(&pdev->dev, "failed to allocate memory\n");
+ return -ENOMEM;
+ }
+
+ ostm->pdev = pdev;
+ platform_set_drvdata(ostm->pdev, ostm);
+
+ res = platform_get_resource(ostm->pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&ostm->pdev->dev, "failed to get I/O memory\n");
+ goto err;
+ }
+
+ ostm->base = ioremap_nocache(res->start, resource_size(res));
+ if (!ostm->base) {
+ dev_err(&ostm->pdev->dev, "failed to remap I/O memory\n");
+ goto err;
+ }
+
+ ostm->irq = platform_get_irq(ostm->pdev, 0);
+ if (ostm->irq < 0) {
+ dev_err(&ostm->pdev->dev, "failed to get irq\n");
+ goto err;
+ }
+
+ ostm->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(ostm->clk)) {
+ dev_err(&ostm->pdev->dev, "failed to get clock\n");
+ ostm->clk = NULL;
+ goto err;
+ }
+
+ ret = clk_prepare_enable(ostm->clk);
+ if (ret) {
+ dev_err(&ostm->pdev->dev, "failed to enable clock\n");
+ goto err;
+ }
+
+ ostm->rate = clk_get_rate(ostm->clk);
+ ostm->ticks_per_jiffy = (ostm->rate + HZ / 2) / HZ;
+
+ /* First probed device will be used as system clocksource */
+ if (!system_clock) {
+ /* use as clocksource */
+ ret = ostm_init_clksrc(ostm);
+
+ /* use as system scheduling clock */
+ if (!ret)
+ ret = ostm_init_sched_clock(ostm);
+
+ if (ret) {
+ dev_err(&pdev->dev, "failed to use as sched_clock\n");
+ system_clock = (void *)-1; /* prevent future attempts */
+ ret = 0; /* still works as clocksource */
+ }
+
+ if (!ret)
+ dev_info(&pdev->dev, "used for clocksource\n");
+ } else {
+ /* use as clock event */
+ ret = ostm_init_clkevt(ostm);
+
+ if (!ret)
+ dev_info(&pdev->dev, "used for clock events\n");
+ }
+
+err:
+ if (ret) {
+ if (ostm->clk)
+ clk_disable_unprepare(ostm->clk);
+ if (ostm->base)
+ iounmap(ostm->base);
+ kfree(ostm);
+ platform_set_drvdata(pdev, NULL);
+ pm_runtime_idle(&pdev->dev);
+ return ret;
+ }
+
+ if (is_early_platform_device(pdev))
+ return ret;
+
+out:
+ pm_runtime_irq_safe(&pdev->dev);
+
+ return ret;
+}
+
+static int ostm_remove(struct platform_device *pdev)
+{
+ return -EBUSY; /* cannot unregister clockevent */
+}
+
+static const struct of_device_id ostm_of_table[] __maybe_unused = {
+ { .compatible = "renesas,ostm" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, ostm_of_table);
+
+static struct platform_driver ostm_timer = {
+ .probe = ostm_probe,
+ .remove = ostm_remove,
+ .driver = {
+ .name = "ostm",
+ .of_match_table = of_match_ptr(ostm_of_table),
+ },
+};
+
+static int __init ostm_init(void)
+{
+ return platform_driver_register(&ostm_timer);
+}
+
+static void __exit ostm_exit(void)
+{
+ platform_driver_unregister(&ostm_timer);
+}
+
+early_platform_init("earlytimer", &ostm_timer);
+subsys_initcall(ostm_init);
+module_exit(ostm_exit);
+
+MODULE_AUTHOR("Chris Brandt");
+MODULE_DESCRIPTION("Renesas OSTM Timer Driver");
+MODULE_LICENSE("GPL v2");
--
2.10.1
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