* Re: [PATCH 2/3] arm64: allwinner: a64: add USB0 OHCI/EHCI related devicetree parts
From: Icenowy Zheng @ 2017-04-05 7:33 UTC (permalink / raw)
To: Maxime Ripard
Cc: Chen-Yu Tsai, Kishon Vijay Abraham I, linux-arm-kernel,
devicetree, linux-kernel, linux-sunxi
In-Reply-To: <20170405072631.ou4e5gafvagwpykq@lukather>
在 2017年04月05日 15:26, Maxime Ripard 写道:
> On Wed, Apr 05, 2017 at 03:17:19PM +0800, Icenowy Zheng wrote:
>>
>>
>> 在 2017年04月05日 15:15, Maxime Ripard 写道:
>>> On Wed, Apr 05, 2017 at 02:45:17AM +0800, Icenowy Zheng wrote:
>>>> As we added USB0 route auto switching support for A64, add related
>>>> device tree parts to the A64 DTSI file (EHCI0/OHCI0 controllers and the
>>>> pmu0 memory area for PHY).
>>>>
>>>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>>>> ---
>>>> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 24 ++++++++++++++++++++++++
>>>> 1 file changed, 24 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>>>> index 1c64ea2d23f9..a8916df99048 100644
>>>> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>>>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>>>> @@ -179,8 +179,10 @@
>>>> usbphy: phy@01c19400 {
>>>> compatible = "allwinner,sun50i-a64-usb-phy";
>>>> reg = <0x01c19400 0x14>,
>>>> + <0x01c1a800 0x4>,
>>>> <0x01c1b800 0x4>;
>>>> reg-names = "phy_ctrl",
>>>> + "pmu0",
>>>
>>> This breaks the older DTs, and that property isn't documented.
>>
>> It's already documented.
>>
>> In the H3 dual-route patchset I have already added this.
>>
>> (" * "pmu0" for H3, V3s and A64")
>
> This is not in linux-next then, sorry.
It's already in next-20160405.
>
>> P.S. to be compatible with older DTs, I think I should adjust
>> the phy driver, make it enable dual-route function only when
>> pmu0 is present.
>
> That, or if we're quick enough, we can still add it to 4.11. There's a
> bit of time left.
Thus the device tree binding patch and the DT part of this patchset
should be all pushed to 4.11 .
The device tree binding patch is commit ee73fd7dfc86 ("dt: bindings: add
pmu0 regs for USB PHYs on Allwinner H3/V3s/A64").
>
> Maxime
>
^ permalink raw reply
* Re: [PATCH 02/11] arm64: allwinner: a64: add NMI controller on A64
From: Maxime Ripard @ 2017-04-05 7:28 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Icenowy Zheng, Lee Jones, Rob Herring, Liam Girdwood, devicetree,
linux-sunxi, linux-kernel, linux-arm-kernel
In-Reply-To: <CAGb2v672Z2JedGF3n+8Hi78QG_hAxz0ZYXaCkw0GAkA3xEdKrA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
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On Wed, Apr 05, 2017 at 02:20:31PM +0800, Chen-Yu Tsai wrote:
> On Wed, Apr 5, 2017 at 2:11 PM, Maxime Ripard
> <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> > On Wed, Apr 05, 2017 at 11:51:45AM +0800, Chen-Yu Tsai wrote:
> >> On Wed, Apr 5, 2017 at 2:01 AM, Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org> wrote:
> >> > Allwinner A64 SoC features a NMI controller, which is usually connected
> >> > to the AXP PMIC.
> >> >
> >> > Add support for it.
> >> >
> >> > Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
> >>
> >> This might not be the best representation of the R_INTC block. Though
> >> we'd need to change it for all SoCs if we want to be accurate. For now,
> >
> > What do you think would be a good representation?
>
> My gut feeling is that this is the old INTC from sun4/5i.
Ah, that would make sense.
> It's supposed to be the interrupt controller for the embedded low
> power core. I've not done a thorough comparison though.
Do we have some documentation / code for this one?
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* Re: [PATCH 2/3] arm64: allwinner: a64: add USB0 OHCI/EHCI related devicetree parts
From: Maxime Ripard @ 2017-04-05 7:26 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Chen-Yu Tsai, Kishon Vijay Abraham I,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <7828ffa0-f570-9841-a9e6-fe175f8169ac-h8G6r0blFSE@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 1781 bytes --]
On Wed, Apr 05, 2017 at 03:17:19PM +0800, Icenowy Zheng wrote:
>
>
> 在 2017年04月05日 15:15, Maxime Ripard 写道:
> > On Wed, Apr 05, 2017 at 02:45:17AM +0800, Icenowy Zheng wrote:
> > > As we added USB0 route auto switching support for A64, add related
> > > device tree parts to the A64 DTSI file (EHCI0/OHCI0 controllers and the
> > > pmu0 memory area for PHY).
> > >
> > > Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
> > > ---
> > > arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 24 ++++++++++++++++++++++++
> > > 1 file changed, 24 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> > > index 1c64ea2d23f9..a8916df99048 100644
> > > --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> > > @@ -179,8 +179,10 @@
> > > usbphy: phy@01c19400 {
> > > compatible = "allwinner,sun50i-a64-usb-phy";
> > > reg = <0x01c19400 0x14>,
> > > + <0x01c1a800 0x4>,
> > > <0x01c1b800 0x4>;
> > > reg-names = "phy_ctrl",
> > > + "pmu0",
> >
> > This breaks the older DTs, and that property isn't documented.
>
> It's already documented.
>
> In the H3 dual-route patchset I have already added this.
>
> (" * "pmu0" for H3, V3s and A64")
This is not in linux-next then, sorry.
> P.S. to be compatible with older DTs, I think I should adjust
> the phy driver, make it enable dual-route function only when
> pmu0 is present.
That, or if we're quick enough, we can still add it to 4.11. There's a
bit of time left.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* Re: [PATCH 2/3] arm64: allwinner: a64: add USB0 OHCI/EHCI related devicetree parts
From: Icenowy Zheng @ 2017-04-05 7:17 UTC (permalink / raw)
To: Maxime Ripard
Cc: Chen-Yu Tsai, Kishon Vijay Abraham I,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <20170405071508.yaur35xuli4jgkfb@lukather>
在 2017年04月05日 15:15, Maxime Ripard 写道:
> On Wed, Apr 05, 2017 at 02:45:17AM +0800, Icenowy Zheng wrote:
>> As we added USB0 route auto switching support for A64, add related
>> device tree parts to the A64 DTSI file (EHCI0/OHCI0 controllers and the
>> pmu0 memory area for PHY).
>>
>> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
>> ---
>> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 24 ++++++++++++++++++++++++
>> 1 file changed, 24 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>> index 1c64ea2d23f9..a8916df99048 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>> @@ -179,8 +179,10 @@
>> usbphy: phy@01c19400 {
>> compatible = "allwinner,sun50i-a64-usb-phy";
>> reg = <0x01c19400 0x14>,
>> + <0x01c1a800 0x4>,
>> <0x01c1b800 0x4>;
>> reg-names = "phy_ctrl",
>> + "pmu0",
>
> This breaks the older DTs, and that property isn't documented.
It's already documented.
In the H3 dual-route patchset I have already added this.
(" * "pmu0" for H3, V3s and A64")
P.S. to be compatible with older DTs, I think I should adjust
the phy driver, make it enable dual-route function only when
pmu0 is present.
>
> Maxime
>
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^ permalink raw reply
* Re: [PATCH 2/3] arm64: allwinner: a64: add USB0 OHCI/EHCI related devicetree parts
From: Maxime Ripard @ 2017-04-05 7:15 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Chen-Yu Tsai, Kishon Vijay Abraham I, linux-arm-kernel,
devicetree, linux-kernel, linux-sunxi
In-Reply-To: <20170404184518.33610-2-icenowy@aosc.io>
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On Wed, Apr 05, 2017 at 02:45:17AM +0800, Icenowy Zheng wrote:
> As we added USB0 route auto switching support for A64, add related
> device tree parts to the A64 DTSI file (EHCI0/OHCI0 controllers and the
> pmu0 memory area for PHY).
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index 1c64ea2d23f9..a8916df99048 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -179,8 +179,10 @@
> usbphy: phy@01c19400 {
> compatible = "allwinner,sun50i-a64-usb-phy";
> reg = <0x01c19400 0x14>,
> + <0x01c1a800 0x4>,
> <0x01c1b800 0x4>;
> reg-names = "phy_ctrl",
> + "pmu0",
This breaks the older DTs, and that property isn't documented.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* Re: [PATCH 1/3] phy: sun4i-usb: enable PHY0 dual route switching for A64 USB PHY
From: Maxime Ripard @ 2017-04-05 7:03 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Chen-Yu Tsai, Kishon Vijay Abraham I,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <20170404184518.33610-1-icenowy-h8G6r0blFSE@public.gmane.org>
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On Wed, Apr 05, 2017 at 02:45:16AM +0800, Icenowy Zheng wrote:
> Allwinner A64 SoC features a switchable PHY0 like the one in H3, which
> can switch between a MUSB controller and a pair of OHCI/EHCI controller.
>
> Enable PHY0 route auto switching for A64.
>
> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* Re: cpu of_node links broken
From: Wesley Terpstra @ 2017-04-05 6:49 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1491374467.4166.81.camel-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org>
On Tue, Apr 4, 2017 at 11:41 PM, Benjamin Herrenschmidt
<benh-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org> wrote:
>> [ 0.010000] cpu cpu0: Error -2 creating of_node link
> Interesting. I've never seen that error, I wonder if that's because
> we fail to link the CPU to an OF node to begin with on our platforms.
You can find quite a few dmesg traces on google that include the
warning. It affects at least nios2, microblaze and riscv.
It's because the 'sd' pointer in the of_node's kobject is null, which
causes sysfs_do_create_link_sd to return -ENOENT. AFAICT, it's null
because the device tree nodes have not yet been linked into sysfs;
that is what of_core_init() does.
> Devices might try to create symlinks to device-tree nodes,
> thus all devices that have OF node linkages should be created
> after of_core_init() has been called.
Your proposed patch fixes the warning for me on riscv.
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^ permalink raw reply
* Re: cpu of_node links broken
From: Benjamin Herrenschmidt @ 2017-04-05 6:41 UTC (permalink / raw)
To: Wesley Terpstra, devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <CAMgXwThQk=3V1HQ8YpoY57mpY0SrdyfAwS5szpsqwkS-r=FPAw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Tue, 2017-04-04 at 23:12 -0700, Wesley Terpstra wrote:
> In commit 5590f3196b293574a12be58d06d5e1120d8856ec symlinks from
> devices to their OF node were added.
Yup. I did that ;)
> Unfortunately, the code looks for them in cpu_dev_init before they
> exist (of_core_init has not run).
> This results in:
> [ 0.010000] cpu cpu0: Error -2 creating of_node link
>
> I don't know if this code used to work and it got broken, but as of
> 4.6 it does not work and still does not work in 4.11. Moving
> of_core_init() before platform_bus_init() in driver_init()
> [drivers/base/init.c] fixes the problem for me.
>
> Is there any downside to reordering these function calls?
Interesting. I've never seen that error, I wonder if that's because
we fail to link the CPU to an OF node to begin with on our platforms.
I agree though. of_core_init() should probably be called before
we create any device that might have an OF node reference.
In fact we should probably be able to move it right before
platform_bus_init(). Something like this (untested):
[PATCH] drivers/base: Initialize OF sysfs core before creating devices
Devices might try to create symlinks to device-tree nodes,
thus all devices that have OF node linkages should be created
after of_core_init() has been called.
This especially includes cpu_dev_init().
Reported-by: Wesley Terpstra <wesley-SpMDHPYPyPbQT0dZR+AlfA@public.gmane.org>
Signed-off-when-somebody-tests-it-by: Benjamin Herrenschmidt <benh-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org>
---
diff --git a/drivers/base/init.c b/drivers/base/init.c
index 48c0e22..f65d686 100644
--- a/drivers/base/init.c
+++ b/drivers/base/init.c
@@ -28,6 +28,13 @@ void __init driver_init(void)
firmware_init();
hypervisor_init();
+ /*
+ * This relies on the firmware_kobj already existing
+ * and should be done before any device that might have
+ * an OF link is created
+ */
+ of_core_init();
+
/* These are also core pieces, but must come after the
* core core pieces.
*/
@@ -35,5 +42,4 @@ void __init driver_init(void)
cpu_dev_init();
memory_dev_init();
container_dev_init();
- of_core_init();
}
Cheers,
Ben.
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* Re: [PATCH 1/2] doc: Add bindings document for Xilinx LogiCore PR Decoupler
From: Michal Simek @ 2017-04-05 6:26 UTC (permalink / raw)
To: Moritz Fischer, Rob Herring
Cc: Alan Tull, Greg Kroah-Hartman, Linux Kernel Mailing List,
linux-fpga, Moritz Fischer, Michal Simek, Sören Brinkmann,
Devicetree List
In-Reply-To: <CAAtXAHe0qnu7Ub6sing4VUgFa-tkdvH767kNbZnu1S5THHS2oQ@mail.gmail.com>
On 5.4.2017 01:36, Moritz Fischer wrote:
> On Thu, Mar 30, 2017 at 05:44:29PM -0500, Rob Herring wrote:
>> On Fri, Mar 24, 2017 at 10:33:20AM -0500, Alan Tull wrote:
>>> From: Moritz Fischer <mdf@kernel.org>
>>
>> Please use "dt-bindings: fpga: ..." for the subject.
>>
>>
>>>
>>> This adds the binding documentation for the Xilinx LogiCORE PR
>>> Decoupler soft core.
>>>
>>> Signed-off-by: Moritz Fischer <mdf@kernel.org>
>>> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
>>> Acked-by: Alan Tull <atull@kernel.org>
>>
>> I'm confused why you are sending these instead of Moritz? If it goes
>> through you, then it should have your S-o-B too.
>
> Do you want me to resend this Alan (with Rob's suggestions)?
>>
>>> Cc: Sören Brinkmann <soren.brinkmann@xilinx.com>
>>> Cc: linux-kernel@vger.kernel.org
>>> Cc: devicetree@vger.kernel.org
>>> ---
>>> .../bindings/fpga/xilinx-pr-decoupler.txt | 35 ++++++++++++++++++++++
>>> 1 file changed, 35 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
>>> new file mode 100644
>>> index 000000000000..2c527ac30398
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
>>> @@ -0,0 +1,35 @@
>>> +Xilinx LogiCORE Partial Reconfig Decoupler Softcore
>>> +
>>> +The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more
>>> +decouplers / fpga bridges.
>>> +The controller can decouple/disable the bridges which prevents signal
>>> +changes from passing through the bridge. The controller can also
>>> +couple / enable the bridges which allows traffic to pass through the
>>> +bridge normally.
>>> +
>>> +The Driver supports only MMIO handling. A PR region can have multiple
>>> +PR Decouplers which can be handled independently or chained via decouple/
>>> +decouple_status signals.
>>> +
>>> +Required properties:
>>> +- compatible : Should contain "xlnx,pr-decoupler-1.00" or "xlnx,pr-decoupler"
>>
>> I'd drop xlnx,pr-decoupler, but in any case, it should not be OR rather
>> "followed by". Plus the example has both.
>
> Michal wanted to have both, so I put both. Personally I don't care. I
> think they have some downstream stuff that relied on it.
Agree with Rob with using "followed by" instead of or.
M
^ permalink raw reply
* Re: [PATCH] mmc: core: add mmc-card hardware reset enable support
From: Richard Leitner @ 2017-04-05 6:23 UTC (permalink / raw)
To: Jaehoon Chung, ulf.hansson, robh+dt, mark.rutland
Cc: shawn.lin, adrian.hunter, linus.walleij, linux-mmc, linux-kernel,
devicetree, dev
In-Reply-To: <ea610a5c-3857-14f8-3039-414bee724223@samsung.com>
On 04/05/2017 06:40 AM, Jaehoon Chung wrote:
> Hi,
>
> On 04/04/2017 11:16 PM, Richard Leitner wrote:
>> Some eMMCs disable their hardware reset line (RST_N) by default. To enable
>> it the host must set the corresponding bit in ECSD. An example for such
>> a device is the Micron MTFCxGACAANA-4M.
>>
>> This patch adds a new mmc-card devicetree property to let the host enable
>> this feature during card initialization.
>>
>> Signed-off-by: Richard Leitner <richard.leitner@skidata.com>
>> ---
>> Documentation/devicetree/bindings/mmc/mmc-card.txt | 3 +++
>> drivers/mmc/core/mmc.c | 21 +++++++++++++++++++++
>> 2 files changed, 24 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/mmc-card.txt b/Documentation/devicetree/bindings/mmc/mmc-card.txt
>> index a70fcd6..8590a40 100644
>> --- a/Documentation/devicetree/bindings/mmc/mmc-card.txt
>> +++ b/Documentation/devicetree/bindings/mmc/mmc-card.txt
>> @@ -12,6 +12,9 @@ Required properties:
>> Optional properties:
>> -broken-hpi : Use this to indicate that the mmc-card has a broken hpi
>> implementation, and that hpi should not be used
>> +-enable-hw-reset : some eMMC devices have disabled the hw reset functionality
>> + (RST_N_FUNCTION) by default. By adding this property the
>> + host will enable it during initialization.
>
> As i know, RST_N_FUNCTION is controlled bit[1:0]
> 0x0 : RST_n disabled (by default)
> 0x1 : permanently enabled
> 0x2 : permanently disabled
>
> I think that it needs to add the description about these..
Ok.
>>
>> Example:
>>
>> diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
>> index b502601..518d0e3 100644
>> --- a/drivers/mmc/core/mmc.c
>> +++ b/drivers/mmc/core/mmc.c
>> @@ -1520,9 +1520,16 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
>> int err;
>> u32 cid[4];
>> u32 rocr;
>> + struct device_node *np;
>> + bool enable_rst_n = false;
>>
>> WARN_ON(!host->claimed);
>>
>> + np = mmc_of_find_child_device(host, 0);
>> + if (np && of_device_is_compatible(np, "mmc-card"))
>> + enable_rst_n = of_property_read_bool(np, "enable-hw-reset");
>> + of_node_put(np);
>> +
>> /* Set correct bus mode for MMC before attempting init */
>> if (!mmc_host_is_spi(host))
>> mmc_set_bus_mode(host, MMC_BUSMODE_OPENDRAIN);
>> @@ -1810,6 +1817,20 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
>> }
>> }
>>
>> + /*
>> + * try to enable RST_N if requested
>> + * This is needed because some eMMC chips disable this function by
>> + * default.
>> + */
>> + if (enable_rst_n) {
>> + err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
>> + EXT_CSD_RST_N_FUNCTION, EXT_CSD_RST_N_ENABLED,
>> + card->ext_csd.generic_cmd6_time);
>> + if (err && err != -EBADMSG)
>> + pr_warn("%s: Enabling RST_N feature failed\n",
>> + mmc_hostname(card->host));
>> + }
>
> If enabled hw-reset, it doesn't need to re-enable this bit.
Ok. I can add a check to prevent setting it, if it is set already.
> i didn't check the mmc-util..
> If mmc-util provides the changing this, the using mmc-util is better than this.
mmc-utils is providing a enable/disable hwreset feature. But as this
setting is required for my hardware to allow rebooting it, I thought it
would be better if it's in the kernel. So I/the hw doesn't have to
depend on userspace tools.
Nonetheless you're the experts, therefore if you say it shouldn't be in
the kernel/dt I'd be fine with that too. ;-)
^ permalink raw reply
* Re: [PATCH v4 0/6] ARM: dts: sunxi: Add CAN node and can0_pins_a pinctrl settings
From: Maxime Ripard @ 2017-04-05 6:22 UTC (permalink / raw)
To: Patrick Menschel
Cc: robh+dt, mark.rutland, linux, wens, devicetree, linux-arm-kernel,
linux-kernel, linux-can
In-Reply-To: <1491330992-9876-1-git-send-email-menschel.p@posteo.de>
[-- Attachment #1: Type: text/plain, Size: 828 bytes --]
On Tue, Apr 04, 2017 at 08:36:26PM +0200, Patrick Menschel wrote:
> The Allwinner A10/A20 SoCs have an on-board CAN (Controller Area Network)
> controller. This patch adds the CAN core to the SoC's include files,
> sun4i-a10.dtsi and sun7i-a20.dtsi.
>
> On linux-can mailing list was a discussion about updating the device tree bindings
> https://lkml.org/lkml/2015/9/17/220
> but it did not progress past writing the documentation file.
> Documentation/devicetree/bindings/net/can/sun4i_can.txt
>
> The CAN controller can be enabled in a board specific dts file as
> described in the documentation file or by using a device tree overlay.
Applied 1 and 4. The others were already merged.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 801 bytes --]
^ permalink raw reply
* Re: [PATCH 02/11] arm64: allwinner: a64: add NMI controller on A64
From: Chen-Yu Tsai @ 2017-04-05 6:20 UTC (permalink / raw)
To: Maxime Ripard
Cc: Chen-Yu Tsai, Icenowy Zheng, Lee Jones, Rob Herring,
Liam Girdwood, devicetree, linux-sunxi, linux-kernel,
linux-arm-kernel
In-Reply-To: <20170405061137.n66ectbkl7a2fv5f@lukather>
On Wed, Apr 5, 2017 at 2:11 PM, Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> On Wed, Apr 05, 2017 at 11:51:45AM +0800, Chen-Yu Tsai wrote:
>> On Wed, Apr 5, 2017 at 2:01 AM, Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org> wrote:
>> > Allwinner A64 SoC features a NMI controller, which is usually connected
>> > to the AXP PMIC.
>> >
>> > Add support for it.
>> >
>> > Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
>>
>> This might not be the best representation of the R_INTC block. Though
>> we'd need to change it for all SoCs if we want to be accurate. For now,
>
> What do you think would be a good representation?
My gut feeling is that this is the old INTC from sun4/5i. It's supposed
to be the interrupt controller for the embedded low power core. I've not
done a thorough comparison though.
ChenYu
^ permalink raw reply
* RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
From: Andy Tang @ 2017-04-05 6:16 UTC (permalink / raw)
To: mturquette@baylibre.com, sboyd@codeaurora.org
Cc: robh+dt@kernel.org, mark.rutland@arm.com,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, Scott Wood
In-Reply-To: <1489977443-33582-1-git-send-email-andy.tang@nxp.com>
Hello Stephen and Michael,
Do you have any comments on this patch set which was acked by Rob?
Regards,
Andy
> -----Original Message-----
> From: Yuantian Tang [mailto:andy.tang@nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturquette@baylibre.com
> Cc: sboyd@codeaurora.org; robh+dt@kernel.org; mark.rutland@arm.com;
> linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott Wood
> <oss@buserror.net>; Andy Tang <andy.tang@nxp.com>
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>
> From: Scott Wood <oss@buserror.net>
>
> ls1012a has separate input root clocks for core PLLs versus the platform PLL,
> with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named
> "coreclk". If present, this clock will be used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> v2:
> -- change the author to Scott
> Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
> - clocks: If clock-frequency is not specified, sysclk may be provided
> as an input clock. Either clock-frequency or clocks must be
> provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present. Valid names are
> + "sysclk" and "coreclk".
>
> 2. Clock Provider
>
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> 2 hwaccel index (n in CLKCGnHWACSR)
> 3 fman 0 for fm1, 1 for fm2
> 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5 coreclk must be 0
>
> 3. Example
>
> --
> 2.1.0.27.g96db324
^ permalink raw reply
* Re: [linux-sunxi] Re: [PATCH 10/11] arm64: allwinner: a64: enable AXP803 regulators for Pine64
From: Icenowy Zheng @ 2017-04-05 6:15 UTC (permalink / raw)
To: Maxime Ripard
Cc: Rob Herring, linux-kernel, devicetree, Lee Jones, Liam Girdwood,
linux-arm-kernel, linux-sunxi, Chen-Yu Tsai
2017年4月5日 14:13于 Maxime Ripard <maxime.ripard@free-electrons.com>写道：
>
> On Wed, Apr 05, 2017 at 02:01:44AM +0800, Icenowy Zheng wrote:
> > Add support of AXP803 regulators in the Pine64 device tree, in order to
> > enable many future functionalities, e.g. Wi-Fi.
> >
> > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> > ---
> > .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 109 +++++++++++++++++++++
> > 1 file changed, 109 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
> > index 2132d8e6cb3d..7da074f95065 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
> > @@ -106,6 +106,115 @@
> > };
> > };
> >
> > +#include "axp803.dtsi"
> > +
> > +®_aldo1 {
> > + regulator-min-microvolt = <2800000>;
> > + regulator-max-microvolt = <2800000>;
> > + regulator-name = "vcc-csi";
> > +};
> > +
> > +®_aldo2 {
> > + regulator-always-on;
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc-pl";
> > +};
> > +
> > +®_aldo3 {
> > + regulator-always-on;
> > + regulator-min-microvolt = <2700000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc-pll-avcc";
> > +};
> > +
> > +®_dc1sw {
> > + regulator-name = "vcc-phy";
> > +};
> > +
> > +®_dcdc1 {
> > + regulator-always-on;
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc-3v3";
> > +};
> > +
> > +®_dcdc2 {
> > + regulator-always-on;
> > + regulator-min-microvolt = <1000000>;
> > + regulator-max-microvolt = <1300000>;
> > + regulator-name = "vdd-cpux";
> > +};
> > +
> > +/* DCDC3 is polyphased with DCDC2 */
> > +
> > +®_dcdc5 {
> > + regulator-always-on;
> > + regulator-min-microvolt = <1500000>;
> > + regulator-max-microvolt = <1500000>;
> > + regulator-name = "vcc-dram";
> > +};
> > +
> > +®_dcdc6 {
> > + regulator-always-on;
> > + regulator-min-microvolt = <1100000>;
> > + regulator-max-microvolt = <1100000>;
> > + regulator-name = "vdd-sys";
> > +};
> > +
> > +®_dldo1 {
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc-hdmi";
> > +};
> > +
> > +®_dldo2 {
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc-mipi";
> > +};
> > +
> > +®_dldo3 {
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "avdd-csi";
> > +};
> > +
> > +®_dldo4 {
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc-wifi";
> > +};
> > +
> > +®_eldo1 {
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + regulator-name = "cpvdd";
> > +};
> > +
> > +®_eldo3 {
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + regulator-name = "vdd-1v8-csi";
> > +};
> > +
> > +®_fldo1 {
> > + regulator-min-microvolt = <1200000>;
> > + regulator-max-microvolt = <1200000>;
> > + regulator-name = "vcc-1v2-hsic";
> > +};
> > +
> > +®_fldo2 {
> > + regulator-always-on;
> > + regulator-min-microvolt = <1100000>;
> > + regulator-max-microvolt = <1100000>;
> > + regulator-name = "vdd-cpus";
> > +};
>
> Why do you need to always power the AR100 on?
It's for CPUS power domain, not the AR100 processor.
Kill it will lead to instantly system hang.
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> For more options, visit https://groups.google.com/d/optout.
^ permalink raw reply
* Re: Re: [PATCH 10/11] arm64: allwinner: a64: enable AXP803 regulators for Pine64
From: Icenowy Zheng @ 2017-04-05 6:15 UTC (permalink / raw)
To: Maxime Ripard
Cc: Rob Herring, linux-kernel, devicetree-u79uwXL29TY76Z2rM5mHXA,
Lee Jones, Liam Girdwood,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Chen-Yu Tsai
2017年4月5日 14:13于 Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>写道：
>
> On Wed, Apr 05, 2017 at 02:01:44AM +0800, Icenowy Zheng wrote:
> > Add support of AXP803 regulators in the Pine64 device tree, in order to
> > enable many future functionalities, e.g. Wi-Fi.
> >
> > Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
> > ---
> > .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 109 +++++++++++++++++++++
> > 1 file changed, 109 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
> > index 2132d8e6cb3d..7da074f95065 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
> > @@ -106,6 +106,115 @@
> > };
> > };
> >
> > +#include "axp803.dtsi"
> > +
> > +®_aldo1 {
> > + regulator-min-microvolt = <2800000>;
> > + regulator-max-microvolt = <2800000>;
> > + regulator-name = "vcc-csi";
> > +};
> > +
> > +®_aldo2 {
> > + regulator-always-on;
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc-pl";
> > +};
> > +
> > +®_aldo3 {
> > + regulator-always-on;
> > + regulator-min-microvolt = <2700000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc-pll-avcc";
> > +};
> > +
> > +®_dc1sw {
> > + regulator-name = "vcc-phy";
> > +};
> > +
> > +®_dcdc1 {
> > + regulator-always-on;
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc-3v3";
> > +};
> > +
> > +®_dcdc2 {
> > + regulator-always-on;
> > + regulator-min-microvolt = <1000000>;
> > + regulator-max-microvolt = <1300000>;
> > + regulator-name = "vdd-cpux";
> > +};
> > +
> > +/* DCDC3 is polyphased with DCDC2 */
> > +
> > +®_dcdc5 {
> > + regulator-always-on;
> > + regulator-min-microvolt = <1500000>;
> > + regulator-max-microvolt = <1500000>;
> > + regulator-name = "vcc-dram";
> > +};
> > +
> > +®_dcdc6 {
> > + regulator-always-on;
> > + regulator-min-microvolt = <1100000>;
> > + regulator-max-microvolt = <1100000>;
> > + regulator-name = "vdd-sys";
> > +};
> > +
> > +®_dldo1 {
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc-hdmi";
> > +};
> > +
> > +®_dldo2 {
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc-mipi";
> > +};
> > +
> > +®_dldo3 {
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "avdd-csi";
> > +};
> > +
> > +®_dldo4 {
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc-wifi";
> > +};
> > +
> > +®_eldo1 {
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + regulator-name = "cpvdd";
> > +};
> > +
> > +®_eldo3 {
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + regulator-name = "vdd-1v8-csi";
> > +};
> > +
> > +®_fldo1 {
> > + regulator-min-microvolt = <1200000>;
> > + regulator-max-microvolt = <1200000>;
> > + regulator-name = "vcc-1v2-hsic";
> > +};
> > +
> > +®_fldo2 {
> > + regulator-always-on;
> > + regulator-min-microvolt = <1100000>;
> > + regulator-max-microvolt = <1100000>;
> > + regulator-name = "vdd-cpus";
> > +};
>
> Why do you need to always power the AR100 on?
It's for CPUS power domain, not the AR100 processor.
Kill it will lead to instantly system hang.
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
> For more options, visit https://groups.google.com/d/optout.
--
You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
For more options, visit https://groups.google.com/d/optout.
^ permalink raw reply
* Re: [PATCH 10/11] arm64: allwinner: a64: enable AXP803 regulators for Pine64
From: Maxime Ripard @ 2017-04-05 6:13 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Lee Jones, Rob Herring, Chen-Yu Tsai, Liam Girdwood,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20170404180145.12897-11-icenowy-h8G6r0blFSE@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 3286 bytes --]
On Wed, Apr 05, 2017 at 02:01:44AM +0800, Icenowy Zheng wrote:
> Add support of AXP803 regulators in the Pine64 device tree, in order to
> enable many future functionalities, e.g. Wi-Fi.
>
> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
> ---
> .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 109 +++++++++++++++++++++
> 1 file changed, 109 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
> index 2132d8e6cb3d..7da074f95065 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
> @@ -106,6 +106,115 @@
> };
> };
>
> +#include "axp803.dtsi"
> +
> +®_aldo1 {
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-name = "vcc-csi";
> +};
> +
> +®_aldo2 {
> + regulator-always-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc-pl";
> +};
> +
> +®_aldo3 {
> + regulator-always-on;
> + regulator-min-microvolt = <2700000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc-pll-avcc";
> +};
> +
> +®_dc1sw {
> + regulator-name = "vcc-phy";
> +};
> +
> +®_dcdc1 {
> + regulator-always-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc-3v3";
> +};
> +
> +®_dcdc2 {
> + regulator-always-on;
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-name = "vdd-cpux";
> +};
> +
> +/* DCDC3 is polyphased with DCDC2 */
> +
> +®_dcdc5 {
> + regulator-always-on;
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-name = "vcc-dram";
> +};
> +
> +®_dcdc6 {
> + regulator-always-on;
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-name = "vdd-sys";
> +};
> +
> +®_dldo1 {
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc-hdmi";
> +};
> +
> +®_dldo2 {
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc-mipi";
> +};
> +
> +®_dldo3 {
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "avdd-csi";
> +};
> +
> +®_dldo4 {
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc-wifi";
> +};
> +
> +®_eldo1 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-name = "cpvdd";
> +};
> +
> +®_eldo3 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-name = "vdd-1v8-csi";
> +};
> +
> +®_fldo1 {
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-name = "vcc-1v2-hsic";
> +};
> +
> +®_fldo2 {
> + regulator-always-on;
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-name = "vdd-cpus";
> +};
Why do you need to always power the AR100 on?
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* cpu of_node links broken
From: Wesley Terpstra @ 2017-04-05 6:12 UTC (permalink / raw)
To: Benjamin Herrenschmidt, devicetree-u79uwXL29TY76Z2rM5mHXA
In commit 5590f3196b293574a12be58d06d5e1120d8856ec symlinks from
devices to their OF node were added. Unfortunately, the code looks for
them in cpu_dev_init before they exist (of_core_init has not run).
This results in:
[ 0.010000] cpu cpu0: Error -2 creating of_node link
I don't know if this code used to work and it got broken, but as of
4.6 it does not work and still does not work in 4.11. Moving
of_core_init() before platform_bus_init() in driver_init()
[drivers/base/init.c] fixes the problem for me.
Is there any downside to reordering these function calls?
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^ permalink raw reply
* Re: [linux-sunxi] [PATCH 02/11] arm64: allwinner: a64: add NMI controller on A64
From: Maxime Ripard @ 2017-04-05 6:11 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Icenowy Zheng, Lee Jones, Rob Herring, Liam Girdwood, devicetree,
linux-sunxi, linux-kernel, linux-arm-kernel
In-Reply-To: <CAGb2v67BucT8=FTgem3AmSU9XJA7OHoTCq3t3wBzDWyuwzZqaA@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 642 bytes --]
On Wed, Apr 05, 2017 at 11:51:45AM +0800, Chen-Yu Tsai wrote:
> On Wed, Apr 5, 2017 at 2:01 AM, Icenowy Zheng <icenowy@aosc.io> wrote:
> > Allwinner A64 SoC features a NMI controller, which is usually connected
> > to the AXP PMIC.
> >
> > Add support for it.
> >
> > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>
> This might not be the best representation of the R_INTC block. Though
> we'd need to change it for all SoCs if we want to be accurate. For now,
What do you think would be a good representation?
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 801 bytes --]
^ permalink raw reply
* [PATCH 1/1] ARM: dts: armada-xp-linksys-mamba: use wan instead of internet for DSA port
From: Ralph Sennhauser @ 2017-04-05 5:28 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Ralph Sennhauser, Jason Cooper, Andrew Lunn, Gregory Clement,
Sebastian Hesselbarth, Rob Herring, Mark Rutland, Russell King,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
The LEDs for the "wan" port are already labeled "mamba:amber:wan" resp.
"mamba:white:wan". So besides being an outlier with regard to the rest
of the product line (see table below) changing the label fixes an
internal inconsistency as well.
This will be visible in user space. Given commit cb4f71c42988 ("ARM:
dts: armada-38x: change order of ethernet DT nodes on Armada 38x") it's
expected to happen anyway. Commit 499400c9ac20 ("ARM: dts:
armada-xp-linksys-mamba: Utilize new DSA binding") switches to the new
bindings, use this opportunity to do it now rather than later.
|-----------------------------------------------------------------|
| Labels used for the case and those used for the DSA ports |
|-----------------------------------------------------------------|
| case labels | armada-385-linksys-* | armada-xp-linksys-mamba |
|---------------|-----------------------|-------------------------|
| internet | wan | internet |
| 1 | lan1 | lan1 |
| 2 | lan2 | lan2 |
| 3 | lan3 | lan3 |
| 4 | lan4 | lan4 |
|-----------------------------------------------------------------|
Signed-off-by: Ralph Sennhauser <ralph.sennhauser-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
Hi everybody,
I underestimated the urge of people to make all the same before. While I do not
particularly like this sort of change I see it coming anyway. So this patch is
meant to make it a deliberate decision so it no longer is an item lurking in
the shadows. Whether this patch gets taken or rejected my goal is reached.
In hindsight wan would have been the better choice.
Ralph
arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
index 9efcf59..0143aed 100644
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -354,7 +354,7 @@
port@4 {
reg = <4>;
- label = "internet";
+ label = "wan";
};
port@5 {
@@ -452,7 +452,7 @@
port@4 {
reg = <4>;
- label = "internet";
+ label = "wan";
};
port@5 {
--
2.10.2
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^ permalink raw reply related
* Re: [linux-sunxi] Re: [PATCH v3 04/11] drm/sun4i: abstract the layer type
From: Icenowy Zheng @ 2017-04-05 5:23 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: devicetree, Jernej Skrabec, linux-kernel, dri-devel, linux-sunxi,
Rob Herring, Maxime Ripard, linux-clk, linux-arm-kernel
2017年4月5日 10:27于 Chen-Yu Tsai <wens@csie.org>写道：
>
> On Wed, Apr 5, 2017 at 3:53 AM, Icenowy Zheng <icenowy@aosc.io> wrote:
> >
> >
> > 在 2017年04月05日 03:28, Sean Paul 写道:
> >>
> >> On Thu, Mar 30, 2017 at 03:46:06AM +0800, Icenowy Zheng wrote:
> >>>
> >>> As we are going to add support for the Allwinner DE2 Mixer in sun4i-drm
> >>> driver, we will finally have two types of layer.
> >>>
> >>> Abstract the layer type to void * and a ops struct, which contains the
> >>> only function used by crtc -- get the drm_plane struct of the layer.
> >>>
> >>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> >>> ---
> >>> Refactored patch in v3.
> >>>
> >>> drivers/gpu/drm/sun4i/sun4i_crtc.c | 19 +++++++++++--------
> >>> drivers/gpu/drm/sun4i/sun4i_crtc.h | 3 ++-
> >>> drivers/gpu/drm/sun4i/sun4i_layer.c | 19 ++++++++++++++++++-
> >>> drivers/gpu/drm/sun4i/sun4i_layer.h | 2 +-
> >>> drivers/gpu/drm/sun4i/sunxi_layer.h | 17 +++++++++++++++++
> >>> 5 files changed, 49 insertions(+), 11 deletions(-)
> >>> create mode 100644 drivers/gpu/drm/sun4i/sunxi_layer.h
> >>>
> >>> diff --git a/drivers/gpu/drm/sun4i/sun4i_crtc.c
> >>> b/drivers/gpu/drm/sun4i/sun4i_crtc.c
> >>> index 3c876c3a356a..33854ee7f636 100644
> >>> --- a/drivers/gpu/drm/sun4i/sun4i_crtc.c
> >>> +++ b/drivers/gpu/drm/sun4i/sun4i_crtc.c
> >>> @@ -29,6 +29,7 @@
> >>> #include "sun4i_crtc.h"
> >>> #include "sun4i_drv.h"
> >>> #include "sun4i_layer.h"
> >>> +#include "sunxi_layer.h"
> >>> #include "sun4i_tcon.h"
> >>>
> >>> static void sun4i_crtc_atomic_begin(struct drm_crtc *crtc,
> >>> @@ -149,7 +150,7 @@ struct sun4i_crtc *sun4i_crtc_init(struct drm_device
> >>> *drm,
> >>> scrtc->tcon = tcon;
> >>>
> >>> /* Create our layers */
> >>> - scrtc->layers = sun4i_layers_init(drm, scrtc->backend);
> >>> + scrtc->layers = (void **)sun4i_layers_init(drm, scrtc);
> >>> if (IS_ERR(scrtc->layers)) {
> >>> dev_err(drm->dev, "Couldn't create the planes\n");
> >>> return NULL;
> >>> @@ -157,14 +158,15 @@ struct sun4i_crtc *sun4i_crtc_init(struct
> >>> drm_device *drm,
> >>>
> >>> /* find primary and cursor planes for drm_crtc_init_with_planes
> >>> */
> >>> for (i = 0; scrtc->layers[i]; i++) {
> >>> - struct sun4i_layer *layer = scrtc->layers[i];
> >>> + void *layer = scrtc->layers[i];
> >>> + struct drm_plane *plane =
> >>> scrtc->layer_ops->get_plane(layer);
> >>>
> >>> - switch (layer->plane.type) {
> >>> + switch (plane->type) {
> >>> case DRM_PLANE_TYPE_PRIMARY:
> >>> - primary = &layer->plane;
> >>> + primary = plane;
> >>> break;
> >>> case DRM_PLANE_TYPE_CURSOR:
> >>> - cursor = &layer->plane;
> >>> + cursor = plane;
> >>> break;
> >>> default:
> >>> break;
> >>> @@ -190,10 +192,11 @@ struct sun4i_crtc *sun4i_crtc_init(struct
> >>> drm_device *drm,
> >>> /* Set possible_crtcs to this crtc for overlay planes */
> >>> for (i = 0; scrtc->layers[i]; i++) {
> >>> uint32_t possible_crtcs =
> >>> BIT(drm_crtc_index(&scrtc->crtc));
> >>> - struct sun4i_layer *layer = scrtc->layers[i];
> >>> + void *layer = scrtc->layers[i];
> >>> + struct drm_plane *plane =
> >>> scrtc->layer_ops->get_plane(layer);
> >>>
> >>> - if (layer->plane.type == DRM_PLANE_TYPE_OVERLAY)
> >>> - layer->plane.possible_crtcs = possible_crtcs;
> >>> + if (plane->type == DRM_PLANE_TYPE_OVERLAY)
> >>> + plane->possible_crtcs = possible_crtcs;
> >>> }
> >>>
> >>> return scrtc;
> >>> diff --git a/drivers/gpu/drm/sun4i/sun4i_crtc.h
> >>> b/drivers/gpu/drm/sun4i/sun4i_crtc.h
> >>> index 230cb8f0d601..a4036ee44cf8 100644
> >>> --- a/drivers/gpu/drm/sun4i/sun4i_crtc.h
> >>> +++ b/drivers/gpu/drm/sun4i/sun4i_crtc.h
> >>> @@ -19,7 +19,8 @@ struct sun4i_crtc {
> >>>
> >>> struct sun4i_backend *backend;
> >>> struct sun4i_tcon *tcon;
> >>> - struct sun4i_layer **layers;
> >>> + void **layers;
> >>> + const struct sunxi_layer_ops *layer_ops;
> >>
> >>
> >> I think you should probably take a different approach to abstract the
> >> layer
> >> type. How about creating
> >>
> >> struct sunxi_layer {
> >> struct drm_plane plane;
> >> }
> >>
> >> base and then subclassing that for sun4i and sun8i? By doing this you can
> >> avoid
> >> the nasty casting and you can also get rid of the get_plane() hook and
> >> layer_ops.
> >
> >
> > For the situation that using ** things are easily to get weird.
>
> That code could be reworked, by initializing the layers directly within
> the crtc init code. If you look at rockchip's drm driver, you'll see
> they do this. There is a good reason to do it this way, as you need
> to first create the primary and cursor layers, pass them in when you
> create the crtc, then initialize any additional layers with the
> possible_crtcs bitmap.
But furthurly maybe more layers will be created for DE2 mixer, and may even depends on mixer type (On A83T/H3/A64/H5 mixer1 has fewer channel than mixer0).
>
> In our driver we are currently initializing all layers, then going
> back and filling in possible_crtcs for the extra layers.
>
> And as Maxime and I mentioned in the other thread, we don't really
> need to keep a reference to **layers.
>
> Regards
> ChenYu
>
> >
> >>
> >> Sean
> >>
> >>
> >>
> >>> };
> >>>
> >>> static inline struct sun4i_crtc *drm_crtc_to_sun4i_crtc(struct drm_crtc
> >>> *crtc)
> >>> diff --git a/drivers/gpu/drm/sun4i/sun4i_layer.c
> >>> b/drivers/gpu/drm/sun4i/sun4i_layer.c
> >>> index f26bde5b9117..bc4a70d6968b 100644
> >>> --- a/drivers/gpu/drm/sun4i/sun4i_layer.c
> >>> +++ b/drivers/gpu/drm/sun4i/sun4i_layer.c
> >>> @@ -16,7 +16,9 @@
> >>> #include <drm/drmP.h>
> >>>
> >>> #include "sun4i_backend.h"
> >>> +#include "sun4i_crtc.h"
> >>> #include "sun4i_layer.h"
> >>> +#include "sunxi_layer.h"
> >>>
> >>> struct sun4i_plane_desc {
> >>> enum drm_plane_type type;
> >>> @@ -100,6 +102,17 @@ static const struct sun4i_plane_desc
> >>> sun4i_backend_planes[] = {
> >>> },
> >>> };
> >>>
> >>> +static struct drm_plane *sun4i_layer_get_plane(void *layer)
> >>> +{
> >>> + struct sun4i_layer *sun4i_layer = layer;
> >>> +
> >>> + return &sun4i_layer->plane;
> >>> +}
> >>> +
> >>> +static const struct sunxi_layer_ops layer_ops = {
> >>> + .get_plane = sun4i_layer_get_plane,
> >>> +};
> >>> +
> >>> static struct sun4i_layer *sun4i_layer_init_one(struct drm_device *drm,
> >>> struct sun4i_backend
> >>> *backend,
> >>> const struct
> >>> sun4i_plane_desc *plane)
> >>> @@ -129,9 +142,10 @@ static struct sun4i_layer
> >>> *sun4i_layer_init_one(struct drm_device *drm,
> >>> }
> >>>
> >>> struct sun4i_layer **sun4i_layers_init(struct drm_device *drm,
> >>> - struct sun4i_backend *backend)
> >>> + struct sun4i_crtc *crtc)
> >>> {
> >>> struct sun4i_layer **layers;
> >>> + struct sun4i_backend *backend = crtc->backend;
> >>> int i;
> >>>
> >>> layers = devm_kcalloc(drm->dev, ARRAY_SIZE(sun4i_backend_planes)
> >>> + 1,
> >>> @@ -181,5 +195,8 @@ struct sun4i_layer **sun4i_layers_init(struct
> >>> drm_device *drm,
> >>> layers[i] = layer;
> >>> };
> >>>
> >>> + /* Assign layer ops to the CRTC */
> >>> + crtc->layer_ops = &layer_ops;
> >>> +
> >>> return layers;
> >>> }
> >>> diff --git a/drivers/gpu/drm/sun4i/sun4i_layer.h
> >>> b/drivers/gpu/drm/sun4i/sun4i_layer.h
> >>> index 4be1f0919df2..425eea7b9e3b 100644
> >>> --- a/drivers/gpu/drm/sun4i/sun4i_layer.h
> >>> +++ b/drivers/gpu/drm/sun4i/sun4i_layer.h
> >>> @@ -27,6 +27,6 @@ plane_to_sun4i_layer(struct drm_plane *plane)
> >>> }
> >>>
> >>> struct sun4i_layer **sun4i_layers_init(struct drm_device *drm,
> >>> - struct sun4i_backend *backend);
> >>> + struct sun4i_crtc *crtc);
> >>>
> >>> #endif /* _SUN4I_LAYER_H_ */
> >>> diff --git a/drivers/gpu/drm/sun4i/sunxi_layer.h
> >>> b/drivers/gpu/drm/sun4i/sunxi_layer.h
> >>> new file mode 100644
> >>> index 000000000000..d8838ec39299
> >>> --- /dev/null
> >>> +++ b/drivers/gpu/drm/sun4i/sunxi_layer.h
> >>> @@ -0,0 +1,17 @@
> >>> +/*
> >>> + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.xyz>
> >>> + *
> >>> + * This program is free software; you can redistribute it and/or
> >>> + * modify it under the terms of the GNU General Public License as
> >>> + * published by the Free Software Foundation; either version 2 of
> >>> + * the License, or (at your option) any later version.
> >>> + */
> >>> +
> >>> +#ifndef _SUNXI_LAYER_H_
> >>> +#define _SUNXI_LAYER_H_
> >>> +
> >>> +struct sunxi_layer_ops {
> >>> + struct drm_plane *(*get_plane)(void *layer);
> >>> +};
> >>> +
> >>> +#endif /* _SUNXI_LAYER_H_ */
> >>> --
> >>> 2.12.0
> >>>
> >>>
> >>> _______________________________________________
> >>> linux-arm-kernel mailing list
> >>> linux-arm-kernel@lists.infradead.org
> >>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> >>
> >>
> >
> > --
> > You received this message because you are subscribed to the Google Groups
> > "linux-sunxi" group.
> > To unsubscribe from this group and stop receiving emails from it, send an
> > email to linux-sunxi+unsubscribe@googlegroups.com.
> > For more options, visit https://groups.google.com/d/optout.
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^ permalink raw reply
* Re: Re: [PATCH v3 04/11] drm/sun4i: abstract the layer type
From: Icenowy Zheng @ 2017-04-05 5:23 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: linux-arm-kernel, Sean Paul, linux-sunxi, Rob Herring,
linux-kernel, devicetree, Jernej Skrabec, Maxime Ripard,
linux-clk, dri-devel
2017年4月5日 10:27于 Chen-Yu Tsai <wens@csie.org>写道：
>
> On Wed, Apr 5, 2017 at 3:53 AM, Icenowy Zheng <icenowy@aosc.io> wrote:
> >
> >
> > 在 2017年04月05日 03:28, Sean Paul 写道:
> >>
> >> On Thu, Mar 30, 2017 at 03:46:06AM +0800, Icenowy Zheng wrote:
> >>>
> >>> As we are going to add support for the Allwinner DE2 Mixer in sun4i-drm
> >>> driver, we will finally have two types of layer.
> >>>
> >>> Abstract the layer type to void * and a ops struct, which contains the
> >>> only function used by crtc -- get the drm_plane struct of the layer.
> >>>
> >>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> >>> ---
> >>> Refactored patch in v3.
> >>>
> >>> drivers/gpu/drm/sun4i/sun4i_crtc.c | 19 +++++++++++--------
> >>> drivers/gpu/drm/sun4i/sun4i_crtc.h | 3 ++-
> >>> drivers/gpu/drm/sun4i/sun4i_layer.c | 19 ++++++++++++++++++-
> >>> drivers/gpu/drm/sun4i/sun4i_layer.h | 2 +-
> >>> drivers/gpu/drm/sun4i/sunxi_layer.h | 17 +++++++++++++++++
> >>> 5 files changed, 49 insertions(+), 11 deletions(-)
> >>> create mode 100644 drivers/gpu/drm/sun4i/sunxi_layer.h
> >>>
> >>> diff --git a/drivers/gpu/drm/sun4i/sun4i_crtc.c
> >>> b/drivers/gpu/drm/sun4i/sun4i_crtc.c
> >>> index 3c876c3a356a..33854ee7f636 100644
> >>> --- a/drivers/gpu/drm/sun4i/sun4i_crtc.c
> >>> +++ b/drivers/gpu/drm/sun4i/sun4i_crtc.c
> >>> @@ -29,6 +29,7 @@
> >>> #include "sun4i_crtc.h"
> >>> #include "sun4i_drv.h"
> >>> #include "sun4i_layer.h"
> >>> +#include "sunxi_layer.h"
> >>> #include "sun4i_tcon.h"
> >>>
> >>> static void sun4i_crtc_atomic_begin(struct drm_crtc *crtc,
> >>> @@ -149,7 +150,7 @@ struct sun4i_crtc *sun4i_crtc_init(struct drm_device
> >>> *drm,
> >>> scrtc->tcon = tcon;
> >>>
> >>> /* Create our layers */
> >>> - scrtc->layers = sun4i_layers_init(drm, scrtc->backend);
> >>> + scrtc->layers = (void **)sun4i_layers_init(drm, scrtc);
> >>> if (IS_ERR(scrtc->layers)) {
> >>> dev_err(drm->dev, "Couldn't create the planes\n");
> >>> return NULL;
> >>> @@ -157,14 +158,15 @@ struct sun4i_crtc *sun4i_crtc_init(struct
> >>> drm_device *drm,
> >>>
> >>> /* find primary and cursor planes for drm_crtc_init_with_planes
> >>> */
> >>> for (i = 0; scrtc->layers[i]; i++) {
> >>> - struct sun4i_layer *layer = scrtc->layers[i];
> >>> + void *layer = scrtc->layers[i];
> >>> + struct drm_plane *plane =
> >>> scrtc->layer_ops->get_plane(layer);
> >>>
> >>> - switch (layer->plane.type) {
> >>> + switch (plane->type) {
> >>> case DRM_PLANE_TYPE_PRIMARY:
> >>> - primary = &layer->plane;
> >>> + primary = plane;
> >>> break;
> >>> case DRM_PLANE_TYPE_CURSOR:
> >>> - cursor = &layer->plane;
> >>> + cursor = plane;
> >>> break;
> >>> default:
> >>> break;
> >>> @@ -190,10 +192,11 @@ struct sun4i_crtc *sun4i_crtc_init(struct
> >>> drm_device *drm,
> >>> /* Set possible_crtcs to this crtc for overlay planes */
> >>> for (i = 0; scrtc->layers[i]; i++) {
> >>> uint32_t possible_crtcs =
> >>> BIT(drm_crtc_index(&scrtc->crtc));
> >>> - struct sun4i_layer *layer = scrtc->layers[i];
> >>> + void *layer = scrtc->layers[i];
> >>> + struct drm_plane *plane =
> >>> scrtc->layer_ops->get_plane(layer);
> >>>
> >>> - if (layer->plane.type == DRM_PLANE_TYPE_OVERLAY)
> >>> - layer->plane.possible_crtcs = possible_crtcs;
> >>> + if (plane->type == DRM_PLANE_TYPE_OVERLAY)
> >>> + plane->possible_crtcs = possible_crtcs;
> >>> }
> >>>
> >>> return scrtc;
> >>> diff --git a/drivers/gpu/drm/sun4i/sun4i_crtc.h
> >>> b/drivers/gpu/drm/sun4i/sun4i_crtc.h
> >>> index 230cb8f0d601..a4036ee44cf8 100644
> >>> --- a/drivers/gpu/drm/sun4i/sun4i_crtc.h
> >>> +++ b/drivers/gpu/drm/sun4i/sun4i_crtc.h
> >>> @@ -19,7 +19,8 @@ struct sun4i_crtc {
> >>>
> >>> struct sun4i_backend *backend;
> >>> struct sun4i_tcon *tcon;
> >>> - struct sun4i_layer **layers;
> >>> + void **layers;
> >>> + const struct sunxi_layer_ops *layer_ops;
> >>
> >>
> >> I think you should probably take a different approach to abstract the
> >> layer
> >> type. How about creating
> >>
> >> struct sunxi_layer {
> >> struct drm_plane plane;
> >> }
> >>
> >> base and then subclassing that for sun4i and sun8i? By doing this you can
> >> avoid
> >> the nasty casting and you can also get rid of the get_plane() hook and
> >> layer_ops.
> >
> >
> > For the situation that using ** things are easily to get weird.
>
> That code could be reworked, by initializing the layers directly within
> the crtc init code. If you look at rockchip's drm driver, you'll see
> they do this. There is a good reason to do it this way, as you need
> to first create the primary and cursor layers, pass them in when you
> create the crtc, then initialize any additional layers with the
> possible_crtcs bitmap.
But furthurly maybe more layers will be created for DE2 mixer, and may even depends on mixer type (On A83T/H3/A64/H5 mixer1 has fewer channel than mixer0).
>
> In our driver we are currently initializing all layers, then going
> back and filling in possible_crtcs for the extra layers.
>
> And as Maxime and I mentioned in the other thread, we don't really
> need to keep a reference to **layers.
>
> Regards
> ChenYu
>
> >
> >>
> >> Sean
> >>
> >>
> >>
> >>> };
> >>>
> >>> static inline struct sun4i_crtc *drm_crtc_to_sun4i_crtc(struct drm_crtc
> >>> *crtc)
> >>> diff --git a/drivers/gpu/drm/sun4i/sun4i_layer.c
> >>> b/drivers/gpu/drm/sun4i/sun4i_layer.c
> >>> index f26bde5b9117..bc4a70d6968b 100644
> >>> --- a/drivers/gpu/drm/sun4i/sun4i_layer.c
> >>> +++ b/drivers/gpu/drm/sun4i/sun4i_layer.c
> >>> @@ -16,7 +16,9 @@
> >>> #include <drm/drmP.h>
> >>>
> >>> #include "sun4i_backend.h"
> >>> +#include "sun4i_crtc.h"
> >>> #include "sun4i_layer.h"
> >>> +#include "sunxi_layer.h"
> >>>
> >>> struct sun4i_plane_desc {
> >>> enum drm_plane_type type;
> >>> @@ -100,6 +102,17 @@ static const struct sun4i_plane_desc
> >>> sun4i_backend_planes[] = {
> >>> },
> >>> };
> >>>
> >>> +static struct drm_plane *sun4i_layer_get_plane(void *layer)
> >>> +{
> >>> + struct sun4i_layer *sun4i_layer = layer;
> >>> +
> >>> + return &sun4i_layer->plane;
> >>> +}
> >>> +
> >>> +static const struct sunxi_layer_ops layer_ops = {
> >>> + .get_plane = sun4i_layer_get_plane,
> >>> +};
> >>> +
> >>> static struct sun4i_layer *sun4i_layer_init_one(struct drm_device *drm,
> >>> struct sun4i_backend
> >>> *backend,
> >>> const struct
> >>> sun4i_plane_desc *plane)
> >>> @@ -129,9 +142,10 @@ static struct sun4i_layer
> >>> *sun4i_layer_init_one(struct drm_device *drm,
> >>> }
> >>>
> >>> struct sun4i_layer **sun4i_layers_init(struct drm_device *drm,
> >>> - struct sun4i_backend *backend)
> >>> + struct sun4i_crtc *crtc)
> >>> {
> >>> struct sun4i_layer **layers;
> >>> + struct sun4i_backend *backend = crtc->backend;
> >>> int i;
> >>>
> >>> layers = devm_kcalloc(drm->dev, ARRAY_SIZE(sun4i_backend_planes)
> >>> + 1,
> >>> @@ -181,5 +195,8 @@ struct sun4i_layer **sun4i_layers_init(struct
> >>> drm_device *drm,
> >>> layers[i] = layer;
> >>> };
> >>>
> >>> + /* Assign layer ops to the CRTC */
> >>> + crtc->layer_ops = &layer_ops;
> >>> +
> >>> return layers;
> >>> }
> >>> diff --git a/drivers/gpu/drm/sun4i/sun4i_layer.h
> >>> b/drivers/gpu/drm/sun4i/sun4i_layer.h
> >>> index 4be1f0919df2..425eea7b9e3b 100644
> >>> --- a/drivers/gpu/drm/sun4i/sun4i_layer.h
> >>> +++ b/drivers/gpu/drm/sun4i/sun4i_layer.h
> >>> @@ -27,6 +27,6 @@ plane_to_sun4i_layer(struct drm_plane *plane)
> >>> }
> >>>
> >>> struct sun4i_layer **sun4i_layers_init(struct drm_device *drm,
> >>> - struct sun4i_backend *backend);
> >>> + struct sun4i_crtc *crtc);
> >>>
> >>> #endif /* _SUN4I_LAYER_H_ */
> >>> diff --git a/drivers/gpu/drm/sun4i/sunxi_layer.h
> >>> b/drivers/gpu/drm/sun4i/sunxi_layer.h
> >>> new file mode 100644
> >>> index 000000000000..d8838ec39299
> >>> --- /dev/null
> >>> +++ b/drivers/gpu/drm/sun4i/sunxi_layer.h
> >>> @@ -0,0 +1,17 @@
> >>> +/*
> >>> + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.xyz>
> >>> + *
> >>> + * This program is free software; you can redistribute it and/or
> >>> + * modify it under the terms of the GNU General Public License as
> >>> + * published by the Free Software Foundation; either version 2 of
> >>> + * the License, or (at your option) any later version.
> >>> + */
> >>> +
> >>> +#ifndef _SUNXI_LAYER_H_
> >>> +#define _SUNXI_LAYER_H_
> >>> +
> >>> +struct sunxi_layer_ops {
> >>> + struct drm_plane *(*get_plane)(void *layer);
> >>> +};
> >>> +
> >>> +#endif /* _SUNXI_LAYER_H_ */
> >>> --
> >>> 2.12.0
> >>>
> >>>
> >>> _______________________________________________
> >>> linux-arm-kernel mailing list
> >>> linux-arm-kernel@lists.infradead.org
> >>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> >>
> >>
> >
> > --
> > You received this message because you are subscribed to the Google Groups
> > "linux-sunxi" group.
> > To unsubscribe from this group and stop receiving emails from it, send an
> > email to linux-sunxi+unsubscribe@googlegroups.com.
> > For more options, visit https://groups.google.com/d/optout.
--
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^ permalink raw reply
* [PATCH 6/6] arm64: dts: msm8996: Add CPU clock controller node
From: Rajendra Nayak @ 2017-04-05 4:55 UTC (permalink / raw)
To: sboyd-sgV2jX0FEOL9JmXXK+q4OQ, mturquette-rdvid1DuHRBWk0Htik3J/w
Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rajendra Nayak
In-Reply-To: <1491368129-24721-1-git-send-email-rnayak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Add the DT node for Kryo CPU clock controller on msm8996
devices.
Signed-off-by: Rajendra Nayak <rnayak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index ed7223d..baae195 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -311,6 +311,12 @@
reg = <0x300000 0x90000>;
};
+ kryocc: clock-controller@6400000 {
+ compatible = "qcom,apcc-msm8996";
+ reg = <0x6400000 0x90000>;
+ #clock-cells = <1>;
+ };
+
blsp1_spi0: spi@07575000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x07575000 0x600>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
--
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^ permalink raw reply related
* [PATCH 5/6] clk: qcom: cpu-8996: Add support to switch below 600Mhz
From: Rajendra Nayak @ 2017-04-05 4:55 UTC (permalink / raw)
To: sboyd-sgV2jX0FEOL9JmXXK+q4OQ, mturquette-rdvid1DuHRBWk0Htik3J/w
Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rajendra Nayak
In-Reply-To: <1491368129-24721-1-git-send-email-rnayak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
The CPU clock controllers primary PLL operates on a single VCO range,
between 600Mhz and 3Ghz. However the CPUs do support OPPs with
frequencies between 300Mhz and 600Mhz. In order to support running the
CPUs at those frequencies we end up having to lock the PLL at twice the
rate and drive the CPU clk via the PLL/2 output and SMUX.
So for frequencies above 600Mhz we follow the following path
Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk
and for frequencies between 300Mhz and 600Mhz we follow
Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk
Signed-off-by: Rajendra Nayak <rnayak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
drivers/clk/qcom/clk-cpu-8996.c | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c
index 9bb25be..79db4e8 100644
--- a/drivers/clk/qcom/clk-cpu-8996.c
+++ b/drivers/clk/qcom/clk-cpu-8996.c
@@ -28,6 +28,7 @@
#define PLL_INDEX 1
#define ACD_INDEX 2
#define ALT_INDEX 3
+#define DIV_2_THRESHOLD 600000000
/* PLLs */
@@ -121,6 +122,7 @@ struct clk_cpu_8996_mux {
u32 width;
struct notifier_block nb;
struct clk_hw *pll;
+ struct clk_hw *pll_div_2;
struct clk_regmap clkr;
};
@@ -171,6 +173,13 @@ static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index)
if (!cpuclk->pll)
return -EINVAL;
+ if (cpuclk->pll_div_2 && req->rate < DIV_2_THRESHOLD) {
+ if (req->rate < (DIV_2_THRESHOLD / 2))
+ return -EINVAL;
+
+ parent = cpuclk->pll_div_2;
+ }
+
req->best_parent_rate = clk_hw_round_rate(parent, req->rate);
req->best_parent_hw = parent;
@@ -182,13 +191,19 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
{
int ret;
struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_nb(nb);
+ struct clk_notifier_data *cnd = data;
switch (event) {
case PRE_RATE_CHANGE:
ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, ALT_INDEX);
break;
case POST_RATE_CHANGE:
- ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, PLL_INDEX);
+ if (cnd->new_rate < DIV_2_THRESHOLD)
+ ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw,
+ DIV_2_INDEX);
+ else
+ ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw,
+ PLL_INDEX);
break;
default:
ret = 0;
@@ -241,6 +256,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
.shift = 0,
.width = 2,
.pll = &pwrcl_pll.clkr.hw,
+ .pll_div_2 = &pwrcl_smux.clkr.hw,
.nb.notifier_call = cpu_clk_notifier_cb,
.clkr.hw.init = &(struct clk_init_data) {
.name = "pwrcl_pmux",
@@ -261,6 +277,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
.shift = 0,
.width = 2,
.pll = &perfcl_pll.clkr.hw,
+ .pll_div_2 = &perfcl_smux.clkr.hw,
.nb.notifier_call = cpu_clk_notifier_cb,
.clkr.hw.init = &(struct clk_init_data) {
.name = "perfcl_pmux",
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
--
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^ permalink raw reply related
* [PATCH 4/6] clk: qcom: cpu-8996: Add support to switch to alternate PLL
From: Rajendra Nayak @ 2017-04-05 4:55 UTC (permalink / raw)
To: sboyd, mturquette; +Cc: linux-clk, linux-arm-msm, devicetree, Rajendra Nayak
In-Reply-To: <1491368129-24721-1-git-send-email-rnayak@codeaurora.org>
Each of the CPU clusters on msm8996 and powered via a primary
PLL and a secondary PLL. The primary PLL is what drivers the
CPU clk, except for times when we are reprogramming the PLL
itself, when we temporarily switch to an alternate PLL.
Use clock rate change notifiers to support this.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/clk-cpu-8996.c | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c
index bc60111..9bb25be 100644
--- a/drivers/clk/qcom/clk-cpu-8996.c
+++ b/drivers/clk/qcom/clk-cpu-8996.c
@@ -119,10 +119,14 @@ struct clk_cpu_8996_mux {
u32 reg;
u32 shift;
u32 width;
+ struct notifier_block nb;
struct clk_hw *pll;
struct clk_regmap clkr;
};
+#define to_clk_cpu_8996_mux_nb(_nb) \
+ container_of(_nb, struct clk_cpu_8996_mux, nb)
+
static inline
struct clk_cpu_8996_mux *to_clk_cpu_8996_mux_hw(struct clk_hw *hw)
{
@@ -173,6 +177,27 @@ static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index)
return 0;
}
+int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
+ void *data)
+{
+ int ret;
+ struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_nb(nb);
+
+ switch (event) {
+ case PRE_RATE_CHANGE:
+ ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, ALT_INDEX);
+ break;
+ case POST_RATE_CHANGE:
+ ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, PLL_INDEX);
+ break;
+ default:
+ ret = 0;
+ break;
+ }
+
+ return notifier_from_errno(ret);
+};
+
const struct clk_ops clk_cpu_8996_mux_ops = {
.set_parent = clk_cpu_8996_mux_set_parent,
.get_parent = clk_cpu_8996_mux_get_parent,
@@ -216,6 +241,7 @@ static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index)
.shift = 0,
.width = 2,
.pll = &pwrcl_pll.clkr.hw,
+ .nb.notifier_call = cpu_clk_notifier_cb,
.clkr.hw.init = &(struct clk_init_data) {
.name = "pwrcl_pmux",
.parent_names = (const char *[]){
@@ -235,6 +261,7 @@ static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index)
.shift = 0,
.width = 2,
.pll = &perfcl_pll.clkr.hw,
+ .nb.notifier_call = cpu_clk_notifier_cb,
.clkr.hw.init = &(struct clk_init_data) {
.name = "perfcl_pmux",
.parent_names = (const char *[]){
@@ -310,6 +337,14 @@ struct clk_hw_clks {
clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config);
clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config);
+ ret = clk_notifier_register(pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb);
+ if (ret)
+ return ret;
+
+ ret = clk_notifier_register(perfcl_pmux.clkr.hw.clk, &perfcl_pmux.nb);
+ if (ret)
+ return ret;
+
return ret;
}
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH 3/6] clk: qcom: Add CPU clock driver for msm8996
From: Rajendra Nayak @ 2017-04-05 4:55 UTC (permalink / raw)
To: sboyd, mturquette; +Cc: linux-clk, linux-arm-msm, devicetree, Rajendra Nayak
In-Reply-To: <1491368129-24721-1-git-send-email-rnayak@codeaurora.org>
Each of the CPU clusters (Power and Perf) on msm8996 are
clocked via 2 PLLs, a primary and alternate. There are also
2 Mux'es, a primary and secondary all connected together
as shown below
+-------+
XO | |
+------------------>0 |
| |
PLL/2 | SMUX +----+
+------->1 | |
| | | |
| +-------+ | +-------+
| +---->0 |
| | |
+---------------+ | +----------->1 | CPU clk
|Primary PLL +----+ PLL_EARLY | | +------>
| +------+-----------+ +------>2 PMUX |
+---------------+ | | | |
| +------+ | +-->3 |
+--^+ ACD +-----+ | +-------+
+---------------+ +------+ |
|Alt PLL | |
| +---------------------------+
+---------------+ PLL_EARLY
The primary PLL is what drives the CPU clk, except for times
when we are reprogramming the PLL itself (for rate changes) when
we temporarily switch to an alternate PLL. A subsequent patch adds
support to switch between primary and alternate PLL during rate
changes.
The primary PLL operates on a single VCO range, between 600Mhz
and 3Ghz. However the CPUs do support OPPs with frequencies
between 300Mhz and 600Mhz. In order to support running the CPUs
at those frequencies we end up having to lock the PLL at twice
the rate and drive the CPU clk via the PLL/2 output and SMUX.
So for frequencies above 600Mhz we follow the following path
Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk
and for frequencies between 300Mhz and 600Mhz we follow
Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk
Support for this is added in a subsequent patch as well.
ACD stands for Adaptive Clock Distribution and is used to
detect voltage droops. We do not add support for ACD as yet.
This can be added at a later point as needed.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
.../devicetree/bindings/clock/qcom,kryocc.txt | 17 +
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-cpu-8996.c | 388 +++++++++++++++++++++
4 files changed, 414 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,kryocc.txt
create mode 100644 drivers/clk/qcom/clk-cpu-8996.c
diff --git a/Documentation/devicetree/bindings/clock/qcom,kryocc.txt b/Documentation/devicetree/bindings/clock/qcom,kryocc.txt
new file mode 100644
index 0000000..c45de03
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,kryocc.txt
@@ -0,0 +1,17 @@
+Qualcomm CPUSS clock controller for Kryo CPUs
+----------------------------------------------------
+
+Required properties :
+- compatible : shall contain only one of the following:
+
+ "qcom,apcc-msm8996"
+
+- reg : shall contain base register location and length
+- #clock-cells : shall contain 1
+
+Example:
+ kryocc: clock-controller@6400000 {
+ compatible = "qcom,apcc-msm8996";
+ reg = <0x6400000 0x90000>;
+ #clock-cells = <1>;
+ };
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 5fb8d74..94d4a8f 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -187,3 +187,11 @@ config MSM_MMCC_8996
Support for the multimedia clock controller on msm8996 devices.
Say Y if you want to support multimedia devices such as display,
graphics, video encode/decode, camera, etc.
+
+config MSM_APCC_8996
+ tristate "MSM8996 CPU Clock Controller"
+ depends on COMMON_CLK_QCOM
+ help
+ Support for the CPU clock controller on msm8996 devices.
+ Say Y if you want to support CPU clock scaling using CPUfreq
+ drivers for dyanmic power management.
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 1c3e222..bc452a6 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -30,5 +30,6 @@ obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
+obj-$(CONFIG_MSM_APCC_8996) += clk-cpu-8996.o
obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c
new file mode 100644
index 0000000..bc60111
--- /dev/null
+++ b/drivers/clk/qcom/clk-cpu-8996.c
@@ -0,0 +1,388 @@
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include "clk-alpha-pll.h"
+
+#define VCO(a, b, c) { \
+ .val = a,\
+ .min_freq = b,\
+ .max_freq = c,\
+}
+
+#define DIV_2_INDEX 0
+#define PLL_INDEX 1
+#define ACD_INDEX 2
+#define ALT_INDEX 3
+
+/* PLLs */
+
+static const struct alpha_pll_config hfpll_config = {
+ .l = 60,
+ .config_ctl_val = 0x200d4828,
+ .config_ctl_hi_val = 0x006,
+ .pre_div_mask = BIT(12),
+ .post_div_mask = 0x3 << 8,
+ .main_output_mask = BIT(0),
+ .early_output_mask = BIT(3),
+};
+
+static struct clk_alpha_pll perfcl_pll = {
+ .offset = 0x80000,
+ .min_rate = 600000000,
+ .max_rate = 3000000000,
+ .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_16BIT_ALPHA
+ | SUPPORTS_FSM_MODE,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "perfcl_pll",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_hwfsm_ops,
+ },
+};
+
+static struct clk_alpha_pll pwrcl_pll = {
+ .offset = 0x0,
+ .min_rate = 600000000,
+ .max_rate = 3000000000,
+ .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_16BIT_ALPHA
+ | SUPPORTS_FSM_MODE,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pwrcl_pll",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_hwfsm_ops,
+ },
+};
+
+static const struct pll_vco alt_pll_vco_modes[] = {
+ VCO(3, 250000000, 500000000),
+ VCO(2, 500000000, 750000000),
+ VCO(1, 750000000, 1000000000),
+ VCO(0, 1000000000, 2150400000),
+};
+
+static const struct alpha_pll_config altpll_config = {
+ .l = 16,
+ .vco_val = 0x3 << 20,
+ .vco_mask = 0x3 << 20,
+ .config_ctl_val = 0x4001051b,
+ .post_div_mask = 0x3 << 8,
+ .post_div_val = 0x1,
+ .main_output_mask = BIT(0),
+ .early_output_mask = BIT(3),
+};
+
+static struct clk_alpha_pll perfcl_alt_pll = {
+ .offset = 0x80100,
+ .vco_table = alt_pll_vco_modes,
+ .num_vco = ARRAY_SIZE(alt_pll_vco_modes),
+ .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "perfcl_alt_pll",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_hwfsm_ops,
+ },
+};
+
+static struct clk_alpha_pll pwrcl_alt_pll = {
+ .offset = 0x100,
+ .vco_table = alt_pll_vco_modes,
+ .num_vco = ARRAY_SIZE(alt_pll_vco_modes),
+ .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "pwrcl_alt_pll",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_hwfsm_ops,
+ },
+};
+
+/* Mux'es */
+
+struct clk_cpu_8996_mux {
+ u32 reg;
+ u32 shift;
+ u32 width;
+ struct clk_hw *pll;
+ struct clk_regmap clkr;
+};
+
+static inline
+struct clk_cpu_8996_mux *to_clk_cpu_8996_mux_hw(struct clk_hw *hw)
+{
+ return container_of(to_clk_regmap(hw), struct clk_cpu_8996_mux, clkr);
+}
+
+static u8 clk_cpu_8996_mux_get_parent(struct clk_hw *hw)
+{
+ unsigned int val;
+ struct clk_regmap *clkr = to_clk_regmap(hw);
+ struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
+ unsigned int mask = GENMASK(cpuclk->width - 1, 0);
+
+ regmap_read(clkr->regmap, cpuclk->reg, &val);
+
+ val >>= cpuclk->shift;
+ val &= mask;
+
+ return val;
+}
+
+static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ unsigned int val;
+ struct clk_regmap *clkr = to_clk_regmap(hw);
+ struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
+ unsigned int mask = GENMASK(cpuclk->width + cpuclk->shift - 1,
+ cpuclk->shift);
+
+ val = index;
+ val = cpuclk->shift;
+
+ return regmap_update_bits(clkr->regmap, cpuclk->reg, mask, val);
+}
+
+static int
+clk_cpu_8996_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
+{
+ struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
+ struct clk_hw *parent = cpuclk->pll;
+
+ if (!cpuclk->pll)
+ return -EINVAL;
+
+ req->best_parent_rate = clk_hw_round_rate(parent, req->rate);
+ req->best_parent_hw = parent;
+
+ return 0;
+}
+
+const struct clk_ops clk_cpu_8996_mux_ops = {
+ .set_parent = clk_cpu_8996_mux_set_parent,
+ .get_parent = clk_cpu_8996_mux_get_parent,
+ .determine_rate = clk_cpu_8996_mux_determine_rate,
+};
+
+static struct clk_cpu_8996_mux pwrcl_smux = {
+ .reg = 0x40,
+ .shift = 2,
+ .width = 2,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "pwrcl_smux",
+ .parent_names = (const char *[]){
+ "xo",
+ "pwrcl_pll_main",
+ },
+ .num_parents = 2,
+ .ops = &clk_cpu_8996_mux_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_cpu_8996_mux perfcl_smux = {
+ .reg = 0x80040,
+ .shift = 2,
+ .width = 2,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "perfcl_smux",
+ .parent_names = (const char *[]){
+ "xo",
+ "perfcl_pll_main",
+ },
+ .num_parents = 2,
+ .ops = &clk_cpu_8996_mux_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_cpu_8996_mux pwrcl_pmux = {
+ .reg = 0x40,
+ .shift = 0,
+ .width = 2,
+ .pll = &pwrcl_pll.clkr.hw,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "pwrcl_pmux",
+ .parent_names = (const char *[]){
+ "pwrcl_smux",
+ "pwrcl_pll",
+ "pwrcl_pll_acd",
+ "pwrcl_alt_pll",
+ },
+ .num_parents = 4,
+ .ops = &clk_cpu_8996_mux_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_cpu_8996_mux perfcl_pmux = {
+ .reg = 0x80040,
+ .shift = 0,
+ .width = 2,
+ .pll = &perfcl_pll.clkr.hw,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "perfcl_pmux",
+ .parent_names = (const char *[]){
+ "perfcl_smux",
+ "perfcl_pll",
+ "pwrcl_pll_acd",
+ "perfcl_alt_pll",
+ },
+ .num_parents = 4,
+ .ops = &clk_cpu_8996_mux_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct regmap_config cpu_msm8996_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x80210,
+ .fast_io = true,
+ .val_format_endian = REGMAP_ENDIAN_LITTLE,
+};
+
+static const struct of_device_id match_table[] = {
+ { .compatible = "qcom,apcc-msm8996" },
+ {}
+};
+
+struct clk_regmap *clks[] = {
+ /* PLLs */
+ &perfcl_pll.clkr,
+ &pwrcl_pll.clkr,
+ &perfcl_alt_pll.clkr,
+ &pwrcl_alt_pll.clkr,
+ /* MUXs */
+ &perfcl_smux.clkr,
+ &pwrcl_smux.clkr,
+ &perfcl_pmux.clkr,
+ &pwrcl_pmux.clkr,
+};
+
+struct clk_hw_clks {
+ unsigned int num;
+ struct clk_hw *hws[];
+};
+
+static int
+qcom_cpu_clk_msm8996_register_clks(struct device *dev, struct clk_hw_clks *hws,
+ struct regmap *regmap)
+{
+ int i, ret;
+
+ hws->hws[0] = clk_hw_register_fixed_factor(dev, "perfcl_pll_main",
+ "perfcl_pll",
+ CLK_SET_RATE_PARENT, 1, 2);
+ perfcl_smux.pll = hws->hws[0];
+
+ hws->hws[1] = clk_hw_register_fixed_factor(dev, "pwrcl_pll_main",
+ "pwrcl_pll",
+ CLK_SET_RATE_PARENT, 1, 2);
+ pwrcl_smux.pll = hws->hws[1];
+
+ hws->num = 2;
+
+ for (i = 0; i < ARRAY_SIZE(clks); i++) {
+ ret = devm_clk_register_regmap(dev, clks[i]);
+ if (ret)
+ return ret;
+ }
+
+ clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config);
+ clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config);
+ clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config);
+ clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config);
+
+ return ret;
+}
+
+static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev)
+{
+ int ret;
+ void __iomem *base;
+ struct resource *res;
+ struct regmap *regmap_cpu;
+ struct clk_hw_clks *hws;
+ struct clk_hw_onecell_data *data;
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->of_node;
+
+ data = devm_kzalloc(dev, sizeof(*data) + 2 * sizeof(struct clk_hw *),
+ GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ hws = devm_kzalloc(dev, sizeof(*hws) + 2 * sizeof(struct clk_hw *),
+ GFP_KERNEL);
+ if (!hws)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ regmap_cpu = devm_regmap_init_mmio(dev, base,
+ &cpu_msm8996_regmap_config);
+ if (IS_ERR(regmap_cpu))
+ return PTR_ERR(regmap_cpu);
+
+ ret = qcom_cpu_clk_msm8996_register_clks(dev, hws, regmap_cpu);
+ if (ret)
+ return ret;
+
+ data->hws[0] = &pwrcl_pmux.clkr.hw;
+ data->hws[1] = &perfcl_pmux.clkr.hw;
+
+ data->num = 2;
+
+ platform_set_drvdata(pdev, hws);
+
+ return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, data);
+}
+
+static int qcom_cpu_clk_msm8996_driver_remove(struct platform_device *pdev)
+{
+ int i;
+ struct device *dev = &pdev->dev;
+ struct clk_hw_clks *hws = platform_get_drvdata(pdev);
+
+ for (i = 0; i < hws->num; i++)
+ clk_hw_unregister_fixed_rate(hws->hws[i]);
+
+ of_clk_del_provider(dev->of_node);
+
+ return 0;
+}
+
+static struct platform_driver qcom_cpu_clk_msm8996_driver = {
+ .probe = qcom_cpu_clk_msm8996_driver_probe,
+ .remove = qcom_cpu_clk_msm8996_driver_remove,
+ .driver = {
+ .name = "qcom-apcc-msm8996",
+ .of_match_table = match_table,
+ },
+};
+
+module_platform_driver(qcom_cpu_clk_msm8996_driver);
+
+MODULE_ALIAS("platform:apcc-msm8996");
+MODULE_DESCRIPTION("QCOM MSM8996 CPU clock Driver");
+MODULE_LICENSE("GPL v2");
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
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