* [PATCH 01/12] remoteproc: qcom: Add PRNG proxy clock
From: Gokul Sriram Palanisamy @ 2019-07-11 15:40 UTC (permalink / raw)
To: agross, david.brown, robh+dt, mark.rutland, mturquette, sboyd,
jassisinghbrar, ohad, bjorn.andersson, linux-arm-msm, devicetree,
linux-kernel, linux-clk, linux-remoteproc, sricharan, gokulsri
In-Reply-To: <1562859668-14209-1-git-send-email-gokulsri@codeaurora.org>
PRNG clock is needed by the secure PIL, support for the same
is added in subsequent patches.
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_wcss.c | 63 +++++++++++++++++++++++++++----------
1 file changed, 46 insertions(+), 17 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c
index 0821c94..dc2bae4 100644
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -88,18 +88,6 @@ enum {
WCSS_QCS404,
};
-struct wcss_data {
- const char *firmware_name;
- int crash_reason_smem;
- u8 version;
- bool aon_reset_required;
- const char *ssr_name;
- const char *sysmon_name;
- int ssctl_id;
- const struct rproc_ops *ops;
- bool requires_force_stop;
-};
-
struct q6v5_wcss {
struct device *dev;
@@ -124,6 +112,7 @@ struct q6v5_wcss {
struct clk *qdsp6ss_xo_cbcr;
struct clk *qdsp6ss_core_gfmux;
struct clk *wcss_bcr_cbcr;
+ struct clk *prng_clk;
struct regulator *cx_supply;
struct qcom_rproc_glink glink_subdev;
@@ -146,6 +135,20 @@ struct q6v5_wcss {
bool requires_force_stop;
};
+struct wcss_data {
+ int (*init_clock)(struct q6v5_wcss *wcss);
+ int (*init_regulator)(struct q6v5_wcss *wcss);
+ const char *firmware_name;
+ int crash_reason_smem;
+ u8 version;
+ bool aon_reset_required;
+ const char *ssr_name;
+ const char *sysmon_name;
+ int ssctl_id;
+ const struct rproc_ops *ops;
+ bool requires_force_stop;
+};
+
static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
{
int ret;
@@ -235,6 +238,12 @@ static int q6v5_wcss_start(struct rproc *rproc)
struct q6v5_wcss *wcss = rproc->priv;
int ret;
+ ret = clk_prepare_enable(wcss->prng_clk);
+ if (ret) {
+ dev_err(wcss->dev, "prng clock enable failed\n");
+ return ret;
+ }
+
qcom_q6v5_prepare(&wcss->q6v5);
/* Release Q6 and WCSS reset */
@@ -703,6 +712,7 @@ static int q6v5_wcss_stop(struct rproc *rproc)
return ret;
}
+ clk_disable_unprepare(wcss->prng_clk);
qcom_q6v5_unprepare(&wcss->q6v5);
return 0;
@@ -858,7 +868,21 @@ static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss)
return 0;
}
-static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss)
+static int ipq8074_init_clock(struct q6v5_wcss *wcss)
+{
+ int ret;
+
+ wcss->prng_clk = devm_clk_get(wcss->dev, "prng");
+ if (IS_ERR(wcss->prng_clk)) {
+ ret = PTR_ERR(wcss->prng_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(wcss->dev, "Failed to get prng clock\n");
+ return ret;
+ }
+ return 0;
+}
+
+static int qcs404_init_clock(struct q6v5_wcss *wcss)
{
int ret;
@@ -973,7 +997,7 @@ static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss)
return 0;
}
-static int q6v5_wcss_init_regulator(struct q6v5_wcss *wcss)
+static int qcs404_init_regulator(struct q6v5_wcss *wcss)
{
wcss->cx_supply = devm_regulator_get(wcss->dev, "cx");
if (IS_ERR(wcss->cx_supply))
@@ -1017,12 +1041,14 @@ static int q6v5_wcss_probe(struct platform_device *pdev)
if (ret)
goto free_rproc;
- if (wcss->version == WCSS_QCS404) {
- ret = q6v5_wcss_init_clock(wcss);
+ if (desc->init_clock) {
+ ret = desc->init_clock(wcss);
if (ret)
goto free_rproc;
+ }
- ret = q6v5_wcss_init_regulator(wcss);
+ if (desc->init_regulator) {
+ ret = desc->init_regulator(wcss);
if (ret)
goto free_rproc;
}
@@ -1067,6 +1093,7 @@ static int q6v5_wcss_remove(struct platform_device *pdev)
}
static const struct wcss_data wcss_ipq8074_res_init = {
+ .init_clock = ipq8074_init_clock,
.firmware_name = "IPQ8074/q6_fw.mdt",
.crash_reason_smem = 421,
.aon_reset_required = true,
@@ -1075,6 +1102,8 @@ static int q6v5_wcss_remove(struct platform_device *pdev)
};
static const struct wcss_data wcss_qcs404_res_init = {
+ .init_clock = qcs404_init_clock,
+ .init_regulator = qcs404_init_regulator,
.crash_reason_smem = 421,
.firmware_name = "wcnss.mdt",
.version = WCSS_QCS404,
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH 00/12] remoteproc: qcom: q6v5-wcss: Add support for secure pil
From: Gokul Sriram Palanisamy @ 2019-07-11 15:40 UTC (permalink / raw)
To: agross, david.brown, robh+dt, mark.rutland, mturquette, sboyd,
jassisinghbrar, ohad, bjorn.andersson, linux-arm-msm, devicetree,
linux-kernel, linux-clk, linux-remoteproc, sricharan, gokulsri
IPQ8074 needs support for secure pil as well.
Also, currently only unified firmware is supported.
IPQ8074 supports split firmware for q6 and m3, so
adding support for that.
Gokul Sriram Palanisamy (12):
remoteproc: qcom: Add PRNG proxy clock
remoteproc: qcom: Add secure PIL support
remoteproc: qcom: Add support for split q6 + m3 wlan firmware
remoteproc: qcom: Add ssr subdevice identifier
remoteproc: qcom: Update regmap offsets for halt register
dt-bindings: clock: qcom: Add reset for WCSSAON
clk: qcom: Add WCSSAON reset
dt-bindings: mailbox: qom: Add ipq8074 APPS compatible
mailbox: qcom: Add support for IPQ8074 APCS
dt-bindings: firmware: qcom: Add compatible for IPQ8074 SoC
arm64: dts: Add support for scm on IPQ8074 SoCs
arm64: dts: qcom: Enable Q6v5 WCSS for ipq8074 SoC
.../devicetree/bindings/firmware/qcom,scm.txt | 1 +
.../bindings/mailbox/qcom,apcs-kpss-global.txt | 1 +
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 131 +++++++++++++++++
drivers/clk/qcom/gcc-ipq8074.c | 1 +
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 1 +
drivers/remoteproc/qcom_q6v5_wcss.c | 158 +++++++++++++++++----
include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 +
7 files changed, 264 insertions(+), 30 deletions(-)
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply
* Re: [PATCH v3 01/14] clk: qcom: gcc: limit GPLL0_AO_OUT operating frequency
From: Bjorn Andersson @ 2019-07-11 15:30 UTC (permalink / raw)
To: Jorge Ramirez-Ortiz
Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
linux-clk, linux-arm-msm, khasim.mohammed
In-Reply-To: <20190625164733.11091-2-jorge.ramirez-ortiz@linaro.org>
On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> Limit the GPLL0_AO_OUT_MAIN operating frequency as per its hardware
> specifications.
>
> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
> drivers/clk/qcom/clk-alpha-pll.c | 8 ++++++++
> drivers/clk/qcom/clk-alpha-pll.h | 1 +
> drivers/clk/qcom/gcc-qcs404.c | 2 +-
> 3 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index 0ced4a5a9a17..ef51f302bdf0 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -730,6 +730,14 @@ static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
> return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
> }
>
> +const struct clk_ops clk_alpha_pll_fixed_ops = {
> + .enable = clk_alpha_pll_enable,
> + .disable = clk_alpha_pll_disable,
> + .is_enabled = clk_alpha_pll_is_enabled,
> + .recalc_rate = clk_alpha_pll_recalc_rate,
> +};
> +EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops);
> +
> const struct clk_ops clk_alpha_pll_ops = {
> .enable = clk_alpha_pll_enable,
> .disable = clk_alpha_pll_disable,
> diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
> index 66755f0f84fc..6b4eb74706b4 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.h
> +++ b/drivers/clk/qcom/clk-alpha-pll.h
> @@ -104,6 +104,7 @@ struct alpha_pll_config {
> };
>
> extern const struct clk_ops clk_alpha_pll_ops;
> +extern const struct clk_ops clk_alpha_pll_fixed_ops;
> extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
> extern const struct clk_ops clk_alpha_pll_postdiv_ops;
> extern const struct clk_ops clk_alpha_pll_huayra_ops;
> diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
> index 29cf464dd2c8..18c6563889f3 100644
> --- a/drivers/clk/qcom/gcc-qcs404.c
> +++ b/drivers/clk/qcom/gcc-qcs404.c
> @@ -330,7 +330,7 @@ static struct clk_alpha_pll gpll0_ao_out_main = {
> .parent_names = (const char *[]){ "cxo" },
> .num_parents = 1,
> .flags = CLK_IS_CRITICAL,
> - .ops = &clk_alpha_pll_ops,
> + .ops = &clk_alpha_pll_fixed_ops,
> },
> },
> };
> --
> 2.21.0
>
^ permalink raw reply
* Re: [PATCH v3 13/14] arm64: dts: qcom: qcs404: Add DVFS support
From: Bjorn Andersson @ 2019-07-11 15:29 UTC (permalink / raw)
To: Jorge Ramirez-Ortiz
Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
linux-clk, linux-arm-msm, khasim.mohammed
In-Reply-To: <20190625164733.11091-14-jorge.ramirez-ortiz@linaro.org>
On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> Support dynamic voltage and frequency scaling on qcs404.
>
> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
I agree with Niklas on the possibility of squashing this with the opp
table. But unless you respin this
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/qcs404.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> index 9569686dbc41..4b4ce0b5df76 100644
> --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> @@ -34,6 +34,9 @@
> enable-method = "psci";
> cpu-idle-states = <&CPU_SLEEP_0>;
> next-level-cache = <&L2_0>;
> + clocks = <&apcs_glb>;
> + operating-points-v2 = <&cpu_opp_table>;
> + cpu-supply = <&pms405_s3>;
> };
>
> CPU1: cpu@101 {
> @@ -43,6 +46,9 @@
> enable-method = "psci";
> cpu-idle-states = <&CPU_SLEEP_0>;
> next-level-cache = <&L2_0>;
> + clocks = <&apcs_glb>;
> + operating-points-v2 = <&cpu_opp_table>;
> + cpu-supply = <&pms405_s3>;
> };
>
> CPU2: cpu@102 {
> @@ -52,6 +58,9 @@
> enable-method = "psci";
> cpu-idle-states = <&CPU_SLEEP_0>;
> next-level-cache = <&L2_0>;
> + clocks = <&apcs_glb>;
> + operating-points-v2 = <&cpu_opp_table>;
> + cpu-supply = <&pms405_s3>;
> };
>
> CPU3: cpu@103 {
> @@ -61,6 +70,9 @@
> enable-method = "psci";
> cpu-idle-states = <&CPU_SLEEP_0>;
> next-level-cache = <&L2_0>;
> + clocks = <&apcs_glb>;
> + operating-points-v2 = <&cpu_opp_table>;
> + cpu-supply = <&pms405_s3>;
> };
>
> L2_0: l2-cache {
> --
> 2.21.0
>
^ permalink raw reply
* Re: [PATCH v3 14/14] arm64: defconfig: Enable HFPLL
From: Bjorn Andersson @ 2019-07-11 15:27 UTC (permalink / raw)
To: Jorge Ramirez-Ortiz
Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
linux-clk, linux-arm-msm, khasim.mohammed
In-Reply-To: <20190625164733.11091-15-jorge.ramirez-ortiz@linaro.org>
On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> The high frequency pll is required on compatible Qualcomm SoCs to
> support the CPU frequency scaling feature.
>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> ---
> arch/arm64/configs/defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index fbbc065415d4..7cc4ad24dfe5 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -671,6 +671,7 @@ CONFIG_MSM_MMCC_8996=y
> CONFIG_MSM_GCC_8998=y
> CONFIG_QCS_GCC_404=y
> CONFIG_SDM_GCC_845=y
> +CONFIG_QCOM_HFPLL=y
> CONFIG_HWSPINLOCK=y
> CONFIG_HWSPINLOCK_QCOM=y
> CONFIG_ARM_MHU=y
> --
> 2.21.0
>
^ permalink raw reply
* Re: [PATCH v3 12/14] arm64: dts: qcom: qcs404: Add the clocks for APCS mux/divider
From: Bjorn Andersson @ 2019-07-11 15:27 UTC (permalink / raw)
To: Jorge Ramirez-Ortiz
Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
linux-clk, linux-arm-msm, khasim.mohammed
In-Reply-To: <20190625164733.11091-13-jorge.ramirez-ortiz@linaro.org>
On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> Specify the clocks that feed the APCS mux/divider instead of using
> default hardcoded values in the source code.
>
> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/qcs404.dtsi | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> index 94471aa31979..9569686dbc41 100644
> --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> @@ -850,6 +850,9 @@
> compatible = "qcom,qcs404-apcs-apps-global", "syscon";
> reg = <0x0b011000 0x1000>;
> #mbox-cells = <1>;
> + clocks = <&gcc GCC_GPLL0_AO_OUT_MAIN>, <&apcs_hfpll>;
> + clock-names = "aux", "pll";
> + #clock-cells = <0>;
> };
>
> apcs_hfpll: clock-controller@b016000 {
> --
> 2.21.0
>
^ permalink raw reply
* Re: [PATCH v3 11/14] arm64: dts: qcom: qcs404: Add HFPLL node
From: Bjorn Andersson @ 2019-07-11 15:25 UTC (permalink / raw)
To: Jorge Ramirez-Ortiz
Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
linux-clk, linux-arm-msm, khasim.mohammed
In-Reply-To: <20190625164733.11091-12-jorge.ramirez-ortiz@linaro.org>
On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> The high frequency pll functionality is required to enable CPU
> frequency scaling operation.
>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/qcs404.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> index d876dae5b0a5..94471aa31979 100644
> --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> @@ -852,6 +852,15 @@
> #mbox-cells = <1>;
> };
>
> + apcs_hfpll: clock-controller@b016000 {
> + compatible = "qcom,hfpll";
> + reg = <0x0b016000 0x30>;
> + #clock-cells = <0>;
> + clock-output-names = "apcs_hfpll";
> + clocks = <&xo_board>;
> + clock-names = "xo";
> + };
> +
> timer@b120000 {
> #address-cells = <1>;
> #size-cells = <1>;
> --
> 2.21.0
>
^ permalink raw reply
* Re: [PATCH v3 10/14] arm64: dts: qcom: qcs404: Add OPP table
From: Bjorn Andersson @ 2019-07-11 15:25 UTC (permalink / raw)
To: Jorge Ramirez-Ortiz
Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
linux-clk, linux-arm-msm, khasim.mohammed
In-Reply-To: <20190625164733.11091-11-jorge.ramirez-ortiz@linaro.org>
On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> Add a CPU OPP table to qcs404
>
> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/qcs404.dtsi | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> index 3f17e1b09c13..d876dae5b0a5 100644
> --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> @@ -83,6 +83,24 @@
> };
> };
>
> + cpu_opp_table: cpu-opp-table {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-1094400000 {
> + opp-hz = /bits/ 64 <1094400000>;
> + opp-microvolt = <1224000 1224000 1224000>;
> + };
> + opp-1248000000 {
> + opp-hz = /bits/ 64 <1248000000>;
> + opp-microvolt = <1288000 1288000 1288000>;
> + };
> + opp-1401600000 {
> + opp-hz = /bits/ 64 <1401600000>;
> + opp-microvolt = <1384000 1384000 1384000>;
> + };
> + };
> +
> firmware {
> scm: scm {
> compatible = "qcom,scm-qcs404", "qcom,scm";
> --
> 2.21.0
>
^ permalink raw reply
* Re: [PATCH v3 09/14] arm64: dts: qcom: msm8916: Add the clocks for the APCS mux/divider
From: Bjorn Andersson @ 2019-07-11 15:24 UTC (permalink / raw)
To: Jorge Ramirez-Ortiz
Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
linux-clk, linux-arm-msm, khasim.mohammed
In-Reply-To: <20190625164733.11091-10-jorge.ramirez-ortiz@linaro.org>
On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> Specify the clocks that feed the APCS mux/divider instead of using
> default hardcoded values in the source code.
>
> The driver still supports the previous bindings; however with this
> update it we allow the msm8916 to access the parent clock names
> required by the driver operation using the device tree node.
>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/msm8916.dtsi | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> index 5ea9fb8f2f87..96dc7a12aa94 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> @@ -429,7 +429,8 @@
> compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
> reg = <0xb011000 0x1000>;
> #mbox-cells = <1>;
> - clocks = <&a53pll>;
> + clocks = <&gcc GPLL0_VOTE>, <&a53pll>;
> + clock-names = "aux", "pll";
> #clock-cells = <0>;
> };
>
> --
> 2.21.0
>
^ permalink raw reply
* Re: [PATCH v3 08/14] clk: qcom: hfpll: CLK_IGNORE_UNUSED
From: Bjorn Andersson @ 2019-07-11 15:16 UTC (permalink / raw)
To: Jorge Ramirez-Ortiz
Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
linux-clk, linux-arm-msm, khasim.mohammed
In-Reply-To: <20190625164733.11091-9-jorge.ramirez-ortiz@linaro.org>
On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> When COMMON_CLK_DISABLED_UNUSED is set, in an effort to save power and
> to keep the software model of the clock in line with reality, the
> framework transverses the clock tree and disables those clocks that
> were enabled by the firmware but have not been enabled by any device
> driver.
>
> If CPUFREQ is enabled, early during the system boot, it might attempt
> to change the CPU frequency ("set_rate"). If the HFPLL is selected as
> a provider, it will then change the rate for this clock.
>
> As boot continues, clk_disable_unused_subtree will run. Since it wont
> find a valid counter (enable_count) for a clock that is actually
> enabled it will attempt to disable it which will cause the CPU to
> stop.
But if CPUfreq has acquired the CPU clock and the hfpll is the currently
selected input, why does the clock framework not know about this clock
being used?
> Notice that in this driver, calls to check whether the clock is
> enabled are routed via the is_enabled callback which queries the
> hardware.
>
> The following commit, rather than marking the clock critical and
> forcing the clock to be always enabled, addresses the above scenario
> making sure the clock is not disabled but it continues to rely on the
> firmware to enable the clock.
>
> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
I can see that we have a real issue in the case where CPUfreq is not
enabled and hence there are no clients, according to Linux. And that I
don't know another way to guard against.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> ---
> drivers/clk/qcom/hfpll.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
> index 0ffed0d41c50..d5fd27938e7b 100644
> --- a/drivers/clk/qcom/hfpll.c
> +++ b/drivers/clk/qcom/hfpll.c
> @@ -58,6 +58,13 @@ static int qcom_hfpll_probe(struct platform_device *pdev)
> .parent_names = (const char *[]){ "xo" },
> .num_parents = 1,
> .ops = &clk_ops_hfpll,
> + /*
> + * rather than marking the clock critical and forcing the clock
> + * to be always enabled, we make sure that the clock is not
> + * disabled: the firmware remains responsible of enabling this
> + * clock (for more info check the commit log)
> + */
> + .flags = CLK_IGNORE_UNUSED,
> };
>
> h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL);
> --
> 2.21.0
>
^ permalink raw reply
* Re: [PATCH v3 07/14] clk: qcom: hfpll: register as clock provider
From: Bjorn Andersson @ 2019-07-11 15:07 UTC (permalink / raw)
To: Jorge Ramirez-Ortiz
Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
linux-clk, linux-arm-msm, khasim.mohammed
In-Reply-To: <20190625164733.11091-8-jorge.ramirez-ortiz@linaro.org>
On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> Make the output of the high frequency pll a clock provider.
> On the QCS404 this PLL controls cpu frequency scaling.
>
> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
> drivers/clk/qcom/hfpll.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
> index 87b7f46d27e0..0ffed0d41c50 100644
> --- a/drivers/clk/qcom/hfpll.c
> +++ b/drivers/clk/qcom/hfpll.c
> @@ -53,6 +53,7 @@ static int qcom_hfpll_probe(struct platform_device *pdev)
> struct regmap *regmap;
> struct clk_hfpll *h;
> struct clk *pclk;
> + int ret;
> struct clk_init_data init = {
> .parent_names = (const char *[]){ "xo" },
> .num_parents = 1,
> @@ -87,7 +88,14 @@ static int qcom_hfpll_probe(struct platform_device *pdev)
> h->clkr.hw.init = &init;
> spin_lock_init(&h->lock);
>
> - return devm_clk_register_regmap(&pdev->dev, &h->clkr);
> + ret = devm_clk_register_regmap(dev, &h->clkr);
> + if (ret) {
> + dev_err(dev, "failed to register regmap clock: %d\n", ret);
> + return ret;
> + }
> +
> + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
> + &h->clkr.hw);
> }
>
> static struct platform_driver qcom_hfpll_driver = {
> --
> 2.21.0
>
^ permalink raw reply
* Re: [PATCH v3 06/14] clk: qcom: hfpll: get parent clock names from DT
From: Bjorn Andersson @ 2019-07-11 15:07 UTC (permalink / raw)
To: Jorge Ramirez-Ortiz
Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
linux-clk, linux-arm-msm, khasim.mohammed
In-Reply-To: <20190625164733.11091-7-jorge.ramirez-ortiz@linaro.org>
On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> Allow accessing the parent clock name required for the driver
> operation using the device tree node.
>
> This permits extending the driver to other platforms without having to
> modify its source code.
>
> For backwards compatibility leave the previous value as default.
>
> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
The driver should be updated to use parent_data instead, but I consider
that's an independent change.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
> drivers/clk/qcom/hfpll.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
> index a6de7101430c..87b7f46d27e0 100644
> --- a/drivers/clk/qcom/hfpll.c
> +++ b/drivers/clk/qcom/hfpll.c
> @@ -52,6 +52,7 @@ static int qcom_hfpll_probe(struct platform_device *pdev)
> void __iomem *base;
> struct regmap *regmap;
> struct clk_hfpll *h;
> + struct clk *pclk;
> struct clk_init_data init = {
> .parent_names = (const char *[]){ "xo" },
> .num_parents = 1,
> @@ -75,6 +76,13 @@ static int qcom_hfpll_probe(struct platform_device *pdev)
> 0, &init.name))
> return -ENODEV;
>
> + /* get parent clock from device tree (optional) */
> + pclk = devm_clk_get(dev, "xo");
> + if (!IS_ERR(pclk))
> + init.parent_names = (const char *[]){ __clk_get_name(pclk) };
> + else if (PTR_ERR(pclk) == -EPROBE_DEFER)
> + return -EPROBE_DEFER;
> +
> h->d = &hdata;
> h->clkr.hw.init = &init;
> spin_lock_init(&h->lock);
> --
> 2.21.0
>
^ permalink raw reply
* Re: [PATCH 00/10] Improvements and fixes for mxsfb DRM driver
From: Guido Günther @ 2019-07-11 15:04 UTC (permalink / raw)
To: Robert Chiras
Cc: Marek Vasut, Stefan Agner, David Airlie, Daniel Vetter,
Rob Herring, Mark Rutland, Shawn Guo, Sascha Hauer, Fabio Estevam,
devicetree, linux-kernel, dri-devel, NXP Linux Team,
Pengutronix Kernel Team, linux-arm-kernel
In-Reply-To: <1561555938-21595-1-git-send-email-robert.chiras@nxp.com>
Hi Robert,
On Wed, Jun 26, 2019 at 04:32:08PM +0300, Robert Chiras wrote:
> This patch-set improves the use of eLCDIF block on iMX 8 SoCs (like 8MQ, 8MM
> and 8QXP). Following, are the new features added and fixes from this
> patch-set:
>
> 1. Add support for drm_bridge
> On 8MQ and 8MM, the LCDIF block is not directly connected to a parallel
> display connector, where an LCD panel can be attached, but instead it is
> connected to DSI controller. Since this DSI stands between the display
> controller (eLCDIF) and the physical connector, the DSI can be implemented
> as a DRM bridge. So, in order to be able to connect the mxsfb driver to
> the DSI driver, the support for a drm_bridge was needed in mxsfb DRM
> driver (the actual driver for the eLCDIF block).
So I wanted to test this but with both my somewhat cleaned up nwl
driver¹ and the nwl driver forward ported from the nxp vendor tree I'm
looking at a black screen with current mainline - while my dcss forward
port gives me nice output on mipi dsi. Do you have a tree that uses mipi
dsi on imx8mq where I could look at to check for differences?
Cheers,
-- Guido
>
> 2. Add support for additional pixel formats
> Some of the pixel formats needed by Android were not implemented in this
> driver, but they were actually supported. So, add support for them.
>
> 3. Add support for horizontal stride
> Having support for horizontal stride allows the use of eLCDIF with a GPU
> (for example) that can only output resolution sizes multiple of a power of
> 8. For example, 1080 is not a power of 16, so in order to support 1920x1080
> output from GPUs that can produce linear buffers only in sizes multiple to 16,
> this feature is needed.
>
> 3. Few minor features and bug-fixing
> The addition of max-res DT property was actually needed in order to limit
> the bandwidth usage of the eLCDIF block. This is need on systems where
> multiple display controllers are presend and the memory bandwidth is not
> enough to handle all of them at maximum capacity (like it is the case on
> 8MQ, where there are two display controllers: DCSS and eLCDIF).
> The rest of the patches are bug-fixes.
>
> Mirela Rabulea (1):
> drm/mxsfb: Signal mode changed when bpp changed
>
> Robert Chiras (9):
> drm/mxsfb: Update mxsfb to support a bridge
> drm/mxsfb: Update mxsfb with additional pixel formats
> drm/mxsfb: Fix the vblank events
> dt-bindings: display: Add max-res property for mxsfb
> drm/mxsfb: Add max-res property for MXSFB
> drm/mxsfb: Update mxsfb to support LCD reset
> drm/mxsfb: Improve the axi clock usage
> drm/mxsfb: Clear OUTSTANDING_REQS bits
> drm/mxsfb: Add support for horizontal stride
>
> .../devicetree/bindings/display/mxsfb.txt | 6 +
> drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 290 ++++++++++++++++++---
> drivers/gpu/drm/mxsfb/mxsfb_drv.c | 189 +++++++++++---
> drivers/gpu/drm/mxsfb/mxsfb_drv.h | 10 +-
> drivers/gpu/drm/mxsfb/mxsfb_out.c | 26 +-
> drivers/gpu/drm/mxsfb/mxsfb_regs.h | 128 ++++++---
> 6 files changed, 531 insertions(+), 118 deletions(-)
>
> --
> 2.7.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
¹ https://lists.freedesktop.org/archives/dri-devel/2019-March/209685.html
^ permalink raw reply
* [PATCH v2 4/4] arm64: dts: marvell: armada-ap806: add smmu support
From: Gregory CLEMENT @ 2019-07-11 15:02 UTC (permalink / raw)
To: Robin Murphy, Joerg Roedel, linux-kernel, iommu
Cc: Rob Herring, devicetree, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Gregory CLEMENT, Thomas Petazzoni,
linux-arm-kernel, Catalin Marinas, Will Deacon, Antoine Tenart,
Miquèl Raynal, Maxime Chevallier, Nadav Haklai
In-Reply-To: <20190711150242.25290-1-gregory.clement@bootlin.com>
Add IOMMU node for Marvell AP806 based SoCs.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 91dad7e4ee59..8e29d593970a 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -115,6 +115,23 @@
interrupts = <17>;
};
+ smmu: iommu@5000000 {
+ compatible = "marvell,mmu-500";
+ reg = <0x100000 0x100000>;
+ dma-coherent;
+ #iommu-cells = <1>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
odmi: odmi@300000 {
compatible = "marvell,odmi-controller";
interrupt-controller;
--
2.20.1
^ permalink raw reply related
* [PATCH v2 3/4] dt-bindings: iommu/arm,smmu: add compatible string for Marvell
From: Gregory CLEMENT @ 2019-07-11 15:02 UTC (permalink / raw)
To: Robin Murphy, Joerg Roedel, linux-kernel, iommu
Cc: Rob Herring, devicetree, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Gregory CLEMENT, Thomas Petazzoni,
linux-arm-kernel, Catalin Marinas, Will Deacon, Antoine Tenart,
Miquèl Raynal, Maxime Chevallier, Nadav Haklai, Hanna Hawa
In-Reply-To: <20190711150242.25290-1-gregory.clement@bootlin.com>
From: Hanna Hawa <hannah@marvell.com>
Add specific compatible string for Marvell usage due errata of
accessing 64bits registers of ARM SMMU, in AP806.
AP806 SoC uses the generic ARM-MMU500, and there's no specific
implementation of Marvell, this compatible is used for errata only.
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
index 3133f3ba7567..7ed58d51846e 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
@@ -16,6 +16,7 @@ conditions.
"arm,mmu-400"
"arm,mmu-401"
"arm,mmu-500"
+ "marvell,mmu-500"
"cavium,smmu-v2"
"qcom,smmu-v2"
--
2.20.1
^ permalink raw reply related
* [PATCH v2 2/4] iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum #582743
From: Gregory CLEMENT @ 2019-07-11 15:02 UTC (permalink / raw)
To: Robin Murphy, Joerg Roedel, linux-kernel, iommu
Cc: Rob Herring, devicetree, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Gregory CLEMENT, Thomas Petazzoni,
linux-arm-kernel, Catalin Marinas, Will Deacon, Antoine Tenart,
Miquèl Raynal, Maxime Chevallier, Nadav Haklai, Hanna Hawa
In-Reply-To: <20190711150242.25290-1-gregory.clement@bootlin.com>
From: Hanna Hawa <hannah@marvell.com>
Due to erratum #582743, the Marvell Armada-AP806 can't access 64bit to
ARM SMMUv2 registers.
This patch split the writeq/readq to two accesses of writel/readl.
We also mask the MMU_IDR2.PTFSv8 fields to not use AArch64 format but
only AARCH32_L. Indeed with AArch64 format 32 bits acces is not
supported.
Note that separate writes/reads to 2 is not problem regards to
atomicity, because the driver use the readq/writeq while initialize
the SMMU, report for SMMU fault, and use spinlock in one
case (iova_to_phys).
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
Documentation/arm64/silicon-errata.txt | 2 ++
drivers/iommu/arm-smmu.c | 42 +++++++++++++++++++++++---
2 files changed, 40 insertions(+), 4 deletions(-)
diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index d1e2bb801e1b..3f78ae7a7690 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -72,6 +72,8 @@ stable kernels.
| Cavium | ThunderX2 SMMUv3| #74 | N/A |
| Cavium | ThunderX2 SMMUv3| #126 | N/A |
| | | | |
+| Marvell | ARM-MMU-500 | #582743 | N/A |
+| | | | |
| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
| | | | |
| Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 |
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index ac0784b5b675..32536ccae22d 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -126,6 +126,7 @@ enum arm_smmu_arch_version {
enum arm_smmu_implementation {
GENERIC_SMMU,
ARM_MMU500,
+ MRVL_MMU500,
CAVIUM_SMMUV2,
QCOM_SMMUV2,
};
@@ -301,13 +302,35 @@ static inline void smmu_writeq_relaxed(struct arm_smmu_device *smmu,
u64 val,
void __iomem *addr)
{
- writeq_relaxed(val, addr);
+ /*
+ * Marvell Armada-AP806 erratum #582743.
+ * Split all the writeq to double writel
+ */
+ if (smmu->model != MRVL_MMU500) {
+ writeq_relaxed(val, addr);
+ return;
+ }
+
+ writel_relaxed(upper_32_bits(val), addr + 4);
+ writel_relaxed(lower_32_bits(val), addr);
}
static inline u64 smmu_readq_relaxed(struct arm_smmu_device *smmu,
void __iomem *addr)
{
- return readq_relaxed(addr);
+ u64 val;
+
+ /*
+ * Marvell Armada-AP806 erratum #582743.
+ * Split all the readq to double readl
+ */
+ if (smmu->model != MRVL_MMU500)
+ return readq_relaxed(addr);
+
+ val = (u64)readl_relaxed(addr + 4) << 32;
+ val |= readl_relaxed(addr);
+
+ return val;
}
static void parse_driver_options(struct arm_smmu_device *smmu)
@@ -1741,7 +1764,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
for (i = 0; i < smmu->num_mapping_groups; ++i)
arm_smmu_write_sme(smmu, i);
- if (smmu->model == ARM_MMU500) {
+ if (smmu->model == ARM_MMU500 || smmu->model == MRVL_MMU500) {
/*
* Before clearing ARM_MMU500_ACTLR_CPRE, need to
* clear CACHE_LOCK bit of ACR first. And, CACHE_LOCK
@@ -1770,7 +1793,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
* Disable MMU-500's not-particularly-beneficial next-page
* prefetcher for the sake of errata #841119 and #826419.
*/
- if (smmu->model == ARM_MMU500) {
+ if (smmu->model == ARM_MMU500 || smmu->model == MRVL_MMU500) {
reg = readl_relaxed(cb_base + ARM_SMMU_CB_ACTLR);
reg &= ~ARM_MMU500_ACTLR_CPRE;
writel_relaxed(reg, cb_base + ARM_SMMU_CB_ACTLR);
@@ -1987,6 +2010,15 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
if (id & ID2_VMID16)
smmu->features |= ARM_SMMU_FEAT_VMID16;
+ /*
+ * Armada-AP806 erratum #582743.
+ * Hide the SMMU_IDR2.PTFSv8 fields to sidestep the AArch64
+ * formats altogether and allow using 32 bits access on the
+ * interconnect.
+ */
+ if (smmu->model == MRVL_MMU500)
+ id &= ~(ID2_PTFS_4K | ID2_PTFS_16K | ID2_PTFS_64K);
+
/*
* What the page table walker can address actually depends on which
* descriptor format is in use, but since a) we don't know that yet,
@@ -2053,6 +2085,7 @@ ARM_SMMU_MATCH_DATA(smmu_generic_v1, ARM_SMMU_V1, GENERIC_SMMU);
ARM_SMMU_MATCH_DATA(smmu_generic_v2, ARM_SMMU_V2, GENERIC_SMMU);
ARM_SMMU_MATCH_DATA(arm_mmu401, ARM_SMMU_V1_64K, GENERIC_SMMU);
ARM_SMMU_MATCH_DATA(arm_mmu500, ARM_SMMU_V2, ARM_MMU500);
+ARM_SMMU_MATCH_DATA(mrvl_mmu500, ARM_SMMU_V2, MRVL_MMU500);
ARM_SMMU_MATCH_DATA(cavium_smmuv2, ARM_SMMU_V2, CAVIUM_SMMUV2);
ARM_SMMU_MATCH_DATA(qcom_smmuv2, ARM_SMMU_V2, QCOM_SMMUV2);
@@ -2062,6 +2095,7 @@ static const struct of_device_id arm_smmu_of_match[] = {
{ .compatible = "arm,mmu-400", .data = &smmu_generic_v1 },
{ .compatible = "arm,mmu-401", .data = &arm_mmu401 },
{ .compatible = "arm,mmu-500", .data = &arm_mmu500 },
+ { .compatible = "marvell,mmu-500", .data = &mrvl_mmu500 },
{ .compatible = "cavium,smmu-v2", .data = &cavium_smmuv2 },
{ .compatible = "qcom,smmu-v2", .data = &qcom_smmuv2 },
{ },
--
2.20.1
^ permalink raw reply related
* [PATCH v2 1/4] iommu/arm-smmu: Introduce wrapper for writeq/readq
From: Gregory CLEMENT @ 2019-07-11 15:02 UTC (permalink / raw)
To: Robin Murphy, Joerg Roedel, linux-kernel, iommu
Cc: Rob Herring, devicetree, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Gregory CLEMENT, Thomas Petazzoni,
linux-arm-kernel, Catalin Marinas, Will Deacon, Antoine Tenart,
Miquèl Raynal, Maxime Chevallier, Nadav Haklai, Hanna Hawa
In-Reply-To: <20190711150242.25290-1-gregory.clement@bootlin.com>
From: Hanna Hawa <hannah@marvell.com>
This patch introduces the smmu_writeq_relaxed/smmu_readq_relaxed
helpers, as preparation to add specific Marvell work-around for
accessing 64 bits width registers of ARM SMMU.
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
drivers/iommu/arm-smmu.c | 36 +++++++++++++++++++++++++++---------
1 file changed, 27 insertions(+), 9 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 045d93884164..ac0784b5b675 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -91,9 +91,11 @@
* therefore this actually makes more sense than it might first appear.
*/
#ifdef CONFIG_64BIT
-#define smmu_write_atomic_lq writeq_relaxed
+#define smmu_write_atomic_lq(smmu, val, reg) \
+ smmu_writeq_relaxed(smmu, val, reg)
#else
-#define smmu_write_atomic_lq writel_relaxed
+#define smmu_write_atomic_lq(smmu, val, reg) \
+ writel_relaxed(val, reg)
#endif
/* Translation context bank */
@@ -295,6 +297,19 @@ static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)
return container_of(dom, struct arm_smmu_domain, domain);
}
+static inline void smmu_writeq_relaxed(struct arm_smmu_device *smmu,
+ u64 val,
+ void __iomem *addr)
+{
+ writeq_relaxed(val, addr);
+}
+
+static inline u64 smmu_readq_relaxed(struct arm_smmu_device *smmu,
+ void __iomem *addr)
+{
+ return readq_relaxed(addr);
+}
+
static void parse_driver_options(struct arm_smmu_device *smmu)
{
int i = 0;
@@ -495,6 +510,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
size_t granule, bool leaf, void *cookie)
{
struct arm_smmu_domain *smmu_domain = cookie;
+ struct arm_smmu_device *smmu = smmu_domain->smmu;
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
void __iomem *reg = ARM_SMMU_CB(smmu_domain->smmu, cfg->cbndx);
@@ -516,7 +532,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
iova >>= 12;
iova |= (u64)cfg->asid << 48;
do {
- writeq_relaxed(iova, reg);
+ smmu_writeq_relaxed(smmu, iova, reg);
iova += granule >> 12;
} while (size -= granule);
}
@@ -525,7 +541,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
ARM_SMMU_CB_S2_TLBIIPAS2;
iova >>= 12;
do {
- smmu_write_atomic_lq(iova, reg);
+ smmu_write_atomic_lq(smmu, iova, reg);
iova += granule >> 12;
} while (size -= granule);
}
@@ -584,7 +600,7 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
return IRQ_NONE;
fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
- iova = readq_relaxed(cb_base + ARM_SMMU_CB_FAR);
+ iova = smmu_readq_relaxed(smmu, cb_base + ARM_SMMU_CB_FAR);
dev_err_ratelimited(smmu->dev,
"Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cb=%d\n",
@@ -734,9 +750,11 @@ static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx)
writel_relaxed(cb->ttbr[0], cb_base + ARM_SMMU_CB_TTBR0);
writel_relaxed(cb->ttbr[1], cb_base + ARM_SMMU_CB_TTBR1);
} else {
- writeq_relaxed(cb->ttbr[0], cb_base + ARM_SMMU_CB_TTBR0);
+ smmu_writeq_relaxed(smmu, cb->ttbr[0],
+ cb_base + ARM_SMMU_CB_TTBR0);
if (stage1)
- writeq_relaxed(cb->ttbr[1], cb_base + ARM_SMMU_CB_TTBR1);
+ smmu_writeq_relaxed(smmu, cb->ttbr[1],
+ cb_base + ARM_SMMU_CB_TTBR1);
}
/* MAIRs (stage-1 only) */
@@ -1367,7 +1385,7 @@ static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
/* ATS1 registers can only be written atomically */
va = iova & ~0xfffUL;
if (smmu->version == ARM_SMMU_V2)
- smmu_write_atomic_lq(va, cb_base + ARM_SMMU_CB_ATS1PR);
+ smmu_write_atomic_lq(smmu, va, cb_base + ARM_SMMU_CB_ATS1PR);
else /* Register is only 32-bit in v1 */
writel_relaxed(va, cb_base + ARM_SMMU_CB_ATS1PR);
@@ -1380,7 +1398,7 @@ static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
return ops->iova_to_phys(ops, iova);
}
- phys = readq_relaxed(cb_base + ARM_SMMU_CB_PAR);
+ phys = smmu_readq_relaxed(smmu, cb_base + ARM_SMMU_CB_PAR);
spin_unlock_irqrestore(&smmu_domain->cb_lock, flags);
if (phys & CB_PAR_F) {
dev_err(dev, "translation fault!\n");
--
2.20.1
^ permalink raw reply related
* [PATCH v2 0/4] Add system mmu support for Armada-806
From: Gregory CLEMENT @ 2019-07-11 15:02 UTC (permalink / raw)
To: Robin Murphy, Joerg Roedel, linux-kernel, iommu
Cc: Rob Herring, devicetree, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Gregory CLEMENT, Thomas Petazzoni,
linux-arm-kernel, Catalin Marinas, Will Deacon, Antoine Tenart,
Miquèl Raynal, Maxime Chevallier, Nadav Haklai
Hello,
last year a first version of this series was submitted to add support
for IOMMU for AP806, including workaround for accessing ARM SMMU 64bit
registers[1].
For the record, AP-806 can't access SMMU registers with 64bit width,
this patches split the readq/writeq for 32bit access, due to erratanum
#582743.
Based on the feedback from Robin Murphy, I also add code ensuring that
we won't try to use AArch64 format with 32 bits acces.
It was also discussed to not use compatible but propertu to support
this workaround. I agree to make this change if needed, but for now I
would like to have a feedback on the current code to know if it is
acceptable if there is still potential issue.
The series was tested on a vanilla v5.1 kernel, and without the
series, an USB stick was not detected under QEMU whereas with this
series it worked as expected.
Greogry
[1]: https://lkml.org/lkml/2018/10/15/373
Gregory CLEMENT (1):
arm64: dts: marvell: armada-ap806: add smmu support
Hanna Hawa (3):
iommu/arm-smmu: Introduce wrapper for writeq/readq
iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum
#582743
dt-bindings: iommu/arm,smmu: add compatible string for Marvell
Documentation/arm64/silicon-errata.txt | 2 +
.../devicetree/bindings/iommu/arm,smmu.txt | 1 +
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 17 +++++
drivers/iommu/arm-smmu.c | 74 ++++++++++++++++---
4 files changed, 83 insertions(+), 11 deletions(-)
--
2.20.1
^ permalink raw reply
* Re: [PATCH v3 05/14] clk: qcom: apcs-msm8916: get parent clock names from DT
From: Bjorn Andersson @ 2019-07-11 14:58 UTC (permalink / raw)
To: Jorge Ramirez-Ortiz
Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
linux-clk, linux-arm-msm, khasim.mohammed
In-Reply-To: <20190625164733.11091-6-jorge.ramirez-ortiz@linaro.org>
On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> Allow accessing the parent clock names required for the driver
> operation by using the device tree node.
>
> This permits extending the driver to other platforms without having to
> modify its source code.
>
> For backwards compatibility leave previous values as default.
>
> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
> drivers/clk/qcom/apcs-msm8916.c | 23 ++++++++++++++++++++---
> 1 file changed, 20 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/qcom/apcs-msm8916.c b/drivers/clk/qcom/apcs-msm8916.c
> index a6c89a310b18..dd82eb1e5202 100644
> --- a/drivers/clk/qcom/apcs-msm8916.c
> +++ b/drivers/clk/qcom/apcs-msm8916.c
> @@ -19,7 +19,7 @@
>
> static const u32 gpll0_a53cc_map[] = { 4, 5 };
>
> -static const char * const gpll0_a53cc[] = {
> +static const char *gpll0_a53cc[] = {
> "gpll0_vote",
> "a53pll",
> };
> @@ -50,6 +50,8 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev)
> struct regmap *regmap;
> struct clk_init_data init = { };
> int ret = -ENODEV;
> + const char *parents[2];
> + int pll_index = 0;
>
> regmap = dev_get_regmap(parent, NULL);
> if (!regmap) {
> @@ -61,6 +63,16 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev)
> if (!a53cc)
> return -ENOMEM;
>
> + /* legacy bindings only defined the pll parent clock (index = 0) with no
> + * name; when both of the parents are specified in the bindings, the
> + * pll is the second one (index = 1).
> + */
> + if (of_clk_parent_fill(parent->of_node, parents, 2) == 2) {
> + gpll0_a53cc[0] = parents[0];
> + gpll0_a53cc[1] = parents[1];
> + pll_index = 1;
> + }
> +
> init.name = "a53mux";
> init.parent_names = gpll0_a53cc;
> init.num_parents = ARRAY_SIZE(gpll0_a53cc);
> @@ -76,10 +88,11 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev)
> a53cc->src_shift = 8;
> a53cc->parent_map = gpll0_a53cc_map;
>
> - a53cc->pclk = devm_clk_get(parent, NULL);
> + a53cc->pclk = of_clk_get(parent->of_node, pll_index);
> if (IS_ERR(a53cc->pclk)) {
> ret = PTR_ERR(a53cc->pclk);
> - dev_err(dev, "failed to get clk: %d\n", ret);
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev, "failed to get clk: %d\n", ret);
> return ret;
> }
>
> @@ -87,6 +100,7 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev)
> ret = clk_notifier_register(a53cc->pclk, &a53cc->clk_nb);
> if (ret) {
> dev_err(dev, "failed to register clock notifier: %d\n", ret);
> + clk_put(a53cc->pclk);
> return ret;
> }
>
> @@ -109,6 +123,8 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev)
>
> err:
> clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb);
> + clk_put(a53cc->pclk);
> +
> return ret;
> }
>
> @@ -117,6 +133,7 @@ static int qcom_apcs_msm8916_clk_remove(struct platform_device *pdev)
> struct clk_regmap_mux_div *a53cc = platform_get_drvdata(pdev);
>
> clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb);
> + clk_put(a53cc->pclk);
>
> return 0;
> }
> --
> 2.21.0
>
^ permalink raw reply
* [PATCH 8/8] PCI: dw: Add support for PCI_PROBE_ONLY/PCI_REASSIGN_ALL_BUS flags
From: Jonathan Chocron @ 2019-07-11 14:57 UTC (permalink / raw)
To: lorenzo.pieralisi, bhelgaas, jingoohan1, gustavo.pimentel,
robh+dt, mark.rutland
Cc: dwmw, benh, alisaidi, ronenk, barakw, talel, hanochu, hhhawa,
linux-pci, linux-kernel, devicetree, jonnyc
In-Reply-To: <20190710164519.17883-1-jonnyc@amazon.com>
This basically aligns the usage of PCI_PROBE_ONLY and
PCI_REASSIGN_ALL_BUS in dw_pcie_host_init() with the logic in
pci_host_common_probe().
Now it will be possible to control via the devicetree whether to just
probe the PCI bus (in cases where FW already configured it) or to fully
configure it.
Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
---
.../pci/controller/dwc/pcie-designware-host.c | 23 +++++++++++++++----
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index d2ca748e4c85..0a294d8aa21a 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -342,6 +342,8 @@ int dw_pcie_host_init(struct pcie_port *pp)
if (!bridge)
return -ENOMEM;
+ of_pci_check_probe_only();
+
ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
&bridge->windows, &pp->io_base);
if (ret)
@@ -474,6 +476,10 @@ int dw_pcie_host_init(struct pcie_port *pp)
pp->root_bus_nr = pp->busn->start;
+ /* Do not reassign bus nums if probe only */
+ if (!pci_has_flag(PCI_PROBE_ONLY))
+ pci_add_flags(PCI_REASSIGN_ALL_BUS);
+
bridge->dev.parent = dev;
bridge->sysdata = pp;
bridge->busnr = pp->root_bus_nr;
@@ -490,11 +496,20 @@ int dw_pcie_host_init(struct pcie_port *pp)
if (pp->ops->scan_bus)
pp->ops->scan_bus(pp);
- pci_bus_size_bridges(pp->root_bus);
- pci_bus_assign_resources(pp->root_bus);
+ /*
+ * We insert PCI resources into the iomem_resource and
+ * ioport_resource trees in either pci_bus_claim_resources()
+ * or pci_bus_assign_resources().
+ */
+ if (pci_has_flag(PCI_PROBE_ONLY)) {
+ pci_bus_claim_resources(pp->root_bus);
+ } else {
+ pci_bus_size_bridges(pp->root_bus);
+ pci_bus_assign_resources(pp->root_bus);
- list_for_each_entry(child, &pp->root_bus->children, node)
- pcie_bus_configure_settings(child);
+ list_for_each_entry(child, &pp->root_bus->children, node)
+ pcie_bus_configure_settings(child);
+ }
pci_bus_add_devices(pp->root_bus);
return 0;
--
2.17.1
^ permalink raw reply related
* [PATCH 7/8] PCI: dw: Add validation that PCIe core is set to correct mode
From: Jonathan Chocron @ 2019-07-11 14:57 UTC (permalink / raw)
To: lorenzo.pieralisi, bhelgaas, jingoohan1, gustavo.pimentel,
robh+dt, mark.rutland
Cc: dwmw, benh, alisaidi, ronenk, barakw, talel, hanochu, hhhawa,
linux-pci, linux-kernel, devicetree, jonnyc
In-Reply-To: <20190710164519.17883-1-jonnyc@amazon.com>
Some PCIe controllers can be set to either Host or EP according to some
early boot FW. To make sure there is no discrepancy (e.g. FW configured
the port to EP mode while the DT specifies it as a host bridge or vice
versa), a check has been added for each mode.
Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 8 ++++++++
drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++++
2 files changed, 16 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 2bf5a35c0570..00e59a134b93 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -531,6 +531,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
int ret;
u32 reg;
void *addr;
+ u8 hdr_type;
unsigned int nbars;
unsigned int offset;
struct pci_epc *epc;
@@ -543,6 +544,13 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
return -EINVAL;
}
+ hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
+ if (hdr_type != PCI_HEADER_TYPE_NORMAL) {
+ dev_err(pci->dev, "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n",
+ hdr_type);
+ return -EIO;
+ }
+
ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows);
if (ret < 0) {
dev_err(dev, "Unable to read *num-ib-windows* property\n");
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index f93252d0da5b..d2ca748e4c85 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -323,6 +323,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
struct pci_bus *child;
struct pci_host_bridge *bridge;
struct resource *cfg_res;
+ u8 hdr_type;
int ret;
raw_spin_lock_init(&pci->pp.lock);
@@ -396,6 +397,13 @@ int dw_pcie_host_init(struct pcie_port *pp)
}
}
+ hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
+ if (hdr_type != PCI_HEADER_TYPE_BRIDGE) {
+ dev_err(pci->dev, "PCIe controller is not set to bridge type (hdr_type: 0x%x)!\n",
+ hdr_type);
+ return -EIO;
+ }
+
pp->mem_base = pp->mem->start;
if (!pp->va_cfg0_base) {
--
2.17.1
^ permalink raw reply related
* [PATCH 6/8] PCI: al: Add support for DW based driver type
From: Jonathan Chocron @ 2019-07-11 14:57 UTC (permalink / raw)
To: lorenzo.pieralisi, bhelgaas, jingoohan1, gustavo.pimentel,
robh+dt, mark.rutland
Cc: dwmw, benh, alisaidi, ronenk, barakw, talel, hanochu, hhhawa,
linux-pci, linux-kernel, devicetree, jonnyc
In-Reply-To: <20190710164519.17883-1-jonnyc@amazon.com>
This driver is DT based and utilizes the DesignWare APIs.
It allows using a smaller ECAM range for a larger bus range -
usually an entire bus uses 1MB of address space, but the driver
can use it for a larger number of buses.
All link initializations are handled by the boot FW.
Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
---
drivers/pci/controller/dwc/Kconfig | 11 +
drivers/pci/controller/dwc/pcie-al.c | 397 +++++++++++++++++++++++++++
2 files changed, 408 insertions(+)
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index a6ce1ee51b4c..51da9cb219aa 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -230,4 +230,15 @@ config PCIE_UNIPHIER
Say Y here if you want PCIe controller support on UniPhier SoCs.
This driver supports LD20 and PXs3 SoCs.
+config PCIE_AL
+ bool "Amazon Annapurna Labs PCIe controller"
+ depends on OF && (ARM64 || COMPILE_TEST)
+ depends on PCI_MSI_IRQ_DOMAIN
+ select PCIE_DW_HOST
+ help
+ Say Y here to enable support of the Annapurna Labs PCIe controller IP
+ on Amazon SoCs.
+ The PCIe controller uses the DesignWare core plus
+ Amazon-specific hardware wrappers.
+
endmenu
diff --git a/drivers/pci/controller/dwc/pcie-al.c b/drivers/pci/controller/dwc/pcie-al.c
index 3ab58f0584a8..2742a0895aab 100644
--- a/drivers/pci/controller/dwc/pcie-al.c
+++ b/drivers/pci/controller/dwc/pcie-al.c
@@ -91,3 +91,400 @@ struct pci_ecam_ops al_pcie_ops = {
};
#endif /* defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) */
+
+#ifdef CONFIG_PCIE_AL
+
+#include <linux/of_pci.h>
+#include "pcie-designware.h"
+
+#define AL_PCIE_REV_ID_2 2
+#define AL_PCIE_REV_ID_3 3
+#define AL_PCIE_REV_ID_4 4
+
+/* The AXI regs are always at the beginning of the PCIE controller reg space. */
+#define AXI_BASE_OFFSET 0x0
+
+#define DEVICE_ID_OFFSET 0x16c
+
+#define DEVICE_REV_ID 0x0
+#define DEVICE_REV_ID_DEV_ID_MASK 0xFFFF0000
+#define DEVICE_REV_ID_DEV_ID_SHIFT 16
+
+#define DEVICE_REV_ID_DEV_ID_X4 (0 << DEVICE_REV_ID_DEV_ID_SHIFT)
+#define DEVICE_REV_ID_DEV_ID_X8 (2 << DEVICE_REV_ID_DEV_ID_SHIFT)
+#define DEVICE_REV_ID_DEV_ID_X16 (4 << DEVICE_REV_ID_DEV_ID_SHIFT)
+
+/* The ob_ctrl offset inside the axi regs is different between revisions.
+ */
+#define OB_CTRL_REV1_2_OFFSET 0x0040
+#define OB_CTRL_REV3_5_OFFSET 0x0030
+
+#define CFG_TARGET_BUS 0x0
+#define CFG_TARGET_BUS_MASK_SHIFT 0
+#define CFG_TARGET_BUS_BUSNUM_SHIFT 8
+
+#define CFG_CONTROL 0x4
+#define CFG_CONTROL_SUBBUS_MASK 0x0000FF00
+#define CFG_CONTROL_SUBBUS_SHIFT 8
+#define CFG_CONTROL_SEC_BUS_MASK 0x00FF0000
+#define CFG_CONTROL_SEC_BUS_SHIFT 16
+
+struct al_pcie_reg_offsets {
+ unsigned int ob_ctrl;
+};
+
+struct al_pcie_target_bus_cfg {
+ u8 reg_val;
+ u8 reg_mask;
+ u8 ecam_mask;
+};
+
+struct al_pcie {
+ struct dw_pcie *pci;
+ void __iomem *controller_base; /* base of PCIe unit (not DW core) */
+ void __iomem *dbi_base;
+ resource_size_t ecam_size;
+ struct device *dev;
+ unsigned int controller_rev_id;
+ struct al_pcie_reg_offsets reg_offsets;
+ struct al_pcie_target_bus_cfg target_bus_cfg;
+};
+
+#define PCIE_ECAM_DEVFN(x) (((x) & 0xff) << 12)
+
+#define to_al_pcie(x) dev_get_drvdata((x)->dev)
+
+static int al_pcie_rev_id_get(struct al_pcie *pcie, unsigned int *rev_id)
+{
+ void __iomem *dev_rev_id_addr;
+ u32 dev_rev_id;
+
+ dev_rev_id_addr = (void __iomem *)((uintptr_t)pcie->controller_base +
+ AXI_BASE_OFFSET + DEVICE_ID_OFFSET + DEVICE_REV_ID);
+
+ dev_rev_id = readl(dev_rev_id_addr) & DEVICE_REV_ID_DEV_ID_MASK;
+
+ switch (dev_rev_id) {
+ case DEVICE_REV_ID_DEV_ID_X4:
+ *rev_id = AL_PCIE_REV_ID_2;
+ break;
+ case DEVICE_REV_ID_DEV_ID_X8:
+ *rev_id = AL_PCIE_REV_ID_3;
+ break;
+ case DEVICE_REV_ID_DEV_ID_X16:
+ *rev_id = AL_PCIE_REV_ID_4;
+ break;
+ default:
+ dev_err(pcie->dev, "Unsupported dev_rev_id (0x%08x)\n",
+ dev_rev_id);
+ return -EINVAL;
+ }
+
+ dev_dbg(pcie->dev, "dev_rev_id: 0x%08x\n", dev_rev_id);
+
+ return 0;
+}
+
+static int al_pcie_reg_offsets_set(struct al_pcie *pcie)
+{
+ switch (pcie->controller_rev_id) {
+ case AL_PCIE_REV_ID_2:
+ pcie->reg_offsets.ob_ctrl = OB_CTRL_REV1_2_OFFSET;
+ break;
+ case AL_PCIE_REV_ID_3:
+ case AL_PCIE_REV_ID_4:
+ pcie->reg_offsets.ob_ctrl = OB_CTRL_REV3_5_OFFSET;
+ break;
+ default:
+ dev_err(pcie->dev, "Unsupported controller rev_id: 0x%x\n",
+ pcie->controller_rev_id);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static inline void al_pcie_target_bus_set(struct al_pcie *pcie,
+ u8 target_bus,
+ u8 mask_target_bus)
+{
+ void __iomem *cfg_control_addr;
+ u32 reg = (target_bus << CFG_TARGET_BUS_BUSNUM_SHIFT) |
+ mask_target_bus;
+
+ cfg_control_addr = (void __iomem *)((uintptr_t)pcie->controller_base +
+ AXI_BASE_OFFSET + pcie->reg_offsets.ob_ctrl +
+ CFG_TARGET_BUS);
+
+ writel(reg, cfg_control_addr);
+}
+
+static void __iomem *al_pcie_conf_addr_map(struct al_pcie *pcie,
+ unsigned int busnr,
+ unsigned int devfn)
+{
+ void __iomem *pci_base_addr;
+ struct pcie_port *pp = &pcie->pci->pp;
+ struct al_pcie_target_bus_cfg *target_bus_cfg = &pcie->target_bus_cfg;
+ unsigned int busnr_ecam = busnr & target_bus_cfg->ecam_mask;
+ unsigned int busnr_reg = busnr & target_bus_cfg->reg_mask;
+
+ pci_base_addr = (void __iomem *)((uintptr_t)pp->va_cfg0_base +
+ (busnr_ecam << 20) +
+ PCIE_ECAM_DEVFN(devfn));
+
+ if (busnr_reg != target_bus_cfg->reg_val) {
+ dev_dbg(pcie->pci->dev, "Changing target bus busnum val from %d to %d\n",
+ target_bus_cfg->reg_val, busnr_reg);
+ target_bus_cfg->reg_val = busnr_reg;
+ al_pcie_target_bus_set(pcie,
+ target_bus_cfg->reg_val,
+ target_bus_cfg->reg_mask);
+ }
+
+ return pci_base_addr;
+}
+
+static int al_pcie_rd_other_conf(struct pcie_port *pp,
+ struct pci_bus *bus,
+ unsigned int devfn,
+ int where,
+ int size,
+ u32 *val)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct al_pcie *pcie = to_al_pcie(pci);
+ unsigned int busnr = bus->number;
+ void __iomem *pci_addr;
+ int rc;
+
+ pci_addr = al_pcie_conf_addr_map(pcie, busnr, devfn);
+
+ rc = dw_pcie_read(pci_addr + where, size, val);
+
+ dev_dbg(pci->dev, "%d-byte config read from %04x:%02x:%02x.%d offset %#x (pci_addr: 0x%p) - val:0x%x\n",
+ size, pci_domain_nr(bus), bus->number,
+ PCI_SLOT(devfn), PCI_FUNC(devfn), where,
+ (pci_addr + where), *val);
+
+ return rc;
+}
+
+static int al_pcie_wr_other_conf(struct pcie_port *pp,
+ struct pci_bus *bus,
+ unsigned int devfn,
+ int where,
+ int size,
+ u32 val)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct al_pcie *pcie = to_al_pcie(pci);
+ unsigned int busnr = bus->number;
+ void __iomem *pci_addr;
+ int rc;
+
+ pci_addr = al_pcie_conf_addr_map(pcie, busnr, devfn);
+
+ rc = dw_pcie_write(pci_addr + where, size, val);
+
+ dev_dbg(pci->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x (pci_addr: 0x%p) - val:0x%x\n",
+ size, pci_domain_nr(bus), bus->number,
+ PCI_SLOT(devfn), PCI_FUNC(devfn), where,
+ (pci_addr + where), val);
+
+ return rc;
+}
+
+static int al_pcie_config_prepare(struct al_pcie *pcie)
+{
+ struct al_pcie_target_bus_cfg *target_bus_cfg;
+ struct pcie_port *pp = &pcie->pci->pp;
+ unsigned int ecam_bus_mask;
+ u8 secondary_bus;
+ u8 subordinate_bus;
+ void __iomem *cfg_control_addr;
+ u32 cfg_control;
+ u32 reg = 0;
+
+ target_bus_cfg = &pcie->target_bus_cfg;
+
+ ecam_bus_mask = (pcie->ecam_size >> 20) - 1;
+ if (ecam_bus_mask > 255) {
+ dev_warn(pcie->dev, "ECAM window size is larger than 256MB. Cutting off at 256\n");
+ ecam_bus_mask = 255;
+ }
+
+ /* This portion is taken from the transaction address */
+ target_bus_cfg->ecam_mask = ecam_bus_mask;
+ /* This portion is taken from the cfg_target_bus reg */
+ target_bus_cfg->reg_mask = ~target_bus_cfg->ecam_mask;
+ target_bus_cfg->reg_val = pp->busn->start & target_bus_cfg->reg_mask;
+
+ al_pcie_target_bus_set(pcie,
+ target_bus_cfg->reg_val,
+ target_bus_cfg->reg_mask);
+
+ secondary_bus = pp->busn->start + 1;
+ subordinate_bus = pp->busn->end;
+
+ /* Set the valid values of secondary and subordinate buses */
+ cfg_control_addr = pcie->controller_base +
+ AXI_BASE_OFFSET + pcie->reg_offsets.ob_ctrl + CFG_CONTROL;
+
+ cfg_control = readl(cfg_control_addr);
+
+ reg = (cfg_control & ~CFG_CONTROL_SEC_BUS_MASK) |
+ (secondary_bus << CFG_CONTROL_SEC_BUS_SHIFT);
+ reg = (reg & ~CFG_CONTROL_SUBBUS_MASK) |
+ (subordinate_bus << CFG_CONTROL_SUBBUS_SHIFT);
+
+ writel(reg, cfg_control_addr);
+
+ return 0;
+}
+
+static int al_pcie_host_init(struct pcie_port *pp)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct al_pcie *pcie = to_al_pcie(pci);
+ int link_up = 0;
+ u32 reg = 0;
+ int rc;
+
+ reg = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
+ if (reg != PCI_HEADER_TYPE_BRIDGE) {
+ dev_err(pci->dev, "PCIe controller is not set to bridge type (%d)!\n",
+ reg);
+ return -EIO;
+ }
+
+ link_up = dw_pcie_link_up(pci);
+ if (!link_up) {
+ dev_err(pci->dev, "link in not up!\n");
+ return -ENOLINK;
+ }
+
+ dev_info(pci->dev, "link is up\n");
+
+ rc = al_pcie_rev_id_get(pcie, &pcie->controller_rev_id);
+ if (rc)
+ return rc;
+
+ rc = al_pcie_reg_offsets_set(pcie);
+ if (rc)
+ return rc;
+
+ rc = al_pcie_config_prepare(pcie);
+ if (rc)
+ return rc;
+
+ return 0;
+}
+
+static const struct dw_pcie_host_ops al_pcie_host_ops = {
+ .rd_other_conf = al_pcie_rd_other_conf,
+ .wr_other_conf = al_pcie_wr_other_conf,
+ .host_init = al_pcie_host_init,
+};
+
+static int al_add_pcie_port(struct pcie_port *pp,
+ struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ pp->ops = &al_pcie_host_ops;
+
+ ret = dw_pcie_host_init(pp);
+ if (ret) {
+ dev_err(dev, "failed to initialize host\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct dw_pcie_ops dw_pcie_ops = {
+};
+
+static int al_pcie_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct al_pcie *al_pcie;
+ struct dw_pcie *pci;
+ struct resource *dbi_res;
+ struct resource *controller_res;
+ struct resource *ecam_res;
+ int ret;
+
+ al_pcie = devm_kzalloc(dev, sizeof(*al_pcie), GFP_KERNEL);
+ if (!al_pcie)
+ return -ENOMEM;
+
+ pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
+ if (!pci)
+ return -ENOMEM;
+
+ pci->dev = dev;
+ pci->ops = &dw_pcie_ops;
+
+ al_pcie->pci = pci;
+ al_pcie->dev = dev;
+
+ dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
+ pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_res);
+ if (IS_ERR(pci->dbi_base)) {
+ dev_err(dev, "couldn't remap dbi base %p\n", dbi_res);
+ return PTR_ERR(pci->dbi_base);
+ }
+
+ ecam_res = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM,
+ "config");
+ if (!ecam_res) {
+ dev_err(dev, "couldn't find 'config' reg in DT\n");
+ return -ENOENT;
+ }
+ al_pcie->ecam_size = resource_size(ecam_res);
+
+ controller_res = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM,
+ "controller");
+ al_pcie->controller_base = devm_ioremap_resource(dev,
+ controller_res);
+ if (IS_ERR(al_pcie->controller_base)) {
+ dev_err(dev, "couldn't remap controller base %p\n",
+ controller_res);
+ return PTR_ERR(al_pcie->controller_base);
+ }
+
+ dev_dbg(dev, "From DT: dbi_base: 0x%llx, controller_base: 0x%llx\n",
+ dbi_res->start, controller_res->start);
+
+ platform_set_drvdata(pdev, al_pcie);
+
+ ret = al_add_pcie_port(&pci->pp, pdev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static const struct of_device_id al_pcie_of_match[] = {
+ { .compatible = "amazon,al-pcie",
+ .data = NULL,
+ },
+ {},
+};
+
+static struct platform_driver al_pcie_driver = {
+ .driver = {
+ .name = "al-pcie",
+ .of_match_table = al_pcie_of_match,
+ .suppress_bind_attrs = true,
+ },
+ .probe = al_pcie_probe,
+};
+builtin_platform_driver(al_pcie_driver);
+
+#endif /* CONFIG_PCIE_AL*/
--
2.17.1
^ permalink raw reply related
* [PATCH 4/8] PCI: Add quirk to disable MSI support for Amazon's Annapurna Labs host bridge
From: Jonathan Chocron @ 2019-07-11 14:56 UTC (permalink / raw)
To: lorenzo.pieralisi, bhelgaas, jingoohan1, gustavo.pimentel,
robh+dt, mark.rutland
Cc: dwmw, benh, alisaidi, ronenk, barakw, talel, hanochu, hhhawa,
linux-pci, linux-kernel, devicetree, jonnyc
In-Reply-To: <20190710164519.17883-1-jonnyc@amazon.com>
On some platforms, the host bridge exposes an MSI-X capability but
doesn't actually support it.
This causes a crash during initialization by the pcieport driver, since
it tries to configure the MSI-X capability.
Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
---
drivers/pci/quirks.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 11850b030637..0fb70d755977 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2925,6 +2925,14 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
quirk_msi_intx_disable_qca_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
quirk_msi_intx_disable_qca_bug);
+
+static void quirk_al_msi_disable(struct pci_dev *dev)
+{
+ dev->no_msi = 1;
+ dev_warn(&dev->dev, "Annapurna Labs pcie quirk - disabling MSI\n");
+}
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
+ PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable);
#endif /* CONFIG_PCI_MSI */
/*
--
2.17.1
^ permalink raw reply related
* [PATCH 3/8] PCI/VPD: Add VPD release quirk for Amazon Annapurna Labs host bridge
From: Jonathan Chocron @ 2019-07-11 14:55 UTC (permalink / raw)
To: lorenzo.pieralisi, bhelgaas, jingoohan1, gustavo.pimentel,
robh+dt, mark.rutland
Cc: dwmw, benh, alisaidi, ronenk, barakw, talel, hanochu, hhhawa,
linux-pci, linux-kernel, devicetree, jonnyc
In-Reply-To: <20190710164519.17883-1-jonnyc@amazon.com>
The Amazon Annapurna Labs pcie host bridge exposes the VPD capability,
but there is no actual support for it.
The reason for not using the already existing quirk_blacklist_vpd()
is that, although this fails pci_vpd_read/write, the 'vpd' sysfs
entry still exists. When running lspci -vv, for example, this
results in the following error:
pcilib: sysfs_read_vpd: read failed: Input/output error
This quirk removes the sysfs entry, which avoids the error print.
Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
---
drivers/pci/vpd.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/pci/vpd.c b/drivers/pci/vpd.c
index 4963c2e2bd4c..b594b2895ffe 100644
--- a/drivers/pci/vpd.c
+++ b/drivers/pci/vpd.c
@@ -644,4 +644,16 @@ static void quirk_chelsio_extend_vpd(struct pci_dev *dev)
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
quirk_chelsio_extend_vpd);
+static void quirk_al_vpd_release(struct pci_dev *dev)
+{
+ if (dev->vpd) {
+ pci_vpd_release(dev);
+ dev->vpd = NULL;
+ pci_warn(dev, FW_BUG "Annapurna Labs pcie quirk - Releasing VPD capability (No support for VPD read/write transactions)\n");
+ }
+}
+
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
+ PCI_CLASS_BRIDGE_PCI, 8, quirk_al_vpd_release);
+
#endif
--
2.17.1
^ permalink raw reply related
* [PATCH 2/8] PCI: Add ACS quirk for Amazon Annapurna Labs root ports
From: Jonathan Chocron @ 2019-07-11 14:55 UTC (permalink / raw)
To: lorenzo.pieralisi, bhelgaas, jingoohan1, gustavo.pimentel,
robh+dt, mark.rutland
Cc: dwmw, benh, alisaidi, ronenk, barakw, talel, hanochu, hhhawa,
linux-pci, linux-kernel, devicetree, jonnyc
In-Reply-To: <20190710164519.17883-1-jonnyc@amazon.com>
From: Ali Saidi <alisaidi@amazon.com>
The Amazon's Annapurna Labs root ports don't advertise an ACS
capability, but they don't allow peer-to-peer transactions and do
validate bus numbers through the SMMU. Additionally, it's not possible
for one RP to pass traffic to another RP.
Signed-off-by: Ali Saidi <alisaidi@amazon.com>
Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
---
drivers/pci/quirks.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index c66c0ca446c4..11850b030637 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -4366,6 +4366,23 @@ static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
return ret;
}
+static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
+{
+ /*
+ * Amazon's Annapurna Labs root ports don't include an ACS capability,
+ * but do include ACS-like functionality. The hardware doesn't support
+ * peer-to-peer transactions via the root port and each has a unique
+ * segment number.
+ * Additionally, the root ports cannot send traffic to each other.
+ */
+ acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF);
+
+ if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
+ return -ENOTTY;
+
+ return acs_flags ? 0 : 1;
+}
+
/*
* Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
* the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
@@ -4559,6 +4576,8 @@ static const struct pci_dev_acs_enabled {
{ PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
{ PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
{ PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
+ /* Amazon Annapurna Labs */
+ { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
{ 0 }
};
--
2.17.1
^ permalink raw reply related
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