* Re: [PATCH 1/1] ARM: dts: imx6ul: fix clock frequency property name of I2C buses
From: Shawn Guo @ 2019-07-22 6:50 UTC (permalink / raw)
To: Sébastien Szymanski
Cc: Mark Rutland, devicetree, Sascha Hauer, Rob Herring,
NXP Linux Team, Pengutronix Kernel Team, Fabio Estevam,
linux-arm-kernel
In-Reply-To: <20190704110053.19028-1-sebastien.szymanski@armadeus.com>
On Thu, Jul 04, 2019 at 01:00:53PM +0200, Sébastien Szymanski wrote:
> A few boards set clock frequency of their I2C buses with
> "clock_frequency" property. The right property is "clock-frequency".
>
> Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Applied, thanks.
^ permalink raw reply
* Re: [PATCH] arm64: dts: imx8mq: Default parents for PCIE1 clocks
From: Shawn Guo @ 2019-07-22 6:48 UTC (permalink / raw)
To: Abel Vesa
Cc: Rob Herring, Mark Rutland, Leonard Crestez, Andrey Smirnov,
Sascha Hauer, NXP Linux Team, linux-arm-kernel, devicetree,
Linux Kernel Mailing List
In-Reply-To: <1562235864-12953-1-git-send-email-abel.vesa@nxp.com>
On Thu, Jul 04, 2019 at 01:24:24PM +0300, Abel Vesa wrote:
> Set default parents for PCIE1_CTRL and PCIE1_PHY clocks.
Can you add a few words about why this change is necessary?
Shawn
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> index e3df9b8..23bf85f 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> @@ -235,6 +235,10 @@
> <&clk IMX8MQ_CLK_PCIE1_PHY>,
> <&pcie0_refclk>;
> clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> + assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>,
> + <&clk IMX8MQ_CLK_PCIE1_PHY>;
> + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
> + <&clk IMX8MQ_SYS2_PLL_100M>;
> status = "okay";
> };
>
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH arm64/dts 1/1] arm64: dts: imx8qxp: add lpuart baud clock
From: Shawn Guo @ 2019-07-22 6:46 UTC (permalink / raw)
To: fugang.duan; +Cc: devicetree, daniel.baluta, festevam, linux-arm-kernel
In-Reply-To: <20190704100443.10957-1-fugang.duan@nxp.com>
On Thu, Jul 04, 2019 at 06:04:43PM +0800, fugang.duan@nxp.com wrote:
> From: Fugang Duan <fugang.duan@nxp.com>
>
> Add imx8qxp lpuart baud clock.
>
> Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 23 +++++++++++++++--------
> 1 file changed, 15 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index 05fa0b7..4402b2e 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -30,6 +30,9 @@
> mmc2 = &usdhc3;
> mu1 = &lsio_mu1;
> serial0 = &adma_lpuart0;
> + serial1 = &adma_lpuart1;
> + serial2 = &adma_lpuart2;
> + serial3 = &adma_lpuart3;
This is not about adding baud clock, right? Please either mention the
change in the commit log, or have it as a separate patch.
Shawn
> };
>
> cpus {
> @@ -209,8 +212,9 @@
> reg = <0x5a060000 0x1000>;
> interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-parent = <&gic>;
> - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>;
> - clock-names = "ipg";
> + clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>,
> + <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>;
> + clock-names = "ipg", "baud";
> power-domains = <&pd IMX_SC_R_UART_0>;
> status = "disabled";
> };
> @@ -220,8 +224,9 @@
> reg = <0x5a070000 0x1000>;
> interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-parent = <&gic>;
> - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
> - clock-names = "ipg";
> + clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>,
> + <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
> + clock-names = "ipg", "baud";
> power-domains = <&pd IMX_SC_R_UART_1>;
> status = "disabled";
> };
> @@ -231,8 +236,9 @@
> reg = <0x5a080000 0x1000>;
> interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-parent = <&gic>;
> - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
> - clock-names = "ipg";
> + clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>,
> + <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
> + clock-names = "ipg", "baud";
> power-domains = <&pd IMX_SC_R_UART_2>;
> status = "disabled";
> };
> @@ -242,8 +248,9 @@
> reg = <0x5a090000 0x1000>;
> interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-parent = <&gic>;
> - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
> - clock-names = "ipg";
> + clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>,
> + <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
> + clock-names = "ipg", "baud";
> power-domains = <&pd IMX_SC_R_UART_3>;
> status = "disabled";
> };
> --
> 2.7.4
>
^ permalink raw reply
* Re: [Question] orphan platform data header
From: Enrico Weigelt, metux IT consult @ 2019-07-22 6:46 UTC (permalink / raw)
To: Arnd Bergmann, Masahiro Yamada
Cc: DTML, Greg Kroah-Hartman, Linux Kernel Mailing List, Ben Dooks,
Linus Torvalds, linux-arm-kernel
In-Reply-To: <CAK8P3a133ekPqkLWfC2ee0mT3iLbFzSjJ9FDokSyaX+hMVigKA@mail.gmail.com>
On 21.07.19 16:15, Arnd Bergmann wrote:
> That is different: the hardware attaches to a serial port and may well
> be usable, and the user space side just contains a copy of the header,
> see https://github.com/nwdigitalradio/ax25-tools/tree/master/yamdrv
I believe that such header copies in userland applications are
conceptionally wrong. Whenever something changes, both sides need
to be kept in sync.
Maybe we should talk to the hamradio folks to get this cleaned up.
IMHO, this header should go to uapi.
> It seems more useful to keep looking for drivers with a platform_data
> header file that is no longer included by any platform for candidates
> that may be obsolete.
Some folks see platform_data old legacy that should be removed, but I
don't aggree. For example w/ apu2 board driver (and corresponding
amd-fch-gpio driver) I even had to introduce a pdata struct, so the
board driver could configure the gpio driver. Certainly, I would have
preferred doing everything via DT, but that's not available on x86/acpi
targets (if anybody knows a way to inject a DT snippet just for one
driver in such a scenario, please let me know).
--mtx
--
Enrico Weigelt, metux IT consult
Free software and Linux embedded engineering
info@metux.net -- +49-151-27565287
^ permalink raw reply
* Re: [PATCH 3/3] arm64: defconfig: Build imx8 ddr pmu as module
From: Shawn Guo @ 2019-07-22 6:41 UTC (permalink / raw)
To: Leonard Crestez
Cc: Mark Rutland, Dong Aisheng, Jacky Bai, devicetree, Andrey Smirnov,
Frank Li, Rob Herring, linux-imx, kernel, Fabio Estevam,
Will Deacon, linux-arm-kernel
In-Reply-To: <e51a2f95044f0a9003c3be2e82c3c4b2653670a7.1562230183.git.leonard.crestez@nxp.com>
On Thu, Jul 04, 2019 at 11:53:22AM +0300, Leonard Crestez wrote:
> This is available on all imx8 but is not "boot critical" in any way so
> build as a module.
>
> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Applied, thanks.
^ permalink raw reply
* Re: [PATCH 2/3] arm64: dts: imx8m: Add ddr-pmu nodes
From: Shawn Guo @ 2019-07-22 6:40 UTC (permalink / raw)
To: Leonard Crestez
Cc: Will Deacon, Frank Li, Rob Herring, Andrey Smirnov, Mark Rutland,
Dong Aisheng, Fabio Estevam, Jacky Bai, devicetree, kernel,
linux-imx, linux-arm-kernel
In-Reply-To: <b8aeb9caf6c2380a7c8f65b19e420e18498d5c1a.1562230183.git.leonard.crestez@nxp.com>
On Thu, Jul 04, 2019 at 11:53:21AM +0300, Leonard Crestez wrote:
> The same ddr perfomance counter IP from 8qxp is also available on imx8m
> series so add it to dts.
>
> Tested with `perf stat` and `memtester` on imx8mm-evk and obtained
> plausible results.
>
> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Applied, thanks.
^ permalink raw reply
* Re: [PATCH V6 09/21] clk: tegra: clk-super: Fix to enable PLLP branches to CPU
From: Dmitry Osipenko @ 2019-07-22 6:32 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <7933a83c-3208-b551-d41d-70285ae528e3@nvidia.com>
22.07.2019 6:17, Sowjanya Komatineni пишет:
>
> On 7/21/19 3:39 PM, Sowjanya Komatineni wrote:
>>
>> On 7/21/19 2:16 PM, Dmitry Osipenko wrote:
>>> 21.07.2019 22:40, Sowjanya Komatineni пишет:
>>>> This patch has a fix to enable PLLP branches to CPU before changing
>>>> the CPU clusters clock source to PLLP for Gen5 Super clock.
>>>>
>>>> During system suspend entry and exit, CPU source will be switched
>>>> to PLLP and this needs PLLP branches to be enabled to CPU prior to
>>>> the switch.
>>>>
>>>> On system resume, warmboot code enables PLLP branches to CPU and
>>>> powers up the CPU with PLLP clock source.
>>>>
>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>> ---
>>>> drivers/clk/tegra/clk-super.c | 11 +++++++++++
>>>> drivers/clk/tegra/clk-tegra-super-gen4.c | 4 ++--
>>>> drivers/clk/tegra/clk.h | 4 ++++
>>>> 3 files changed, 17 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/clk/tegra/clk-super.c
>>>> b/drivers/clk/tegra/clk-super.c
>>>> index 39ef31b46df5..d73c587e4853 100644
>>>> --- a/drivers/clk/tegra/clk-super.c
>>>> +++ b/drivers/clk/tegra/clk-super.c
>>>> @@ -28,6 +28,9 @@
>>>> #define super_state_to_src_shift(m, s) ((m->width * s))
>>>> #define super_state_to_src_mask(m) (((1 << m->width) - 1))
>>>> +#define CCLK_SRC_PLLP_OUT0 4
>>>> +#define CCLK_SRC_PLLP_OUT4 5
>>>> +
>>>> static u8 clk_super_get_parent(struct clk_hw *hw)
>>>> {
>>>> struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
>>>> @@ -97,6 +100,14 @@ static int clk_super_set_parent(struct clk_hw
>>>> *hw, u8 index)
>>>> if (index == mux->div2_index)
>>>> index = mux->pllx_index;
>>>> }
>>>> +
>>>> + /*
>>>> + * Enable PLLP branches to CPU before selecting PLLP source
>>>> + */
>>>> + if ((mux->flags & TEGRA_CPU_CLK) &&
>>>> + ((index == CCLK_SRC_PLLP_OUT0) || (index ==
>>>> CCLK_SRC_PLLP_OUT4)))
>>>> + tegra_clk_set_pllp_out_cpu(true);
>>> Should somewhere here be tegra_clk_set_pllp_out_cpu(false) when
>>> switching from PLLP?
>> PLLP may be used for other CPU clusters.
>
> Though to avoid flag and check needed to make sure other CPU is not
> using before disabling PLLP branch to CPU.
>
> But leaving it enabled shouldn't impact much as clock source mux is
> after this in design anyway.
>
> But can add as well if its clear that way.
The TRM doc says "The CPU subsystem supports a switch-cluster mode
meaning that only one of the clusters can be active at any given time".
Given that cluster-switching isn't supported in upstream, I don't think
that you need to care about the other cluster at all, at least for now.
The cluster-switching implementation in upstream is very complicated
because it requires a special "hotplugging" CPU governor, which
apparently no other platform needs.
[snip]
^ permalink raw reply
* Re: [PATCH 0/5] Add Bitmain BM1880 clock driver
From: Manivannan Sadhasivam @ 2019-07-22 6:20 UTC (permalink / raw)
To: sboyd, mturquette, robh+dt
Cc: linux-clk, linux-arm-kernel, linux-kernel, devicetree, haitao.suo,
darren.tsao, fisher.cheng, alec.lin
In-Reply-To: <20190705151440.20844-1-manivannan.sadhasivam@linaro.org>
On Fri, Jul 05, 2019 at 08:44:35PM +0530, Manivannan Sadhasivam wrote:
> Hello,
>
> This patchset adds common clock driver for Bitmain BM1880 SoC clock
> controller. The clock controller consists of gate, divider, mux
> and pll clocks with different compositions. Hence, the driver uses
> composite clock structure in place where multiple clocking units are
> combined together.
>
> This patchset also removes UART fixed clock and sources clocks from clock
> controller for Sophon Edge board where the driver has been validated.
>
Ping on this series.
Thanks,
Mani
> Thanks,
> Mani
>
> Manivannan Sadhasivam (5):
> dt-bindings: clock: Add Bitmain BM1880 SoC clock controller binding
> arm64: dts: bitmain: Add clock controller support for BM1880 SoC
> arm64: dts: bitmain: Source common clock for UART controllers
> clk: Add driver for Bitmain BM1880 SoC clock controller
> MAINTAINERS: Add entry for Bitmain BM1880 SoC clock driver
>
> .../bindings/clock/bitmain,bm1880-clk.txt | 47 +
> MAINTAINERS | 2 +
> .../boot/dts/bitmain/bm1880-sophon-edge.dts | 9 -
> arch/arm64/boot/dts/bitmain/bm1880.dtsi | 27 +
> drivers/clk/Kconfig | 6 +
> drivers/clk/Makefile | 1 +
> drivers/clk/clk-bm1880.c | 947 ++++++++++++++++++
> include/dt-bindings/clock/bm1880-clock.h | 82 ++
> 8 files changed, 1112 insertions(+), 9 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt
> create mode 100644 drivers/clk/clk-bm1880.c
> create mode 100644 include/dt-bindings/clock/bm1880-clock.h
>
> --
> 2.17.1
>
^ permalink raw reply
* Re: [PATCH V6 14/21] clk: tegra210: Add suspend and resume support
From: Dmitry Osipenko @ 2019-07-22 6:10 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <88da46d2-b90d-f57e-7611-b8653b56bdf6@nvidia.com>
22.07.2019 1:45, Sowjanya Komatineni пишет:
>
> On 7/21/19 2:38 PM, Dmitry Osipenko wrote:
>> 21.07.2019 22:40, Sowjanya Komatineni пишет:
>>> This patch adds support for clk: tegra210: suspend-resume.
>>>
>>> All the CAR controller settings are lost on suspend when core
>>> power goes off.
>>>
>>> This patch has implementation for saving and restoring all PLLs
>>> and clocks context during system suspend and resume to have the
>>> clocks back to same state for normal operation.
>>>
>>> Acked-by: Thierry Reding <treding@nvidia.com>
>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>> ---
>>> drivers/clk/tegra/clk-tegra210.c | 68
>>> ++++++++++++++++++++++++++++++++++++++--
>>> drivers/clk/tegra/clk.c | 14 +++++++++
>>> drivers/clk/tegra/clk.h | 1 +
>>> 3 files changed, 80 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/clk/tegra/clk-tegra210.c
>>> b/drivers/clk/tegra/clk-tegra210.c
>>> index 55a88c0824a5..68271873acc1 100644
>>> --- a/drivers/clk/tegra/clk-tegra210.c
>>> +++ b/drivers/clk/tegra/clk-tegra210.c
>>> @@ -9,6 +9,7 @@
>>> #include <linux/clkdev.h>
>>> #include <linux/of.h>
>>> #include <linux/of_address.h>
>>> +#include <linux/syscore_ops.h>
>>> #include <linux/delay.h>
>>> #include <linux/export.h>
>>> #include <linux/mutex.h>
>>> @@ -220,11 +221,15 @@
>>> #define CLK_M_DIVISOR_SHIFT 2
>>> #define CLK_M_DIVISOR_MASK 0x3
>>> +#define CLK_MASK_ARM 0x44
>>> +#define MISC_CLK_ENB 0x48
>>> +
>>> #define RST_DFLL_DVCO 0x2f4
>>> #define DVFS_DFLL_RESET_SHIFT 0
>>> #define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8
>>> #define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac
>>> +#define CPU_SOFTRST_CTRL 0x380
>>> #define LVL2_CLK_GATE_OVRA 0xf8
>>> #define LVL2_CLK_GATE_OVRC 0x3a0
>>> @@ -2825,6 +2830,7 @@ static int tegra210_enable_pllu(void)
>>> struct tegra_clk_pll_freq_table *fentry;
>>> struct tegra_clk_pll pllu;
>>> u32 reg;
>>> + int ret;
>>> for (fentry = pll_u_freq_table; fentry->input_rate; fentry++) {
>>> if (fentry->input_rate == pll_ref_freq)
>>> @@ -2853,9 +2859,8 @@ static int tegra210_enable_pllu(void)
>>> reg |= PLL_ENABLE;
>>> writel(reg, clk_base + PLLU_BASE);
>>> - readl_relaxed_poll_timeout_atomic(clk_base + PLLU_BASE, reg,
>>> - reg & PLL_BASE_LOCK, 2, 1000);
>>> - if (!(reg & PLL_BASE_LOCK)) {
>>> + ret = tegra210_wait_for_mask(&pllu, PLLU_BASE, PLL_BASE_LOCK);
>>> + if (ret) {
>> Why this is needed? Was there a bug?
>>
> during resume pllu init is needed and to use same terga210_init_pllu,
> poll_timeout_atomic can't be used as its ony for atomic context.
>
> So changed to use wait_for_mask which should work in both cases.
Atomic variant could be used from any context, not sure what do you
mean. The 'atomic' part only means that function won't cause scheduling
and that's it.
>>> pr_err("Timed out waiting for PLL_U to lock\n");
>>> return -ETIMEDOUT;
>>> }
>>> @@ -3288,6 +3293,56 @@ static void tegra210_disable_cpu_clock(u32 cpu)
>>> }
>>> #ifdef CONFIG_PM_SLEEP
>>> +#define car_readl(_base, _off) readl_relaxed(clk_base + (_base) +
>>> ((_off) * 4))
>>> +#define car_writel(_val, _base, _off) \
>>> + writel_relaxed(_val, clk_base + (_base) + ((_off) * 4))
>>> +
>>> +static u32 spare_reg_ctx, misc_clk_enb_ctx, clk_msk_arm_ctx;
>>> +static u32 cpu_softrst_ctx[3];
>>> +
>>> +static int tegra210_clk_suspend(void)
>>> +{
>>> + unsigned int i;
>>> +
>>> + clk_save_context();
>>> +
>>> + /*
>>> + * save the bootloader configured clock registers SPARE_REG0,
>>> + * MISC_CLK_ENB, CLK_MASK_ARM, CPU_SOFTRST_CTRL
>> Nit: Start all multi-line comments with a capital letter and put dot in
>> the end of sentence.
>>
>>> + */
>>> + spare_reg_ctx = readl_relaxed(clk_base + SPARE_REG0);
>>> + misc_clk_enb_ctx = readl_relaxed(clk_base + MISC_CLK_ENB);
>>> + clk_msk_arm_ctx = readl_relaxed(clk_base + CLK_MASK_ARM);
>>> +
>>> + for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++)
>>> + cpu_softrst_ctx[i] = car_readl(CPU_SOFTRST_CTRL, i);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static void tegra210_clk_resume(void)
>>> +{
>>> + unsigned int i;
>>> +
>>> + tegra_clk_osc_resume(clk_base);
>>> +
>>> + /*
>>> + * restore the bootloader configured clock registers SPARE_REG0,
>>> + * MISC_CLK_ENB, CLK_MASK_ARM, CPU_SOFTRST_CTRL from saved context.
>> Same here.
>>
>>> + */
>>> + writel_relaxed(spare_reg_ctx, clk_base + SPARE_REG0);
>>> + writel_relaxed(misc_clk_enb_ctx, clk_base + MISC_CLK_ENB);
>>> + writel_relaxed(clk_msk_arm_ctx, clk_base + CLK_MASK_ARM);
>>> +
>>> + for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++)
>>> + car_writel(cpu_softrst_ctx[i], CPU_SOFTRST_CTRL, i);
>>> +
>>> + fence_udelay(5, clk_base);
>>> +
>>> + tegra210_init_pllu();
>>> + clk_restore_context();
>>> +}
>>> +
>>> static void tegra210_cpu_clock_suspend(void)
>>> {
>>> /* switch coresite to clk_m, save off original source */
>>> @@ -3303,6 +3358,11 @@ static void tegra210_cpu_clock_resume(void)
>>> }
>>> #endif
>>> +static struct syscore_ops tegra_clk_syscore_ops = {
>>> + .suspend = tegra210_clk_suspend,
>>> + .resume = tegra210_clk_resume,
>>> +};
>>> +
>>> static struct tegra_cpu_car_ops tegra210_cpu_car_ops = {
>>> .wait_for_reset = tegra210_wait_cpu_in_reset,
>>> .disable_clock = tegra210_disable_cpu_clock,
>>> @@ -3587,5 +3647,7 @@ static void __init tegra210_clock_init(struct
>>> device_node *np)
>>> tegra210_mbist_clk_init();
>>> tegra_cpu_car_ops = &tegra210_cpu_car_ops;
>>> +
>>> + register_syscore_ops(&tegra_clk_syscore_ops);
>>> }
>>> CLK_OF_DECLARE(tegra210, "nvidia,tegra210-car", tegra210_clock_init);
>>> diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
>>> index 573e3c967ae1..eb08047fd02f 100644
>>> --- a/drivers/clk/tegra/clk.c
>>> +++ b/drivers/clk/tegra/clk.c
>>> @@ -23,6 +23,7 @@
>>> #define CLK_OUT_ENB_W 0x364
>>> #define CLK_OUT_ENB_X 0x280
>>> #define CLK_OUT_ENB_Y 0x298
>>> +#define CLK_ENB_PLLP_OUT_CPU BIT(31)
>>> #define CLK_OUT_ENB_SET_L 0x320
>>> #define CLK_OUT_ENB_CLR_L 0x324
>>> #define CLK_OUT_ENB_SET_H 0x328
>>> @@ -199,6 +200,19 @@ const struct tegra_clk_periph_regs
>>> *get_reg_bank(int clkid)
>>> }
>>> }
>>> +void tegra_clk_set_pllp_out_cpu(bool enable)
>>> +{
>>> + u32 val;
>>> +
>>> + val = readl_relaxed(clk_base + CLK_OUT_ENB_Y);
>>> + if (enable)
>>> + val |= CLK_ENB_PLLP_OUT_CPU;
>>> + else
>>> + val &= ~CLK_ENB_PLLP_OUT_CPU;
>>> +
>>> + writel_relaxed(val, clk_base + CLK_OUT_ENB_Y);
>>> +}
>>> +
>>> struct clk ** __init tegra_clk_init(void __iomem *regs, int num,
>>> int banks)
>>> {
>>> clk_base = regs;
>>> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
>>> index 562a3ee2d537..0ffa763c755b 100644
>>> --- a/drivers/clk/tegra/clk.h
>>> +++ b/drivers/clk/tegra/clk.h
>>> @@ -863,6 +863,7 @@ int div_frac_get(unsigned long rate, unsigned
>>> parent_rate, u8 width,
>>> u8 frac_width, u8 flags);
>>> void tegra_clk_sync_state_pll(struct clk_hw *hw);
>>> void tegra_clk_osc_resume(void __iomem *clk_base);
>>> +void tegra_clk_set_pllp_out_cpu(bool enable);
>>> /* Combined read fence with delay */
>>> #define fence_udelay(delay, reg) \
>>>
^ permalink raw reply
* Re: [PATCH] of/fdt: Make sure no-map does not remove already reserved regions
From: Nicolas Boichat @ 2019-07-22 5:53 UTC (permalink / raw)
To: Florian Fainelli
Cc: Rob Herring, KarimAllah Ahmed, Frank Rowand, devicetree,
linux-kernel@vger.kernel.org, Ian Campbell, Grant Likely,
Stephen Boyd
In-Reply-To: <421844aa-cf68-d4d2-f02d-aefaf8954fdf@gmail.com>
On Wed, Jul 17, 2019 at 7:17 AM Florian Fainelli <f.fainelli@gmail.com> wrote:
>
> On 7/16/19 4:12 PM, Rob Herring wrote:
> > On Tue, Jul 16, 2019 at 4:46 PM Florian Fainelli <f.fainelli@gmail.com> wrote:
> >>
> >> On 7/2/19 10:08 PM, Nicolas Boichat wrote:
> >>> If the device tree is incorrectly configured, and attempts to
> >>> define a "no-map" reserved memory that overlaps with the kernel
> >>> data/code, the kernel would crash quickly after boot, with no
> >>> obvious clue about the nature of the issue.
> >>>
> >>> For example, this would happen if we have the kernel mapped at
> >>> these addresses (from /proc/iomem):
> >>> 40000000-41ffffff : System RAM
> >>> 40080000-40dfffff : Kernel code
> >>> 40e00000-411fffff : reserved
> >>> 41200000-413e0fff : Kernel data
> >>>
> >>> And we declare a no-map shared-dma-pool region at a fixed address
> >>> within that range:
> >>> mem_reserved: mem_region {
> >>> compatible = "shared-dma-pool";
> >>> reg = <0 0x40000000 0 0x01A00000>;
> >>> no-map;
> >>> };
> >>>
> >>> To fix this, when removing memory regions at early boot (which is
> >>> what "no-map" regions do), we need to make sure that the memory
> >>> is not already reserved. If we do, __reserved_mem_reserve_reg
> >>> will throw an error:
> >>> [ 0.000000] OF: fdt: Reserved memory: failed to reserve memory
> >>> for node 'mem_region': base 0x0000000040000000, size 26 MiB
> >>> and the code that will try to use the region should also fail,
> >>> later on.
> >>>
> >>> We do not do anything for non-"no-map" regions, as memblock
> >>> explicitly allows reserved regions to overlap, and the commit
> >>> that this fixes removed the check for that precise reason.
> >>>
> >>> Fixes: 094cb98179f19b7 ("of/fdt: memblock_reserve /memreserve/ regions in the case of partial overlap")
> >>> Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
> >>> ---
> >>> drivers/of/fdt.c | 10 +++++++++-
> >>> 1 file changed, 9 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
> >>> index cd17dc62a71980a..a1ded43fc332d0c 100644
> >>> --- a/drivers/of/fdt.c
> >>> +++ b/drivers/of/fdt.c
> >>> @@ -1138,8 +1138,16 @@ int __init __weak early_init_dt_mark_hotplug_memory_arch(u64 base, u64 size)
> >>> int __init __weak early_init_dt_reserve_memory_arch(phys_addr_t base,
> >>> phys_addr_t size, bool nomap)
> >>> {
> >>> - if (nomap)
> >>> + if (nomap) {
> >>> + /*
> >>> + * If the memory is already reserved (by another region), we
> >>> + * should not allow it to be removed altogether.
> >>> + */
> >>> + if (memblock_is_region_reserved(base, size))
> >>> + return -EBUSY;
> >>> +
> >>> return memblock_remove(base, size);
> >>
> >> While you are it, the nomap argument (introduced with
> >> e8d9d1f5485b52ec3c4d7af839e6914438f6c285) predates the introduction of
> >> memblock_is_nomap() (bf3d3cc580f9960883ebf9ea05868f336d9491c2), so
> >> should just remove memblock_remove() and use memblock_mark_nomap()
> >> instead here.
> >
> > Perhaps like this patch[1]? Though the reasoning is different and the
> > commit message here is more thorough, so can I get a combined patch.
>
> From a quick reading it does look like memblock_isolate_range(), as
> called by memblock_setclr_flag() should be able to detect this region
> was already reserved, though I have not tried it.
I quickly tested it, and just using memblock_mark_nomap does not seem
be be enough (the call does not fail, and the nomap memory is still
allocated).
> > However, I don't under how handling a misconfigured DT and aligned
> > with EFI are the same patch. What's considered valid for EFI is not
> > for DT regions?
>
> That I don't know how to answer.
> --
> Florian
^ permalink raw reply
* Re: [PATCHv8 5/5] coresight: cpu-debug: Add support for Qualcomm Kryo
From: Sai Prakash Ranjan @ 2019-07-22 5:48 UTC (permalink / raw)
To: Leo Yan, Mathieu Poirier
Cc: Greg Kroah-Hartman, Suzuki K Poulose, Alexander Shishkin,
Mike Leach, Rob Herring, Bjorn Andersson, devicetree, David Brown,
Mark Rutland, Rajendra Nayak, Vivek Gautam, Sibi Sankar,
linux-arm-kernel, linux-kernel, linux-arm-msm, Marc Gonzalez
In-Reply-To: <20190721143553.GA25136@leoy-ThinkPad-X240s>
On 7/21/2019 8:05 PM, Leo Yan wrote:
> On Wed, Jul 17, 2019 at 10:56:02AM -0600, Mathieu Poirier wrote:
>> On Fri, Jul 12, 2019 at 07:46:27PM +0530, Sai Prakash Ranjan wrote:
>>> Add support for coresight CPU debug module on Qualcomm
>>> Kryo CPUs. This patch adds the UCI entries for Kryo CPUs
>>> found on MSM8996 which shares the same PIDs as ETMs.
>>>
>>> Without this, below error is observed on MSM8996:
>>>
>>> [ 5.429867] OF: graph: no port node found in /soc/debug@3810000
>>> [ 5.429938] coresight-etm4x: probe of 3810000.debug failed with error -22
>>> [ 5.435415] coresight-cpu-debug 3810000.debug: Coresight debug-CPU0 initialized
>>> [ 5.446474] OF: graph: no port node found in /soc/debug@3910000
>>> [ 5.448927] coresight-etm4x: probe of 3910000.debug failed with error -22
>>> [ 5.454681] coresight-cpu-debug 3910000.debug: Coresight debug-CPU1 initialized
>>> [ 5.487765] OF: graph: no port node found in /soc/debug@3a10000
>>> [ 5.488007] coresight-etm4x: probe of 3a10000.debug failed with error -22
>>> [ 5.493024] coresight-cpu-debug 3a10000.debug: Coresight debug-CPU2 initialized
>>> [ 5.501802] OF: graph: no port node found in /soc/debug@3b10000
>>> [ 5.512901] coresight-etm4x: probe of 3b10000.debug failed with error -22
>>> [ 5.513192] coresight-cpu-debug 3b10000.debug: Coresight debug-CPU3 initialized
>>>
>>> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
>>> ---
>>> .../hwtracing/coresight/coresight-cpu-debug.c | 33 +++++++++----------
>>> drivers/hwtracing/coresight/coresight-priv.h | 10 +++---
>>> 2 files changed, 21 insertions(+), 22 deletions(-)
>>>
>>> diff --git a/drivers/hwtracing/coresight/coresight-cpu-debug.c b/drivers/hwtracing/coresight/coresight-cpu-debug.c
>>> index 2463aa7ab4f6..96544b348c27 100644
>>> --- a/drivers/hwtracing/coresight/coresight-cpu-debug.c
>>> +++ b/drivers/hwtracing/coresight/coresight-cpu-debug.c
>>> @@ -646,24 +646,23 @@ static int debug_remove(struct amba_device *adev)
>>> return 0;
>>> }
>>>
>>> +static const struct amba_cs_uci_id uci_id_debug[] = {
>>> + {
>>> + /* CPU Debug UCI data */
>>> + .devarch = 0x47706a15,
>>> + .devarch_mask = 0xfff0ffff,
>>> + .devtype = 0x00000015,
>>> + }
>>> +};
>>> +
>>> static const struct amba_id debug_ids[] = {
>>> - { /* Debug for Cortex-A53 */
>>> - .id = 0x000bbd03,
>>> - .mask = 0x000fffff,
>>> - },
>>> - { /* Debug for Cortex-A57 */
>>> - .id = 0x000bbd07,
>>> - .mask = 0x000fffff,
>>> - },
>>> - { /* Debug for Cortex-A72 */
>>> - .id = 0x000bbd08,
>>> - .mask = 0x000fffff,
>>> - },
>>> - { /* Debug for Cortex-A73 */
>>> - .id = 0x000bbd09,
>>> - .mask = 0x000fffff,
>>> - },
>>> - { 0, 0 },
>>> + CS_AMBA_ID(0x000bbd03), /* Cortex-A53 */
>>> + CS_AMBA_ID(0x000bbd07), /* Cortex-A57 */
>>> + CS_AMBA_ID(0x000bbd08), /* Cortex-A72 */
>>> + CS_AMBA_ID(0x000bbd09), /* Cortex-A73 */
>>> + CS_AMBA_UCI_ID(0x000f0205, uci_id_debug), /* Qualcomm Kryo */
>>> + CS_AMBA_UCI_ID(0x000f0211, uci_id_debug), /* Qualcomm Kryo */
>>> + {},
>>> };
>>>
>>> static struct amba_driver debug_driver = {
>>> diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
>>> index 7d401790dd7e..41ae5863104d 100644
>>> --- a/drivers/hwtracing/coresight/coresight-priv.h
>>> +++ b/drivers/hwtracing/coresight/coresight-priv.h
>>> @@ -185,11 +185,11 @@ static inline int etm_writel_cp14(u32 off, u32 val) { return 0; }
>>> }
>>>
>>> /* coresight AMBA ID, full UCI structure: id table entry. */
>>> -#define CS_AMBA_UCI_ID(pid, uci_ptr) \
>>> - { \
>>> - .id = pid, \
>>> - .mask = 0x000fffff, \
>>> - .data = uci_ptr \
>>> +#define CS_AMBA_UCI_ID(pid, uci_ptr) \
>>> + { \
>>> + .id = pid, \
>>> + .mask = 0x000fffff, \
>>> + .data = (void *)uci_ptr \
>>> }
>>
>> I will pickup this patch - it will show up in my next tree when rc1 comes out.
>
> I tested this patch on the mainline kernel with latest commit
> f1a3b43cc1f5 ("Merge branch 'for-linus' of
> git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input"). FWIW:
>
> Tested-by: Leo Yan <leo.yan@linaro.org>
>
> P.s. Acutally I tested this patch for 5.2-rcx a few days ago and found
> a regression for CPU debug module: I observed the CPU debug module
> panic dump will stuck. After I pulled to latest kernel code base the
> CPU debug module can work well; also works well with this patch. F.Y.I.
>
Thanks Leo.
-Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply
* Re: [PATCH v4 0/5] soc: ti: k3: Allow for exclusive and shared device requests
From: Lokesh Vutla @ 2019-07-22 5:11 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Rob Herring
Cc: Device Tree Mailing List, Sekhar Nori, Linux ARM Mailing List
In-Reply-To: <20190722050757.29893-1-lokeshvutla@ti.com>
On 22/07/19 10:37 AM, Lokesh Vutla wrote:
> Sysfw provides an option for requesting exclusive access for a
> device using the flags MSG_FLAG_DEVICE_EXCLUSIVE. If this flag is
> not used, the device is meant to be shared across hosts. Once a device
> is requested from a host with this flag set, any request to this
> device from a different host will be nacked by sysfw.
>
> Current tisci firmware and pm drivers always requests for device with
> exclusive permissions set. But this is not be true for certain devices
> that are expcted to be shared across different host contexts.
> So add support for getting the shared or exclusive permissions from DT
> and request firmware accordingly.
Tested Boot log:
AM65x-base-board: https://pastebin.ubuntu.com/p/T5fSNrrFCV/
J721e-common-proc-board: https://pastebin.ubuntu.com/p/9fXzCR596n/
Thanks and regards,
Lokesh
^ permalink raw reply
* [PATCH v4 5/5] arm64: dts: ti: k3-j721e: Update the power domain cells
From: Lokesh Vutla @ 2019-07-22 5:07 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Rob Herring
Cc: Sekhar Nori, Linux ARM Mailing List, Device Tree Mailing List,
Lokesh Vutla
In-Reply-To: <20190722050757.29893-1-lokeshvutla@ti.com>
Update the power-domain cells to 2 and mark all devices as
exclusive. Main uart 0 is the debug console for processor boards
and it is used by different software entities like u-boot, atf,
linux simultaneously. So just mark main_uart0 as shared device
for common processor board.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
.../dts/ti/k3-j721e-common-proc-board.dts | 4 ++++
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 20 +++++++++----------
.../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 6 +++---
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 +
4 files changed, 18 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index c680123f067c..63b47b839388 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -19,6 +19,10 @@
status = "disabled";
};
+&main_uart0 {
+ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+};
+
&main_uart3 {
/* UART not brought out */
status = "disabled";
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index a01308142f77..01661c22c39d 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -119,7 +119,7 @@
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 146>;
+ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 146 0>;
clock-names = "fclk";
};
@@ -132,7 +132,7 @@
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 278>;
+ power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 278 0>;
clock-names = "fclk";
};
@@ -145,7 +145,7 @@
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 279>;
+ power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 279 0>;
clock-names = "fclk";
};
@@ -158,7 +158,7 @@
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 280>;
+ power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 280 0>;
clock-names = "fclk";
};
@@ -171,7 +171,7 @@
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 281>;
+ power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 281 0>;
clock-names = "fclk";
};
@@ -184,7 +184,7 @@
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 282>;
+ power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 282 0>;
clock-names = "fclk";
};
@@ -197,7 +197,7 @@
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 283>;
+ power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 283 0>;
clock-names = "fclk";
};
@@ -210,7 +210,7 @@
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 284>;
+ power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 284 0>;
clock-names = "fclk";
};
@@ -223,7 +223,7 @@
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 285>;
+ power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 285 0>;
clock-names = "fclk";
};
@@ -236,7 +236,7 @@
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 286>;
+ power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 286 0>;
clock-names = "fclk";
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
index 07b58eeebceb..e616c2481f51 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -20,7 +20,7 @@
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
- #power-domain-cells = <1>;
+ #power-domain-cells = <2>;
};
k3_clks: clocks {
@@ -59,7 +59,7 @@
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 287>;
+ power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 287 0>;
clock-names = "fclk";
};
@@ -72,7 +72,7 @@
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <96000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 149>;
+ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 149 0>;
clock-names = "fclk";
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index f8dd74b17bfb..43ea1ba97922 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
/ {
model = "Texas Instruments K3 J721E SoC";
--
2.21.0
^ permalink raw reply related
* [PATCH v4 4/5] arm64: dts: ti: k3-am654: Update the power domain cells
From: Lokesh Vutla @ 2019-07-22 5:07 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Rob Herring
Cc: Lokesh Vutla, Device Tree Mailing List, Sekhar Nori,
Linux ARM Mailing List
In-Reply-To: <20190722050757.29893-1-lokeshvutla@ti.com>
Update the power-domain cells to 2 and mark all devices as
exclusive. Main uart 0 is the debug console for based boards
and it is used by different software entities like u-boot, atf,
linux. So just mark main_uart0 as shared device for base board.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 44 +++++++++----------
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 10 ++---
arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 6 +--
arch/arm64/boot/dts/ti/k3-am65.dtsi | 1 +
.../arm64/boot/dts/ti/k3-am654-base-board.dts | 1 +
5 files changed, 32 insertions(+), 30 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index ca70ff73f171..12a977f1ab87 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -67,7 +67,7 @@
reg = <0x0 0x900000 0x0 0x2000>;
reg-names = "serdes";
#phy-cells = <2>;
- power-domains = <&k3_pds 153>;
+ power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
@@ -82,7 +82,7 @@
reg = <0x0 0x910000 0x0 0x2000>;
reg-names = "serdes";
#phy-cells = <2>;
- power-domains = <&k3_pds 154>;
+ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
@@ -100,7 +100,7 @@
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 146>;
+ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
};
main_uart1: serial@2810000 {
@@ -110,7 +110,7 @@
reg-io-width = <4>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- power-domains = <&k3_pds 147>;
+ power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
};
main_uart2: serial@2820000 {
@@ -120,7 +120,7 @@
reg-io-width = <4>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- power-domains = <&k3_pds 148>;
+ power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
};
main_pmx0: pinmux@11c000 {
@@ -147,7 +147,7 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 110 1>;
- power-domains = <&k3_pds 110>;
+ power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c1: i2c@2010000 {
@@ -158,7 +158,7 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 111 1>;
- power-domains = <&k3_pds 111>;
+ power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c2: i2c@2020000 {
@@ -169,7 +169,7 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 112 1>;
- power-domains = <&k3_pds 112>;
+ power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c3: i2c@2030000 {
@@ -180,14 +180,14 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 113 1>;
- power-domains = <&k3_pds 113>;
+ power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
};
ecap0: pwm@3100000 {
compatible = "ti,am654-ecap", "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x0 0x03100000 0x0 0x60>;
- power-domains = <&k3_pds 39>;
+ power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 39 0>;
clock-names = "fck";
};
@@ -197,7 +197,7 @@
reg = <0x0 0x2100000 0x0 0x400>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 137 1>;
- power-domains = <&k3_pds 137>;
+ power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
@@ -207,7 +207,7 @@
reg = <0x0 0x2110000 0x0 0x400>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 138 1>;
- power-domains = <&k3_pds 138>;
+ power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
assigned-clocks = <&k3_clks 137 1>;
@@ -219,7 +219,7 @@
reg = <0x0 0x2120000 0x0 0x400>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 139 1>;
- power-domains = <&k3_pds 139>;
+ power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
@@ -229,7 +229,7 @@
reg = <0x0 0x2130000 0x0 0x400>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 140 1>;
- power-domains = <&k3_pds 140>;
+ power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
@@ -239,7 +239,7 @@
reg = <0x0 0x2140000 0x0 0x400>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 141 1>;
- power-domains = <&k3_pds 141>;
+ power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
@@ -247,7 +247,7 @@
sdhci0: sdhci@4f80000 {
compatible = "ti,am654-sdhci-5.1";
reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
- power-domains = <&k3_pds 47>;
+ power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
clock-names = "clk_ahb", "clk_xin";
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
@@ -306,7 +306,7 @@
ranges = <0x0 0x0 0x4000000 0x20000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
- power-domains = <&k3_pds 151>;
+ power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
<&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
@@ -345,7 +345,7 @@
ranges = <0x0 0x0 0x4020000 0x20000>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
- power-domains = <&k3_pds 152>;
+ power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 152 2>;
assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
@@ -451,7 +451,7 @@
compatible = "ti,am654-pcie-rc";
reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
reg-names = "app", "dbics", "config", "atu";
- power-domains = <&k3_pds 120>;
+ power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000
@@ -470,7 +470,7 @@
compatible = "ti,am654-pcie-ep";
reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
reg-names = "app", "dbics", "addr_space", "atu";
- power-domains = <&k3_pds 120>;
+ power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
ti,syscon-pcie-mode = <&pcie0_mode>;
num-ib-windows = <16>;
num-ob-windows = <16>;
@@ -483,7 +483,7 @@
compatible = "ti,am654-pcie-rc";
reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
reg-names = "app", "dbics", "config", "atu";
- power-domains = <&k3_pds 121>;
+ power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000
@@ -502,7 +502,7 @@
compatible = "ti,am654-pcie-ep";
reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
reg-names = "app", "dbics", "addr_space", "atu";
- power-domains = <&k3_pds 121>;
+ power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
ti,syscon-pcie-mode = <&pcie1_mode>;
num-ib-windows = <16>;
num-ob-windows = <16>;
diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
index afc29eaa2638..7bdf5342f58f 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
@@ -14,7 +14,7 @@
interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <96000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 149>;
+ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
};
mcu_ram: sram@41c00000 {
@@ -33,7 +33,7 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 114 1>;
- power-domains = <&k3_pds 114>;
+ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
};
mcu_spi0: spi@40300000 {
@@ -41,7 +41,7 @@
reg = <0x0 0x40300000 0x0 0x400>;
interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 142 1>;
- power-domains = <&k3_pds 142>;
+ power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
@@ -51,7 +51,7 @@
reg = <0x0 0x40310000 0x0 0x400>;
interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 143 1>;
- power-domains = <&k3_pds 143>;
+ power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
@@ -61,7 +61,7 @@
reg = <0x0 0x40320000 0x0 0x400>;
interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 144 1>;
- power-domains = <&k3_pds 144>;
+ power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
index 9cf2c0849a24..f4227e2743f2 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
@@ -20,7 +20,7 @@
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
- #power-domain-cells = <1>;
+ #power-domain-cells = <2>;
};
k3_clks: clocks {
@@ -50,7 +50,7 @@
interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 150>;
+ power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
};
wkup_i2c0: i2c@42120000 {
@@ -61,7 +61,7 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 115 1>;
- power-domains = <&k3_pds 115>;
+ power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
};
intr_wkup_gpio: interrupt-controller2 {
diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi
index 82edf10b2378..6dfccd5d56c8 100644
--- a/arch/arm64/boot/dts/ti/k3-am65.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
/ {
model = "Texas Instruments K3 AM654 SoC";
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index 52c245d36db9..1102b84f853d 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -151,6 +151,7 @@
&main_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
+ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};
&wkup_i2c0 {
--
2.21.0
^ permalink raw reply related
* [PATCH v4 3/5] soc: ti: ti_sci_pm_domains: Add support for exclusive and shared access
From: Lokesh Vutla @ 2019-07-22 5:07 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Rob Herring
Cc: Lokesh Vutla, Device Tree Mailing List, Sekhar Nori,
Linux ARM Mailing List
In-Reply-To: <20190722050757.29893-1-lokeshvutla@ti.com>
TISCI protocol supports for enabling the device either with exclusive
permissions for the requesting host or with sharing across the hosts.
There are certain devices which are exclusive to Linux context and
there are certain devices that are shared across different host contexts.
So add support for getting this information from DT by increasing
the power-domain cells to 2.
For keeping the DT backward compatibility intact, defaulting the
device permissions to set the exclusive flag set. In this case the
power-domain-cells is 1.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
drivers/soc/ti/ti_sci_pm_domains.c | 23 +++++++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/ti/ti_sci_pm_domains.c b/drivers/soc/ti/ti_sci_pm_domains.c
index 97817dd7ba24..8c2a2f23982c 100644
--- a/drivers/soc/ti/ti_sci_pm_domains.c
+++ b/drivers/soc/ti/ti_sci_pm_domains.c
@@ -15,15 +15,19 @@
#include <linux/pm_domain.h>
#include <linux/slab.h>
#include <linux/soc/ti/ti_sci_protocol.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
/**
* struct ti_sci_genpd_dev_data: holds data needed for every device attached
* to this genpd
* @idx: index of the device that identifies it with the system
* control processor.
+ * @exclusive: Permissions for exclusive request or shared request of the
+ * device.
*/
struct ti_sci_genpd_dev_data {
int idx;
+ u8 exclusive;
};
/**
@@ -55,6 +59,14 @@ static int ti_sci_dev_id(struct device *dev)
return sci_dev_data->idx;
}
+static u8 is_ti_sci_dev_exclusive(struct device *dev)
+{
+ struct generic_pm_domain_data *genpd_data = dev_gpd_data(dev);
+ struct ti_sci_genpd_dev_data *sci_dev_data = genpd_data->data;
+
+ return sci_dev_data->exclusive;
+}
+
/**
* ti_sci_dev_to_sci_handle(): get pointer to ti_sci_handle
* @dev: pointer to device associated with this genpd
@@ -79,7 +91,10 @@ static int ti_sci_dev_start(struct device *dev)
const struct ti_sci_handle *ti_sci = ti_sci_dev_to_sci_handle(dev);
int idx = ti_sci_dev_id(dev);
- return ti_sci->ops.dev_ops.get_device(ti_sci, idx);
+ if (is_ti_sci_dev_exclusive(dev))
+ return ti_sci->ops.dev_ops.get_device_exclusive(ti_sci, idx);
+ else
+ return ti_sci->ops.dev_ops.get_device(ti_sci, idx);
}
/**
@@ -110,7 +125,7 @@ static int ti_sci_pd_attach_dev(struct generic_pm_domain *domain,
if (ret < 0)
return ret;
- if (pd_args.args_count != 1)
+ if (pd_args.args_count != 1 && pd_args.args_count != 2)
return -EINVAL;
idx = pd_args.args[0];
@@ -128,6 +143,10 @@ static int ti_sci_pd_attach_dev(struct generic_pm_domain *domain,
return -ENOMEM;
sci_dev_data->idx = idx;
+ /* Enable the exclusive permissions by default */
+ sci_dev_data->exclusive = TI_SCI_PD_EXCLUSIVE;
+ if (pd_args.args_count == 2)
+ sci_dev_data->exclusive = pd_args.args[1] & 0x1;
genpd_data = dev_gpd_data(dev);
genpd_data->data = sci_dev_data;
--
2.21.0
^ permalink raw reply related
* [PATCH v4 2/5] dt-bindings: ti_sci_pm_domains: Add support for exclusive and shared access
From: Lokesh Vutla @ 2019-07-22 5:07 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Rob Herring
Cc: Lokesh Vutla, Device Tree Mailing List, Sekhar Nori,
Linux ARM Mailing List
In-Reply-To: <20190722050757.29893-1-lokeshvutla@ti.com>
TISCI protocol supports for enabling the device either with exclusive
permissions for the requesting host or with sharing across the hosts.
There are certain devices which are exclusive to Linux context and
there are certain devices that are shared across different host contexts.
So add support for getting this information from DT by increasing
the power-domain cells to 2.
Acked-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
.../devicetree/bindings/soc/ti/sci-pm-domain.txt | 11 +++++++++--
MAINTAINERS | 1 +
include/dt-bindings/soc/ti,sci_pm_domain.h | 9 +++++++++
3 files changed, 19 insertions(+), 2 deletions(-)
create mode 100644 include/dt-bindings/soc/ti,sci_pm_domain.h
diff --git a/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt b/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
index f7b00a7c0f68..f541d1f776a2 100644
--- a/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+++ b/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
@@ -19,8 +19,15 @@ child of the pmmc node.
Required Properties:
--------------------
- compatible: should be "ti,sci-pm-domain"
-- #power-domain-cells: Must be 1 so that an id can be provided in each
- device node.
+- #power-domain-cells: Can be one of the following:
+ 1: Containing the device id of each node
+ 2: First entry should be device id
+ Second entry should be one of the floowing:
+ TI_SCI_PD_EXCLUSIVE: To allow device to be
+ exclusively controlled by
+ the requesting hosts.
+ TI_SCI_PD_SHARED: To allow device to be shared
+ by multiple hosts.
Example (K2G):
-------------
diff --git a/MAINTAINERS b/MAINTAINERS
index 783569e3c4b4..ceb06e7ba6d1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15853,6 +15853,7 @@ F: drivers/firmware/ti_sci*
F: include/linux/soc/ti/ti_sci_protocol.h
F: Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
F: drivers/soc/ti/ti_sci_pm_domains.c
+F: include/dt-bindings/soc/ti,sci_pm_domain.h
F: Documentation/devicetree/bindings/reset/ti,sci-reset.txt
F: Documentation/devicetree/bindings/clock/ti,sci-clk.txt
F: drivers/clk/keystone/sci-clk.c
diff --git a/include/dt-bindings/soc/ti,sci_pm_domain.h b/include/dt-bindings/soc/ti,sci_pm_domain.h
new file mode 100644
index 000000000000..8f2a7360b65e
--- /dev/null
+++ b/include/dt-bindings/soc/ti,sci_pm_domain.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __DT_BINDINGS_TI_SCI_PM_DOMAIN_H
+#define __DT_BINDINGS_TI_SCI_PM_DOMAIN_H
+
+#define TI_SCI_PD_EXCLUSIVE 1
+#define TI_SCI_PD_SHARED 0
+
+#endif /* __DT_BINDINGS_TI_SCI_PM_DOMAIN_H */
--
2.21.0
^ permalink raw reply related
* [PATCH v4 1/5] firmware: ti_sci: Allow for device shared and exclusive requests
From: Lokesh Vutla @ 2019-07-22 5:07 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Rob Herring
Cc: Lokesh Vutla, Device Tree Mailing List, Sekhar Nori,
Linux ARM Mailing List
In-Reply-To: <20190722050757.29893-1-lokeshvutla@ti.com>
Sysfw provides an option for requesting exclusive access for a
device using the flags MSG_FLAG_DEVICE_EXCLUSIVE. If this flag is
not used, the device is meant to be shared across hosts. Once a device
is requested from a host with this flag set, any request to this
device from a different host will be nacked by sysfw. Current tisci
driver enables this flag for every device requests. But this may not
be true for all the devices. So provide a separate commands in driver
for exclusive and shared device requests.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
drivers/firmware/ti_sci.c | 45 ++++++++++++++++++++++++--
include/linux/soc/ti/ti_sci_protocol.h | 3 ++
2 files changed, 46 insertions(+), 2 deletions(-)
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index cdee0b45943d..4126be9e3216 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -635,6 +635,7 @@ static int ti_sci_get_device_state(const struct ti_sci_handle *handle,
/**
* ti_sci_cmd_get_device() - command to request for device managed by TISCI
+ * that can be shared with other hosts.
* @handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
* @id: Device Identifier
*
@@ -642,11 +643,29 @@ static int ti_sci_get_device_state(const struct ti_sci_handle *handle,
* usage count by balancing get_device with put_device. No refcounting is
* managed by driver for that purpose.
*
- * NOTE: The request is for exclusive access for the processor.
- *
* Return: 0 if all went fine, else return appropriate error.
*/
static int ti_sci_cmd_get_device(const struct ti_sci_handle *handle, u32 id)
+{
+ return ti_sci_set_device_state(handle, id, 0,
+ MSG_DEVICE_SW_STATE_ON);
+}
+
+/**
+ * ti_sci_cmd_get_device_exclusive() - command to request for device managed by
+ * TISCI that is exclusively owned by the
+ * requesting host.
+ * @handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
+ * @id: Device Identifier
+ *
+ * Request for the device - NOTE: the client MUST maintain integrity of
+ * usage count by balancing get_device with put_device. No refcounting is
+ * managed by driver for that purpose.
+ *
+ * Return: 0 if all went fine, else return appropriate error.
+ */
+static int ti_sci_cmd_get_device_exclusive(const struct ti_sci_handle *handle,
+ u32 id)
{
return ti_sci_set_device_state(handle, id,
MSG_FLAG_DEVICE_EXCLUSIVE,
@@ -665,6 +684,26 @@ static int ti_sci_cmd_get_device(const struct ti_sci_handle *handle, u32 id)
* Return: 0 if all went fine, else return appropriate error.
*/
static int ti_sci_cmd_idle_device(const struct ti_sci_handle *handle, u32 id)
+{
+ return ti_sci_set_device_state(handle, id, 0,
+ MSG_DEVICE_SW_STATE_RETENTION);
+}
+
+/**
+ * ti_sci_cmd_idle_device_exclusive() - Command to idle a device managed by
+ * TISCI that is exclusively owned by
+ * requesting host.
+ * @handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
+ * @id: Device Identifier
+ *
+ * Request for the device - NOTE: the client MUST maintain integrity of
+ * usage count by balancing get_device with put_device. No refcounting is
+ * managed by driver for that purpose.
+ *
+ * Return: 0 if all went fine, else return appropriate error.
+ */
+static int ti_sci_cmd_idle_device_exclusive(const struct ti_sci_handle *handle,
+ u32 id)
{
return ti_sci_set_device_state(handle, id,
MSG_FLAG_DEVICE_EXCLUSIVE,
@@ -2894,7 +2933,9 @@ static void ti_sci_setup_ops(struct ti_sci_info *info)
core_ops->reboot_device = ti_sci_cmd_core_reboot;
dops->get_device = ti_sci_cmd_get_device;
+ dops->get_device_exclusive = ti_sci_cmd_get_device_exclusive;
dops->idle_device = ti_sci_cmd_idle_device;
+ dops->idle_device_exclusive = ti_sci_cmd_idle_device_exclusive;
dops->put_device = ti_sci_cmd_put_device;
dops->is_valid = ti_sci_cmd_dev_is_valid;
diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h
index 6c610e188a44..9531ec823298 100644
--- a/include/linux/soc/ti/ti_sci_protocol.h
+++ b/include/linux/soc/ti/ti_sci_protocol.h
@@ -97,7 +97,10 @@ struct ti_sci_core_ops {
*/
struct ti_sci_dev_ops {
int (*get_device)(const struct ti_sci_handle *handle, u32 id);
+ int (*get_device_exclusive)(const struct ti_sci_handle *handle, u32 id);
int (*idle_device)(const struct ti_sci_handle *handle, u32 id);
+ int (*idle_device_exclusive)(const struct ti_sci_handle *handle,
+ u32 id);
int (*put_device)(const struct ti_sci_handle *handle, u32 id);
int (*is_valid)(const struct ti_sci_handle *handle, u32 id);
int (*get_context_loss_count)(const struct ti_sci_handle *handle,
--
2.21.0
^ permalink raw reply related
* [PATCH v4 0/5] soc: ti: k3: Allow for exclusive and shared device requests
From: Lokesh Vutla @ 2019-07-22 5:07 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Rob Herring
Cc: Lokesh Vutla, Device Tree Mailing List, Sekhar Nori,
Linux ARM Mailing List
Sysfw provides an option for requesting exclusive access for a
device using the flags MSG_FLAG_DEVICE_EXCLUSIVE. If this flag is
not used, the device is meant to be shared across hosts. Once a device
is requested from a host with this flag set, any request to this
device from a different host will be nacked by sysfw.
Current tisci firmware and pm drivers always requests for device with
exclusive permissions set. But this is not be true for certain devices
that are expcted to be shared across different host contexts.
So add support for getting the shared or exclusive permissions from DT
and request firmware accordingly.
Changes since v3: https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=103447
- Rebased on top of v5.3-rc1
- Updated power-domain cells for j721e.
- Mark the console uart as shared in am65x-base-board
- Added Reviewed-by from Rob
Lokesh Vutla (5):
firmware: ti_sci: Allow for device shared and exclusive requests
dt-bindings: ti_sci_pm_domains: Add support for exclusive and shared
access
soc: ti: ti_sci_pm_domains: Add support for exclusive and shared
access
arm64: dts: ti: k3-am654: Update the power domain cells
arm64: dts: ti: k3-j721e: Update the power domain cells
.../bindings/soc/ti/sci-pm-domain.txt | 11 ++++-
MAINTAINERS | 1 +
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 44 +++++++++---------
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 10 ++---
arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 6 +--
arch/arm64/boot/dts/ti/k3-am65.dtsi | 1 +
.../arm64/boot/dts/ti/k3-am654-base-board.dts | 1 +
.../dts/ti/k3-j721e-common-proc-board.dts | 4 ++
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 20 ++++-----
.../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 6 +--
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 +
drivers/firmware/ti_sci.c | 45 ++++++++++++++++++-
drivers/soc/ti/ti_sci_pm_domains.c | 23 +++++++++-
include/dt-bindings/soc/ti,sci_pm_domain.h | 9 ++++
include/linux/soc/ti/ti_sci_protocol.h | 3 ++
15 files changed, 136 insertions(+), 49 deletions(-)
create mode 100644 include/dt-bindings/soc/ti,sci_pm_domain.h
--
2.21.0
^ permalink raw reply
* RE: [PATCH v2 00/11] Arasan SDHCI enhancements and ZynqMP Tap Delays Handling
From: Manish Narani @ 2019-07-22 4:56 UTC (permalink / raw)
To: ulf.hansson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com,
heiko@sntech.de, Michal Simek, adrian.hunter@intel.com,
christoph.muellner@theobroma-systems.com,
philipp.tomsich@theobroma-systems.com, viresh.kumar@linaro.org,
scott.branden@broadcom.com, ayaka@soulik.info, kernel@esmil.dk,
tony.xie@rock-chips.com, mdf@kernel.org, olof@lixom.net
Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org
In-Reply-To: <MN2PR02MB602959626A4F6E462A321F35C1CF0@MN2PR02MB6029.namprd02.prod.outlook.com>
Gentle Ping!
> -----Original Message-----
> From: Manish Narani
> Sent: Monday, July 15, 2019 12:46 PM
> To: Manish Narani <MNARANI@xilinx.com>; ulf.hansson@linaro.org;
> robh+dt@kernel.org; mark.rutland@arm.com; heiko@sntech.de; Michal Simek
> <michals@xilinx.com>; adrian.hunter@intel.com;
> christoph.muellner@theobroma-systems.com; philipp.tomsich@theobroma-
> systems.com; viresh.kumar@linaro.org; scott.branden@broadcom.com;
> ayaka@soulik.info; kernel@esmil.dk; tony.xie@rock-chips.com;
> mdf@kernel.org; olof@lixom.net
> Cc: linux-mmc@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> rockchip@lists.infradead.org
> Subject: RE: [PATCH v2 00/11] Arasan SDHCI enhancements and ZynqMP Tap
> Delays Handling
>
> Ping!
>
> > -----Original Message-----
> > From: Manish Narani <manish.narani@xilinx.com>
> > Sent: Monday, July 1, 2019 11:00 AM
> > To: ulf.hansson@linaro.org; robh+dt@kernel.org; mark.rutland@arm.com;
> > heiko@sntech.de; Michal Simek <michals@xilinx.com>;
> > adrian.hunter@intel.com; christoph.muellner@theobroma-systems.com;
> > philipp.tomsich@theobroma-systems.com; viresh.kumar@linaro.org;
> > scott.branden@broadcom.com; ayaka@soulik.info; kernel@esmil.dk;
> > tony.xie@rock-chips.com; Rajan Vaja <RAJANV@xilinx.com>; Jolly Shah
> > <JOLLYS@xilinx.com>; Nava kishore Manne <navam@xilinx.com>;
> > mdf@kernel.org; Manish Narani <MNARANI@xilinx.com>; olof@lixom.net
> > Cc: linux-mmc@vger.kernel.org; devicetree@vger.kernel.org; linux-
> > kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> > rockchip@lists.infradead.org
> > Subject: [PATCH v2 00/11] Arasan SDHCI enhancements and ZynqMP Tap
> > Delays Handling
> >
> > This patch series does the following:
> > - Reorganize the Clock Handling in Arasan SD driver
> > - Adds new sampling clock in Arasan SD driver
> > - Adds support to set Clock Delays in SD Arasan Driver
> > - Add SDIO Tap Delay handling in ZynqMP firmware driver
> > - Add support for ZynqMP Tap Delays setting in Arasan SD driver
> >
> > Changes in v2:
> > - Replaced the deprecated calls to clock framework APIs
> > - Added support for dev_clk_get() call to work for SD card clock
> > - Separated the clock data struct
> > - Fragmented the patch series in smaller patches to make it more
> > readable
> >
> > This patch series contains a DT patch, which I think should be there to
> > maintain the order of commits.
> >
> > Manish Narani (11):
> > dt-bindings: mmc: arasan: Update documentation for SD Card Clock
> > arm64: dts: rockchip: Add optional clock property indicating sdcard
> > clock
> > mmc: sdhci-of-arasan: Replace deprecated clk API calls
> > mmc: sdhci-of-arasan: Separate out clk related data to another
> > structure
> > dt-bindings: mmc: arasan: Update Documentation for the input clock
> > mmc: sdhci-of-arasan: Add sampling clock for a phy to use
> > dt-bindings: mmc: arasan: Add optional properties for Arasan SDHCI
> > mmc: sdhci-of-arasan: Add support to set clock phase delays for SD
> > firmware: xilinx: Add SDIO Tap Delay APIs
> > dt-bindings: mmc: arasan: Document 'xlnx,zynqmp-8.9a' controller
> > mmc: sdhci-of-arasan: Add support for ZynqMP Platform Tap Delays Setup
> >
> > .../devicetree/bindings/mmc/arasan,sdhci.txt | 49 ++-
> > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 +-
> > drivers/firmware/xilinx/zynqmp.c | 48 +++
> > drivers/mmc/host/sdhci-of-arasan.c | 453
> ++++++++++++++++++++-
> > include/linux/firmware/xlnx-zynqmp.h | 15 +-
> > 5 files changed, 540 insertions(+), 29 deletions(-)
> >
> > --
> > 2.1.1
^ permalink raw reply
* Re: [PATCH 2/3] macb: Update compatibility string for SiFive FU540-C000
From: Yash Shah @ 2019-07-22 4:39 UTC (permalink / raw)
To: Nicolas Ferre
Cc: David Miller, Rob Herring, Paul Walmsley, netdev, devicetree,
linux-kernel@vger.kernel.org List, linux-riscv, Mark Rutland,
Palmer Dabbelt, Albert Ou, Petr Štetiar, Sachin Ghadi
In-Reply-To: <4075b955-a187-6fd7-a2e6-deb82b5d4fb6@microchip.com>
On Fri, Jul 19, 2019 at 5:36 PM <Nicolas.Ferre@microchip.com> wrote:
>
> On 19/07/2019 at 13:10, Yash Shah wrote:
> > Update the compatibility string for SiFive FU540-C000 as per the new
> > string updated in the binding doc.
> > Reference: https://lkml.org/lkml/2019/7/17/200
>
> Maybe referring to lore.kernel.org is better:
> https://lore.kernel.org/netdev/CAJ2_jOFEVZQat0Yprg4hem4jRrqkB72FKSeQj4p8P5KA-+rgww@mail.gmail.com/
Sure. Will keep that in mind for future reference.
>
> > Signed-off-by: Yash Shah <yash.shah@sifive.com>
>
> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Thanks.
- Yash
^ permalink raw reply
* Re: [PATCH 3/5] clk: imx8mm: correct the usb1_ctrl parent to be usb_bus
From: Shawn Guo @ 2019-07-22 3:34 UTC (permalink / raw)
To: jun.li
Cc: mark.rutland, Peter.Chen, peng.fan, ping.bai, Anson.Huang,
devicetree, sboyd, daniel.baluta, s.hauer, linux-clk, robh+dt,
linux-imx, kernel, aisheng.dong, leonard.crestez, festevam,
mturquette, linux-arm-kernel
In-Reply-To: <20190703072327.38165-1-jun.li@nxp.com>
On Wed, Jul 03, 2019 at 03:23:25PM +0800, jun.li@nxp.com wrote:
> From: Li Jun <jun.li@nxp.com>
>
> Per latest imx8mm datasheet of CCM, the parent of usb1_ctrl_root_clk
> should be usb_bus.
>
> Signed-off-by: Li Jun <jun.li@nxp.com>
I only received 3 patches as a series. In that case, the patches should
have subject prefix like '[PATCH 1/3]' ...
The patches look good to me. Applied all 3, thanks.
Shawn
> ---
> drivers/clk/imx/clk-imx8mm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
> index 6b8e75d..735cf9d 100644
> --- a/drivers/clk/imx/clk-imx8mm.c
> +++ b/drivers/clk/imx/clk-imx8mm.c
> @@ -631,7 +631,7 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node)
> clks[IMX8MM_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
> clks[IMX8MM_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
> clks[IMX8MM_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0);
> - clks[IMX8MM_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_core_ref", base + 0x44d0, 0);
> + clks[IMX8MM_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0);
> clks[IMX8MM_CLK_GPU3D_ROOT] = imx_clk_gate4("gpu3d_root_clk", "gpu3d_div", base + 0x44f0, 0);
> clks[IMX8MM_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0);
> clks[IMX8MM_CLK_USDHC2_ROOT] = imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0);
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH] clk: imx8: Add DSP related clocks
From: Shawn Guo @ 2019-07-22 3:24 UTC (permalink / raw)
To: Daniel Baluta
Cc: mturquette, sboyd, s.hauer, kernel, festevam, linux-imx, robh+dt,
mark.rutland, aisheng.dong, weiyongjun1, linux-clk,
linux-arm-kernel, linux-kernel, devicetree, shengjiu.wang
In-Reply-To: <20190702152007.12190-1-daniel.baluta@nxp.com>
On Tue, Jul 02, 2019 at 06:20:07PM +0300, Daniel Baluta wrote:
> i.MX8QXP contains Hifi4 DSP. There are four clocks
> associated with DSP:
> * dsp_lpcg_core_clk
> * dsp_lpcg_ipg_clk
> * dsp_lpcg_adb_aclk
> * ocram_lpcg_ipg_clk
>
> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Applied, thanks.
^ permalink raw reply
* Re: [PATCH v2] arm64: dts: add the console node for DPAA2 platforms
From: Shawn Guo @ 2019-07-22 3:23 UTC (permalink / raw)
To: Ioana Ciornei; +Cc: leoyang.li, devicetree
In-Reply-To: <1562080578-31677-1-git-send-email-ioana.ciornei@nxp.com>
On Tue, Jul 02, 2019 at 06:16:18PM +0300, Ioana Ciornei wrote:
> Add the console device tree node for the following
> DPAA2 based platforms: LS1088A, LS2080A, LS2088A and LX2160A.
>
> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Please copy linux-arm-kernel@lists.infradead.org as well.
> ---
> Changes in v2:
> - use a generic node name
> - remove leading zeros and 0x from the unit-address
>
> arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 5 +++++
> arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 5 +++++
> arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 5 +++++
> 3 files changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> index 661137ffa319..d190d5490e31 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> @@ -665,6 +665,11 @@
> clock-names = "apb_pclk", "wdog_clk";
> };
>
> + console@8340020 {
Please sort node in unit-address. Hint: it should be added right before
node ptp-timer@8b95000.
Shawn
> + compatible = "fsl,dpaa2-console";
> + reg = <0x00000000 0x08340020 0 0x2>;
> + };
> +
> fsl_mc: fsl-mc@80c000000 {
> compatible = "fsl,qoriq-mc";
> reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
> index d7e78dcd153d..229d7f7d293d 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
> @@ -321,6 +321,11 @@
> };
> };
>
> + console@8340020 {
> + compatible = "fsl,dpaa2-console";
> + reg = <0x00000000 0x08340020 0 0x2>;
> + };
> +
> fsl_mc: fsl-mc@80c000000 {
> compatible = "fsl,qoriq-mc";
> reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> index 125a8cc2c5b3..0426e2230447 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> @@ -848,6 +848,11 @@
> dma-coherent;
> };
>
> + console@8340020 {
> + compatible = "fsl,dpaa2-console";
> + reg = <0x00000000 0x08340020 0 0x2>;
> + };
> +
> fsl_mc: fsl-mc@80c000000 {
> compatible = "fsl,qoriq-mc";
> reg = <0x00000008 0x0c000000 0 0x40>,
> --
> 1.9.1
>
^ permalink raw reply
* Re: [PATCH V6 06/21] clk: tegra: pll: Save and restore pll context
From: Sowjanya Komatineni @ 2019-07-22 3:22 UTC (permalink / raw)
To: Dmitry Osipenko, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <e383bf0e-fee7-3aa2-a9af-c0fb36c44219@gmail.com>
On 7/21/19 3:21 PM, Dmitry Osipenko wrote:
> 21.07.2019 22:40, Sowjanya Komatineni пишет:
>> This patch implements save and restore of PLL context.
>>
>> During system suspend, core power goes off and looses the settings
>> of the Tegra CAR controller registers.
>>
>> So during suspend entry pll rate is stored and on resume it is
>> restored back along with its state.
>>
>> Acked-by: Thierry Reding <treding@nvidia.com>
>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>> ---
>> drivers/clk/tegra/clk-pll.c | 121 ++++++++++++++++++++++++++++-----------
>> drivers/clk/tegra/clk-tegra210.c | 2 +-
>> drivers/clk/tegra/clk.h | 10 +++-
>> 3 files changed, 99 insertions(+), 34 deletions(-)
>>
>> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
>> index 1583f5fc992f..f136964e6c44 100644
>> --- a/drivers/clk/tegra/clk-pll.c
>> +++ b/drivers/clk/tegra/clk-pll.c
>> @@ -1008,6 +1008,59 @@ static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
>> return rate;
>> }
>>
>> +void tegra_clk_sync_state_pll(struct clk_hw *hw)
>> +{
>> + if (!__clk_get_enable_count(hw->clk))
>> + clk_pll_disable(hw);
>> + else
>> + clk_pll_enable(hw);
>> +}
>> +
>> +static int tegra_clk_pll_save_context(struct clk_hw *hw)
>> +{
>> + struct tegra_clk_pll *pll = to_clk_pll(hw);
>> + u32 val = 0;
>> +
>> + pll->rate = clk_hw_get_rate(hw);
> Again, clk_hw_get_rate() returns cached value. Why do you need to
> duplicate it?
true, will remove storing in next version. thanks.
>> + if (pll->params->flags & TEGRA_PLLMB)
>> + val = pll_readl_base(pll);
>> + else if (pll->params->flags & TEGRA_PLLRE)
>> + val = pll_readl_base(pll) & divp_mask_shifted(pll);
>> +
>> + pll->pllbase_ctx = val;
>> +
>> + return 0;
>> +}
>> +
>> +static void tegra_clk_pll_restore_context(struct clk_hw *hw)
>> +{
>> + struct tegra_clk_pll *pll = to_clk_pll(hw);
>> + struct clk_hw *parent = clk_hw_get_parent(hw);
>> + unsigned long parent_rate = clk_hw_get_rate(parent);
>> + u32 val;
>> +
>> + if (clk_pll_is_enabled(hw))
>> + return;
>> +
>> + if (pll->params->flags & TEGRA_PLLMB) {
>> + pll_writel_base(pll->pllbase_ctx, pll);
>> + } else if (pll->params->flags & TEGRA_PLLRE) {
>> + val = pll_readl_base(pll);
>> + val &= ~(divp_mask_shifted(pll));
>> + pll_writel_base(pll->pllbase_ctx | val, pll);
>> + }
>> +
>> + if (pll->params->set_defaults)
>> + pll->params->set_defaults(pll);
>> +
>> + clk_pll_set_rate(hw, pll->rate, parent_rate);
>> +
>> + /* do not sync pllx state here. pllx is sync'd after dfll resume */
>> + if (!(pll->params->flags & TEGRA_PLLX))
>> + tegra_clk_sync_state_pll(hw);
>> +}
>> +
>> const struct clk_ops tegra_clk_pll_ops = {
>> .is_enabled = clk_pll_is_enabled,
>> .enable = clk_pll_enable,
>> @@ -1015,6 +1068,8 @@ const struct clk_ops tegra_clk_pll_ops = {
>> .recalc_rate = clk_pll_recalc_rate,
>> .round_rate = clk_pll_round_rate,
>> .set_rate = clk_pll_set_rate,
>> + .save_context = tegra_clk_pll_save_context,
>> + .restore_context = tegra_clk_pll_restore_context,
>> };
>>
>> const struct clk_ops tegra_clk_plle_ops = {
>> @@ -1802,6 +1857,27 @@ static int clk_pllu_tegra114_enable(struct clk_hw *hw)
>>
>> return ret;
>> }
>> +
>> +static void _clk_plle_tegra_init_parent(struct tegra_clk_pll *pll)
>> +{
>> + u32 val, val_aux;
>> +
>> + /* ensure parent is set to pll_ref */
>> + val = pll_readl_base(pll);
>> + val_aux = pll_readl(pll->params->aux_reg, pll);
>> +
>> + if (val & PLL_BASE_ENABLE) {
>> + if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
>> + (val_aux & PLLE_AUX_PLLP_SEL))
>> + WARN(1, "pll_e enabled with unsupported parent %s\n",
>> + (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
>> + "pll_re_vco");
>> + } else {
>> + val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
>> + pll_writel(val_aux, pll->params->aux_reg, pll);
>> + fence_udelay(1, pll->clk_base);
>> + }
>> +}
>> #endif
>>
>> static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
>> @@ -2214,27 +2290,12 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name,
>> {
>> struct tegra_clk_pll *pll;
>> struct clk *clk;
>> - u32 val, val_aux;
>>
>> pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
>> if (IS_ERR(pll))
>> return ERR_CAST(pll);
>>
>> - /* ensure parent is set to pll_re_vco */
>> -
>> - val = pll_readl_base(pll);
>> - val_aux = pll_readl(pll_params->aux_reg, pll);
>> -
>> - if (val & PLL_BASE_ENABLE) {
>> - if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
>> - (val_aux & PLLE_AUX_PLLP_SEL))
>> - WARN(1, "pll_e enabled with unsupported parent %s\n",
>> - (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
>> - "pll_re_vco");
>> - } else {
>> - val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
>> - pll_writel(val_aux, pll_params->aux_reg, pll);
>> - }
>> + _clk_plle_tegra_init_parent(pll);
>>
>> clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
>> &tegra_clk_plle_tegra114_ops);
>> @@ -2276,6 +2337,8 @@ static const struct clk_ops tegra_clk_pllss_ops = {
>> .recalc_rate = clk_pll_recalc_rate,
>> .round_rate = clk_pll_ramp_round_rate,
>> .set_rate = clk_pllxc_set_rate,
>> + .save_context = tegra_clk_pll_save_context,
>> + .restore_context = tegra_clk_pll_restore_context,
>> };
>>
>> struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
>> @@ -2375,6 +2438,7 @@ struct clk *tegra_clk_register_pllre_tegra210(const char *name,
>> pll_params->vco_min = pll_params->adjust_vco(pll_params,
>> parent_rate);
>>
>> + pll_params->flags |= TEGRA_PLLRE;
>> pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
>> if (IS_ERR(pll))
>> return ERR_CAST(pll);
>> @@ -2520,11 +2584,19 @@ static void clk_plle_tegra210_disable(struct clk_hw *hw)
>> spin_unlock_irqrestore(pll->lock, flags);
>> }
>>
>> +static void tegra_clk_plle_t210_restore_context(struct clk_hw *hw)
>> +{
>> + struct tegra_clk_pll *pll = to_clk_pll(hw);
>> +
>> + _clk_plle_tegra_init_parent(pll);
>> +}
>> +
>> static const struct clk_ops tegra_clk_plle_tegra210_ops = {
>> .is_enabled = clk_plle_tegra210_is_enabled,
>> .enable = clk_plle_tegra210_enable,
>> .disable = clk_plle_tegra210_disable,
>> .recalc_rate = clk_pll_recalc_rate,
>> + .restore_context = tegra_clk_plle_t210_restore_context,
>> };
>>
>> struct clk *tegra_clk_register_plle_tegra210(const char *name,
>> @@ -2535,27 +2607,12 @@ struct clk *tegra_clk_register_plle_tegra210(const char *name,
>> {
>> struct tegra_clk_pll *pll;
>> struct clk *clk;
>> - u32 val, val_aux;
>>
>> pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
>> if (IS_ERR(pll))
>> return ERR_CAST(pll);
>>
>> - /* ensure parent is set to pll_re_vco */
>> -
>> - val = pll_readl_base(pll);
>> - val_aux = pll_readl(pll_params->aux_reg, pll);
>> -
>> - if (val & PLLE_BASE_ENABLE) {
>> - if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
>> - (val_aux & PLLE_AUX_PLLP_SEL))
>> - WARN(1, "pll_e enabled with unsupported parent %s\n",
>> - (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
>> - "pll_re_vco");
>> - } else {
>> - val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
>> - pll_writel(val_aux, pll_params->aux_reg, pll);
>> - }
>> + _clk_plle_tegra_init_parent(pll);
>>
>> clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
>> &tegra_clk_plle_tegra210_ops);
>> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
>> index 4721ee030d1c..58397f93166c 100644
>> --- a/drivers/clk/tegra/clk-tegra210.c
>> +++ b/drivers/clk/tegra/clk-tegra210.c
>> @@ -1602,7 +1602,7 @@ static struct tegra_clk_pll_params pll_x_params = {
>> .pdiv_tohw = pll_qlin_pdiv_to_hw,
>> .div_nmp = &pllx_nmp,
>> .freq_table = pll_x_freq_table,
>> - .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
>> + .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLLX,
>> .dyn_ramp = tegra210_pllx_dyn_ramp,
>> .set_defaults = tegra210_pllx_set_defaults,
>> .calc_rate = tegra210_pll_fixed_mdiv_cfg,
>> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
>> index fb29a8c27873..8532f5150091 100644
>> --- a/drivers/clk/tegra/clk.h
>> +++ b/drivers/clk/tegra/clk.h
>> @@ -235,6 +235,8 @@ struct tegra_clk_pll;
>> * TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This
>> * flag indicated that it is PLLMB.
>> * TEGRA_PLL_VCO_OUT - Used to indicate that the PLL has a VCO output
>> + * TEGRA_PLLRE - Used to indicate that it is PLLRE.
>> + * TEGRA_PLLX - Used to indicate that it is PLLX.
>> */
>> struct tegra_clk_pll_params {
>> unsigned long input_min;
>> @@ -301,6 +303,8 @@ struct tegra_clk_pll_params {
>> #define TEGRA_MDIV_NEW BIT(11)
>> #define TEGRA_PLLMB BIT(12)
>> #define TEGRA_PLL_VCO_OUT BIT(13)
>> +#define TEGRA_PLLRE BIT(14)
>> +#define TEGRA_PLLX BIT(15)
>>
>> /**
>> * struct tegra_clk_pll - Tegra PLL clock
>> @@ -310,6 +314,8 @@ struct tegra_clk_pll_params {
>> * @pmc: address of PMC, required to read override bits
>> * @lock: register lock
>> * @params: PLL parameters
>> + * @rate: rate during system suspend and resume
>> + * @pllbase_ctx: pll base register value during suspend and resume
>> */
>> struct tegra_clk_pll {
>> struct clk_hw hw;
>> @@ -317,6 +323,8 @@ struct tegra_clk_pll {
>> void __iomem *pmc;
>> spinlock_t *lock;
>> struct tegra_clk_pll_params *params;
>> + unsigned long rate;
>> + u32 pllbase_ctx;
>> };
>>
>> #define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw)
>> @@ -840,7 +848,7 @@ u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
>> int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
>> int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
>> u8 frac_width, u8 flags);
>> -
>> +void tegra_clk_sync_state_pll(struct clk_hw *hw);
>>
>> /* Combined read fence with delay */
>> #define fence_udelay(delay, reg) \
>>
^ permalink raw reply
* Re: [PATCH 1/4] arm64: Enable TIMER_IMX_SYS_CTR for ARCH_MXC platforms
From: Shawn Guo @ 2019-07-22 3:19 UTC (permalink / raw)
To: Anson Huang
Cc: mark.rutland@arm.com, Aisheng Dong, Peng Fan, festevam@gmail.com,
Jacky Bai, devicetree@vger.kernel.org, sboyd@kernel.org,
catalin.marinas@arm.com, s.hauer@pengutronix.de,
linux-kernel@vger.kernel.org, Daniel Baluta,
linux-clk@vger.kernel.org, robh+dt@kernel.org, dl-linux-imx,
kernel@pengutronix.de, Leonard Crestez, will@kernel.org, mturqu
In-Reply-To: <AM6PR0402MB39113A76EE8A63F9C9F589C1F5C40@AM6PR0402MB3911.eurprd04.prod.outlook.com>
On Mon, Jul 22, 2019 at 02:15:10AM +0000, Anson Huang wrote:
> Hi, Shawn
>
> > On Mon, Jun 24, 2019 at 02:35:10AM +0000, Anson Huang wrote:
> > > Hi, Shawn
> > >
> > > > -----Original Message-----
> > > > From: Shawn Guo <shawnguo@kernel.org>
> > > > Sent: Monday, June 24, 2019 10:27 AM
> > > > To: Anson Huang <anson.huang@nxp.com>
> > > > Cc: mark.rutland@arm.com; Aisheng Dong <aisheng.dong@nxp.com>;
> > Peng
> > > > Fan <peng.fan@nxp.com>; festevam@gmail.com; Jacky Bai
> > > > <ping.bai@nxp.com>; devicetree@vger.kernel.org; sboyd@kernel.org;
> > > > catalin.marinas@arm.com; s.hauer@pengutronix.de; linux-
> > > > kernel@vger.kernel.org; Daniel Baluta <daniel.baluta@nxp.com>;
> > > > linux- clk@vger.kernel.org; robh+dt@kernel.org; dl-linux-imx <linux-
> > > > imx@nxp.com>; kernel@pengutronix.de; Leonard Crestez
> > > > <leonard.crestez@nxp.com>; will@kernel.org; mturquette@baylibre.com;
> > > > linux-arm-kernel@lists.infradead.org; Abel Vesa <abel.vesa@nxp.com>
> > > > Subject: Re: [PATCH 1/4] arm64: Enable TIMER_IMX_SYS_CTR for
> > > > ARCH_MXC platforms
> > > >
> > > > On Mon, Jun 24, 2019 at 10:22:01AM +0800, Shawn Guo wrote:
> > > > > On Fri, Jun 21, 2019 at 03:07:17PM +0800, Anson.Huang@nxp.com
> > wrote:
> > > > > > From: Anson Huang <Anson.Huang@nxp.com>
> > > > > >
> > > > > > ARCH_MXC platforms needs system counter as broadcast timer to
> > > > > > support cpuidle, enable it by default.
> > > > > >
> > > > > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> > > > > > ---
> > > > > > arch/arm64/Kconfig.platforms | 1 +
> > > > > > 1 file changed, 1 insertion(+)
> > > > > >
> > > > > > diff --git a/arch/arm64/Kconfig.platforms
> > > > > > b/arch/arm64/Kconfig.platforms index 4778c77..f5e623f 100644
> > > > > > --- a/arch/arm64/Kconfig.platforms
> > > > > > +++ b/arch/arm64/Kconfig.platforms
> > > > > > @@ -173,6 +173,7 @@ config ARCH_MXC
> > > > > > select PM
> > > > > > select PM_GENERIC_DOMAINS
> > > > > > select SOC_BUS
> > > > > > + select TIMER_IMX_SYS_CTR
> > > > >
> > > > > Where is that driver?
> > > >
> > > > Okay, just found it in the mailbox. They seem to be sent in the wrong
> > order.
> > > > Really, you should send this series only after the driver lands on mainline.
> > >
> > > OK, just noticed that mainline does NOT have it, since I did it based on next
> > tree.
> > > I will resend the patch series after the system counter driver landing on
> > mainline.
> >
> > I just picked the series up, so no need to resend.
>
> Something changed for this series, the system counter clock related implementation
> are changed after some comments from maintainer, so I think you should picked up
> below patch series instead, and drop this series,
>
> https://patchwork.kernel.org/patch/11037953/
Okay, dropped clk and dts patches. arch/arm64/Kconfig.platforms one is kept.
Shawn
^ permalink raw reply
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