* Re: [PATCH v2 20/20] cpufreq: Return zero on success in boost sw setting
From: Rafael J. Wysocki @ 2020-05-15 15:58 UTC (permalink / raw)
To: Sergey.Semin, Thomas Bogendoerfer, Rafael J. Wysocki,
Viresh Kumar, Ulf Hansson, Matthias Kaehlcke
Cc: Serge Semin, Alexey Malahov, Paul Burton, Ralf Baechle,
Arnd Bergmann, Rob Herring, linux-mips, devicetree, stable,
Frederic Weisbecker, Ingo Molnar, Yue Hu, linux-pm, linux-kernel
In-Reply-To: <20200506174238.15385-21-Sergey.Semin@baikalelectronics.ru>
On 5/6/2020 7:42 PM, Sergey.Semin@baikalelectronics.ru wrote:
> From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
>
> Recent commit e61a41256edf ("cpufreq: dev_pm_qos_update_request() can
> return 1 on success") fixed a problem when active policies traverse
> was falsely stopped due to invalidly treating the non-zero return value
> from freq_qos_update_request() method as an error. Yes, that function
> can return positive values if the requested update actually took place.
> The current problem is that the returned value is then passed to the
> return cell of the cpufreq_boost_set_sw() (set_boost callback) method.
> This value is then also analyzed for being non-zero, which is also
> treated as having an error. As a result during the boost activation
> we'll get an error returned while having the QOS frequency update
> successfully performed. Fix this by returning a negative value from the
> cpufreq_boost_set_sw() if actual error was encountered and zero
> otherwise treating any positive values as the successful operations
> completion.
>
> Fixes: 18c49926c4bf ("cpufreq: Add QoS requests for userspace constraints")
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: stable@vger.kernel.org
> ---
> drivers/cpufreq/cpufreq.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c
> index 045f9fe157ce..5870cdca88cf 100644
> --- a/drivers/cpufreq/cpufreq.c
> +++ b/drivers/cpufreq/cpufreq.c
> @@ -2554,7 +2554,7 @@ static int cpufreq_boost_set_sw(int state)
> break;
> }
>
> - return ret;
> + return ret < 0 ? ret : 0;
> }
>
> int cpufreq_boost_trigger_state(int state)
IMO it is better to update the caller of this function to handle the
positive value possibly returned by it correctly.
Thanks!
^ permalink raw reply
* Re: [PATCH v1 5/9] dt-bindings: dmaengine: convert Actions Semi Owl SoCs bindings to yaml
From: André Przywara @ 2020-05-15 15:54 UTC (permalink / raw)
To: Amit Singh Tomar, afaerber, manivannan.sadhasivam, robh+dt
Cc: cristian.ciocaltea, linux-arm-kernel, linux-actions, devicetree
In-Reply-To: <1589472657-3930-6-git-send-email-amittomer25@gmail.com>
On 14/05/2020 17:10, Amit Singh Tomar wrote:
Hi,
> Converts the device tree bindings for the Actions Semi Owl SoCs DMA
> Controller over to YAML schemas.
>
> It also adds new compatible string "actions,s700-dma" to match
> the driver.
>
> Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
> ---
> New patch, was not there in RFC.
> ---
> Documentation/devicetree/bindings/dma/owl-dma.txt | 47 ------------
> Documentation/devicetree/bindings/dma/owl-dma.yaml | 84 ++++++++++++++++++++++
> 2 files changed, 84 insertions(+), 47 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/dma/owl-dma.txt
> create mode 100644 Documentation/devicetree/bindings/dma/owl-dma.yaml
>
> diff --git a/Documentation/devicetree/bindings/dma/owl-dma.txt b/Documentation/devicetree/bindings/dma/owl-dma.txt
> deleted file mode 100644
> index 03e9bb12b75f..000000000000
> --- a/Documentation/devicetree/bindings/dma/owl-dma.txt
> +++ /dev/null
> @@ -1,47 +0,0 @@
> -* Actions Semi Owl SoCs DMA controller
> -
> -This binding follows the generic DMA bindings defined in dma.txt.
> -
> -Required properties:
> -- compatible: Should be "actions,s900-dma".
> -- reg: Should contain DMA registers location and length.
> -- interrupts: Should contain 4 interrupts shared by all channel.
> -- #dma-cells: Must be <1>. Used to represent the number of integer
> - cells in the dmas property of client device.
> -- dma-channels: Physical channels supported.
> -- dma-requests: Number of DMA request signals supported by the controller.
> - Refer to Documentation/devicetree/bindings/dma/dma.txt
> -- clocks: Phandle and Specifier of the clock feeding the DMA controller.
> -
> -Example:
> -
> -Controller:
> - dma: dma-controller@e0260000 {
> - compatible = "actions,s900-dma";
> - reg = <0x0 0xe0260000 0x0 0x1000>;
> - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> - #dma-cells = <1>;
> - dma-channels = <12>;
> - dma-requests = <46>;
> - clocks = <&clock CLK_DMAC>;
> - };
> -
> -Client:
> -
> -DMA clients connected to the Actions Semi Owl SoCs DMA controller must
> -use the format described in the dma.txt file, using a two-cell specifier
> -for each channel.
> -
> -The two cells in order are:
> -1. A phandle pointing to the DMA controller.
> -2. The channel id.
> -
> -uart5: serial@e012a000 {
> - ...
> - dma-names = "tx", "rx";
> - dmas = <&dma 26>, <&dma 27>;
> - ...
> -};
> diff --git a/Documentation/devicetree/bindings/dma/owl-dma.yaml b/Documentation/devicetree/bindings/dma/owl-dma.yaml
> new file mode 100644
> index 000000000000..12e68c0ece67
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/owl-dma.yaml
> @@ -0,0 +1,84 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/owl-dma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Actions Semi Owl SoCs DMA controller
> +
> +description: |
> + The OWL DMA is a general-purpose direct memory access controller capable of
> + supporting 10 and 12 independent DMA channels for S700 and S900 SoCs
> + respectively.
From here on the description is pretty much how DMA controller
references work in general, so I don't see the point of including this
in the description here.
> + DMA clients connected to the Actions Semi Owl SoCs DMA controller must
> + use the format described in the owl-dma.yaml file, using a two-cell specifier
> + for each channel.
> +
> + The two cells in order are:
> + 1. A phandle pointing to the DMA controller.
> + 2. The channel id.
> +
> + uart5: serial@e012a000 {
> + ...
> + dma-names = "tx", "rx";
> + dmas = <&dma 26>, <&dma 27>;
> + ...
> + };
> +
> +maintainers:
> + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> +
> +allOf:
> + - $ref: "dma-controller.yaml#"
> +
> +properties:
> + compatible:
> + enum:
> + - actions,s900-dma
> + - actions,s700-dma
> +
> + reg:
> + maxItems: 1
Could you replace those "maxItems: 1" here and below with:
- description: ...., copying in the explanation from the .txt binding?
That should serve the same purpose as "maxItems: 1", but is more
descriptive.
> +
> + interrupts:
> + maxItems: 4
Please mention that the controller supports 4 interrupts, which are
freely assignable to the interrupt channels.
(The kernel chose to use only one, but that's nothing the binding is
concerned about).
> +
> + "#dma-cells":
> + const: 1
> +
> + dma-channels:
> + maxItems: 1
> +
> + dma-requests:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - "#dma-cells"
> + - dma-channels
> + - dma-requests
> + - clocks
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/actions,s700-cmu.h>
I would drop this line and replace CLK_DMAC with some number below, to
keep this *example* as independent as possible.
Cheers,
Andre
> + dma: dma-controller@e0260000 {
> + compatible = "actions,s900-dma";
> + reg = <0x0 0xe0260000 0x0 0x1000>;
> + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> + #dma-cells = <1>;
> + dma-channels = <12>;
> + dma-requests = <46>;
> + clocks = <&clock CLK_DMAC>;
> + };
> +
> +...
>
^ permalink raw reply
* Re: [PATCH 09/14] pinctrl: ocelot: Add Sparx5 SoC support
From: Lars Povlsen @ 2020-05-15 15:52 UTC (permalink / raw)
To: kbuild test robot
Cc: SoC Team, Arnd Bergmann, Stephen Boyd, Linus Walleij, kbuild-all,
Lars Povlsen, Steen Hegelund, Microchip Linux Driver Support,
Olof Johansson, Michael Turquette, devicetree, linux-clk,
linux-gpio, linux-arm-kernel
In-Reply-To: <202005150200.wnjISCrm%lkp@intel.com>
kbuild test robot writes:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi Lars,
>
> I love your patch! Perhaps something to improve:
>
> [auto build test WARNING on robh/for-next]
> [also build test WARNING on pinctrl/devel clk/clk-next linus/master v5.7-rc5 next-20200512]
> [if your patch is applied to the wrong git tree, please drop us a note to help
> improve the system. BTW, we also suggest to use '--base' option to specify the
> base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
>
> url: https://github.com/0day-ci/linux/commits/Lars-Povlsen/Adding-support-for-Microchip-Sparx5-SoC/20200514-163536
> base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
> config: powerpc-allyesconfig (attached as .config)
> compiler: powerpc64-linux-gcc (GCC) 9.3.0
> reproduce:
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # save the attached .config to linux build tree
> COMPILER_INSTALL_PATH=$HOME/0day GCC_VERSION=9.3.0 make.cross ARCH=powerpc
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kbuild test robot <lkp@intel.com>
>
> All warnings (new ones prefixed by >>, old ones prefixed by <<):
>
>>> drivers/pinctrl/pinctrl-ocelot.c:28: warning: "clrsetbits" redefined
> 28 | #define clrsetbits(addr, clear, set) |
> In file included from include/linux/io.h:13,
> from include/linux/irq.h:20,
> from include/linux/gpio/driver.h:7,
> from drivers/pinctrl/pinctrl-ocelot.c:10:
> arch/powerpc/include/asm/io.h:849: note: this is the location of the previous definition
> 849 | #define clrsetbits(type, addr, clear, set) |
>
> vim +/clrsetbits +28 drivers/pinctrl/pinctrl-ocelot.c
>
> 27
> > 28 #define clrsetbits(addr, clear, set) \
> 29 writel((readl(addr) & ~(clear)) | (set), (addr))
> 30
>
I'll change the code to avoid the name clash.
Thanks,
> ---
> 0-DAY CI Kernel Test Service, Intel Corporation
> https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
--
Lars Povlsen,
Microchip
^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: mmc: Add Sparx5 SDHCI controller bindings
From: Lars Povlsen @ 2020-05-15 15:50 UTC (permalink / raw)
To: Rob Herring
Cc: Lars Povlsen, Alexandre Belloni, linux-arm-kernel, SoC Team,
linux-mmc, Ulf Hansson, linux-kernel,
Microchip Linux Driver Support, devicetree, Adrian Hunter,
Rob Herring
In-Reply-To: <20200514130351.GA17797@bogus>
Rob Herring writes:
> On Wed, 13 May 2020 15:31:20 +0200, Lars Povlsen wrote:
>> The Sparx5 SDHCI controller is based on the Designware controller IP.
>>
>> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
>> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
>> ---
>> .../mmc/microchip,dw-sparx5-sdhci.yaml | 57 +++++++++++++++++++
>> 1 file changed, 57 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml
>>
>
>
> My bot found errors running 'make dt_binding_check' on your patch:
>
> Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.example.dts:20:18: fatal error: dt-bindings/clock/microchip,sparx5.h: No such file or directory
> #include <dt-bindings/clock/microchip,sparx5.h>
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> compilation terminated.
> scripts/Makefile.lib:312: recipe for target 'Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.example.dt.yaml' failed
> make[1]: *** [Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.example.dt.yaml] Error 1
> make[1]: *** Waiting for unfinished jobs....
> Makefile:1300: recipe for target 'dt_binding_check' failed
> make: *** [dt_binding_check] Error 2
>
> See https://patchwork.ozlabs.org/patch/1289290
>
Rob,
The header file is added with the "parent" SoC series for Sparx5, which
was submitted separately to the SoC list.
Should I rewrite the example to avoid using the (normal) header file, or
can you add the header file?
I have verified the YAML pass dt_binding_check with the header file.
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure dt-schema is up to date:
>
> pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade
>
> Please check and re-submit.
--
Lars Povlsen,
Microchip
^ permalink raw reply
* Re: [PATCH v2 1/7] usb: gadget: udc: atmel: use of_find_matching_node_and_match
From: Felipe Balbi @ 2020-05-15 15:47 UTC (permalink / raw)
To: cristian.birsan, gregkh, nicolas.ferre, alexandre.belloni,
ludovic.desroches, robh+dt, mark.rutland, linux-arm-kernel,
linux-usb, devicetree, linux-kernel
Cc: Claudiu Beznea
In-Reply-To: <20200515111631.31210-2-cristian.birsan@microchip.com>
[-- Attachment #1: Type: text/plain, Size: 506 bytes --]
<cristian.birsan@microchip.com> writes:
> From: Claudiu Beznea <claudiu.beznea@microchip.com>
>
> Instead of trying to match every possible compatible use
> of_find_matching_node_and_match() and pass the compatible array.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
please rebase on my testing/next
checking file drivers/usb/gadget/udc/atmel_usba_udc.c
Hunk #1 succeeded at 2098 (offset 46 lines).
Hunk #2 FAILED at 2074.
1 out of 2 hunks FAILED
--
balbi
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 832 bytes --]
^ permalink raw reply
* [PATCH v3] dt-bindings: gpio: renesas,rcar-gpio: Add r8a7742 (RZ/G1H) support
From: Lad Prabhakar @ 2020-05-15 15:45 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski, Rob Herring
Cc: Geert Uytterhoeven, linux-gpio, devicetree, linux-kernel,
Prabhakar, Lad Prabhakar
Renesas RZ/G1H (R8A7742) SoC GPIO blocks are identical to the R-Car Gen2
family. Add support for its GPIO controllers.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
---
v2->v3:
1: Rebased the patch as binding were converted into json format.
I have restored the Acks' from Geert and Rob
(https://patchwork.kernel.org/patch/11518759/).
v1->v2:
* No change
---
Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml b/Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml
index bcece7e..397d938 100644
--- a/Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml
@@ -20,6 +20,7 @@ properties:
- items:
- enum:
+ - renesas,gpio-r8a7742 # RZ/G1H
- renesas,gpio-r8a7743 # RZ/G1M
- renesas,gpio-r8a7744 # RZ/G1N
- renesas,gpio-r8a7745 # RZ/G1E
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v2 01/19] dt-bindings: spi: dw: Add Tx/Rx DMA properties
From: Serge Semin @ 2020-05-15 15:43 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Andy Shevchenko, Rob Herring, Georgy Vlasov,
Ramil Zaripov, Alexey Malahov, Thomas Bogendoerfer, Paul Burton,
Ralf Baechle, Arnd Bergmann, Allison Randal, Gareth Williams,
linux-mips, Wan Ahmad Zainie, linux-spi, devicetree, linux-kernel
In-Reply-To: <20200515122715.GC5066@sirena.org.uk>
On Fri, May 15, 2020 at 01:27:15PM +0100, Mark Brown wrote:
> On Fri, May 15, 2020 at 02:51:51PM +0300, Andy Shevchenko wrote:
> > On Fri, May 15, 2020 at 01:47:40PM +0300, Serge Semin wrote:
>
> > > Since commit 22d48ad7bfac ("spi: dw: Add Elkhart Lake PSE DMA support")
> > > the spi-dw-mid.c module supports a platform DMA engine handling the DW APB
> > > SSI controller requests. Lets alter the DW SPI bindings file to accept the
> > > Rx and Tx DMA line specifiers.
>
> > I'm wondering if these properties are implied by the SPI generic one?
> > (forgive me if I'm not understanding all DT schema relations)
>
> Which SPI generic DMA bindings are you thinking of here? There aren't
> any in spi-controller.yaml.
There are default schemas in the dt-core, which defines the dmas and dma-names
type, but the exact naming and number of phandler+identifiers are implementation
specific. So it's either supposed to be implemented on the generic SPI controller
basis (like in someplace of spi-controller.yaml) or in individual controllers DT
schema. As Mark said we don't have any DMA properties definition in the generic
SPI controller schema (spi-controller.yaml), so the particular SPI controllers
DT schemas have got their own DMA properties declared. Most of them BTW use the
same naming as we do here: "rx" and "tx", but some alas don't.
-Sergey
^ permalink raw reply
* Re: [PATCHv1 13/19] power: supply: sbs-battery: add POWER_SUPPLY_HEALTH_CALIBRATION_REQUIRED support
From: Emil Velikov @ 2020-05-15 15:35 UTC (permalink / raw)
To: Sebastian Reichel
Cc: Sebastian Reichel, Rob Herring, Greg Kroah-Hartman,
Rafael J . Wysocki, linux-pm, devicetree, linux-kernel, kernel
In-Reply-To: <20200513185615.508236-14-sebastian.reichel@collabora.com>
On 2020/05/13, Sebastian Reichel wrote:
> Add support for reporting the SBS battery's condition flag
> to userspace using the new "Calibration required" health status.
>
> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> ---
> drivers/power/supply/sbs-battery.c | 27 ++++++++++++++++++++++++---
> 1 file changed, 24 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/power/supply/sbs-battery.c b/drivers/power/supply/sbs-battery.c
> index 4fa553d61db2..2a2b926ad75c 100644
> --- a/drivers/power/supply/sbs-battery.c
> +++ b/drivers/power/supply/sbs-battery.c
> @@ -23,6 +23,7 @@
>
> enum {
> REG_MANUFACTURER_DATA,
> + REG_BATTERY_MODE,
> REG_TEMPERATURE,
> REG_VOLTAGE,
> REG_CURRENT_NOW,
> @@ -94,6 +95,8 @@ static const struct chip_data {
> } sbs_data[] = {
> [REG_MANUFACTURER_DATA] =
> SBS_DATA(POWER_SUPPLY_PROP_PRESENT, 0x00, 0, 65535),
> + [REG_BATTERY_MODE] =
> + SBS_DATA(-1, 0x03, 0, 65535),
Fwiw I really like how neatly the driver is split into components. One thing
which makes me wonder, have you considered reshuffling the sbs_data struct.
In particular:
- index POWER_SUPPLY_PROP, kill off the REG_ enum
- sbs_get_property_index() can go, alongside a couple of unreachable paths
- replace batter_mode (needs calibration) with with PROP_HEALTH + comment
- perhaps even add REG_ADDR_SPEC_INFO 0x1a under POWER_SUPPLY_PROP_PRESENT
- using the min/max seems wasteful, considering only one register is in s16
range while everything else is within u16
Regardless of the questions and trivial suggestions, the series looks spot on.
For the lot:
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
-Emil
P.S. The reg table is nearly complete only 0x01-0x07, 0x0E, 0x11, 0x1d-0x1f
remain o/
^ permalink raw reply
* Re: [PATCH] [RESEND] arm64: dts: mt8173: fix cooling device range
From: Matthias Brugger @ 2020-05-15 15:33 UTC (permalink / raw)
To: Michael Kao, Zhang Rui, Eduardo Valentin, Daniel Lezcano,
Rob Herring, Mark Rutland, hsinyi, linux-pm, srv_heupstream
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <20200424082340.4127-1-michael.kao@mediatek.com>
On 24/04/2020 10:23, Michael Kao wrote:
> When thermal reaches target temperature,it would be pinned to state 0
> (max frequency and power).
> Fix the throttling range to no limit.
>
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> Signed-off-by: Michael Kao <michael.kao@mediatek.com>
applied to v5.7-next/dts64
Thanks!
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 13 +++++++++----
> 1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index ccb8e88a60c5..cae2cec46cdc 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -19,6 +19,7 @@
> #include <dt-bindings/power/mt8173-power.h>
> #include <dt-bindings/reset/mt8173-resets.h>
> #include <dt-bindings/gce/mt8173-gce.h>
> +#include <dt-bindings/thermal/thermal.h>
> #include "mt8173-pinfunc.h"
>
> / {
> @@ -294,14 +295,18 @@
> cooling-maps {
> map@0 {
> trip = <&target>;
> - cooling-device = <&cpu0 0 0>,
> - <&cpu1 0 0>;
> + cooling-device = <&cpu0 THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>,
> + <&cpu1 THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>;
> contribution = <3072>;
> };
> map@1 {
> trip = <&target>;
> - cooling-device = <&cpu2 0 0>,
> - <&cpu3 0 0>;
> + cooling-device = <&cpu2 THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>,
> + <&cpu3 THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>;
> contribution = <1024>;
> };
> };
>
^ permalink raw reply
* Re: [PATCH v2 0/7] usb: gadget: udc: atmel: add usb device support for SAM9x60 SoC
From: Cristian.Birsan @ 2020-05-15 15:32 UTC (permalink / raw)
To: alexandre.belloni
Cc: balbi, gregkh, Nicolas.Ferre, Ludovic.Desroches, robh+dt,
mark.rutland, linux-arm-kernel, linux-usb, devicetree,
linux-kernel
In-Reply-To: <20200515150228.GW34497@piout.net>
On 5/15/20 6:02 PM, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi,
>
> On 15/05/2020 14:16:24+0300, cristian.birsan@microchip.com wrote:
>> From: Cristian Birsan <cristian.birsan@microchip.com>
>>
>> This patch set adds usb device support for SAM9x60 SoC.
>> The DPRAM memory for the USB High Speed Device Port (UDPHS) hardware
>> block was increased and the allocation method is changed. This patch
>> series simplifies the endpoint allocation scheme to acomodate this SoC
>> and the old ones.
>>
>> Changes in v2:
>> - drop the patch that adds reference to pmc for sam9x60
>> - use dt-bindings: usb prefix
>> - enable usb device in device tree
>>
>> Claudiu Beznea (1):
>> usb: gadget: udc: atmel: use of_find_matching_node_and_match
>>
>> Cristian Birsan (6):
>> dt-bindings: usb: atmel: Update DT bindings documentation for sam9x60
>> usb: gadget: udc: atmel: simplify endpoint allocation
>> usb: gadget: udc: atmel: use 1 bank endpoints for control transfers
>> usb: gadget: udc: atmel: rename errata into caps
>> usb: gadget: udc: atmel: update endpoint allocation for sam9x60
>> ARM: dts: at91: sam9x60ek: enable usb device
>
> This should probably be rebased on top of
> https://lore.kernel.org/linux-arm-kernel/20200507155651.1094142-1-gregory.clement@bootlin.com/
> so we avoid having to define the endpoints in the device tree in the
> first place.
I know the patch series and I Ack-ed it some time ago. On the other hand, it was not applied yet,
so to be consistent I created this series based on what is already available on usb-next.
Depending on which one gets applied first, the other will need to rebase. I have no problem with that.
The end goal is to have both of them.
Cristian
>
> --
> Alexandre Belloni, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
>
^ permalink raw reply
* Re: [PATCH 06/14] arm64: dts: sparx5: Add basic cpu support
From: Robin Murphy @ 2020-05-15 15:30 UTC (permalink / raw)
To: Lars Povlsen, Marc Zyngier
Cc: devicetree, Alexandre Belloni, Arnd Bergmann, Stephen Boyd,
Linus Walleij, linux-kernel, linux-clk, linux-gpio, SoC Team,
Michael Turquette, linux-arm-kernel, Olof Johansson,
Microchip Linux Driver Support, Steen Hegelund
In-Reply-To: <871rnlp740.fsf@soft-dev15.microsemi.net>
On 2020-05-15 16:09, Lars Povlsen wrote:
[...]
>>> + cpu0: cpu@0 {
>>> + compatible = "arm,cortex-a53", "arm,armv8";
Side note: only one compatible string for the real CPU please, running a
DT bindings check should complain about that.
>>> + device_type = "cpu";
>>> + reg = <0x0 0x0>;
>>> + enable-method = "spin-table";
>>
>> Really? This is 2020, not 2012 any more. Surely a new platform
>> boots using PSCI, and not *this*.
>>
>
> We don't currently support PSCI. The platform does not have TrustZone,
> hence we don't use ATF.
AIUI, part of the purpose of ATF is to provide a nice standardised
platform interface regardless of whether you care about Secure software
or not. It shouldn't take much to knock up a trivial ATF port that just
uses an internal spin-table for its PSCI backend - in fact I suspect
that's probably just a copy-paste from the RPi3 port ;)
Robin.
^ permalink raw reply
* Re: [PATCH v2 00/19] spi: dw: Add generic DW DMA controller support
From: Serge Semin @ 2020-05-15 15:30 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Serge Semin, Mark Brown, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Maxim Kaurkin, Pavel Parkhomenko,
Ekaterina Skachko, Vadim Vlasov, Alexey Kolotnikov,
Thomas Bogendoerfer, Paul Burton, Ralf Baechle, Arnd Bergmann,
Allison Randal, Gareth Williams, Rob Herring, linux-mips,
linux-spi, devicetree, linux-kernel
In-Reply-To: <20200515114950.GT185537@smile.fi.intel.com>
On Fri, May 15, 2020 at 02:49:50PM +0300, Andy Shevchenko wrote:
> On Fri, May 15, 2020 at 01:47:39PM +0300, Serge Semin wrote:
> > Baikal-T1 SoC provides a DW DMA controller to perform low-speed peripherals
> > Mem-to-Dev and Dev-to-Mem transaction. This is also applicable to the DW
> > APB SSI devices embedded into the SoC. Currently the DMA-based transfers
> > are supported by the DW APB SPI driver only as a middle layer code for
> > Intel MID/Elkhart PCI devices. Seeing the same code can be used for normal
> > platform DMAC device we introduced a set of patches to fix it within this
> > series.
> >
> > First of all we need to add the Tx and Rx DMA channels support into the DW
> > APB SSI binding. Then there are several fixes and cleanups provided as a
> > initial preparation for the Generic DMA support integration: add Tx/Rx
> > finish wait methods, clear DMAC register when done or stopped, Fix native
> > CS being unset, enable interrupts in accordance with DMA xfer mode,
> > discard static DW DMA slave structures, discard unused void priv pointer
> > and dma_width member of the dw_spi structure, provide the DMA Tx/Rx burst
> > length parametrisation and make sure it's optionally set in accordance
> > with the DMA max-burst capability.
> >
> > In order to have the DW APB SSI MMIO driver working with DMA we need to
> > initialize the paddr field with the physical base address of the DW APB SSI
> > registers space. Then we unpin the Intel MID specific code from the
> > generic DMA one and placed it into the spi-dw-pci.c driver, which is a
> > better place for it anyway. After that the naming cleanups are performed
> > since the code is going to be used for a generic DMAC device. Finally the
> > Generic DMA initialization can be added to the generic version of the
> > DW APB SSI IP.
> >
> > Last but not least we traditionally convert the legacy plain text-based
> > dt-binding file with yaml-based one and as a cherry on a cake replace
> > the manually written DebugFS registers read method with a ready-to-use
> > for the same purpose regset32 DebugFS interface usage.
> >
> > This patchset is rebased and tested on the spi/for-next (5.7-rc5):
> > base-commit: fe9fce6b2cf3 ("Merge remote-tracking branch 'spi/for-5.8' into spi-next")
>
> Thanks! I'm going to review it soon.
>
> Hint for the next time, please start always a new thread with new version.
Thanks for suggestion. Indeed my knowledge of the submission procedure has
been incomplete: "However, for a multi-patch series, it is generally best
to avoid using In-Reply-To: to link to older versions of the series.
This way multiple versions of the patch don't become an unmanageable
forest of references in email clients." [1]
[1] Documentation/process/submitting-patches.rst
-Sergey
>
> > Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> > Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> > Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> > Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> > Cc: Maxim Kaurkin <Maxim.Kaurkin@baikalelectronics.ru>
> > Cc: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
> > Cc: Ekaterina Skachko <Ekaterina.Skachko@baikalelectronics.ru>
> > Cc: Vadim Vlasov <V.Vlasov@baikalelectronics.ru>
> > Cc: Alexey Kolotnikov <Alexey.Kolotnikov@baikalelectronics.ru>
> > Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> > Cc: Paul Burton <paulburton@kernel.org>
> > Cc: Ralf Baechle <ralf@linux-mips.org>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: Allison Randal <allison@lohutok.net>
> > Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Cc: linux-mips@vger.kernel.org
> > Cc: linux-spi@vger.kernel.org
> > Cc: devicetree@vger.kernel.org
> > Cc: linux-kernel@vger.kernel.org
> >
> > ---
> >
> > Changelog v2:
> > - Rebase on top of the spi repository for-next branch.
> > - Move bindings conversion patch to the tail of the series.
> > - Move fixes to the head of the series.
> > - Apply as many changes as possible to be applied the Generic DMA
> > functionality support is added and the spi-dw-mid is moved to the
> > spi-dw-dma driver.
> > - Discard patch "spi: dw: Fix dma_slave_config used partly uninitialized"
> > since the problem has already been fixed.
> > - Add new patch "spi: dw: Discard unused void priv pointer".
> > - Add new patch "spi: dw: Discard dma_width member of the dw_spi structure".
> > n_bytes member of the DW SPI data can be used instead.
> > - Build the DMA functionality into the DW APB SSI core if required instead
> > of creating a separate kernel module.
> > - Use conditional statement instead of the ternary operator in the ref
> > clock getter.
> >
> > Serge Semin (19):
> > dt-bindings: spi: dw: Add Tx/Rx DMA properties
> > spi: dw: Add Tx/Rx finish wait methods to the MID DMA
> > spi: dw: Clear DMAC register when done or stopped
> > spi: dw: Fix native CS being unset
> > spi: dw: Enable interrupts in accordance with DMA xfer mode
> > spi: dw: Discard static DW DMA slave structures
> > spi: dw: Discard unused void priv pointer
> > spi: dw: Discard dma_width member of the dw_spi structure
> > spi: dw: Parameterize the DMA Rx/Tx burst length
> > spi: dw: Use DMA max burst to set the request thresholds
> > spi: dw: Initialize paddr in DW SPI MMIO private data
> > spi: dw: Fix Rx-only DMA transfers
> > spi: dw: Move Non-DMA code to the DW PCIe-SPI driver
> > spi: dw: Remove DW DMA code dependency from DW_DMAC_PCI
> > spi: dw: Add DW SPI DMA/PCI/MMIO dependency on the DW SPI core
> > spi: dw: Cleanup generic DW DMA code namings
> > spi: dw: Add DMA support to the DW SPI MMIO driver
> > spi: dw: Use regset32 DebugFS method to create regdump file
> > dt-bindings: spi: Convert DW SPI binding to DT schema
> >
> > .../bindings/spi/snps,dw-apb-ssi.txt | 42 ---
> > .../bindings/spi/snps,dw-apb-ssi.yaml | 127 +++++++++
> > .../devicetree/bindings/spi/spi-dw.txt | 24 --
> > drivers/spi/Kconfig | 15 +-
> > drivers/spi/Makefile | 7 +-
> > drivers/spi/{spi-dw-mid.c => spi-dw-dma.c} | 257 ++++++++++--------
> > drivers/spi/spi-dw-mmio.c | 9 +-
> > drivers/spi/spi-dw-pci.c | 50 +++-
> > drivers/spi/spi-dw.c | 98 +++----
> > drivers/spi/spi-dw.h | 33 ++-
> > 10 files changed, 405 insertions(+), 257 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> > create mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> > delete mode 100644 Documentation/devicetree/bindings/spi/spi-dw.txt
> > rename drivers/spi/{spi-dw-mid.c => spi-dw-dma.c} (53%)
> >
> > --
> > 2.25.1
> >
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
^ permalink raw reply
* Re: [PATCH] arm64: dts: mt8173: fix vcodec-enc clock
From: Matthias Brugger @ 2020-05-15 15:28 UTC (permalink / raw)
To: Hsin-Yi Wang, linux-arm-kernel
Cc: Rob Herring, Yunfei Dong, Qianqian Yan, devicetree, gtk_ruiwang,
linux-mediatek, linux-kernel
In-Reply-To: <20200504124442.208004-1-hsinyi@chromium.org>
On 04/05/2020 14:44, Hsin-Yi Wang wrote:
> Fix the assigned-clock-parents to higher frequency clock to avoid h264
> encode timeout:
>
> [ 134.763465] mtk_vpu 10020000.vpu: vpu ipi 4 ack time out !
> [ 134.769008] [MTK_VCODEC][ERROR][18]: vpu_enc_send_msg() vpu_ipi_send msg_id c002 len 32 fail -5
> [ 134.777707] [MTK_VCODEC][ERROR][18]: vpu_enc_encode() AP_IPIMSG_ENC_ENCODE 0 fail
>
> venc_sel is the clock used by h264 encoder, and venclt_sel is the clock
> used by vp8 encoder. Assign venc_sel to vcodecpll_ck and venclt_sel to
> vcodecpll_370p5.
>
> vcodecpll 1482000000
> vcodecpll_ck 494000000
> venc_sel 494000000
> ...
> vcodecpll_370p5 370500000
> venclt_sel 370500000
>
> Fixes: fbbad0287cec ("arm64: dts: Using standard CCF interface to set vcodec clk")
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Applied to v5.7-fixes
Thanks!
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index a212bf124e81..d0e9a2aada2e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -1422,8 +1422,8 @@ vcodec_enc: vcodec@18002000 {
> "venc_lt_sel";
> assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
> <&topckgen CLK_TOP_VENC_LT_SEL>;
> - assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>,
> - <&topckgen CLK_TOP_UNIVPLL1_D2>;
> + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>,
> + <&topckgen CLK_TOP_VCODECPLL_370P5>;
> };
>
> jpegdec: jpegdec@18004000 {
>
^ permalink raw reply
* Re: [Linux-stm32] [PATCH v7 5/6] clocksource: Add Low Power STM32 timers driver
From: Daniel Lezcano @ 2020-05-15 15:25 UTC (permalink / raw)
To: Benjamin GAIGNARD, Fabrice GASNIER, lee.jones@linaro.org,
robh+dt@kernel.org, mark.rutland@arm.com,
mcoquelin.stm32@gmail.com, Alexandre TORGUE, tglx@linutronix.de
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Pascal PAILLET-LME, Benjamin Gaignard,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <bbac5aa5-1c95-456e-3141-006d4fa86095@st.com>
Hi Benjamin,
On 05/05/2020 09:26, Benjamin GAIGNARD wrote:
>
>
> On 4/20/20 2:16 PM, Benjamin Gaignard wrote:
>> From: Benjamin Gaignard <benjamin.gaignard@linaro.org>
>>
>> Implement clock event driver using low power STM32 timers.
>> Low power timer counters running even when CPUs are stopped.
>> It could be used as clock event broadcaster to wake up CPUs but not like
>> a clocksource because each it rise an interrupt the counter restart from 0.
>>
>> Low power timers have a 16 bits counter and a prescaler which allow to
>> divide the clock per power of 2 to up 128 to target a 32KHz rate.
> Gentle ping to reviewers on this driver part of the series.
> The bindings and the MFD have been reviewed so I hope I can progress
> on the driver part too.
[ ... ]
sorry for the delay.
How do you want these patches to be merged?
Shall I pick patch 6/7 ?
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply
* Re: [PATCH] ARM: dts: at91: Configure I2C SCL gpio as open drain
From: Codrin.Ciubotariu @ 2020-05-15 15:24 UTC (permalink / raw)
To: alexandre.belloni
Cc: devicetree, linux-arm-kernel, linux-kernel, robh+dt,
Nicolas.Ferre, Ludovic.Desroches
In-Reply-To: <20200515145849.GV34497@piout.net>
On 15.05.2020 17:58, Alexandre Belloni wrote:
> On 15/05/2020 17:00:01+0300, Codrin Ciubotariu wrote:
>> The SCL gpio pin used by I2C bus for recovery needs to be configured as
>> open drain.
>>
>> Fixes: 455fec938bbb ("ARM: dts: at91: sama5d2: add i2c gpio pinctrl")
>> Fixes: a4bd8da893a3 ("ARM: dts: at91: sama5d3: add i2c gpio pinctrl")
>> Fixes: 8fb82f050cf6 ("ARM: dts: at91: sama5d4: add i2c gpio pinctrl")
>> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
>> ---
>> arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts | 6 +++---
>> arch/arm/boot/dts/at91-sama5d2_xplained.dts | 6 +++---
>> arch/arm/boot/dts/sama5d3.dtsi | 6 +++---
>> arch/arm/boot/dts/sama5d4.dtsi | 6 +++---
>> 4 files changed, 12 insertions(+), 12 deletions(-)
>>
>
> Applied, thanks. There was a small conflict in the sama5d2 board dts,
> please check.
It is ok, with the exception that it should also be added for the
scl-gpios property from the i2c2 node. I am making a patch.
>
> --
> Alexandre Belloni, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
>
^ permalink raw reply
* [PATCH v10 3/3] hwmon: add Gateworks System Controller support
From: Tim Harvey @ 2020-05-15 15:18 UTC (permalink / raw)
To: Lee Jones, Jean Delvare, Guenter Roeck, linux-hwmon, Rob Herring,
Frank Rowand, devicetree, linux-kernel, Robert Jones
Cc: Tim Harvey
In-Reply-To: <1589555891-16502-1-git-send-email-tharvey@gateworks.com>
The Gateworks System Controller has a hwmon sub-component that exposes
up to 16 ADC's, some of which are temperature sensors, others which are
voltage inputs. The ADC configuration (register mapping and name) is
configured via device-tree and varies board to board.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
---
v10:
- no changes
v9:
- use exported gsc_{read,write}
- added Reviewed-by: Guenter Roeck <linux@roeck-us.net>
v8:
- move regmap init to hwmon
v7:
- fix whitespace in Kconfig
- remove unnecessary device pointer in private data
- change divider from mili-ohms to ohms
- move fan base property to reg
v6:
- fix size of info field
- improve pwm output control documentation
- include unit suffix in divider and offset
- change subnode name to gsc-adc
- change to fan subnode
- fix voltage offset
v5:
- fix various checkpatch issues
- correct gsc-hwmon.rst in MAINTAINERS
- encorporate Gunter's feedback:
- switch to SENSOR_DEVICE_ATTR_{RW,RO}
- use tmp value to avoid excessive pointer deference
- simplify shift operation
- scale voffset once
- simplify is_visible function
- remove empty line at end of file
v4:
- adjust for uV offset from device-tree
- remove unnecessary optional write function
- remove register range check
- change dev_err prints to use gsc dev
- hard-code resolution/scaling for raw adcs
- describe units of ADC resolution
- move to using pwm<n>_auto_point<m>_{pwm,temp} for FAN PWM
- ensure space before/after operators
- remove unnecessary parens
- remove more debugging
- add default case and comment for type_voltage
- remove unnecessary index bounds checks for channel
- remove unnecessary clearing of struct fields
- added Documentation/hwmon/gsc-hwmon.rst
v3:
- add voltage_raw input type and supporting fields
- add channel validation to is_visible function
- remove unnecessary channel validation from read/write functions
v2:
- change license comment style
- remove DEBUG
- simplify regmap_bulk_read err check
- remove break after returns in switch statement
- fix fan setpoint buffer address
- remove unnecessary parens
- consistently use struct device *dev pointer
- change license/comment block
- add validation for hwmon child node props
- move parsing of of to own function
- use strlcpy to ensure null termination
- fix static array sizes and removed unnecessary initializers
- dynamically allocate channels
- fix fan input label
- support platform data
- fixed whitespace issues
---
Documentation/hwmon/gsc-hwmon.rst | 53 +++++
Documentation/hwmon/index.rst | 1 +
MAINTAINERS | 3 +
drivers/hwmon/Kconfig | 9 +
drivers/hwmon/Makefile | 1 +
drivers/hwmon/gsc-hwmon.c | 390 ++++++++++++++++++++++++++++++++
include/linux/platform_data/gsc_hwmon.h | 44 ++++
7 files changed, 501 insertions(+)
create mode 100644 Documentation/hwmon/gsc-hwmon.rst
create mode 100644 drivers/hwmon/gsc-hwmon.c
create mode 100644 include/linux/platform_data/gsc_hwmon.h
diff --git a/Documentation/hwmon/gsc-hwmon.rst b/Documentation/hwmon/gsc-hwmon.rst
new file mode 100644
index 00000000..ffac392
--- /dev/null
+++ b/Documentation/hwmon/gsc-hwmon.rst
@@ -0,0 +1,53 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+Kernel driver gsc-hwmon
+=======================
+
+Supported chips: Gateworks GSC
+Datasheet: http://trac.gateworks.com/wiki/gsc
+Author: Tim Harvey <tharvey@gateworks.com>
+
+Description:
+------------
+
+This driver supports hardware monitoring for the temperature sensor,
+various ADC's connected to the GSC, and optional FAN controller available
+on some boards.
+
+
+Voltage Monitoring
+------------------
+
+The voltage inputs are scaled either internally or by the driver depending
+on the GSC version and firmware. The values returned by the driver do not need
+further scaling. The voltage input labels provide the voltage rail name:
+
+inX_input Measured voltage (mV).
+inX_label Name of voltage rail.
+
+
+Temperature Monitoring
+----------------------
+
+Temperatures are measured with 12-bit or 10-bit resolution and are scaled
+either internally or by the driver depending on the GSC version and firmware.
+The values returned by the driver reflect millidegree Celcius:
+
+tempX_input Measured temperature.
+tempX_label Name of temperature input.
+
+
+PWM Output Control
+------------------
+
+The GSC features 1 PWM output that operates in automatic mode where the
+PWM value will be scalled depending on 6 temperature boundaries.
+The tempeature boundaries are read-write and in millidegree Celcius and the
+read-only PWM values range from 0 (off) to 255 (full speed).
+Fan speed will be set to minimum (off) when the temperature sensor reads
+less than pwm1_auto_point1_temp and maximum when the temperature sensor
+equals or exceeds pwm1_auto_point6_temp.
+
+pwm1_auto_point[1-6]_pwm PWM value.
+pwm1_auto_point[1-6]_temp Temperature boundary.
+
diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst
index 8ef62fd..1c02aa6 100644
--- a/Documentation/hwmon/index.rst
+++ b/Documentation/hwmon/index.rst
@@ -60,6 +60,7 @@ Hardware Monitoring Kernel Drivers
ftsteutates
g760a
g762
+ gsc-hwmon
gl518sm
hih6130
ibmaem
diff --git a/MAINTAINERS b/MAINTAINERS
index c78a014..7f8ece8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7035,6 +7035,9 @@ S: Maintained
F: Documentation/devicetree/bindings/mfd/gateworks-gsc.yaml
F: drivers/mfd/gateworks-gsc.c
F: include/linux/mfd/gsc.h
+F: Documentation/hwmon/gsc-hwmon.rst
+F: drivers/hwmon/gsc-hwmon.c
+F: include/linux/platform_data/gsc_hwmon.h
GASKET DRIVER FRAMEWORK
M: Rob Springer <rspringer@google.com>
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 4c62f90..5549906 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -523,6 +523,15 @@ config SENSORS_F75375S
This driver can also be built as a module. If so, the module
will be called f75375s.
+config SENSORS_GSC
+ tristate "Gateworks System Controller ADC"
+ depends on MFD_GATEWORKS_GSC
+ help
+ Support for the Gateworks System Controller A/D converters.
+
+ To compile this driver as a module, choose M here:
+ the module will be called gsc-hwmon.
+
config SENSORS_MC13783_ADC
tristate "Freescale MC13783/MC13892 ADC"
depends on MFD_MC13XXX
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index b0b9c8e..a6564d0 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -74,6 +74,7 @@ obj-$(CONFIG_SENSORS_G760A) += g760a.o
obj-$(CONFIG_SENSORS_G762) += g762.o
obj-$(CONFIG_SENSORS_GL518SM) += gl518sm.o
obj-$(CONFIG_SENSORS_GL520SM) += gl520sm.o
+obj-$(CONFIG_SENSORS_GSC) += gsc-hwmon.o
obj-$(CONFIG_SENSORS_GPIO_FAN) += gpio-fan.o
obj-$(CONFIG_SENSORS_HIH6130) += hih6130.o
obj-$(CONFIG_SENSORS_ULTRA45) += ultra45_env.o
diff --git a/drivers/hwmon/gsc-hwmon.c b/drivers/hwmon/gsc-hwmon.c
new file mode 100644
index 00000000..2137bc6
--- /dev/null
+++ b/drivers/hwmon/gsc-hwmon.c
@@ -0,0 +1,390 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for Gateworks System Controller Hardware Monitor module
+ *
+ * Copyright (C) 2020 Gateworks Corporation
+ */
+#include <linux/hwmon.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/mfd/gsc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#include <linux/platform_data/gsc_hwmon.h>
+
+#define GSC_HWMON_MAX_TEMP_CH 16
+#define GSC_HWMON_MAX_IN_CH 16
+
+#define GSC_HWMON_RESOLUTION 12
+#define GSC_HWMON_VREF 2500
+
+struct gsc_hwmon_data {
+ struct gsc_dev *gsc;
+ struct gsc_hwmon_platform_data *pdata;
+ struct regmap *regmap;
+ const struct gsc_hwmon_channel *temp_ch[GSC_HWMON_MAX_TEMP_CH];
+ const struct gsc_hwmon_channel *in_ch[GSC_HWMON_MAX_IN_CH];
+ u32 temp_config[GSC_HWMON_MAX_TEMP_CH + 1];
+ u32 in_config[GSC_HWMON_MAX_IN_CH + 1];
+ struct hwmon_channel_info temp_info;
+ struct hwmon_channel_info in_info;
+ const struct hwmon_channel_info *info[3];
+ struct hwmon_chip_info chip;
+};
+
+static struct regmap_bus gsc_hwmon_regmap_bus = {
+ .reg_read = gsc_read,
+ .reg_write = gsc_write,
+};
+
+static const struct regmap_config gsc_hwmon_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .cache_type = REGCACHE_NONE,
+};
+
+static ssize_t pwm_auto_point_temp_show(struct device *dev,
+ struct device_attribute *devattr,
+ char *buf)
+{
+ struct gsc_hwmon_data *hwmon = dev_get_drvdata(dev);
+ struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
+ u8 reg = hwmon->pdata->fan_base + (2 * attr->index);
+ u8 regs[2];
+ int ret;
+
+ ret = regmap_bulk_read(hwmon->regmap, reg, regs, 2);
+ if (ret)
+ return ret;
+
+ ret = regs[0] | regs[1] << 8;
+ return sprintf(buf, "%d\n", ret * 10);
+}
+
+static ssize_t pwm_auto_point_temp_store(struct device *dev,
+ struct device_attribute *devattr,
+ const char *buf, size_t count)
+{
+ struct gsc_hwmon_data *hwmon = dev_get_drvdata(dev);
+ struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
+ u8 reg = hwmon->pdata->fan_base + (2 * attr->index);
+ u8 regs[2];
+ long temp;
+ int err;
+
+ if (kstrtol(buf, 10, &temp))
+ return -EINVAL;
+
+ temp = clamp_val(temp, 0, 10000);
+ temp = DIV_ROUND_CLOSEST(temp, 10);
+
+ regs[0] = temp & 0xff;
+ regs[1] = (temp >> 8) & 0xff;
+ err = regmap_bulk_write(hwmon->regmap, reg, regs, 2);
+ if (err)
+ return err;
+
+ return count;
+}
+
+static ssize_t pwm_auto_point_pwm_show(struct device *dev,
+ struct device_attribute *devattr,
+ char *buf)
+{
+ struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
+
+ return sprintf(buf, "%d\n", 255 * (50 + (attr->index * 10)) / 100);
+}
+
+static SENSOR_DEVICE_ATTR_RO(pwm1_auto_point1_pwm, pwm_auto_point_pwm, 0);
+static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point1_temp, pwm_auto_point_temp, 0);
+
+static SENSOR_DEVICE_ATTR_RO(pwm1_auto_point2_pwm, pwm_auto_point_pwm, 1);
+static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point2_temp, pwm_auto_point_temp, 1);
+
+static SENSOR_DEVICE_ATTR_RO(pwm1_auto_point3_pwm, pwm_auto_point_pwm, 2);
+static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point3_temp, pwm_auto_point_temp, 2);
+
+static SENSOR_DEVICE_ATTR_RO(pwm1_auto_point4_pwm, pwm_auto_point_pwm, 3);
+static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point4_temp, pwm_auto_point_temp, 3);
+
+static SENSOR_DEVICE_ATTR_RO(pwm1_auto_point5_pwm, pwm_auto_point_pwm, 4);
+static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point5_temp, pwm_auto_point_temp, 4);
+
+static SENSOR_DEVICE_ATTR_RO(pwm1_auto_point6_pwm, pwm_auto_point_pwm, 5);
+static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point6_temp, pwm_auto_point_temp, 5);
+
+static struct attribute *gsc_hwmon_attributes[] = {
+ &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
+ &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
+ &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
+ &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
+ &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
+ &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
+ &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
+ &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
+ &sensor_dev_attr_pwm1_auto_point5_pwm.dev_attr.attr,
+ &sensor_dev_attr_pwm1_auto_point5_temp.dev_attr.attr,
+ &sensor_dev_attr_pwm1_auto_point6_pwm.dev_attr.attr,
+ &sensor_dev_attr_pwm1_auto_point6_temp.dev_attr.attr,
+ NULL
+};
+
+static const struct attribute_group gsc_hwmon_group = {
+ .attrs = gsc_hwmon_attributes,
+};
+__ATTRIBUTE_GROUPS(gsc_hwmon);
+
+static int
+gsc_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
+ int channel, long *val)
+{
+ struct gsc_hwmon_data *hwmon = dev_get_drvdata(dev);
+ const struct gsc_hwmon_channel *ch;
+ int sz, ret;
+ long tmp;
+ u8 buf[3];
+
+ switch (type) {
+ case hwmon_in:
+ ch = hwmon->in_ch[channel];
+ break;
+ case hwmon_temp:
+ ch = hwmon->temp_ch[channel];
+ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+
+ sz = (ch->mode == mode_voltage) ? 3 : 2;
+ ret = regmap_bulk_read(hwmon->regmap, ch->reg, buf, sz);
+ if (ret)
+ return ret;
+
+ tmp = 0;
+ while (sz-- > 0)
+ tmp |= (buf[sz] << (8 * sz));
+
+ switch (ch->mode) {
+ case mode_temperature:
+ if (tmp > 0x8000)
+ tmp -= 0xffff;
+ break;
+ case mode_voltage_raw:
+ tmp = clamp_val(tmp, 0, BIT(GSC_HWMON_RESOLUTION));
+ /* scale based on ref voltage and ADC resolution */
+ tmp *= GSC_HWMON_VREF;
+ tmp >>= GSC_HWMON_RESOLUTION;
+ /* scale based on optional voltage divider */
+ if (ch->vdiv[0] && ch->vdiv[1]) {
+ tmp *= (ch->vdiv[0] + ch->vdiv[1]);
+ tmp /= ch->vdiv[1];
+ }
+ /* adjust by uV offset */
+ tmp += ch->mvoffset;
+ break;
+ case mode_voltage:
+ /* no adjustment needed */
+ break;
+ }
+
+ *val = tmp;
+
+ return 0;
+}
+
+static int
+gsc_hwmon_read_string(struct device *dev, enum hwmon_sensor_types type,
+ u32 attr, int channel, const char **buf)
+{
+ struct gsc_hwmon_data *hwmon = dev_get_drvdata(dev);
+
+ switch (type) {
+ case hwmon_in:
+ *buf = hwmon->in_ch[channel]->name;
+ break;
+ case hwmon_temp:
+ *buf = hwmon->temp_ch[channel]->name;
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+
+ return 0;
+}
+
+static umode_t
+gsc_hwmon_is_visible(const void *_data, enum hwmon_sensor_types type, u32 attr,
+ int ch)
+{
+ return 0444;
+}
+
+static const struct hwmon_ops gsc_hwmon_ops = {
+ .is_visible = gsc_hwmon_is_visible,
+ .read = gsc_hwmon_read,
+ .read_string = gsc_hwmon_read_string,
+};
+
+static struct gsc_hwmon_platform_data *
+gsc_hwmon_get_devtree_pdata(struct device *dev)
+{
+ struct gsc_hwmon_platform_data *pdata;
+ struct gsc_hwmon_channel *ch;
+ struct fwnode_handle *child;
+ struct device_node *fan;
+ int nchannels;
+
+ nchannels = device_get_child_node_count(dev);
+ if (nchannels == 0)
+ return ERR_PTR(-ENODEV);
+
+ pdata = devm_kzalloc(dev,
+ sizeof(*pdata) + nchannels * sizeof(*ch),
+ GFP_KERNEL);
+ if (!pdata)
+ return ERR_PTR(-ENOMEM);
+ ch = (struct gsc_hwmon_channel *)(pdata + 1);
+ pdata->channels = ch;
+ pdata->nchannels = nchannels;
+
+ /* fan controller base address */
+ fan = of_find_compatible_node(dev->parent->of_node, NULL, "gw,gsc-fan");
+ if (fan && of_property_read_u32(fan, "reg", &pdata->fan_base)) {
+ dev_err(dev, "fan node without base\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ /* allocate structures for channels and count instances of each type */
+ device_for_each_child_node(dev, child) {
+ if (fwnode_property_read_string(child, "label", &ch->name)) {
+ dev_err(dev, "channel without label\n");
+ fwnode_handle_put(child);
+ return ERR_PTR(-EINVAL);
+ }
+ if (fwnode_property_read_u32(child, "reg", &ch->reg)) {
+ dev_err(dev, "channel without reg\n");
+ fwnode_handle_put(child);
+ return ERR_PTR(-EINVAL);
+ }
+ if (fwnode_property_read_u32(child, "gw,mode", &ch->mode)) {
+ dev_err(dev, "channel without mode\n");
+ fwnode_handle_put(child);
+ return ERR_PTR(-EINVAL);
+ }
+ if (ch->mode > mode_max) {
+ dev_err(dev, "invalid channel mode\n");
+ fwnode_handle_put(child);
+ return ERR_PTR(-EINVAL);
+ }
+
+ if (!fwnode_property_read_u32(child,
+ "gw,voltage-offset-microvolt",
+ &ch->mvoffset))
+ ch->mvoffset /= 1000;
+ fwnode_property_read_u32_array(child,
+ "gw,voltage-divider-ohms",
+ ch->vdiv, ARRAY_SIZE(ch->vdiv));
+ ch++;
+ }
+
+ return pdata;
+}
+
+static int gsc_hwmon_probe(struct platform_device *pdev)
+{
+ struct gsc_dev *gsc = dev_get_drvdata(pdev->dev.parent);
+ struct device *dev = &pdev->dev;
+ struct device *hwmon_dev;
+ struct gsc_hwmon_platform_data *pdata = dev_get_platdata(dev);
+ struct gsc_hwmon_data *hwmon;
+ const struct attribute_group **groups;
+ int i, i_in, i_temp;
+
+ if (!pdata) {
+ pdata = gsc_hwmon_get_devtree_pdata(dev);
+ if (IS_ERR(pdata))
+ return PTR_ERR(pdata);
+ }
+
+ hwmon = devm_kzalloc(dev, sizeof(*hwmon), GFP_KERNEL);
+ if (!hwmon)
+ return -ENOMEM;
+ hwmon->gsc = gsc;
+ hwmon->pdata = pdata;
+
+ hwmon->regmap = devm_regmap_init(dev, &gsc_hwmon_regmap_bus,
+ gsc->i2c_hwmon,
+ &gsc_hwmon_regmap_config);
+ if (IS_ERR(hwmon->regmap))
+ return PTR_ERR(hwmon->regmap);
+
+ for (i = 0, i_in = 0, i_temp = 0; i < hwmon->pdata->nchannels; i++) {
+ const struct gsc_hwmon_channel *ch = &pdata->channels[i];
+
+ switch (ch->mode) {
+ case mode_temperature:
+ if (i_temp == GSC_HWMON_MAX_TEMP_CH) {
+ dev_err(gsc->dev, "too many temp channels\n");
+ return -EINVAL;
+ }
+ hwmon->temp_ch[i_temp] = ch;
+ hwmon->temp_config[i_temp] = HWMON_T_INPUT |
+ HWMON_T_LABEL;
+ i_temp++;
+ break;
+ case mode_voltage:
+ case mode_voltage_raw:
+ if (i_in == GSC_HWMON_MAX_IN_CH) {
+ dev_err(gsc->dev, "too many input channels\n");
+ return -EINVAL;
+ }
+ hwmon->in_ch[i_in] = ch;
+ hwmon->in_config[i_in] =
+ HWMON_I_INPUT | HWMON_I_LABEL;
+ i_in++;
+ break;
+ default:
+ dev_err(gsc->dev, "invalid mode: %d\n", ch->mode);
+ return -EINVAL;
+ }
+ }
+
+ /* setup config structures */
+ hwmon->chip.ops = &gsc_hwmon_ops;
+ hwmon->chip.info = hwmon->info;
+ hwmon->info[0] = &hwmon->temp_info;
+ hwmon->info[1] = &hwmon->in_info;
+ hwmon->temp_info.type = hwmon_temp;
+ hwmon->temp_info.config = hwmon->temp_config;
+ hwmon->in_info.type = hwmon_in;
+ hwmon->in_info.config = hwmon->in_config;
+
+ groups = pdata->fan_base ? gsc_hwmon_groups : NULL;
+ hwmon_dev = devm_hwmon_device_register_with_info(dev,
+ KBUILD_MODNAME, hwmon,
+ &hwmon->chip, groups);
+ return PTR_ERR_OR_ZERO(hwmon_dev);
+}
+
+static const struct of_device_id gsc_hwmon_of_match[] = {
+ { .compatible = "gw,gsc-adc", },
+ {}
+};
+
+static struct platform_driver gsc_hwmon_driver = {
+ .driver = {
+ .name = "gsc-hwmon",
+ .of_match_table = gsc_hwmon_of_match,
+ },
+ .probe = gsc_hwmon_probe,
+};
+
+module_platform_driver(gsc_hwmon_driver);
+
+MODULE_AUTHOR("Tim Harvey <tharvey@gateworks.com>");
+MODULE_DESCRIPTION("GSC hardware monitor driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/platform_data/gsc_hwmon.h b/include/linux/platform_data/gsc_hwmon.h
new file mode 100644
index 00000000..ec1611a
--- /dev/null
+++ b/include/linux/platform_data/gsc_hwmon.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _GSC_HWMON_H
+#define _GSC_HWMON_H
+
+enum gsc_hwmon_mode {
+ mode_temperature,
+ mode_voltage,
+ mode_voltage_raw,
+ mode_max,
+};
+
+/**
+ * struct gsc_hwmon_channel - configuration parameters
+ * @reg: I2C register offset
+ * @mode: channel mode
+ * @name: channel name
+ * @mvoffset: voltage offset
+ * @vdiv: voltage divider array (2 resistor values in milli-ohms)
+ */
+struct gsc_hwmon_channel {
+ unsigned int reg;
+ unsigned int mode;
+ const char *name;
+ unsigned int mvoffset;
+ unsigned int vdiv[2];
+};
+
+/**
+ * struct gsc_hwmon_platform_data - platform data for gsc_hwmon driver
+ * @channels: pointer to array of gsc_hwmon_channel structures
+ * describing channels
+ * @nchannels: number of elements in @channels array
+ * @vreference: voltage reference (mV)
+ * @resolution: ADC bit resolution
+ * @fan_base: register base for FAN controller
+ */
+struct gsc_hwmon_platform_data {
+ const struct gsc_hwmon_channel *channels;
+ int nchannels;
+ unsigned int resolution;
+ unsigned int vreference;
+ unsigned int fan_base;
+};
+#endif
--
2.7.4
^ permalink raw reply related
* [PATCH v10 0/3] Add support for the Gateworks System Controller
From: Tim Harvey @ 2020-05-15 15:18 UTC (permalink / raw)
To: Lee Jones, Jean Delvare, Guenter Roeck, linux-hwmon, Rob Herring,
Frank Rowand, devicetree, linux-kernel, Robert Jones
Cc: Tim Harvey
This series adds support for the Gateworks System Controller used on Gateworks
Laguna, Ventana, and Newport product families.
The GSC is an MSP430 I2C slave controller whose firmware embeds the following
features:
- I/O expander (16 GPIO's emulating a PCA955x)
- EEPROM (enumating AT24)
- RTC (enumating DS1672)
- HWMON
- Interrupt controller with tamper detect, user pushbotton
- Watchdog controller capable of full board power-cycle
- Power Control capable of full board power-cycle
see http://trac.gateworks.com/wiki/gsc for more details
v10:
- mfd: fix typo and gramatical errors in Kconfig and comment block
- mfd: drop unused i2c device-id table
- mfd: added Lee's ack in s-o-b
v9:
- rebase against 5.7-rc2
- dt-binding: remove allOf: see https://lkml.org/lkml/2020/4/15/1930
- dt-binding: encorporate Lee's review comments for item descriptions
- dt-binding: added Reviewed-by: Rob Herring <robh@kernel.org>
- mfd: cleanup gsc_powerdown() by using BIT(), put_unaligned_le32(), and
avoid unnecessary assignments
- mfd: rename GSC_CTRL_1 SLEEP related defines to simplify
- mfd: add better description and sub-module info to driver description
- mfd: whitespace changes per review
- mfd: remove unused irq_data pointer in ddata
- mfd: remove unnecesary i2c_set_clientdata
- mfd: use devm_i2c_new_dummy_device to avoid need of free's
- mfd: change regsiter definitions to enum
- mfd: export gsc_{read,write} instead of sharing them via ddata
- hwmon: use exported gsc_{read,write}
- hwmon: added Reviewed-by: Guenter Roeck <linux@roeck-us.net>
v8:
- mfd: whitespace fixes
- mfd: describe sub-devices in Kconfig
- mfd: add error print for invalid command
- mfd: update copyright
- mfd: use devm_of_platform_populate
- mfd: use probe_new
- mfd: move hwmon's regmap init to hwmon
- hwmon: move hwmon's regmap init to hwmon
- dt-bindings: add register to fan-controller node name
v7:
- dt-bindings: change divider from mili-ohms to ohms
- dt-bindings: add constraints for voltage divider and offset
- dt-bindings: remove unnecessary ref for offset
- dt-bindings: renamed fan to fan-controller and changed base prop to reg
- mfd: remove irq from private data struct
- hwmon: fix whitespace in Kconfig
- hwmon: remove unnecessary device pointer in private data
- hwmon: change divider from mili-ohms to ohms
- hwmon: move fan base property to reg
v6:
- hwmon: fix size of info field
- hwmon: improve pwm output control documentation
- hwmon: include unit suffix in divider and offset
- hwmon: change subnode name to gsc-adc
- hwmon: change to fan subnode
- hwmon: fix voltage offset
- dt-bindings: fix commit message typo
- dt-bindings: drop invalid description from #interrupt-cells property
- dt-bindings: fix adc pattern property
- dt-bindings: add unit suffix
- dt-bindings: replace hwmon/adc with adc/channel
- dt-bindings: changed adc type to gw,mode
- dt-bindings: add unit suffix and drop ref for voltage-divider
- dt-bindings: add unit suffix for voltage-offset
- dt-bindings: moved fan to its own subnode with base register
v5:
- fix checkpatch issues
- fix dt_binding_check issues
- address feedback from v4
v4:
- hwmon: move to using pwm<n>_auto_point<m>_{pwm,temp} for FAN PWM
- hwmon: remove unncessary resolution/scaling properties for ADCs
- bindings: update to yaml Documentation
- removed watchdog driver
v3:
- removed unnecessary input driver
- added wdt driver
- bindings: encorporated feedback from mailng list
- hwmon:
- encoroprated feedback from mailng list
- added support for raw ADC voltage input used in newer GSC firmware
v2:
- change license comment block style
- remove COMPILE_TEST
- fixed whitespace issues
- replaced a printk with dev_err
- remove DEBUG
- simplify regmap_bulk_read err check
- remove break after returns in switch statement
- fix fan setpoint buffer address
- remove unnecessary parens
- consistently use struct device *dev pointer
- add validation for hwmon child node props
- move parsing of of to own function
- use strlcpy to ensure null termination
- fix static array sizes and removed unnecessary initializers
- dynamically allocate channels
- fix fan input label
- support platform data
Tim Harvey (3):
dt-bindings: mfd: Add Gateworks System Controller bindings
mfd: add Gateworks System Controller core driver
hwmon: add Gateworks System Controller support
.../devicetree/bindings/mfd/gateworks-gsc.yaml | 196 +++++++++++
Documentation/hwmon/gsc-hwmon.rst | 53 +++
Documentation/hwmon/index.rst | 1 +
MAINTAINERS | 11 +
drivers/hwmon/Kconfig | 9 +
drivers/hwmon/Makefile | 1 +
drivers/hwmon/gsc-hwmon.c | 390 +++++++++++++++++++++
drivers/mfd/Kconfig | 15 +
drivers/mfd/Makefile | 1 +
drivers/mfd/gateworks-gsc.c | 278 +++++++++++++++
include/linux/mfd/gsc.h | 76 ++++
include/linux/platform_data/gsc_hwmon.h | 44 +++
12 files changed, 1075 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/gateworks-gsc.yaml
create mode 100644 Documentation/hwmon/gsc-hwmon.rst
create mode 100644 drivers/hwmon/gsc-hwmon.c
create mode 100644 drivers/mfd/gateworks-gsc.c
create mode 100644 include/linux/mfd/gsc.h
create mode 100644 include/linux/platform_data/gsc_hwmon.h
--
2.7.4
^ permalink raw reply
* [PATCH v10 2/3] mfd: add Gateworks System Controller core driver
From: Tim Harvey @ 2020-05-15 15:18 UTC (permalink / raw)
To: Lee Jones, Jean Delvare, Guenter Roeck, linux-hwmon, Rob Herring,
Frank Rowand, devicetree, linux-kernel, Robert Jones
Cc: Tim Harvey
In-Reply-To: <1589555891-16502-1-git-send-email-tharvey@gateworks.com>
The Gateworks System Controller (GSC) is an I2C slave controller
implemented with an MSP430 micro-controller whose firmware embeds the
following features:
- I/O expander (16 GPIO's) using PCA955x protocol
- Real Time Clock using DS1672 protocol
- User EEPROM using AT24 protocol
- HWMON using custom protocol
- Interrupt controller with tamper detect, user pushbotton
- Watchdog controller capable of full board power-cycle
- Power Control capable of full board power-cycle
see http://trac.gateworks.com/wiki/gsc for more details
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
---
v10:
- fix typo and gramatical errors in Kconfig and comment block
- drop unused i2c device-id table
- added Lee's ack in s-o-b
v9:
- rebase against 5.7-rc2
- cleanup gsc_powerdown() by using BIT(), put_unaligned_le32(), and avoid
unnecessary assignments
- rename GSC_CTRL_1 SLEEP related defines to simplify
- add better description and sub-module info to driver description
- whitespace changes per review
- remove unused irq_data pointer in ddata
- remove unnecesary i2c_set_clientdata
- use devm_i2c_new_dummy_device to avoid need of free's
- change regsiter definitions to enum
- export gsc_{read,write} instead of sharing them via ddata
v8:
- whitespace fixes
- describe sub-devices in Kconfig
- add error print for invalid command
- update copyright
- use devm_of_platform_populate
- use probe_new
- move hwmon's regmap init to hwmon
v7:
- remove irq from private data struct
v6:
- remove duplicate signature and fix commit log
v5:
- simplify powerdown function
v4:
- remove hwmon max reg check/define
- fix powerdown function
v3:
- rename gsc->gateworks-gsc
- remove uncecessary include for linux/mfd/core.h
- upercase I2C in comments
- remove i2c debug
- remove uncecessary comments
- don't use KBUILD_MODNAME for name
- remove unnecessary v1/v2/v3 tracking
- unregister hwmon i2c adapter on remove
v2:
- change license comment block style
- remove COMPILE_TEST (Randy)
- fixed whitespace issues
- replaced a printk with dev_err
---
MAINTAINERS | 8 ++
drivers/mfd/Kconfig | 15 +++
drivers/mfd/Makefile | 1 +
drivers/mfd/gateworks-gsc.c | 278 ++++++++++++++++++++++++++++++++++++++++++++
include/linux/mfd/gsc.h | 76 ++++++++++++
5 files changed, 378 insertions(+)
create mode 100644 drivers/mfd/gateworks-gsc.c
create mode 100644 include/linux/mfd/gsc.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 091ec22..c78a014 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7028,6 +7028,14 @@ F: kernel/futex.c
F: tools/perf/bench/futex*
F: tools/testing/selftests/futex/
+GATEWORKS SYSTEM CONTROLLER (GSC) DRIVER
+M: Tim Harvey <tharvey@gateworks.com>
+M: Robert Jones <rjones@gateworks.com>
+S: Maintained
+F: Documentation/devicetree/bindings/mfd/gateworks-gsc.yaml
+F: drivers/mfd/gateworks-gsc.c
+F: include/linux/mfd/gsc.h
+
GASKET DRIVER FRAMEWORK
M: Rob Springer <rspringer@google.com>
M: Todd Poynor <toddpoynor@google.com>
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 0a59249..05448e7 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -407,6 +407,21 @@ config MFD_EXYNOS_LPASS
Select this option to enable support for Samsung Exynos Low Power
Audio Subsystem.
+config MFD_GATEWORKS_GSC
+ tristate "Gateworks System Controller"
+ depends on (I2C && OF)
+ select MFD_CORE
+ select REGMAP_I2C
+ select REGMAP_IRQ
+ help
+ Enable support for the Gateworks System Controller (GSC) found
+ on Gateworks Single Board Computers supporting system functions
+ such as push-button monitor, multiple ADC's for voltage and
+ temperature monitoring, fan controller and watchdog monitor.
+ This driver provides common support for accessing the device.
+ Additional drivers must be enabled in order to use the
+ functionality of the device.
+
config MFD_MC13XXX
tristate
depends on (SPI_MASTER || I2C)
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index f935d10..ed433ae 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_MFD_BCM590XX) += bcm590xx.o
obj-$(CONFIG_MFD_BD9571MWV) += bd9571mwv.o
obj-$(CONFIG_MFD_CROS_EC_DEV) += cros_ec_dev.o
obj-$(CONFIG_MFD_EXYNOS_LPASS) += exynos-lpass.o
+obj-$(CONFIG_MFD_GATEWORKS_GSC) += gateworks-gsc.o
obj-$(CONFIG_HTC_PASIC3) += htc-pasic3.o
obj-$(CONFIG_HTC_I2CPLD) += htc-i2cpld.o
diff --git a/drivers/mfd/gateworks-gsc.c b/drivers/mfd/gateworks-gsc.c
new file mode 100644
index 00000000..d43a4dd
--- /dev/null
+++ b/drivers/mfd/gateworks-gsc.c
@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * The Gateworks System Controller (GSC) is a multi-function
+ * device designed for use in Gateworks Single Board Computers.
+ * The control interface is I2C, with an interrupt. The device supports
+ * system functions such as push-button monitoring, multiple ADC's for
+ * voltage and temperature monitoring, fan controller and watchdog monitor.
+ *
+ * Copyright (C) 2020 Gateworks Corporation
+ */
+
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/mfd/gsc.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <asm/unaligned.h>
+
+/*
+ * The GSC suffers from an errata where occasionally during
+ * ADC cycles the chip can NAK I2C transactions. To ensure we have reliable
+ * register access we place retries around register access.
+ */
+#define I2C_RETRIES 3
+
+int gsc_write(void *context, unsigned int reg, unsigned int val)
+{
+ struct i2c_client *client = context;
+ int retry, ret;
+
+ for (retry = 0; retry < I2C_RETRIES; retry++) {
+ ret = i2c_smbus_write_byte_data(client, reg, val);
+ /*
+ * -EAGAIN returned when the i2c host controller is busy
+ * -EIO returned when i2c device is busy
+ */
+ if (ret != -EAGAIN && ret != -EIO)
+ break;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(gsc_write);
+
+int gsc_read(void *context, unsigned int reg, unsigned int *val)
+{
+ struct i2c_client *client = context;
+ int retry, ret;
+
+ for (retry = 0; retry < I2C_RETRIES; retry++) {
+ ret = i2c_smbus_read_byte_data(client, reg);
+ /*
+ * -EAGAIN returned when the i2c host controller is busy
+ * -EIO returned when i2c device is busy
+ */
+ if (ret != -EAGAIN && ret != -EIO)
+ break;
+ }
+ *val = ret & 0xff;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(gsc_read);
+
+/*
+ * gsc_powerdown - API to use GSC to power down board for a specific time
+ *
+ * secs - number of seconds to remain powered off
+ */
+static int gsc_powerdown(struct gsc_dev *gsc, unsigned long secs)
+{
+ int ret;
+ unsigned char regs[4];
+
+ dev_info(&gsc->i2c->dev, "GSC powerdown for %ld seconds\n",
+ secs);
+
+ put_unaligned_le32(secs, regs);
+ ret = regmap_bulk_write(gsc->regmap, GSC_TIME_ADD, regs, 4);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(gsc->regmap, GSC_CTRL_1,
+ BIT(GSC_CTRL_1_SLEEP_ADD),
+ BIT(GSC_CTRL_1_SLEEP_ADD));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(gsc->regmap, GSC_CTRL_1,
+ BIT(GSC_CTRL_1_SLEEP_ACTIVATE) |
+ BIT(GSC_CTRL_1_SLEEP_ENABLE),
+ BIT(GSC_CTRL_1_SLEEP_ACTIVATE) |
+ BIT(GSC_CTRL_1_SLEEP_ENABLE));
+
+
+ return ret;
+}
+
+static ssize_t gsc_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct gsc_dev *gsc = dev_get_drvdata(dev);
+ const char *name = attr->attr.name;
+ int rz = 0;
+
+ if (strcasecmp(name, "fw_version") == 0)
+ rz = sprintf(buf, "%d\n", gsc->fwver);
+ else if (strcasecmp(name, "fw_crc") == 0)
+ rz = sprintf(buf, "0x%04x\n", gsc->fwcrc);
+ else
+ dev_err(dev, "invalid command: '%s'\n", name);
+
+ return rz;
+}
+
+static ssize_t gsc_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct gsc_dev *gsc = dev_get_drvdata(dev);
+ const char *name = attr->attr.name;
+ long value;
+
+ if (strcasecmp(name, "powerdown") == 0) {
+ if (kstrtol(buf, 0, &value) == 0)
+ gsc_powerdown(gsc, value);
+ } else {
+ dev_err(dev, "invalid command: '%s\n", name);
+ }
+
+ return count;
+}
+
+static struct device_attribute attr_fwver =
+ __ATTR(fw_version, 0440, gsc_show, NULL);
+static struct device_attribute attr_fwcrc =
+ __ATTR(fw_crc, 0440, gsc_show, NULL);
+static struct device_attribute attr_pwrdown =
+ __ATTR(powerdown, 0220, NULL, gsc_store);
+
+static struct attribute *gsc_attrs[] = {
+ &attr_fwver.attr,
+ &attr_fwcrc.attr,
+ &attr_pwrdown.attr,
+ NULL,
+};
+
+static struct attribute_group attr_group = {
+ .attrs = gsc_attrs,
+};
+
+static const struct of_device_id gsc_of_match[] = {
+ { .compatible = "gw,gsc", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, gsc_of_match);
+
+static struct regmap_bus gsc_regmap_bus = {
+ .reg_read = gsc_read,
+ .reg_write = gsc_write,
+};
+
+static const struct regmap_config gsc_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .cache_type = REGCACHE_NONE,
+ .max_register = GSC_WP,
+};
+
+static const struct regmap_irq gsc_irqs[] = {
+ REGMAP_IRQ_REG(GSC_IRQ_PB, 0, BIT(GSC_IRQ_PB)),
+ REGMAP_IRQ_REG(GSC_IRQ_KEY_ERASED, 0, BIT(GSC_IRQ_KEY_ERASED)),
+ REGMAP_IRQ_REG(GSC_IRQ_EEPROM_WP, 0, BIT(GSC_IRQ_EEPROM_WP)),
+ REGMAP_IRQ_REG(GSC_IRQ_RESV, 0, BIT(GSC_IRQ_RESV)),
+ REGMAP_IRQ_REG(GSC_IRQ_GPIO, 0, BIT(GSC_IRQ_GPIO)),
+ REGMAP_IRQ_REG(GSC_IRQ_TAMPER, 0, BIT(GSC_IRQ_TAMPER)),
+ REGMAP_IRQ_REG(GSC_IRQ_WDT_TIMEOUT, 0, BIT(GSC_IRQ_WDT_TIMEOUT)),
+ REGMAP_IRQ_REG(GSC_IRQ_SWITCH_HOLD, 0, BIT(GSC_IRQ_SWITCH_HOLD)),
+};
+
+static const struct regmap_irq_chip gsc_irq_chip = {
+ .name = "gateworks-gsc",
+ .irqs = gsc_irqs,
+ .num_irqs = ARRAY_SIZE(gsc_irqs),
+ .num_regs = 1,
+ .status_base = GSC_IRQ_STATUS,
+ .mask_base = GSC_IRQ_ENABLE,
+ .mask_invert = true,
+ .ack_base = GSC_IRQ_STATUS,
+ .ack_invert = true,
+};
+
+static int gsc_probe(struct i2c_client *client)
+{
+ struct device *dev = &client->dev;
+ struct gsc_dev *gsc;
+ struct regmap_irq_chip_data *irq_data;
+ int ret;
+ unsigned int reg;
+
+ gsc = devm_kzalloc(dev, sizeof(*gsc), GFP_KERNEL);
+ if (!gsc)
+ return -ENOMEM;
+
+ gsc->dev = &client->dev;
+ gsc->i2c = client;
+ i2c_set_clientdata(client, gsc);
+
+ gsc->regmap = devm_regmap_init(dev, &gsc_regmap_bus, client,
+ &gsc_regmap_config);
+ if (IS_ERR(gsc->regmap))
+ return PTR_ERR(gsc->regmap);
+
+ if (regmap_read(gsc->regmap, GSC_FW_VER, ®))
+ return -EIO;
+ gsc->fwver = reg;
+
+ regmap_read(gsc->regmap, GSC_FW_CRC, ®);
+ gsc->fwcrc = reg;
+ regmap_read(gsc->regmap, GSC_FW_CRC + 1, ®);
+ gsc->fwcrc |= reg << 8;
+
+ gsc->i2c_hwmon = devm_i2c_new_dummy_device(dev, client->adapter,
+ GSC_HWMON);
+ if (IS_ERR(gsc->i2c_hwmon)) {
+ dev_err(dev, "Failed to allocate I2C device for HWMON\n");
+ return PTR_ERR(gsc->i2c_hwmon);
+ }
+
+ ret = devm_regmap_add_irq_chip(dev, gsc->regmap, client->irq,
+ IRQF_ONESHOT | IRQF_SHARED |
+ IRQF_TRIGGER_FALLING, 0,
+ &gsc_irq_chip, &irq_data);
+ if (ret)
+ return ret;
+
+ dev_info(dev, "Gateworks System Controller v%d: fw 0x%04x\n",
+ gsc->fwver, gsc->fwcrc);
+
+ ret = sysfs_create_group(&dev->kobj, &attr_group);
+ if (ret)
+ dev_err(dev, "failed to create sysfs attrs\n");
+
+ ret = devm_of_platform_populate(dev);
+ if (ret) {
+ sysfs_remove_group(&dev->kobj, &attr_group);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int gsc_remove(struct i2c_client *client)
+{
+ sysfs_remove_group(&client->dev.kobj, &attr_group);
+
+ return 0;
+}
+
+static struct i2c_driver gsc_driver = {
+ .driver = {
+ .name = "gateworks-gsc",
+ .of_match_table = gsc_of_match,
+ },
+ .id_table = gsc_id_table,
+ .probe_new = gsc_probe,
+ .remove = gsc_remove,
+};
+module_i2c_driver(gsc_driver);
+
+MODULE_AUTHOR("Tim Harvey <tharvey@gateworks.com>");
+MODULE_DESCRIPTION("I2C Core interface for GSC");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/gsc.h b/include/linux/mfd/gsc.h
new file mode 100644
index 00000000..6bd639c
--- /dev/null
+++ b/include/linux/mfd/gsc.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020 Gateworks Corporation
+ */
+#ifndef __LINUX_MFD_GSC_H_
+#define __LINUX_MFD_GSC_H_
+
+#include <linux/regmap.h>
+
+/* Device Addresses */
+#define GSC_MISC 0x20
+#define GSC_UPDATE 0x21
+#define GSC_GPIO 0x23
+#define GSC_HWMON 0x29
+#define GSC_EEPROM0 0x50
+#define GSC_EEPROM1 0x51
+#define GSC_EEPROM2 0x52
+#define GSC_EEPROM3 0x53
+#define GSC_RTC 0x68
+
+/* Register offsets */
+enum {
+ GSC_CTRL_0 = 0x00,
+ GSC_CTRL_1 = 0x01,
+ GSC_TIME = 0x02,
+ GSC_TIME_ADD = 0x06,
+ GSC_IRQ_STATUS = 0x0A,
+ GSC_IRQ_ENABLE = 0x0B,
+ GSC_FW_CRC = 0x0C,
+ GSC_FW_VER = 0x0E,
+ GSC_WP = 0x0F,
+};
+
+/* Bit definitions */
+#define GSC_CTRL_0_PB_HARD_RESET 0
+#define GSC_CTRL_0_PB_CLEAR_SECURE_KEY 1
+#define GSC_CTRL_0_PB_SOFT_POWER_DOWN 2
+#define GSC_CTRL_0_PB_BOOT_ALTERNATE 3
+#define GSC_CTRL_0_PERFORM_CRC 4
+#define GSC_CTRL_0_TAMPER_DETECT 5
+#define GSC_CTRL_0_SWITCH_HOLD 6
+
+#define GSC_CTRL_1_SLEEP_ENABLE 0
+#define GSC_CTRL_1_SLEEP_ACTIVATE 1
+#define GSC_CTRL_1_SLEEP_ADD 2
+#define GSC_CTRL_1_SLEEP_NOWAKEPB 3
+#define GSC_CTRL_1_WDT_TIME 4
+#define GSC_CTRL_1_WDT_ENABLE 5
+#define GSC_CTRL_1_SWITCH_BOOT_ENABLE 6
+#define GSC_CTRL_1_SWITCH_BOOT_CLEAR 7
+
+#define GSC_IRQ_PB 0
+#define GSC_IRQ_KEY_ERASED 1
+#define GSC_IRQ_EEPROM_WP 2
+#define GSC_IRQ_RESV 3
+#define GSC_IRQ_GPIO 4
+#define GSC_IRQ_TAMPER 5
+#define GSC_IRQ_WDT_TIMEOUT 6
+#define GSC_IRQ_SWITCH_HOLD 7
+
+int gsc_read(void *context, unsigned int reg, unsigned int *val);
+int gsc_write(void *context, unsigned int reg, unsigned int val);
+
+struct gsc_dev {
+ struct device *dev;
+
+ struct i2c_client *i2c; /* 0x20: interrupt controller, WDT */
+ struct i2c_client *i2c_hwmon; /* 0x29: hwmon, fan controller */
+
+ struct regmap *regmap;
+
+ unsigned int fwver;
+ unsigned short fwcrc;
+};
+
+#endif /* __LINUX_MFD_GSC_H_ */
--
2.7.4
^ permalink raw reply related
* [PATCH v10 1/3] dt-bindings: mfd: Add Gateworks System Controller bindings
From: Tim Harvey @ 2020-05-15 15:18 UTC (permalink / raw)
To: Lee Jones, Jean Delvare, Guenter Roeck, linux-hwmon, Rob Herring,
Frank Rowand, devicetree, linux-kernel, Robert Jones
Cc: Tim Harvey
In-Reply-To: <1589555891-16502-1-git-send-email-tharvey@gateworks.com>
This patch adds documentation of device-tree bindings for the
Gateworks System Controller (GSC).
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
v10:
- no changes
v9:
- added Reviewed-by: Rob Herring <robh@kernel.org>
- remove allOf: see https://lkml.org/lkml/2020/4/15/1930
- encorporate Lee's review comments for item descriptions
v8:
- add register to fan-controller node name
v7:
- change divider from mili-ohms to ohms
- add constraints for voltage divider and offset
- remove unnecessary ref for offset
- renamed fan to fan-controller and changed base prop to reg
v6:
- fix typo
- drop invalid description from #interrupt-cells property
- fix adc pattern property
- add unit suffix
- replace hwmon/adc with adc/channel
- changed adc type to mode and enum int
- add unit suffix and drop ref for voltage-divider
- moved fan to its own subnode with base register
v5:
- resolve dt_binding_check issues
v4:
- move to using pwm<n>_auto_point<m>_{pwm,temp} for FAN PWM
- remove unncessary resolution/scaling properties for ADCs
- update to yaml
- remove watchdog
v3:
- replaced _ with -
- remove input bindings
- added full description of hwmon
- fix unit address of hwmon child nodes
---
.../devicetree/bindings/mfd/gateworks-gsc.yaml | 196 +++++++++++++++++++++
1 file changed, 196 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/gateworks-gsc.yaml
diff --git a/Documentation/devicetree/bindings/mfd/gateworks-gsc.yaml b/Documentation/devicetree/bindings/mfd/gateworks-gsc.yaml
new file mode 100644
index 00000000..487a844
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/gateworks-gsc.yaml
@@ -0,0 +1,196 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/gateworks-gsc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Gateworks System Controller
+
+description: |
+ The Gateworks System Controller (GSC) is a device present across various
+ Gateworks product families that provides a set of system related features
+ such as the following (refer to the board hardware user manuals to see what
+ features are present)
+ - Watchdog Timer
+ - GPIO
+ - Pushbutton controller
+ - Hardware monitor with ADC's for temperature and voltage rails and
+ fan controller
+
+maintainers:
+ - Tim Harvey <tharvey@gateworks.com>
+ - Robert Jones <rjones@gateworks.com>
+
+properties:
+ $nodename:
+ pattern: "gsc@[0-9a-f]{1,2}"
+ compatible:
+ const: gw,gsc
+
+ reg:
+ description: I2C device address
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ adc:
+ type: object
+ description: Optional hardware monitoring module
+
+ properties:
+ compatible:
+ const: gw,gsc-adc
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ patternProperties:
+ "^channel@[0-9]+$":
+ type: object
+ description: |
+ Properties for a single ADC which can report cooked values
+ (i.e. temperature sensor based on thermister), raw values
+ (i.e. voltage rail with a pre-scaling resistor divider).
+
+ properties:
+ reg:
+ description: Register of the ADC
+ maxItems: 1
+
+ label:
+ description: Name of the ADC input
+
+ gw,mode:
+ description: |
+ conversion mode:
+ 0 - temperature, in C*10
+ 1 - pre-scaled voltage value
+ 2 - scaled voltage based on an optional resistor divider
+ and optional offset
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+
+ gw,voltage-divider-ohms:
+ description: Values of resistors for divider on raw ADC input
+ maxItems: 2
+ items:
+ minimum: 1000
+ maximum: 1000000
+
+ gw,voltage-offset-microvolt:
+ description: |
+ A positive voltage offset to apply to a raw ADC
+ (i.e. to compensate for a diode drop).
+ minimum: 0
+ maximum: 1000000
+
+ required:
+ - gw,mode
+ - reg
+ - label
+
+ required:
+ - compatible
+ - "#address-cells"
+ - "#size-cells"
+
+patternProperties:
+ "^fan-controller@[0-9a-f]+$":
+ type: object
+ description: Optional fan controller
+
+ properties:
+ compatible:
+ const: gw,gsc-fan
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ reg:
+ description: The fan controller base address
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - "#interrupt-cells"
+ - "#address-cells"
+ - "#size-cells"
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gsc@20 {
+ compatible = "gw,gsc";
+ reg = <0x20>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <4 GPIO_ACTIVE_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc {
+ compatible = "gw,gsc-adc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 { /* A0: Board Temperature */
+ reg = <0x00>;
+ label = "temp";
+ gw,mode = <0>;
+ };
+
+ channel@2 { /* A1: Input Voltage (raw ADC) */
+ reg = <0x02>;
+ label = "vdd_vin";
+ gw,mode = <1>;
+ gw,voltage-divider-ohms = <22100 1000>;
+ gw,voltage-offset-microvolt = <800000>;
+ };
+
+ channel@b { /* A2: Battery voltage */
+ reg = <0x0b>;
+ label = "vdd_bat";
+ gw,mode = <1>;
+ };
+ };
+
+ fan-controller@2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "gw,gsc-fan";
+ reg = <0x2c>;
+ };
+ };
+ };
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v3 16/20] arm64: dts: juno: Fix GPU interrupt order
From: André Przywara @ 2020-05-15 15:13 UTC (permalink / raw)
To: Sudeep Holla
Cc: Rob Herring, Liviu Dudau, Lorenzo Pieralisi, devicetree,
linux-arm-kernel, Mark Rutland
In-Reply-To: <20200513182405.GE27686@bogus>
On 13/05/2020 19:24, Sudeep Holla wrote:
Hi,
> On Wed, May 13, 2020 at 11:30:12AM +0100, Andre Przywara wrote:
>> The Mali binding insists on the GPU interrupts to be in ordered as: job,
>> mmu, gpu.
>> Sort the GPU interrupts and interrupt-names properties accordingly.
>>
>
> I assume this is not a bug fix, just clean up to make it 100% binding
> compliant. Things work just fine without this too. Just for my info.
Yes, that's true, it works either way right now.
Originally I was under the impression that the purpose of
interrupt-names was to allow any order of interrupts, but according to
Rob this is just to support optional IRQs (so having a shorter list).
The bindings require a certain order, and the dt-schema validation
complains if that differs in the DT.
Cheers,
Andre
^ permalink raw reply
* Re: [PATCHv1 03/19] power: supply: core: add manufacture date properties
From: Sebastian Reichel @ 2020-05-15 15:14 UTC (permalink / raw)
To: Emil Velikov; +Cc: linux-pm, devicetree, linux-kernel, kernel
In-Reply-To: <20200515144732.GC2836808@arch-x1c3>
[-- Attachment #1: Type: text/plain, Size: 725 bytes --]
Hi,
On Fri, May 15, 2020 at 03:47:32PM +0100, Emil Velikov wrote:
> On 2020/05/13, Sebastian Reichel wrote:
> > Some smart batteries store their manufacture date, which is
> > useful to identify the battery and/or to know about the cell
> > quality.
> >
> Have you considered exposing this as a single file? Say following
> the ISO8601 format - YYYY-MM-DD.
Yes. My initial implementation was exactly that. The thing is, that
I suspect some fuel gauge implementations may only expose the year
or just year + month. I chose 3 files, since receiving 'YYYY-MM'
instead of full ISO code might be more unexpected than not having
the DAY file available. But I don't have a strong opinion on this.
-- Sebastian
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* [PATCH 01/17] dt-bindings: i2c: renesas,i2c: Document r8a7742 support
From: Lad Prabhakar @ 2020-05-15 15:08 UTC (permalink / raw)
To: Geert Uytterhoeven, Jens Axboe, Rob Herring, Wolfram Sang,
Ulf Hansson, Sergei Shtylyov, David S. Miller, Wim Van Sebroeck,
Guenter Roeck
Cc: linux-ide, devicetree, linux-kernel, linux-i2c, linux-mmc, netdev,
linux-renesas-soc, linux-watchdog, Prabhakar, Lad Prabhakar
In-Reply-To: <1589555337-5498-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
Document i2c controller for RZ/G1H (R8A7742) SoC, which is compatible
with R-Car Gen2 SoC family.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
---
Documentation/devicetree/bindings/i2c/renesas,i2c.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/i2c/renesas,i2c.txt b/Documentation/devicetree/bindings/i2c/renesas,i2c.txt
index c359965..a03f9f5 100644
--- a/Documentation/devicetree/bindings/i2c/renesas,i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/renesas,i2c.txt
@@ -2,6 +2,7 @@ I2C for R-Car platforms
Required properties:
- compatible:
+ "renesas,i2c-r8a7742" if the device is a part of a R8A7742 SoC.
"renesas,i2c-r8a7743" if the device is a part of a R8A7743 SoC.
"renesas,i2c-r8a7744" if the device is a part of a R8A7744 SoC.
"renesas,i2c-r8a7745" if the device is a part of a R8A7745 SoC.
--
2.7.4
^ permalink raw reply related
* [PATCH 02/17] dt-bindings: i2c: renesas,iic: Document r8a7742 support
From: Lad Prabhakar @ 2020-05-15 15:08 UTC (permalink / raw)
To: Geert Uytterhoeven, Jens Axboe, Rob Herring, Wolfram Sang,
Ulf Hansson, Sergei Shtylyov, David S. Miller, Wim Van Sebroeck,
Guenter Roeck
Cc: linux-ide, devicetree, linux-kernel, linux-i2c, linux-mmc, netdev,
linux-renesas-soc, linux-watchdog, Prabhakar, Lad Prabhakar
In-Reply-To: <1589555337-5498-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
Document IIC controller for RZ/G1H (R8A7742) SoC, which is compatible
with R-Car Gen2 SoC family.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
---
Documentation/devicetree/bindings/i2c/renesas,iic.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/i2c/renesas,iic.txt b/Documentation/devicetree/bindings/i2c/renesas,iic.txt
index ffe085c..89facb0 100644
--- a/Documentation/devicetree/bindings/i2c/renesas,iic.txt
+++ b/Documentation/devicetree/bindings/i2c/renesas,iic.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible :
- "renesas,iic-r8a73a4" (R-Mobile APE6)
- "renesas,iic-r8a7740" (R-Mobile A1)
+ - "renesas,iic-r8a7742" (RZ/G1H)
- "renesas,iic-r8a7743" (RZ/G1M)
- "renesas,iic-r8a7744" (RZ/G1N)
- "renesas,iic-r8a7745" (RZ/G1E)
--
2.7.4
^ permalink raw reply related
* [PATCH 03/17] ARM: dts: r8a7742: Add I2C and IIC support
From: Lad Prabhakar @ 2020-05-15 15:08 UTC (permalink / raw)
To: Geert Uytterhoeven, Jens Axboe, Rob Herring, Wolfram Sang,
Ulf Hansson, Sergei Shtylyov, David S. Miller, Wim Van Sebroeck,
Guenter Roeck
Cc: linux-ide, devicetree, linux-kernel, linux-i2c, linux-mmc, netdev,
linux-renesas-soc, linux-watchdog, Prabhakar, Lad Prabhakar
In-Reply-To: <1589555337-5498-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
Add the I2C[0-3] and IIC[0-3] devices nodes to the R8A7742 device tree.
Automatic transmission for PMIC control is not available on IIC3 hence
compatible string "renesas,rcar-gen2-iic" and "renesas,rmobile-iic" is
not added to iic3 node.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
---
arch/arm/boot/dts/r8a7742.dtsi | 122 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 122 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index 305d808..f28c32d 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -359,6 +359,128 @@
ranges = <0 0 0xe6300000 0x40000>;
};
+ i2c0: i2c@e6508000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7742",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 931>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 931>;
+ i2c-scl-internal-delay-ns = <110>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@e6518000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7742",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6518000 0 0x40>;
+ interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 930>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 930>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@e6530000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7742",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6530000 0 0x40>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 929>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 929>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@e6540000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7742",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6540000 0 0x40>;
+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 928>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 928>;
+ i2c-scl-internal-delay-ns = <110>;
+ status = "disabled";
+ };
+
+ iic0: i2c@e6500000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7742",
+ "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe6500000 0 0x425>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>;
+ dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+ <&dmac1 0x61>, <&dmac1 0x62>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 318>;
+ status = "disabled";
+ };
+
+ iic1: i2c@e6510000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7742",
+ "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe6510000 0 0x425>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 323>;
+ dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+ <&dmac1 0x65>, <&dmac1 0x66>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 323>;
+ status = "disabled";
+ };
+
+ iic2: i2c@e6520000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7742",
+ "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe6520000 0 0x425>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 300>;
+ dmas = <&dmac0 0x69>, <&dmac0 0x6a>,
+ <&dmac1 0x69>, <&dmac1 0x6a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 300>;
+ status = "disabled";
+ };
+
+ iic3: i2c@e60b0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7742";
+ reg = <0 0xe60b0000 0 0x425>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 926>;
+ dmas = <&dmac0 0x77>, <&dmac0 0x78>,
+ <&dmac1 0x77>, <&dmac1 0x78>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 926>;
+ status = "disabled";
+ };
+
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a7742",
"renesas,rcar-dmac";
--
2.7.4
^ permalink raw reply related
* [PATCH 04/17] dt-bindings: mmc: renesas,sdhi: Document r8a7742 support
From: Lad Prabhakar @ 2020-05-15 15:08 UTC (permalink / raw)
To: Geert Uytterhoeven, Jens Axboe, Rob Herring, Wolfram Sang,
Ulf Hansson, Sergei Shtylyov, David S. Miller, Wim Van Sebroeck,
Guenter Roeck
Cc: linux-ide, devicetree, linux-kernel, linux-i2c, linux-mmc, netdev,
linux-renesas-soc, linux-watchdog, Prabhakar, Lad Prabhakar
In-Reply-To: <1589555337-5498-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
Document SDHI controller for RZ/G1H (R8A7742) SoC, which is compatible
with R-Car Gen2 SoC family.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
---
Documentation/devicetree/bindings/mmc/renesas,sdhi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.txt b/Documentation/devicetree/bindings/mmc/renesas,sdhi.txt
index e6cc478..0ca9a62 100644
--- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.txt
+++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.txt
@@ -7,6 +7,7 @@ Required properties:
"renesas,sdhi-r7s9210" - SDHI IP on R7S9210 SoC
"renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC
"renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC
+ "renesas,sdhi-r8a7742" - SDHI IP on R8A7742 SoC
"renesas,sdhi-r8a7743" - SDHI IP on R8A7743 SoC
"renesas,sdhi-r8a7744" - SDHI IP on R8A7744 SoC
"renesas,sdhi-r8a7745" - SDHI IP on R8A7745 SoC
--
2.7.4
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox