* [PATCH v9 7/7] clk: rockchip: rk3588: drop RK3588_LINKED_CLK
From: Sebastian Reichel @ 2024-03-25 19:33 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, linux-clk
Cc: Elaine Zhang, Kever Yang, Heiko Stuebner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, huangtao, andy.yan,
Michal Tomek, Ilya K, Chad LeClair, devicetree, linux-rockchip,
Sebastian Reichel, kernel
In-Reply-To: <20240325193609.237182-1-sebastian.reichel@collabora.com>
With the proper GATE_LINK support, we no longer need to keep the
linked clocks always on. Thus it's time to drop the CLK_IS_CRITICAL
flag for them.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/clk/rockchip/clk-rk3588.c | 27 ++++++++++++---------------
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c
index 1bf84ac44e85..42579b6f74b4 100644
--- a/drivers/clk/rockchip/clk-rk3588.c
+++ b/drivers/clk/rockchip/clk-rk3588.c
@@ -12,9 +12,6 @@
#include <dt-bindings/clock/rockchip,rk3588-cru.h>
#include "clk.h"
-#define RK3588_LINKED_CLK CLK_IS_CRITICAL
-
-
#define RK3588_GRF_SOC_STATUS0 0x600
#define RK3588_PHYREF_ALT_GATE 0xc38
@@ -1439,7 +1436,7 @@ static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = {
COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(77), 0, 2, MFLAGS,
RK3588_CLKGATE_CON(31), 0, GFLAGS),
- COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, RK3588_LINKED_CLK,
+ COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(31), 1, GFLAGS),
GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0,
@@ -1668,13 +1665,13 @@ static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = {
RK3588_CLKGATE_CON(42), 9, GFLAGS),
/* vdpu */
- COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, RK3588_LINKED_CLK,
+ COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0,
RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(44), 0, GFLAGS),
COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0,
RK3588_CLKSEL_CON(98), 7, 2, MFLAGS,
RK3588_CLKGATE_CON(44), 1, GFLAGS),
- COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
+ COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(98), 9, 2, MFLAGS,
RK3588_CLKGATE_CON(44), 2, GFLAGS),
COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0,
@@ -1725,9 +1722,9 @@ static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = {
COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0,
RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(47), 1, GFLAGS),
- GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", RK3588_LINKED_CLK,
+ GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 0,
RK3588_CLKGATE_CON(47), 4, GFLAGS),
- GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", RK3588_LINKED_CLK,
+ GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 0,
RK3588_CLKGATE_CON(47), 5, GFLAGS),
COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0,
RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS,
@@ -1737,10 +1734,10 @@ static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = {
RK3588_CLKGATE_CON(48), 6, GFLAGS),
/* vi */
- COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, RK3588_LINKED_CLK,
+ COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0,
RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(49), 0, GFLAGS),
- COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
+ COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(106), 8, 2, MFLAGS,
RK3588_CLKGATE_CON(49), 1, GFLAGS),
COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0,
@@ -1910,10 +1907,10 @@ static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = {
COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0,
RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(52), 0, GFLAGS),
- COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, RK3588_LINKED_CLK,
+ COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0,
RK3588_CLKSEL_CON(110), 8, 2, MFLAGS,
RK3588_CLKGATE_CON(52), 1, GFLAGS),
- COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
+ COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(110), 10, 2, MFLAGS,
RK3588_CLKGATE_CON(52), 2, GFLAGS),
COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0,
@@ -2416,7 +2413,7 @@ static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = {
static struct rockchip_clk_branch rk3588_clk_branches[] = {
GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", ACLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),
GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", HCLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),
- GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),
+ GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, 0, RK3588_CLKGATE_CON(31), 2, GFLAGS),
GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 2, GFLAGS),
GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", HCLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 3, GFLAGS),
GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 7, GFLAGS),
@@ -2428,9 +2425,9 @@ static struct rockchip_clk_branch rk3588_clk_branches[] = {
GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 4, GFLAGS),
GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 5, GFLAGS),
GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", ACLK_VOP_LOW_ROOT, 0, RK3588_CLKGATE_CON(55), 9, GFLAGS),
- GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS),
+ GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, 0, RK3588_CLKGATE_CON(55), 5, GFLAGS),
GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(59), 6, GFLAGS),
- GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS),
+ GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(59), 9, GFLAGS),
GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 1, GFLAGS),
GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 4, GFLAGS),
GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", HCLK_NVM, 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),
--
2.43.0
^ permalink raw reply related
* [PATCH v9 6/7] clk: rockchip: implement linked gate clock support
From: Sebastian Reichel @ 2024-03-25 19:33 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, linux-clk
Cc: Elaine Zhang, Kever Yang, Heiko Stuebner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, huangtao, andy.yan,
Michal Tomek, Ilya K, Chad LeClair, devicetree, linux-rockchip,
Sebastian Reichel, kernel
In-Reply-To: <20240325193609.237182-1-sebastian.reichel@collabora.com>
Recent Rockchip SoCs have a new hardware block called Native Interface
Unit (NIU), which gates clocks to devices behind them. These clock
gates will only have a running output clock when all of the following
conditions are met:
1. the parent clock is enabled
2. the enable bit is set correctly
3. the linked clock is enabled
To handle them this code registers them as a normal gate type clock,
which takes care of condition 1 + 2. The linked clock is handled by
using runtime PM clocks. Handling it via runtime PM requires setting
up a struct device for each of these clocks with a driver attached
to use the correct runtime PM operations. Thus the complete handling
of these clocks has been moved into its own driver.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-rk3588.c | 23 +------
drivers/clk/rockchip/clk.c | 52 ++++++++++++++++
drivers/clk/rockchip/clk.h | 25 ++++++++
drivers/clk/rockchip/gate-link.c | 99 +++++++++++++++++++++++++++++++
5 files changed, 179 insertions(+), 21 deletions(-)
create mode 100644 drivers/clk/rockchip/gate-link.c
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 36894f6a7022..179be95c6ffb 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -13,6 +13,7 @@ clk-rockchip-y += clk-inverter.o
clk-rockchip-y += clk-mmc-phase.o
clk-rockchip-y += clk-muxgrf.o
clk-rockchip-y += clk-ddr.o
+clk-rockchip-y += gate-link.o
clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o
obj-$(CONFIG_CLK_PX30) += clk-px30.o
diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c
index 29f31a5526fa..1bf84ac44e85 100644
--- a/drivers/clk/rockchip/clk-rk3588.c
+++ b/drivers/clk/rockchip/clk-rk3588.c
@@ -12,25 +12,6 @@
#include <dt-bindings/clock/rockchip,rk3588-cru.h>
#include "clk.h"
-/*
- * Recent Rockchip SoCs have a new hardware block called Native Interface
- * Unit (NIU), which gates clocks to devices behind them. These effectively
- * need two parent clocks.
- *
- * Downstream enables the linked clock via runtime PM whenever the gate is
- * enabled. This implementation uses separate clock nodes for each of the
- * linked gate clocks, which leaks parts of the clock tree into DT.
- *
- * The GATE_LINK macro instead takes the second parent via 'linkname', but
- * ignores the information. Once the clock framework is ready to handle it, the
- * information should be passed on here. But since these clocks are required to
- * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked
- * clocks critical until a better solution is available. This will waste some
- * power, but avoids leaking implementation details into DT or hanging the
- * system.
- */
-#define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \
- GATE(_id, cname, pname, f, o, b, gf)
#define RK3588_LINKED_CLK CLK_IS_CRITICAL
@@ -2513,8 +2494,8 @@ static int clk_rk3588_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
- rockchip_clk_register_branches(ctx, rk3588_clk_branches,
- ARRAY_SIZE(rk3588_clk_branches));
+ rockchip_clk_register_late_branches(dev, ctx, rk3588_clk_branches,
+ ARRAY_SIZE(rk3588_clk_branches));
rk3588_rst_init(np, ctx->reg_base);
rockchip_register_restart_notifier(ctx, RK3588_GLB_SRST_FST, NULL);
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index e150bc1fc319..f5f11cc60046 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -19,6 +19,7 @@
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reboot.h>
@@ -440,6 +441,29 @@ unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list,
}
EXPORT_SYMBOL_GPL(rockchip_clk_find_max_clk_id);
+static struct platform_device *rockchip_clk_register_gate_link(
+ struct device *parent_dev,
+ struct rockchip_clk_provider *ctx,
+ struct rockchip_clk_branch *clkbr)
+{
+ struct rockchip_gate_link_platdata gate_link_pdata = {
+ .ctx = ctx,
+ .clkbr = clkbr,
+ };
+
+ struct platform_device_info pdevinfo = {
+ .parent = parent_dev,
+ .name = "rockchip-gate-link-clk",
+ .id = clkbr->id,
+ .fwnode = dev_fwnode(parent_dev),
+ .of_node_reused = true,
+ .data = &gate_link_pdata,
+ .size_data = sizeof(gate_link_pdata),
+ };
+
+ return platform_device_register_full(&pdevinfo);
+}
+
void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
struct rockchip_clk_branch *list,
unsigned int nr_clk)
@@ -565,6 +589,9 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
list->div_width, list->div_flags,
ctx->reg_base, &ctx->lock);
break;
+ case branch_linked_gate:
+ /* must be registered late, fall-through for error message */
+ break;
}
/* none of the cases above matched */
@@ -585,6 +612,31 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
}
EXPORT_SYMBOL_GPL(rockchip_clk_register_branches);
+void rockchip_clk_register_late_branches(struct device *dev,
+ struct rockchip_clk_provider *ctx,
+ struct rockchip_clk_branch *list,
+ unsigned int nr_clk)
+{
+ unsigned int idx;
+
+ for (idx = 0; idx < nr_clk; idx++, list++) {
+ struct platform_device *pdev = NULL;
+
+ switch (list->branch_type) {
+ case branch_linked_gate:
+ pdev = rockchip_clk_register_gate_link(dev, ctx, list);
+ break;
+ default:
+ dev_err(dev, "unknown clock type %d\n", list->branch_type);
+ break;
+ }
+
+ if (!pdev)
+ dev_err(dev, "failed to register device for clock %s\n", list->name);
+ }
+}
+EXPORT_SYMBOL_GPL(rockchip_clk_register_late_branches);
+
void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
unsigned int lookup_id,
const char *name, const char *const *parent_names,
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index e39392e1c2a2..15aa2fd5265b 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -517,6 +517,7 @@ enum rockchip_clk_branch_type {
branch_divider,
branch_fraction_divider,
branch_gate,
+ branch_linked_gate,
branch_mmc,
branch_inverter,
branch_factor,
@@ -544,6 +545,7 @@ struct rockchip_clk_branch {
int gate_offset;
u8 gate_shift;
u8 gate_flags;
+ unsigned int linked_clk_id;
struct rockchip_clk_branch *child;
};
@@ -842,6 +844,20 @@ struct rockchip_clk_branch {
.gate_flags = gf, \
}
+#define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \
+ { \
+ .id = _id, \
+ .branch_type = branch_linked_gate, \
+ .name = cname, \
+ .parent_names = (const char *[]){ pname }, \
+ .linked_clk_id = linkedclk, \
+ .num_parents = 1, \
+ .flags = f, \
+ .gate_offset = o, \
+ .gate_shift = b, \
+ .gate_flags = gf, \
+ }
+
#define MMC(_id, cname, pname, offset, shift) \
{ \
.id = _id, \
@@ -981,6 +997,11 @@ static inline void rockchip_clk_set_lookup(struct rockchip_clk_provider *ctx,
ctx->clk_data.clks[id] = clk;
}
+struct rockchip_gate_link_platdata {
+ struct rockchip_clk_provider *ctx;
+ struct rockchip_clk_branch *clkbr;
+};
+
struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
void __iomem *base, unsigned long nr_clks);
void rockchip_clk_of_add_provider(struct device_node *np,
@@ -990,6 +1011,10 @@ unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list,
void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
struct rockchip_clk_branch *list,
unsigned int nr_clk);
+void rockchip_clk_register_late_branches(struct device *dev,
+ struct rockchip_clk_provider *ctx,
+ struct rockchip_clk_branch *list,
+ unsigned int nr_clk);
void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
struct rockchip_pll_clock *pll_list,
unsigned int nr_pll, int grf_lock_offset);
diff --git a/drivers/clk/rockchip/gate-link.c b/drivers/clk/rockchip/gate-link.c
new file mode 100644
index 000000000000..47b6f3e7a6a2
--- /dev/null
+++ b/drivers/clk/rockchip/gate-link.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2024 Collabora Ltd.
+ * Author: Sebastian Reichel <sebastian.reichel@collabora.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/pm_clock.h>
+#include <linux/pm_runtime.h>
+#include <linux/property.h>
+#include "clk.h"
+
+static int rk_clk_gate_link_register(struct device *dev,
+ struct rockchip_clk_provider *ctx,
+ struct rockchip_clk_branch *clkbr)
+{
+ unsigned long flags = clkbr->flags | CLK_SET_RATE_PARENT;
+ struct clk *clk;
+
+ clk = clk_register_gate(dev, clkbr->name, clkbr->parent_names[0],
+ flags, ctx->reg_base + clkbr->gate_offset,
+ clkbr->gate_shift, clkbr->gate_flags,
+ &ctx->lock);
+
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ rockchip_clk_set_lookup(ctx, clk, clkbr->id);
+ return 0;
+}
+
+static int rk_clk_gate_link_probe(struct platform_device *pdev)
+{
+ struct rockchip_gate_link_platdata *pdata;
+ struct device *dev = &pdev->dev;
+ struct clk *linked_clk;
+ int ret;
+
+ pdata = dev_get_platdata(dev);
+ if (!pdata)
+ return dev_err_probe(dev, -ENODEV, "missing platform data");
+
+ ret = devm_pm_runtime_enable(dev);
+ if (ret)
+ return ret;
+
+ ret = devm_pm_clk_create(dev);
+ if (ret)
+ return ret;
+
+ linked_clk = rockchip_clk_get_lookup(pdata->ctx, pdata->clkbr->linked_clk_id);
+ ret = pm_clk_add_clk(dev, linked_clk);
+ if (ret)
+ return ret;
+
+ ret = rk_clk_gate_link_register(dev, pdata->ctx, pdata->clkbr);
+ if (ret)
+ goto err;
+
+ return 0;
+
+err:
+ pm_clk_remove_clk(dev, linked_clk);
+ return ret;
+}
+
+static void rk_clk_gate_link_remove(struct platform_device *pdev)
+{
+ struct rockchip_gate_link_platdata *pdata;
+ struct device *dev = &pdev->dev;
+ struct clk *clk, *linked_clk;
+
+ pdata = dev_get_platdata(dev);
+ clk = rockchip_clk_get_lookup(pdata->ctx, pdata->clkbr->id);
+ linked_clk = rockchip_clk_get_lookup(pdata->ctx, pdata->clkbr->linked_clk_id);
+ rockchip_clk_set_lookup(pdata->ctx, ERR_PTR(-ENODEV), pdata->clkbr->id);
+ clk_unregister_gate(clk);
+ pm_clk_remove_clk(dev, linked_clk);
+}
+
+static const struct dev_pm_ops rk_clk_gate_link_pm_ops = {
+ SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
+};
+
+struct platform_driver rk_clk_gate_link_driver = {
+ .probe = rk_clk_gate_link_probe,
+ .remove_new = rk_clk_gate_link_remove,
+ .driver = {
+ .name = "rockchip-gate-link-clk",
+ .pm = &rk_clk_gate_link_pm_ops,
+ },
+};
+
+static int __init rk_clk_gate_link_drv_register(void)
+{
+ return platform_driver_register(&rk_clk_gate_link_driver);
+}
+core_initcall(rk_clk_gate_link_drv_register);
--
2.43.0
^ permalink raw reply related
* [PATCH v9 5/7] clk: rockchip: fix error for unknown clocks
From: Sebastian Reichel @ 2024-03-25 19:33 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, linux-clk
Cc: Elaine Zhang, Kever Yang, Heiko Stuebner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, huangtao, andy.yan,
Michal Tomek, Ilya K, Chad LeClair, devicetree, linux-rockchip,
Sebastian Reichel, kernel
In-Reply-To: <20240325193609.237182-1-sebastian.reichel@collabora.com>
There is a clk == NULL check after the switch to check for
unsupported clk types. Since clk is re-assigned in a loop,
this check is useless right now for anything but the first
round. Let's fix this up by assigning clk = NULL in the
loop before the switch statement.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/clk/rockchip/clk.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index ef2408f10f39..e150bc1fc319 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -444,12 +444,13 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
struct rockchip_clk_branch *list,
unsigned int nr_clk)
{
- struct clk *clk = NULL;
+ struct clk *clk;
unsigned int idx;
unsigned long flags;
for (idx = 0; idx < nr_clk; idx++, list++) {
flags = list->flags;
+ clk = NULL;
/* catch simple muxes */
switch (list->branch_type) {
--
2.43.0
^ permalink raw reply related
* [PATCH v9 3/7] clk: rockchip: rk3588: register GATE_LINK later
From: Sebastian Reichel @ 2024-03-25 19:33 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, linux-clk
Cc: Elaine Zhang, Kever Yang, Heiko Stuebner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, huangtao, andy.yan,
Michal Tomek, Ilya K, Chad LeClair, devicetree, linux-rockchip,
Sebastian Reichel, kernel
In-Reply-To: <20240325193609.237182-1-sebastian.reichel@collabora.com>
The proper GATE_LINK implementation will use runtime PM to handle the
linked gate clocks, which requires device context. Currently all clocks
are registered early via CLK_OF_DECLARE, which is before the kernel
knows about devices.
Moving the full clocks registration to the probe routine does not work,
since the clocks needed for timers must be registered early.
To work around this issue, most of the clock tree is registered early,
but GATE_LINK clocks are handled in the probe routine. Since the resets
are not needed early either, they have also been moved to the probe
routine.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/clk/rockchip/clk-rk3588.c | 64 +++++++++++++++++++++++++++----
1 file changed, 56 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c
index 74051277ecea..29f31a5526fa 100644
--- a/drivers/clk/rockchip/clk-rk3588.c
+++ b/drivers/clk/rockchip/clk-rk3588.c
@@ -266,6 +266,8 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = {
}, \
}
+static struct rockchip_clk_provider *early_ctx;
+
static struct rockchip_cpuclk_rate_table rk3588_cpub0clk_rates[] __initdata = {
RK3588_CPUB01CLK_RATE(2496000000, 1),
RK3588_CPUB01CLK_RATE(2400000000, 1),
@@ -694,7 +696,7 @@ static struct rockchip_pll_clock rk3588_pll_clks[] __initdata = {
RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates),
};
-static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
+static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = {
/*
* CRU Clock-Architecture
*/
@@ -2428,7 +2430,9 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
RK3588_CLKGATE_CON(68), 5, GFLAGS),
GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0,
RK3588_CLKGATE_CON(68), 2, GFLAGS),
+};
+static struct rockchip_clk_branch rk3588_clk_branches[] = {
GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", ACLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),
GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", HCLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),
GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),
@@ -2453,14 +2457,18 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", HCLK_VO1, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS),
};
-static void __init rk3588_clk_init(struct device_node *np)
+static void __init rk3588_clk_early_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
- unsigned long clk_nr_clks;
+ unsigned long clk_nr_clks, max_clk_id1, max_clk_id2;
void __iomem *reg_base;
- clk_nr_clks = rockchip_clk_find_max_clk_id(rk3588_clk_branches,
- ARRAY_SIZE(rk3588_clk_branches)) + 1;
+ max_clk_id1 = rockchip_clk_find_max_clk_id(rk3588_clk_branches,
+ ARRAY_SIZE(rk3588_clk_branches));
+ max_clk_id2 = rockchip_clk_find_max_clk_id(rk3588_early_clk_branches,
+ ARRAY_SIZE(rk3588_early_clk_branches));
+ clk_nr_clks = max(max_clk_id1, max_clk_id2) + 1;
+
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err("%s: could not map cru region\n", __func__);
@@ -2473,6 +2481,7 @@ static void __init rk3588_clk_init(struct device_node *np)
iounmap(reg_base);
return;
}
+ early_ctx = ctx;
rockchip_clk_register_plls(ctx, rk3588_pll_clks,
ARRAY_SIZE(rk3588_pll_clks),
@@ -2491,14 +2500,53 @@ static void __init rk3588_clk_init(struct device_node *np)
&rk3588_cpub1clk_data, rk3588_cpub1clk_rates,
ARRAY_SIZE(rk3588_cpub1clk_rates));
+ rockchip_clk_register_branches(ctx, rk3588_early_clk_branches,
+ ARRAY_SIZE(rk3588_early_clk_branches));
+
+ rockchip_clk_of_add_provider(np, ctx);
+}
+CLK_OF_DECLARE_DRIVER(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_early_init);
+
+static int clk_rk3588_probe(struct platform_device *pdev)
+{
+ struct rockchip_clk_provider *ctx = early_ctx;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+
rockchip_clk_register_branches(ctx, rk3588_clk_branches,
ARRAY_SIZE(rk3588_clk_branches));
- rk3588_rst_init(np, reg_base);
-
+ rk3588_rst_init(np, ctx->reg_base);
rockchip_register_restart_notifier(ctx, RK3588_GLB_SRST_FST, NULL);
+ /*
+ * Re-add clock provider, so that the newly added clocks are also
+ * re-parented and get their defaults configured.
+ */
+ of_clk_del_provider(np);
rockchip_clk_of_add_provider(np, ctx);
+
+ return 0;
}
-CLK_OF_DECLARE(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_init);
+static const struct of_device_id clk_rk3588_match_table[] = {
+ {
+ .compatible = "rockchip,rk3588-cru",
+ },
+ { }
+};
+
+static struct platform_driver clk_rk3588_driver = {
+ .probe = clk_rk3588_probe,
+ .driver = {
+ .name = "clk-rk3588",
+ .of_match_table = clk_rk3588_match_table,
+ .suppress_bind_attrs = true,
+ },
+};
+
+static int __init rockchip_clk_rk3588_drv_register(void)
+{
+ return platform_driver_register(&clk_rk3588_driver);
+}
+core_initcall(rockchip_clk_rk3588_drv_register);
--
2.43.0
^ permalink raw reply related
* [PATCH v9 2/7] clk: rockchip: handle missing clocks with -EPROBE_DEFER
From: Sebastian Reichel @ 2024-03-25 19:33 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, linux-clk
Cc: Elaine Zhang, Kever Yang, Heiko Stuebner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, huangtao, andy.yan,
Michal Tomek, Ilya K, Chad LeClair, devicetree, linux-rockchip,
Sebastian Reichel, kernel
In-Reply-To: <20240325193609.237182-1-sebastian.reichel@collabora.com>
In the future some clocks will be registered using CLK_OF_DECLARE
and some are registered later from the driver probe routine. Any
clock handled by the probe routine should return -EPROBE_DEFER
until that routine has been called.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/clk/rockchip/clk.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 73d2cbdc716b..31b7cc243d82 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -376,7 +376,7 @@ struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
goto err_free;
for (i = 0; i < nr_clks; ++i)
- clk_table[i] = ERR_PTR(-ENOENT);
+ clk_table[i] = ERR_PTR(-EPROBE_DEFER);
ctx->reg_base = base;
ctx->clk_data.clks = clk_table;
--
2.43.0
^ permalink raw reply related
* [PATCH v9 4/7] clk: rockchip: expose rockchip_clk_set_lookup
From: Sebastian Reichel @ 2024-03-25 19:33 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, linux-clk
Cc: Elaine Zhang, Kever Yang, Heiko Stuebner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, huangtao, andy.yan,
Michal Tomek, Ilya K, Chad LeClair, devicetree, linux-rockchip,
Sebastian Reichel, kernel
In-Reply-To: <20240325193609.237182-1-sebastian.reichel@collabora.com>
Move rockchip_clk_add_lookup to clk.h, so that it can be used
by sub-devices with their own driver. These might also have to
do a lookup, so rename the function to rockchip_clk_set_lookup
and add a matching rockchip_clk_add_lookup.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/clk/rockchip/clk.c | 14 ++++----------
drivers/clk/rockchip/clk.h | 12 ++++++++++++
2 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 31b7cc243d82..ef2408f10f39 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -197,12 +197,6 @@ static void rockchip_fractional_approximation(struct clk_hw *hw,
clk_fractional_divider_general_approximation(hw, rate, parent_rate, m, n);
}
-static void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
- struct clk *clk, unsigned int id)
-{
- ctx->clk_data.clks[id] = clk;
-}
-
static struct clk *rockchip_clk_register_frac_branch(
struct rockchip_clk_provider *ctx, const char *name,
const char *const *parent_names, u8 num_parents,
@@ -292,7 +286,7 @@ static struct clk *rockchip_clk_register_frac_branch(
return mux_clk;
}
- rockchip_clk_add_lookup(ctx, mux_clk, child->id);
+ rockchip_clk_set_lookup(ctx, mux_clk, child->id);
/* notifier on the fraction divider to catch rate changes */
if (frac->mux_frac_idx >= 0) {
@@ -424,7 +418,7 @@ void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
continue;
}
- rockchip_clk_add_lookup(ctx, clk, list->id);
+ rockchip_clk_set_lookup(ctx, clk, list->id);
}
}
EXPORT_SYMBOL_GPL(rockchip_clk_register_plls);
@@ -585,7 +579,7 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
continue;
}
- rockchip_clk_add_lookup(ctx, clk, list->id);
+ rockchip_clk_set_lookup(ctx, clk, list->id);
}
}
EXPORT_SYMBOL_GPL(rockchip_clk_register_branches);
@@ -609,7 +603,7 @@ void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
return;
}
- rockchip_clk_add_lookup(ctx, clk, lookup_id);
+ rockchip_clk_set_lookup(ctx, clk, lookup_id);
}
EXPORT_SYMBOL_GPL(rockchip_clk_register_armclk);
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index fd3b476dedda..e39392e1c2a2 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -969,6 +969,18 @@ struct rockchip_clk_branch {
#define SGRF_GATE(_id, cname, pname) \
FACTOR(_id, cname, pname, 0, 1, 1)
+static inline struct clk *rockchip_clk_get_lookup(struct rockchip_clk_provider *ctx,
+ unsigned int id)
+{
+ return ctx->clk_data.clks[id];
+}
+
+static inline void rockchip_clk_set_lookup(struct rockchip_clk_provider *ctx,
+ struct clk *clk, unsigned int id)
+{
+ ctx->clk_data.clks[id] = clk;
+}
+
struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
void __iomem *base, unsigned long nr_clks);
void rockchip_clk_of_add_provider(struct device_node *np,
--
2.43.0
^ permalink raw reply related
* [PATCH v9 1/7] clk: rockchip: rk3588: drop unused code
From: Sebastian Reichel @ 2024-03-25 19:33 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, linux-clk
Cc: Elaine Zhang, Kever Yang, Heiko Stuebner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, huangtao, andy.yan,
Michal Tomek, Ilya K, Chad LeClair, devicetree, linux-rockchip,
Sebastian Reichel, kernel
In-Reply-To: <20240325193609.237182-1-sebastian.reichel@collabora.com>
All clocks are registered early using CLK_OF_DECLARE(), which marks
the DT node as processed. For the processed DT node the probe routine
is never called. Thus this whole code is never executed. This could
be "fixed" by using CLK_OF_DECLARE_DRIVER, which avoids marking the
DT node as processed. But then the probe routine would re-register
all the clocks by calling rk3588_clk_init() again.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/clk/rockchip/clk-rk3588.c | 40 -------------------------------
1 file changed, 40 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c
index b30279a96dc8..74051277ecea 100644
--- a/drivers/clk/rockchip/clk-rk3588.c
+++ b/drivers/clk/rockchip/clk-rk3588.c
@@ -2502,43 +2502,3 @@ static void __init rk3588_clk_init(struct device_node *np)
}
CLK_OF_DECLARE(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_init);
-
-struct clk_rk3588_inits {
- void (*inits)(struct device_node *np);
-};
-
-static const struct clk_rk3588_inits clk_3588_cru_init = {
- .inits = rk3588_clk_init,
-};
-
-static const struct of_device_id clk_rk3588_match_table[] = {
- {
- .compatible = "rockchip,rk3588-cru",
- .data = &clk_3588_cru_init,
- },
- { }
-};
-
-static int __init clk_rk3588_probe(struct platform_device *pdev)
-{
- const struct clk_rk3588_inits *init_data;
- struct device *dev = &pdev->dev;
-
- init_data = device_get_match_data(dev);
- if (!init_data)
- return -EINVAL;
-
- if (init_data->inits)
- init_data->inits(dev->of_node);
-
- return 0;
-}
-
-static struct platform_driver clk_rk3588_driver = {
- .driver = {
- .name = "clk-rk3588",
- .of_match_table = clk_rk3588_match_table,
- .suppress_bind_attrs = true,
- },
-};
-builtin_platform_driver_probe(clk_rk3588_driver, clk_rk3588_probe);
--
2.43.0
^ permalink raw reply related
* [PATCH v9 0/7] rockchip: clk: add GATE_LINK support
From: Sebastian Reichel @ 2024-03-25 19:33 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, linux-clk
Cc: Elaine Zhang, Kever Yang, Heiko Stuebner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, huangtao, andy.yan,
Michal Tomek, Ilya K, Chad LeClair, devicetree, linux-rockchip,
Sebastian Reichel, kernel
Hi,
This implements proper GATE_LINK support following the suggestion from Stephen
Boyd to use clk PM operations by creating MFD dynamically. This required some
restructuring, since CLK_OF_DECLARE() is called before devices are available.
Apart from improved power consumption, this fixes the runtime errors from the
pmdomain driver (failed to set idle on domain '%s').
Changes since PATCHv8:
* https://lore.kernel.org/linux-rockchip/20240126182919.48402-1-sebastian.reichel@collabora.com/
* rebased to v6.9-rc1
* dropped all merged patches (i.e. all but the last one)
* rewrote and split the final patch
- should be easier to review
- properly calls pm_clk_suspend/pm_clk_resume
- now works on Orange Pi
Changes since PATCHv7:
* https://lore.kernel.org/all/20231213185114.47565-1-sebastian.reichel@collabora.com/
* rebased to v6.8-rc1
* Collected Reviewed-by/Acked-by from Krzysztof Kozlowski for DT binding patches
* support nr_clk=0 in rockchip_clk_find_max_clk_id() for smatch
Greetings,
-- Sebstian
Sebastian Reichel (7):
clk: rockchip: rk3588: drop unused code
clk: rockchip: handle missing clocks with -EPROBE_DEFER
clk: rockchip: rk3588: register GATE_LINK later
clk: rockchip: expose rockchip_clk_set_lookup
clk: rockchip: fix error for unknown clocks
clk: rockchip: implement linked gate clock support
clk: rockchip: rk3588: drop RK3588_LINKED_CLK
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-rk3588.c | 124 +++++++++++++-----------------
drivers/clk/rockchip/clk.c | 71 ++++++++++++++---
drivers/clk/rockchip/clk.h | 37 +++++++++
drivers/clk/rockchip/gate-link.c | 99 ++++++++++++++++++++++++
5 files changed, 251 insertions(+), 81 deletions(-)
create mode 100644 drivers/clk/rockchip/gate-link.c
--
2.43.0
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: arm64: marvell: add solidrun cn9130 clearfog boards
From: Krzysztof Kozlowski @ 2024-03-25 19:34 UTC (permalink / raw)
To: Josua Mayer, Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Yazan Shhady, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
In-Reply-To: <0f7ca0ed-a1c1-41d2-a1fa-27431d14c056@solid-run.com>
On 22/03/2024 11:08, Josua Mayer wrote:
> Am 21.03.24 um 22:47 schrieb Josua Mayer:
>> Add bindings for SolidRun Clearfog boards, using a new SoM based on
>> CN9130 SoC.
>> The carrier boards are identical to the older Armada 388 based Clearfog
>> boards. For consistency the carrier part of compatible strings are
>> copied, including the established "-a1" suffix.
>>
>> Signed-off-by: Josua Mayer <josua@solid-run.com>
>> ---
>> .../devicetree/bindings/arm/marvell/armada-7k-8k.yaml | 12 ++++++++++++
>> 1 file changed, 12 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml
>> index 16d2e132d3d1..36bdfd1bedd9 100644
>> --- a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml
>> +++ b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml
>> @@ -82,4 +82,16 @@ properties:
>> - const: marvell,armada-ap807-quad
>> - const: marvell,armada-ap807
>>
>> + - description:
>> + SolidRun CN9130 clearfog family single-board computers
>> + items:
>> + - enum:
>> + - solidrun,clearfog-base-a1
>> + - solidrun,clearfog-pro-a1
>> + - const: solidrun,clearfog-a1
>> + - const: solidrun,cn9130-sr-som
>> + - const: marvell,cn9130
>> + - const: marvell,armada-ap807-quad
>> + - const: marvell,armada-ap807
>> +
>> additionalProperties: true
>
> Before merging I would like some feedback about adding
> another product later, to ensure the compatibles above
> are adequate? In particular:
> - sequence of soc, cp, carrier compatibles
> - name of som compatible
>
> Draft for future bindings:
> - description:
> SolidRun CN9130 SoM based single-board computers
> with 1 external CP on the Carrier.
> items:
> - enum:
> - solidrun,cn9131-solidwan
> - const: marvell,cn9131
> - const: solidrun,cn9130-sr-som
This does not look correct. cn9131 is not compatible with your som.
> - const: marvell,cn9130
SoCs are compatible only in some cases, e.g. one is a subset of another
like stripped out of modem. Are you sure this is your case?
> - const: marvell,armada-ap807-quad
> - const: marvell,armada-ap807
Anyway, 6 compatibles is beyond useful amount. What are you expressing
here? Why is this even armada ap807?
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH] ASoC: dt-bindings: wm8974: Convert to dtschema
From: Krzysztof Kozlowski @ 2024-03-25 19:30 UTC (permalink / raw)
To: Kartik Agarwala, lgirdwood, broonie, robh, krzysztof.kozlowski+dt,
conor+dt
Cc: patches, linux-sound, devicetree, linux-kernel,
javier.carrasco.cruz
In-Reply-To: <20240325181943.116733-1-agarwala.kartik@gmail.com>
On 25/03/2024 19:19, Kartik Agarwala wrote:
> Convert WM8974 audio CODEC bindings from text to dtschema.
>
> Signed-off-by: Kartik Agarwala <agarwala.kartik@gmail.com>
Thank you for your patch. There are no DTS users of this binding, so
while such conversions are useful, they have significantly smaller
impact. In the future, please consider converting bindings from active
platforms (arm64 defconfig, arm multi_v7). This would have significantly
bigger impact.
See also:
https://lore.kernel.org/all/6552bcb8-e046-4882-91da-1094fff3d239@linaro.org/
> ---
> .../devicetree/bindings/sound/wlf,wm8974.txt | 15 -------
> .../devicetree/bindings/sound/wlf,wm8974.yaml | 41 +++++++++++++++++++
> 2 files changed, 41 insertions(+), 15 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/sound/wlf,wm8974.txt
> create mode 100644 Documentation/devicetree/bindings/sound/wlf,wm8974.yaml
>
...
> + "#sound-dai-cells":
> + const: 0
> +
> +required:
> + - compatible
> + - reg
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + i2c {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + codec@1a {
> + compatible = "wlf,wm8974";
> + reg = <0x1a>;
In the future for other patches like this, make example complete, so add
a dai-cells also here.
No need to resend just for that.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 2/2] ARM: dts: qcom: Add support for Motorola Moto G (2013)
From: Konrad Dybcio @ 2024-03-25 19:28 UTC (permalink / raw)
To: Stanislav Jakubek, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-arm-kernel, phone-devel,
linux-kernel
In-Reply-To: <b35ad5ff8a13f9df415b6e6700b3b5d3f13bfce8.1711288736.git.stano.jakubek@gmail.com>
On 24.03.2024 3:04 PM, Stanislav Jakubek wrote:
> Add a device tree for the Motorola Moto G (2013) smartphone based
> on the Qualcomm MSM8226 SoC.
>
> Initially supported features:
> - Buttons (Volume Down/Up, Power)
> - eMMC
> - Hall Effect Sensor
> - SimpleFB display
> - TMP108 temperature sensor
> - Vibrator
>
> Signed-off-by: Stanislav Jakubek <stano.jakubek@gmail.com>
> ---
[...]
> + hob-ram@f500000 {
> + reg = <0x0f500000 0x40000>,
> + <0x0f540000 0x2000>;
> + no-map;
> + };
Any reason it's in two parts? Should it be one contiguous region, or
two separate nodes?
lgtm otherwise
^ permalink raw reply
* Re: [PATCH v5 4/4] clk: imx: add i.MX95 BLK CTL clk driver
From: Krzysztof Kozlowski @ 2024-03-25 19:25 UTC (permalink / raw)
To: Peng Fan (OSS), Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Abel Vesa
Cc: linux-clk, devicetree, imx, linux-arm-kernel, linux-kernel,
Peng Fan
In-Reply-To: <20240324-imx95-blk-ctl-v5-4-7a706174078a@nxp.com>
On 24/03/2024 08:52, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
...
> +
> +static const struct of_device_id imx95_bc_of_match[] = {
> + { .compatible = "nxp,imx95-camera-csr", .data = &camblk_dev_data },
> + { .compatible = "nxp,imx95-display-master-csr", },
> + { .compatible = "nxp,imx95-lvds-csr", .data = &lvds_csr_dev_data },
> + { .compatible = "nxp,imx95-display-csr", .data = &dispmix_csr_dev_data },
> + { .compatible = "nxp,imx95-vpu-csr", .data = &vpublk_dev_data },
> + { /* Sentinel */ },
> +};
> +MODULE_DEVICE_TABLE(of, imx95_bc_of_match);
> +
> +static struct platform_driver imx95_bc_driver = {
> + .probe = imx95_bc_probe,
> + .driver = {
> + .name = "imx95-blk-ctl",
> + .of_match_table = of_match_ptr(imx95_bc_of_match),
Drop of_match_ptr(), causes warnings. From where did you copy such code?
Which mainline driver has such pattern?
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH 1/2] dt-bindings: input: touchscreen: edt-ft5x06: Add ft5426
From: Andreas Kemnade @ 2024-03-25 19:25 UTC (permalink / raw)
To: dmitry.torokhov, robh+dt, krzysztof.kozlowski+dt, conor+dt,
andreas, o.rempel, dario.binacchi, u.kleine-koenig, hdegoede,
p.puschmann, linux-input, devicetree, linux-kernel,
caleb.connolly
In-Reply-To: <20240324184415.206587-1-andreas@kemnade.info>
Add compatible for ft5426.
Searches for documentation reveal neither edt nor evervision
as some related company, only FocalTech.
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
---
.../devicetree/bindings/input/touchscreen/edt-ft5x06.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml
index f2808cb4d99df..17b05522eacd9 100644
--- a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml
+++ b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml
@@ -40,6 +40,7 @@ properties:
- edt,edt-ft5506
- evervision,ev-ft5726
- focaltech,ft6236
+ - focaltech,ft5426
reg:
maxItems: 1
--
2.39.2
^ permalink raw reply related
* Re: [PATCH 4/5] dt-bindings: arm: rockchip: Add GameForce Chi
From: Conor Dooley @ 2024-03-25 19:25 UTC (permalink / raw)
To: Chris Morgan
Cc: linux-rockchip, dri-devel, devicetree, daniel, airlied, sam,
quic_jesszhan, neil.armstrong, megi, kernel, agx, heiko, conor+dt,
krzysztof.kozlowski+dt, robh, Chris Morgan
In-Reply-To: <20240325134959.11807-5-macroalpha82@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 334 bytes --]
On Mon, Mar 25, 2024 at 08:49:58AM -0500, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> The GameForce Chi is a handheld gaming device from GameForce powered
> by the Rockchip RK3326 SoC.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: sm8250-xiaomi-elish: set pm8150b_vbus regulator-min-microamp and regulator-max-microamp
From: Konrad Dybcio @ 2024-03-25 19:25 UTC (permalink / raw)
To: Jianhua Lu, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20240323100443.2478-1-lujianhua000@gmail.com>
On 23.03.2024 11:04 AM, Jianhua Lu wrote:
> Fix the dtb check warnings:
> sm8250-xiaomi-elish-boe.dtb: usb-vbus-regulator@1100: 'regulator-min-microamp' is a required property
> sm8250-xiaomi-elish-boe.dtb: usb-vbus-regulator@1100: 'regulator-max-microamp' is a required property
>
> Fixes: 69652787279d ("arm64: dts: qcom: sm8250-xiaomi-elish: Add pm8150b type-c node and enable usb otg")
> Signed-off-by: Jianhua Lu <lujianhua000@gmail.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
^ permalink raw reply
* Re: [PATCH v5 1/4] dt-bindings: clock: support i.MX95 BLK CTL module
From: Krzysztof Kozlowski @ 2024-03-25 19:24 UTC (permalink / raw)
To: Peng Fan (OSS), Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Abel Vesa
Cc: linux-clk, devicetree, imx, linux-arm-kernel, linux-kernel,
Peng Fan
In-Reply-To: <20240324-imx95-blk-ctl-v5-1-7a706174078a@nxp.com>
On 24/03/2024 08:52, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> i.MX95 includes BLK CTL module in several MIXes, such as VPU_CSR in
> VPUMIX, CAMERA_CSR in CAMERAMIX and etc.
>
> The BLK CTL module is used for various settings of a specific MIX, such
> as clock, QoS and etc.
>
> This patch is to add some BLK CTL modules that has clock features.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> .../bindings/clock/nxp,imx95-blk-ctl.yaml | 56 ++++++++++++++++++++++
> 1 file changed, 56 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
> new file mode 100644
> index 000000000000..2dffc02dcd8b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
> @@ -0,0 +1,56 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/nxp,imx95-blk-ctl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP i.MX95 Block Control
> +
> +maintainers:
> + - Peng Fan <peng.fan@nxp.com>
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - nxp,imx95-lvds-csr
> + - nxp,imx95-display-csr
> + - nxp,imx95-camera-csr
> + - nxp,imx95-vpu-csr
> + - const: syscon
> +
> + reg:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> + description:
> + The clock consumer should specify the desired clock by having the clock
> + ID in its "clocks" phandle cell. See
> + include/dt-bindings/clock/nxp,imx95-clock.h
In such case, put header as your first patch in the patchset. I don't
understand why it was split in the first place...
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v5 2/4] dt-bindings: clock: support i.MX95 Display Master CSR module
From: Krzysztof Kozlowski @ 2024-03-25 19:23 UTC (permalink / raw)
To: Peng Fan (OSS), Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Abel Vesa
Cc: linux-clk, devicetree, imx, linux-arm-kernel, linux-kernel,
Peng Fan
In-Reply-To: <20240324-imx95-blk-ctl-v5-2-7a706174078a@nxp.com>
On 24/03/2024 08:52, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> i.MX95 DISPLAY_MASTER_CSR includes registers to control DSI clock settings,
> clock gating, and pixel link select. Add dt-schema for it.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> .../clock/nxp,imx95-display-master-csr.yaml | 64 ++++++++++++++++++++++
> 1 file changed, 64 insertions(+)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: sdx75: add unit address to soc node
From: Konrad Dybcio @ 2024-03-25 19:23 UTC (permalink / raw)
To: Krzysztof Kozlowski, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel
In-Reply-To: <20240325102924.26820-1-krzysztof.kozlowski@linaro.org>
On 25.03.2024 11:29 AM, Krzysztof Kozlowski wrote:
> Soc node has ranges, thus it must have an unit address. This fixes W=1
> dtc warning:
>
> sdx75.dtsi:399.11-736.4: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
^ permalink raw reply
* Re: [PATCH v5 3/4] dt-bindings: clock: add i.MX95 clock header
From: Krzysztof Kozlowski @ 2024-03-25 19:22 UTC (permalink / raw)
To: Peng Fan (OSS), Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Abel Vesa
Cc: linux-clk, devicetree, imx, linux-arm-kernel, linux-kernel,
Peng Fan
In-Reply-To: <20240324-imx95-blk-ctl-v5-3-7a706174078a@nxp.com>
On 24/03/2024 08:52, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> Add clock header for i.MX95 BLK CTL modules
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> include/dt-bindings/clock/nxp,imx95-clock.h | 32 +++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/include/dt-bindings/clock/nxp,imx95-clock.h b/include/dt-bindings/clock/nxp,imx95-clock.h
> new file mode 100644
> index 000000000000..83fa3ffe78a8
> --- /dev/null
> +++ b/include/dt-bindings/clock/nxp,imx95-clock.h
> @@ -0,0 +1,32 @@
> +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_IMX95_H
> +#define __DT_BINDINGS_CLOCK_IMX95_H
> +
> +#define IMX95_CLK_VPUBLK_WAVE 0
> +#define IMX95_CLK_VPUBLK_JPEG_ENC 1
> +#define IMX95_CLK_VPUBLK_JPEG_DEC 2
> +#define IMX95_CLK_VPUBLK_END 3
No improvements, so again: drop counting.
Same in other places.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v5 0/4] Add support i.MX95 BLK CTL module clock features
From: Krzysztof Kozlowski @ 2024-03-25 19:21 UTC (permalink / raw)
To: Peng Fan (OSS), Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Abel Vesa
Cc: linux-clk, devicetree, imx, linux-arm-kernel, linux-kernel,
Peng Fan
In-Reply-To: <20240324-imx95-blk-ctl-v5-0-7a706174078a@nxp.com>
On 24/03/2024 08:51, Peng Fan (OSS) wrote:
> i.MX95's several MIXes has BLK CTL module which could be used for
> clk settings, QoS settings, Misc settings for a MIX. This patchset
> is to add the clk feature support, including dt-bindings
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> Changes in v5:
> - Merge bindings except the one has mux-controller
> - Separate clock ID headers in a separate patch per Rob's comments
Where did he suggest it?
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 0/2] Input: add ft5426
From: Conor Dooley @ 2024-03-25 19:16 UTC (permalink / raw)
To: Andreas Kemnade
Cc: dmitry.torokhov, robh+dt, krzysztof.kozlowski+dt, conor+dt,
o.rempel, dario.binacchi, u.kleine-koenig, hdegoede, p.puschmann,
linux-input, devicetree, linux-kernel, caleb.connolly
In-Reply-To: <20240324184415.206587-1-andreas@kemnade.info>
[-- Attachment #1: Type: text/plain, Size: 411 bytes --]
On Sun, Mar 24, 2024 at 07:44:13PM +0100, Andreas Kemnade wrote:
> Add ft5426 touchscreen controller and the corresponding compatible.
>
> Andreas Kemnade (2):
> dt-bindings: input: touchscreen: edt-ft5x06: Add ft5426
> Input: edt-ft5x06 - add ft5426
I think something got messed up, I only got the cover and 2/2, no 1/2:
https://lore.kernel.org/all/20240324184415.206587-1-andreas@kemnade.info/
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH 3/3] power: reset: add new gs101-poweroff driver
From: Krzysztof Kozlowski @ 2024-03-25 19:13 UTC (permalink / raw)
To: Peter Griffin
Cc: Alexey Klimov, sre, robh, krzysztof.kozlowski+dt, linux-pm,
devicetree, robh+dt, conor+dt, linux-samsung-soc, semen.protsenko,
linux-kernel, klimov.linux, kernel-team, tudor.ambarus,
andre.draszik, saravanak, willmcvicker, alim.akhtar,
linux-arm-kernel, elder
In-Reply-To: <CADrjBPrthH4cKBpDeGV8u2ydErCJuqbdBhFQs+62k7bfPyJNvA@mail.gmail.com>
On 22/03/2024 13:25, Peter Griffin wrote:
> Hi Krzysztof,
>
> Thanks for your review feedback!
>
> On Wed, 20 Mar 2024 at 07:20, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 20/03/2024 03:05, Alexey Klimov wrote:
>>> +
>>> + ret = devm_work_autocancel(dev, &gs101->shutdown_work,
>>> + gs101_shutdown_work_fn);
>>> + if (ret) {
>>> + dev_err(dev, "failed to register gs101 shutdown_work: %i\n", ret);
>>> + unregister_keyboard_notifier(&gs101->keyboard_nb);
>>> + return ret;
>>> + }
>>> +
>>> + gs101_poweroff_ctx = gs101;
>>> + platform_set_drvdata(pdev, gs101);
>>> +
>>> + /*
>>> + * At this point there is a chance that psci_sys_poweroff already
>>> + * registered as pm_power_off hook but unfortunately it cannot power
>>> + * off the gs101 SoC hence we are rewriting it here just as is.
>>> + */
>>> + pm_power_off = gs101_poweroff;
>>
>> So that's a duplicated syscon power off driver. Why syscon does not
>> work? syscon_node_to_regmap() does not return correct regmap?
>
> Yes, for gs101 the regmap handling PMU registers is now created by
> exynos-pmu driver and is obtained using
> exynos_get_pmu_regmap_by_phandle() API. That was required due to the
> SMC call required to write to these registers from Linux.
>
>> If so,
>> this should be fixed instead of copying the driver with basically only
>> one difference.
>
> Are you suggesting we should add some API to syscon.c that allows
> regmaps created in other drivers like exynos-pmu.c or altera-sysmgr.c
> to be registered in the syscon_list?
Yes, I think this could work.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH] dt-bindings: iio: health: maxim,max30102: fix compatible check
From: Conor Dooley @ 2024-03-25 19:05 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Javier Carrasco, Lars-Peter Clausen, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matt Ranostay,
Jonathan Cameron, linux-iio, devicetree, linux-kernel
In-Reply-To: <20240324110715.0832e6d6@jic23-huawei>
[-- Attachment #1: Type: text/plain, Size: 1196 bytes --]
On Sun, Mar 24, 2024 at 11:07:15AM +0000, Jonathan Cameron wrote:
> On Sun, 17 Mar 2024 14:37:39 +0000
> Conor Dooley <conor@kernel.org> wrote:
>
> > On Sat, Mar 16, 2024 at 11:56:57PM +0100, Javier Carrasco wrote:
> > > The "maxim,green-led-current-microamp" property is only available for
> > > the max30105 part (it provides an extra green LED), and must be set to
> > > false for the max30102 part.
> > >
> > > Instead, the max30100 part has been used for that, which is not
> > > supported by this binding (it has its own binding).
> > >
> > > This error was introduced during the txt to yaml conversion.
> > >
> > > Fixes: 5a6a65b11e3a ("dt-bindings:iio:health:maxim,max30102: txt to yaml conversion")
> > > Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com>
> >
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Applied to the fixes-togreg branch of iio.git (which I'll rebase on rc1 once available)
> and marked for stable. Not really a critical thing to backport, but maybe it is worth
> doing as risk is very low
Yeah, I figure stuff like this is worth just backporting in case someone
is using a stable tree to add some new board.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH v5 7/7] iio: adc: ad7380: add support for ad738x-4 4 channels variants
From: Jonathan Cameron @ 2024-03-25 19:04 UTC (permalink / raw)
To: David Lechner
Cc: Julien Stephan, Lars-Peter Clausen, Michael Hennerich,
Nuno Sá, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Liam Girdwood, Mark Brown, linux-iio, devicetree, linux-kernel,
kernel test robot
In-Reply-To: <CAMknhBH0E258geq8WOKf3X0r7VngdDoSfNB5g6KTGBzEoUtMqA@mail.gmail.com>
On Mon, 25 Mar 2024 10:01:29 -0500
David Lechner <dlechner@baylibre.com> wrote:
> On Sun, Mar 24, 2024 at 8:11 AM Jonathan Cameron <jic23@kernel.org> wrote:
> >
> > On Tue, 19 Mar 2024 11:11:28 +0100
> > Julien Stephan <jstephan@baylibre.com> wrote:
> >
> > > Add support for ad7380/1/2/3-4 parts which are 4 channels
> > > variants from ad7380/1/2/3
> > >
> > > Signed-off-by: Julien Stephan <jstephan@baylibre.com>
> > This and other patches I didn't comment on all look good to me.
> > So just those minor few bits and bobs for v6 and I'll pick this up
> > if nothing else comes in.
> >
>
> Hi Jonathan, as a reminder, this is the driver we dropped from the 6.9
> cycle. We still don't have a patch prepared for the resolution boost
> feature that may require us to reconsider some of our userspace
> interface choices here. Hopefully we can get that sorted out in the
> next 6 weeks, but I just wanted to make you aware ahead of time so
> that we don't end up in the same situation in case things don't go as
> planned again. Do you have "usual" way you prefer to handle a
> situation like this?
My preferences:
Post as an RFC with a comment on what is unresolved.
I'll still review the RFC but won't apply until you let me know it's
good to go (ideally by posting a non RFC version)
Jonathan
^ permalink raw reply
* Re: [PATCH 1/4] dt-bindings: soc: mediatek: Add support for MT8188 VPPSYS
From: Conor Dooley @ 2024-03-25 18:55 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: linux-media, mchehab, robh, krzysztof.kozlowski+dt, conor+dt,
matthias.bgg, amergnat, moudy.ho, hverkuil-cisco,
sebastian.fricke, u.kleine-koenig, chunkuang.hu, p.zabel,
devicetree, linux-kernel, linux-arm-kernel, linux-mediatek,
kernel
In-Reply-To: <f90b2c8b-6eb3-46dc-abcc-600248218b4e@collabora.com>
[-- Attachment #1: Type: text/plain, Size: 1129 bytes --]
On Mon, Mar 25, 2024 at 09:23:58AM +0100, AngeloGioacchino Del Regno wrote:
> Il 22/03/24 18:42, Conor Dooley ha scritto:
> > On Fri, Mar 22, 2024 at 10:28:42AM +0100, AngeloGioacchino Del Regno wrote:
> > > Add compatible for MT8188 VPP mutex.
> > >
> > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> >
> > You should at least mention the difference between this any anything
> > else.
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
>
> It's exactly always the same difference for MuteX blocks: different bits to
> activate mute for some IP ... but yeah, you're right, I'll shoot a word about
> this in the commit description on v2 (waiting a bit before doing that anyway).
Yah, I'm just pointing it out because it goes from an immediate ack to
having check the binding in-tree to see that this is an enum (although
that's due to the shitty looking diff that you can't avoid) and check
the driver patch to see that this is in fact a difference before
acking. I wouldn't bother sending a v2 if this was the only thing, seems
like a waste of your effort.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox