* Re: [RFC PATCH 1/2] dt-bindings: connector: Add gpio-usb-c-connector compatible
From: Conor Dooley @ 2024-03-29 15:37 UTC (permalink / raw)
To: Krishna Kurapati
Cc: Krzysztof Kozlowski, Rob Herring, Greg Kroah-Hartman,
Conor Dooley, Dmitry Baryshkov, Miquel Raynal, Guenter Roeck,
Bjorn Helgaas, Kyle Tso, Fabrice Gasnier, Heikki Krogerus,
u.kleine-koenig, AngeloGioacchino Del Regno, devicetree,
linux-usb, linux-kernel, quic_ppratap, quic_jackp
In-Reply-To: <20240329071948.3101882-2-quic_kriskura@quicinc.com>
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On Fri, Mar 29, 2024 at 12:49:47PM +0530, Krishna Kurapati wrote:
> QDU1000 IDP [1] has a Type-c connector and supports USB 3.0.
> However it relies on usb-conn-gpio driver to read the vbus and id
> gpio's and provide role switch. However the driver currently has
> only gpio-b-connector compatible present in ID table. Adding that
> in DT would mean that the device supports Type-B connector and not
> Type-c connector.
>
> Add gpio-usb-c-connector compatible to the driver to support such
> cases.
This is not a driver. Bindings commit messages should talk about the
hardware they're supporting, not about drivers.
>
> [1]: https://lore.kernel.org/all/20240319091020.15137-3-quic_kbajaj@quicinc.com/
>
> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
> ---
> Documentation/devicetree/bindings/connector/usb-connector.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/connector/usb-connector.yaml b/Documentation/devicetree/bindings/connector/usb-connector.yaml
> index fb216ce68bb3..2af27793c639 100644
> --- a/Documentation/devicetree/bindings/connector/usb-connector.yaml
> +++ b/Documentation/devicetree/bindings/connector/usb-connector.yaml
> @@ -30,6 +30,9 @@ properties:
> - const: samsung,usb-connector-11pin
> - const: usb-b-connector
>
> + - items:
> + - const: gpio-usb-c-connector
This is over complicated, just needs to be "- const: gpio-usb-c-connector"
Thanks,
Conor.
> +
> reg:
> maxItems: 1
>
> --
> 2.34.1
>
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* Re: [PATCH v7 1/2] dt-bindings: dma: Add Loongson-1 APB DMA
From: Conor Dooley @ 2024-03-29 15:40 UTC (permalink / raw)
To: keguang.zhang
Cc: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Huacai Chen, linux-mips, dmaengine, devicetree, linux-kernel
In-Reply-To: <20240329-loongson1-dma-v7-1-37db58608de5@gmail.com>
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On Fri, Mar 29, 2024 at 07:26:57PM +0800, Keguang Zhang via B4 Relay wrote:
> From: Keguang Zhang <keguang.zhang@gmail.com>
>
> Add devicetree binding document for Loongson-1 APB DMA.
>
> Signed-off-by: Keguang Zhang <keguang.zhang@gmail.com>
> ---
> Changes in v7:
> - Change the comptible to 'loongson,ls1*-apbdma' (suggested by Huacai Chen)
> - Update the title and description part accordingly
> - Rename the file to loongson,ls1b-apbdma.yaml
> - Add a compatible string for LS1A
> - Delete minItems of 'interrupts'
> - Change patterns of 'interrupt-names' to const
>
> Changes in v6:
> - Change the compatible to the fallback
> - Some minor fixes
>
> Changes in v5:
> - A newly added patch
> ---
> .../bindings/dma/loongson,ls1b-apbdma.yaml | 65 ++++++++++++++++++++++
> 1 file changed, 65 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/dma/loongson,ls1b-apbdma.yaml b/Documentation/devicetree/bindings/dma/loongson,ls1b-apbdma.yaml
> new file mode 100644
> index 000000000000..449da9fc2de1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/loongson,ls1b-apbdma.yaml
> @@ -0,0 +1,65 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/loongson,ls1b-apbdma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Loongson-1 APB DMA Controller
> +
> +maintainers:
> + - Keguang Zhang <keguang.zhang@gmail.com>
> +
> +description:
> + Loongson-1 APB DMA controller provides 3 independent channels for
> + peripherals such as NAND, audio playback and capture.
> +
> +properties:
> + compatible:
> + oneOf:
> + - const: loongson,ls1b-apbdma
> + - items:
> + - enum:
> + - loongson,ls1a-apbdma
> + - loongson,ls1c-apbdma
> + - const: loongson,ls1b-apbdma
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + description: Each channel has a dedicated interrupt line.
If there's a respin, make this an items list. If you do, you can then
drop the maxItems and description. Ideally with that change made,
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
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* Re: [PATCH v3 8/9] dt-bindings: xlnx: Add VTC and TPG bindings
From: Conor Dooley @ 2024-03-29 15:46 UTC (permalink / raw)
To: Klymenko, Anatoliy
Cc: Krzysztof Kozlowski, Laurent Pinchart, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Daniel Vetter,
Simek, Michal, Andrzej Hajda, Neil Armstrong, Robert Foss,
Jonas Karlman, Jernej Skrabec, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Mauro Carvalho Chehab, Tomi Valkeinen,
dri-devel@lists.freedesktop.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-media@vger.kernel.org
In-Reply-To: <MW4PR12MB716570A3676218F0C6375E37E63A2@MW4PR12MB7165.namprd12.prod.outlook.com>
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On Fri, Mar 29, 2024 at 12:38:33AM +0000, Klymenko, Anatoliy wrote:
> Thank you for the feedback.
> > From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> > Subject: Re: [PATCH v3 8/9] dt-bindings: xlnx: Add VTC and TPG bindings
> > On 22/03/2024 20:12, Klymenko, Anatoliy wrote:
> > >> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> > >> On 21/03/2024 21:43, Anatoliy Klymenko wrote:
> > >>> diff --git a/include/dt-bindings/media/media-bus-format.h
> > >>> b/include/dt-
> > >> bindings/media/media-bus-format.h
> > >>> new file mode 100644
> > >>> index 000000000000..60fc6e11dabc
> > >>> --- /dev/null
> > >>> +++ b/include/dt-bindings/media/media-bus-format.h
> > >>> @@ -0,0 +1,177 @@
> > >>> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
> > >>> +/*
> > >>> + * Media Bus API header
> > >>> + *
> > >>> + * Copyright (C) 2009, Guennadi Liakhovetski
> > >>> +<g.liakhovetski@gmx.de>
> > >>> + *
> > >>> + * This program is free software; you can redistribute it and/or
> > >>> +modify
> > >>> + * it under the terms of the GNU General Public License version 2
> > >>> +as
> > >>> + * published by the Free Software Foundation.
> > >>
> > >> That's not true. Your SPDX tells something entirely different.
> > >>
> > >
> > > Thank you - I'll see how to fix it.
> > >
> > >> Anyway, you did not explain why you need to copy anything anywhere.
> > >>
> > >> Specifically, random hex values *are not bindings*.
> > >>
> > >
> > > The same media bus format values are being used by the reference
> > > driver in patch #9. And, as far as I know, we cannot use headers from
> > > Linux API headers directly (at least I
> >
> > I don't understand what does it mean. You can use in your driver whatever
> > headers you wish, I don't care about them.
> >
> >
> > noticed the same pattern in ../dt-bindings/sdtv-standarts.h for instance).
> > What would be the best approach to reusing the same defines on DT and
> > driver sides from your point of view? Symlink maybe?
> > >
> >
> > Wrap your messages to match mailing list discussion style. There are no
> > defines used in DT. If there are, show me them in *THIS* or other
> > *upstreamed* (being upstreamed) patchset.
> >
>
> Sorry, I didn't explain properly what I'm trying to achieve. I need to
> create a DT node property that represents video signal format, one of
> MEDIA_BUS_FMT_* from include/uapi/linux/media-bus-format.h. It would be
> nice to reuse the same symbolic values in the device tree. What is the
> best approach here? Should I create a separate header in
> include/dt-bindings with the same or similar (to avoid multiple
> definition errors) defines, or is it better to create a symlink to
> media-bus-format.h like include/dt-bindings/linux-event-codes.h?
Isn't there already a property for this, described in
Documentation/devicetree/bindings/media/xilinx/video.txt
?
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* Re: [PATCH 2/2] dt-bindings: iio: imu: add icm42688 inside inv_icm42600
From: Conor Dooley @ 2024-03-29 15:49 UTC (permalink / raw)
To: inv.git-commit
Cc: jic23, robh, krzysztof.kozlowski+dt, conor+dt, lars, linux-iio,
devicetree, Jean-Baptiste Maneyrol
In-Reply-To: <20240329151535.712827-3-inv.git-commit@tdk.com>
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On Fri, Mar 29, 2024 at 03:15:35PM +0000, inv.git-commit@tdk.com wrote:
> From: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>
>
> Add bindings for ICM-42688-P chip.
>
> Signed-off-by: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>
My initial thought was that you're missing a sign-off, but is
"inv.git-commit@tdk.com" some system you have to bypass corporate email
garbage?
> ---
> .../devicetree/bindings/iio/imu/invensense,icm42600.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml b/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml
> index 7cd05bcbee31..152aec8d82ff 100644
> --- a/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml
> +++ b/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml
> @@ -31,6 +31,7 @@ properties:
> - invensense,icm42602
> - invensense,icm42605
> - invensense,icm42622
> + - invensense,icm42688
Can you add this in alphanumerical order please?
Also, this patch should be the first in the series.
Thanks,
Conor.
> - invensense,icm42631
>
> reg:
> --
> 2.34.1
>
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* [PATCH 0/2] iio: imu: inv_icm42600: add support of ICM-42688-P
From: inv.git-commit @ 2024-03-29 15:15 UTC (permalink / raw)
To: jic23, robh, krzysztof.kozlowski+dt, conor+dt
Cc: lars, linux-iio, devicetree, Jean-Baptiste Maneyrol
From: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>
This series is for adding support of high-end specs ICM-42688-P chip.
Jean-Baptiste Maneyrol (2):
iio: imu: inv_icm42600: add support of ICM-42688-P
dt-bindings: iio: imu: add icm42688 inside inv_icm42600
.../devicetree/bindings/iio/imu/invensense,icm42600.yaml | 1 +
drivers/iio/imu/inv_icm42600/inv_icm42600.h | 2 ++
drivers/iio/imu/inv_icm42600/inv_icm42600_core.c | 5 +++++
drivers/iio/imu/inv_icm42600/inv_icm42600_i2c.c | 3 +++
drivers/iio/imu/inv_icm42600/inv_icm42600_spi.c | 3 +++
5 files changed, 14 insertions(+)
--
2.34.1
^ permalink raw reply
* Re: 回复: [PATCH v2 1/2] ASoC: dt-bindings: Add bindings for Cadence I2S-MC controller
From: Krzysztof Kozlowski @ 2024-03-29 16:01 UTC (permalink / raw)
To: Mark Brown
Cc: Xingyu Wu, Liam Girdwood, Claudiu Beznea, Jaroslav Kysela,
Takashi Iwai, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
alsa-devel@alsa-project.org, linux-sound@vger.kernel.org
In-Reply-To: <ZgbDx6oD+mMUIvH1@finisterre.sirena.org.uk>
On 29/03/2024 14:36, Mark Brown wrote:
> On Fri, Mar 29, 2024 at 12:42:22PM +0100, Krzysztof Kozlowski wrote:
>
>> I stated and I keep my statement that such block is usually not usable
>> on its own and always needs some sort of quirks or SoC-specific
>> implementation. At least this is what I saw in other similar cases, but
>> not exactly I2S.
>
> I wouldn't be so pessimistic, especially not for I2S - a good portion of
> quirks there are extra features rather than things needed for basic
> operation, a lot of things that might in the past have been quirks for
> basic operation are these days hidden behind the DT bindings.
OK, I trust your judgement, so cdns as fallback seems okay, but I don't
think it warrants cdns as used alone. Not particularly because cdns is
different, but because we expect specific SoC compatible always.
Thus if cdns,i2s-mc stays, then:
items:
- enum:
- starfive,jh8100-i2s
- cdns,i2s-mc
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v11 3/7] clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCF
From: Neil Armstrong @ 2024-03-29 16:06 UTC (permalink / raw)
To: Jerome Brunet
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Kevin Hilman,
Michael Turquette, Stephen Boyd, Martin Blumenstingl,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Daniel Vetter, Nicolas Belin, Jagan Teki, devicetree,
linux-kernel, linux-amlogic, linux-clk, linux-arm-kernel,
dri-devel
In-Reply-To: <1jv8558b11.fsf@starbuckisacylon.baylibre.com>
On 29/03/2024 13:35, Jerome Brunet wrote:
>
> On Mon 25 Mar 2024 at 12:09, Neil Armstrong <neil.armstrong@linaro.org> wrote:
>
>> In order to setup the DSI clock, let's make the unused VCLK2 clock path
>> configuration via CCF.
>>
>> The nocache option is removed from following clocks:
>> - vclk2_sel
>> - vclk2_input
>> - vclk2_div
>> - vclk2
>> - vclk_div1
>> - vclk2_div2_en
>> - vclk2_div4_en
>> - vclk2_div6_en
>> - vclk2_div12_en
>> - vclk2_div2
>> - vclk2_div4
>> - vclk2_div6
>> - vclk2_div12
>> - cts_encl_sel
>>
>> vclk2 and vclk2_div uses the newly introduced vclk regmap driver
>> to handle the enable and reset bits.
>>
>> In order to set a rate on cts_encl via the vclk2 clock path,
>> the NO_REPARENT flag is set on cts_encl_sel & vclk2_sel in order
>> to keep CCF from selection a parent.
>> The parents of cts_encl_sel & vclk2_sel are expected to be defined
>> in DT or manually set by the display driver at some point.
>>
>> The following clock scheme is to be used for DSI:
>>
>> xtal
>> \_ gp0_pll_dco
>> \_ gp0_pll
>> |- vclk2_sel
>> | \_ vclk2_input
>> | \_ vclk2_div
>> | \_ vclk2
>> | \_ vclk2_div1
>> | \_ cts_encl_sel
>> | \_ cts_encl -> to VPU LCD Encoder
>> |- mipi_dsi_pxclk_sel
>> \_ mipi_dsi_pxclk_div
>> \_ mipi_dsi_pxclk -> to DSI controller
>>
>> The mipi_dsi_pxclk_div is set as bypass with a single /1 entry in div_table
>> in order to use the same GP0 for mipi_dsi_pxclk and vclk2_input.
>>
>> The SET_RATE_PARENT is only set on the mipi_dsi_pxclk_sel clock so the
>> DSI bitclock is the reference base clock to calculate the vclk2_div value
>> when pixel clock is set on the cts_encl endpoint.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
>> drivers/clk/meson/Kconfig | 1 +
>> drivers/clk/meson/g12a.c | 72 ++++++++++++++++++++++++++++++++++-------------
>> 2 files changed, 53 insertions(+), 20 deletions(-)
>>
>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>> index 8a9823789fa3..59a40a49f8e1 100644
>> --- a/drivers/clk/meson/Kconfig
>> +++ b/drivers/clk/meson/Kconfig
>> @@ -144,6 +144,7 @@ config COMMON_CLK_G12A
>> select COMMON_CLK_MESON_EE_CLKC
>> select COMMON_CLK_MESON_CPU_DYNDIV
>> select COMMON_CLK_MESON_VID_PLL_DIV
>> + select COMMON_CLK_MESON_VCLK
>> select MFD_SYSCON
>> help
>> Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
>> diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
>> index 90f4c6103014..083882e53b65 100644
>> --- a/drivers/clk/meson/g12a.c
>> +++ b/drivers/clk/meson/g12a.c
>> @@ -22,6 +22,7 @@
>> #include "clk-regmap.h"
>> #include "clk-cpu-dyndiv.h"
>> #include "vid-pll-div.h"
>> +#include "vclk.h"
>> #include "meson-eeclk.h"
>> #include "g12a.h"
>>
>> @@ -3165,7 +3166,7 @@ static struct clk_regmap g12a_vclk2_sel = {
>> .ops = &clk_regmap_mux_ops,
>> .parent_hws = g12a_vclk_parent_hws,
>> .num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
>> - .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
>> + .flags = CLK_SET_RATE_NO_REPARENT,
>> },
>> };
>>
>> @@ -3193,7 +3194,6 @@ static struct clk_regmap g12a_vclk2_input = {
>> .ops = &clk_regmap_gate_ops,
>> .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },
>> .num_parents = 1,
>> - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> },
>> };
>>
>> @@ -3215,19 +3215,32 @@ static struct clk_regmap g12a_vclk_div = {
>> };
>>
>> static struct clk_regmap g12a_vclk2_div = {
>> - .data = &(struct clk_regmap_div_data){
>> - .offset = HHI_VIID_CLK_DIV,
>> - .shift = 0,
>> - .width = 8,
>> + .data = &(struct meson_vclk_div_data){
>> + .div = {
>> + .reg_off = HHI_VIID_CLK_DIV,
>> + .shift = 0,
>> + .width = 8,
>> + },
>> + .enable = {
>> + .reg_off = HHI_VIID_CLK_DIV,
>> + .shift = 16,
>> + .width = 1,
>> + },
>> + .reset = {
>> + .reg_off = HHI_VIID_CLK_DIV,
>> + .shift = 17,
>> + .width = 1,
>> + },
>> + .flags = CLK_DIVIDER_ROUND_CLOSEST,
>> },
>> .hw.init = &(struct clk_init_data){
>> .name = "vclk2_div",
>> - .ops = &clk_regmap_divider_ops,
>> + .ops = &meson_vclk_div_ops,
>> .parent_hws = (const struct clk_hw *[]) {
>> &g12a_vclk2_input.hw
>> },
>> .num_parents = 1,
>> - .flags = CLK_GET_RATE_NOCACHE,
>> + .flags = CLK_SET_RATE_GATE,
>> },
>> };
>>
>> @@ -3246,16 +3259,24 @@ static struct clk_regmap g12a_vclk = {
>> };
>>
>> static struct clk_regmap g12a_vclk2 = {
>> - .data = &(struct clk_regmap_gate_data){
>> - .offset = HHI_VIID_CLK_CNTL,
>> - .bit_idx = 19,
>> + .data = &(struct meson_vclk_gate_data){
>> + .enable = {
>> + .reg_off = HHI_VIID_CLK_CNTL,
>> + .shift = 19,
>> + .width = 1,
>> + },
>> + .reset = {
>> + .reg_off = HHI_VIID_CLK_CNTL,
>> + .shift = 15,
>> + .width = 1,
>> + },
>> },
>> .hw.init = &(struct clk_init_data) {
>> .name = "vclk2",
>> - .ops = &clk_regmap_gate_ops,
>> + .ops = &meson_vclk_gate_ops,
>> .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },
>> .num_parents = 1,
>> - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> + .flags = CLK_SET_RATE_PARENT,
>> },
>> };
>>
>> @@ -3339,7 +3360,7 @@ static struct clk_regmap g12a_vclk2_div1 = {
>> .ops = &clk_regmap_gate_ops,
>> .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
>> .num_parents = 1,
>> - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> + .flags = CLK_SET_RATE_PARENT,
>> },
>> };
>>
>> @@ -3353,7 +3374,7 @@ static struct clk_regmap g12a_vclk2_div2_en = {
>> .ops = &clk_regmap_gate_ops,
>> .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
>> .num_parents = 1,
>> - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> + .flags = CLK_SET_RATE_PARENT,
>> },
>> };
>>
>> @@ -3367,7 +3388,7 @@ static struct clk_regmap g12a_vclk2_div4_en = {
>> .ops = &clk_regmap_gate_ops,
>> .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
>> .num_parents = 1,
>> - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> + .flags = CLK_SET_RATE_PARENT,
>> },
>> };
>>
>> @@ -3381,7 +3402,7 @@ static struct clk_regmap g12a_vclk2_div6_en = {
>> .ops = &clk_regmap_gate_ops,
>> .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
>> .num_parents = 1,
>> - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> + .flags = CLK_SET_RATE_PARENT,
>> },
>> };
>>
>> @@ -3395,7 +3416,7 @@ static struct clk_regmap g12a_vclk2_div12_en = {
>> .ops = &clk_regmap_gate_ops,
>> .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
>> .num_parents = 1,
>> - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> + .flags = CLK_SET_RATE_PARENT,
>> },
>> };
>>
>> @@ -3461,6 +3482,7 @@ static struct clk_fixed_factor g12a_vclk2_div2 = {
>> &g12a_vclk2_div2_en.hw
>> },
>> .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> },
>> };
>>
>> @@ -3474,6 +3496,7 @@ static struct clk_fixed_factor g12a_vclk2_div4 = {
>> &g12a_vclk2_div4_en.hw
>> },
>> .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> },
>> };
>>
>> @@ -3487,6 +3510,7 @@ static struct clk_fixed_factor g12a_vclk2_div6 = {
>> &g12a_vclk2_div6_en.hw
>> },
>> .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> },
>> };
>>
>> @@ -3500,6 +3524,7 @@ static struct clk_fixed_factor g12a_vclk2_div12 = {
>> &g12a_vclk2_div12_en.hw
>> },
>> .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> },
>> };
>>
>> @@ -3561,7 +3586,7 @@ static struct clk_regmap g12a_cts_encl_sel = {
>> .ops = &clk_regmap_mux_ops,
>> .parent_hws = g12a_cts_parent_hws,
>> .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
>> - .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
>> + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
>> },
>> };
>>
>> @@ -3717,15 +3742,22 @@ static struct clk_regmap g12a_mipi_dsi_pxclk_sel = {
>> .ops = &clk_regmap_mux_ops,
>> .parent_hws = g12a_mipi_dsi_pxclk_parent_hws,
>> .num_parents = ARRAY_SIZE(g12a_mipi_dsi_pxclk_parent_hws),
>> - .flags = CLK_SET_RATE_NO_REPARENT,
>> + .flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
>> },
>> };
>>
>> +/* Force as bypass by forcing a single /1 table entry, and not rely of boot value */
>
> The comment here is not entirely accurate.
>
> The table below will actually force to only use a 1 divider on
> .set_rate(), not on boot, AFAICT.
>
> The boot value will stay in the register until the first call to set_rate().
>
> Considering this is quite fragile as it is, It would be nice to prefix
> the updated comment with "FIXME"
Ack
>
>> +static const struct clk_div_table g12a_mipi_dsi_pxclk_div_table[] = {
>> + { .val = 0, .div = 1 },
>> + { /* sentinel */ },
>> +};
>> +
>> static struct clk_regmap g12a_mipi_dsi_pxclk_div = {
>> .data = &(struct clk_regmap_div_data){
>> .offset = HHI_MIPIDSI_PHY_CLK_CNTL,
>> .shift = 0,
>> .width = 7,
>> + .table = g12a_mipi_dsi_pxclk_div_table,
>> },
>> .hw.init = &(struct clk_init_data){
>> .name = "mipi_dsi_pxclk_div",
>
>
^ permalink raw reply
* Re: [PATCH v11 2/7] clk: meson: add vclk driver
From: Neil Armstrong @ 2024-03-29 16:07 UTC (permalink / raw)
To: Jerome Brunet
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Kevin Hilman,
Michael Turquette, Stephen Boyd, Martin Blumenstingl,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Daniel Vetter, Nicolas Belin, Jagan Teki, devicetree,
linux-kernel, linux-amlogic, linux-clk, linux-arm-kernel,
dri-devel
In-Reply-To: <1jzfuh8bd7.fsf@starbuckisacylon.baylibre.com>
On 29/03/2024 13:33, Jerome Brunet wrote:
>
> On Mon 25 Mar 2024 at 12:09, Neil Armstrong <neil.armstrong@linaro.org> wrote:
>
>> The VCLK and VCLK_DIV clocks have supplementary bits.
>>
>> The VCLK gate has a "SOFT RESET" bit to toggle after the whole
>> VCLK sub-tree rate has been set, this is implemented in
>> the gate enable callback.
>>
>> The VCLK_DIV clocks as enable and reset bits used to disable
>> and reset the divider, associated with CLK_SET_RATE_GATE it ensures
>> the rate is set while the divider is disabled and in reset mode.
>>
>> The VCLK_DIV enable bit isn't implemented as a gate since it's part
>> of the divider logic and vendor does this exact sequence to ensure
>> the divider is correctly set.
>
> checkpatch reports a few easy CHECKs and one WARNING.
> Could you please fix these ?
>
> Other than that, It looks OK.
Ack
thx
Neil
>
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
>> drivers/clk/meson/Kconfig | 4 ++
>> drivers/clk/meson/Makefile | 1 +
>> drivers/clk/meson/vclk.c | 141 +++++++++++++++++++++++++++++++++++++++++++++
>> drivers/clk/meson/vclk.h | 51 ++++++++++++++++
>> 4 files changed, 197 insertions(+)
>>
>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>> index 29ffd14d267b..8a9823789fa3 100644
>> --- a/drivers/clk/meson/Kconfig
>> +++ b/drivers/clk/meson/Kconfig
>> @@ -30,6 +30,10 @@ config COMMON_CLK_MESON_VID_PLL_DIV
>> tristate
>> select COMMON_CLK_MESON_REGMAP
>>
>> +config COMMON_CLK_MESON_VCLK
>> + tristate
>> + select COMMON_CLK_MESON_REGMAP
>> +
>> config COMMON_CLK_MESON_CLKC_UTILS
>> tristate
>>
>> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
>> index 9ee4b954c896..9ba43fe7a07a 100644
>> --- a/drivers/clk/meson/Makefile
>> +++ b/drivers/clk/meson/Makefile
>> @@ -12,6 +12,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o
>> obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o
>> obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o
>> obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o
>> +obj-$(CONFIG_COMMON_CLK_MESON_VCLK) += vclk.o
>>
>> # Amlogic Clock controllers
>>
>> diff --git a/drivers/clk/meson/vclk.c b/drivers/clk/meson/vclk.c
>> new file mode 100644
>> index 000000000000..3ea813a0a995
>> --- /dev/null
>> +++ b/drivers/clk/meson/vclk.c
>> @@ -0,0 +1,141 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (c) 2024 Neil Armstrong <neil.armstrong@linaro.org>
>> + */
>> +
>> +#include <linux/module.h>
>> +#include "vclk.h"
>> +
>> +/* The VCLK gate has a supplementary reset bit to pulse after ungating */
>> +
>> +static inline struct meson_vclk_gate_data *
>> +clk_get_meson_vclk_gate_data(struct clk_regmap *clk)
>> +{
>> + return (struct meson_vclk_gate_data *)clk->data;
>> +}
>> +
>> +static int meson_vclk_gate_enable(struct clk_hw *hw)
>> +{
>> + struct clk_regmap *clk = to_clk_regmap(hw);
>> + struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);
>> +
>> + meson_parm_write(clk->map, &vclk->enable, 1);
>> +
>> + /* Do a reset pulse */
>> + meson_parm_write(clk->map, &vclk->reset, 1);
>> + meson_parm_write(clk->map, &vclk->reset, 0);
>> +
>> + return 0;
>> +}
>> +
>> +static void meson_vclk_gate_disable(struct clk_hw *hw)
>> +{
>> + struct clk_regmap *clk = to_clk_regmap(hw);
>> + struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);
>> +
>> + meson_parm_write(clk->map, &vclk->enable, 0);
>> +}
>> +
>> +static int meson_vclk_gate_is_enabled(struct clk_hw *hw)
>> +{
>> + struct clk_regmap *clk = to_clk_regmap(hw);
>> + struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);
>> +
>> + return meson_parm_read(clk->map, &vclk->enable);
>> +}
>> +
>> +const struct clk_ops meson_vclk_gate_ops = {
>> + .enable = meson_vclk_gate_enable,
>> + .disable = meson_vclk_gate_disable,
>> + .is_enabled = meson_vclk_gate_is_enabled,
>> +};
>> +EXPORT_SYMBOL_GPL(meson_vclk_gate_ops);
>> +
>> +/* The VCLK Divider has supplementary reset & enable bits */
>> +
>> +static inline struct meson_vclk_div_data *
>> +clk_get_meson_vclk_div_data(struct clk_regmap *clk)
>> +{
>> + return (struct meson_vclk_div_data *)clk->data;
>> +}
>> +
>> +static unsigned long meson_vclk_div_recalc_rate(struct clk_hw *hw,
>> + unsigned long prate)
>> +{
>> + struct clk_regmap *clk = to_clk_regmap(hw);
>> + struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
>> +
>> + return divider_recalc_rate(hw, prate, meson_parm_read(clk->map, &vclk->div),
>> + vclk->table, vclk->flags, vclk->div.width);
>> +}
>> +
>> +static int meson_vclk_div_determine_rate(struct clk_hw *hw,
>> + struct clk_rate_request *req)
>> +{
>> + struct clk_regmap *clk = to_clk_regmap(hw);
>> + struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
>> +
>> + return divider_determine_rate(hw, req, vclk->table, vclk->div.width,
>> + vclk->flags);
>> +}
>> +
>> +static int meson_vclk_div_set_rate(struct clk_hw *hw, unsigned long rate,
>> + unsigned long parent_rate)
>> +{
>> + struct clk_regmap *clk = to_clk_regmap(hw);
>> + struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
>> + int ret;
>> +
>> + ret = divider_get_val(rate, parent_rate, vclk->table, vclk->div.width,
>> + vclk->flags);
>> + if (ret < 0)
>> + return ret;
>> +
>> + meson_parm_write(clk->map, &vclk->div, ret);
>> +
>> + return 0;
>> +};
>> +
>> +static int meson_vclk_div_enable(struct clk_hw *hw)
>> +{
>> + struct clk_regmap *clk = to_clk_regmap(hw);
>> + struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
>> +
>> + /* Unreset the divider when ungating */
>> + meson_parm_write(clk->map, &vclk->reset, 0);
>> + meson_parm_write(clk->map, &vclk->enable, 1);
>> +
>> + return 0;
>> +}
>> +
>> +static void meson_vclk_div_disable(struct clk_hw *hw)
>> +{
>> + struct clk_regmap *clk = to_clk_regmap(hw);
>> + struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
>> +
>> + /* Reset the divider when gating */
>> + meson_parm_write(clk->map, &vclk->enable, 0);
>> + meson_parm_write(clk->map, &vclk->reset, 1);
>> +}
>> +
>> +static int meson_vclk_div_is_enabled(struct clk_hw *hw)
>> +{
>> + struct clk_regmap *clk = to_clk_regmap(hw);
>> + struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
>> +
>> + return meson_parm_read(clk->map, &vclk->enable);
>> +}
>> +
>> +const struct clk_ops meson_vclk_div_ops = {
>> + .recalc_rate = meson_vclk_div_recalc_rate,
>> + .determine_rate = meson_vclk_div_determine_rate,
>> + .set_rate = meson_vclk_div_set_rate,
>> + .enable = meson_vclk_div_enable,
>> + .disable = meson_vclk_div_disable,
>> + .is_enabled = meson_vclk_div_is_enabled,
>> +};
>> +EXPORT_SYMBOL_GPL(meson_vclk_div_ops);
>> +
>> +MODULE_DESCRIPTION("Amlogic vclk clock driver");
>> +MODULE_AUTHOR("Neil Armstrong <neil.armstrong@linaro.org>");
>> +MODULE_LICENSE("GPL v2");
>> diff --git a/drivers/clk/meson/vclk.h b/drivers/clk/meson/vclk.h
>> new file mode 100644
>> index 000000000000..20b0b181db09
>> --- /dev/null
>> +++ b/drivers/clk/meson/vclk.h
>> @@ -0,0 +1,51 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * Copyright (c) 2024 Neil Armstrong <neil.armstrong@linaro.org>
>> + */
>> +
>> +#ifndef __VCLK_H
>> +#define __VCLK_H
>> +
>> +#include "clk-regmap.h"
>> +#include "parm.h"
>> +
>> +/**
>> + * struct meson_vclk_gate_data - vclk_gate regmap backed specific data
>> + *
>> + * @enable: vclk enable field
>> + * @reset: vclk reset field
>> + * @flags: hardware-specific flags
>> + *
>> + * Flags:
>> + * Same as clk_gate except CLK_GATE_HIWORD_MASK which is ignored
>> + */
>> +struct meson_vclk_gate_data {
>> + struct parm enable;
>> + struct parm reset;
>> + u8 flags;
>> +};
>> +
>> +extern const struct clk_ops meson_vclk_gate_ops;
>> +
>> +/**
>> + * struct meson_vclk_div_data - vclk_div regmap back specific data
>> + *
>> + * @div: divider field
>> + * @enable: vclk divider enable field
>> + * @reset: vclk divider reset field
>> + * @table: array of value/divider pairs, last entry should have div = 0
>> + *
>> + * Flags:
>> + * Same as clk_divider except CLK_DIVIDER_HIWORD_MASK which is ignored
>> + */
>> +struct meson_vclk_div_data {
>> + struct parm div;
>> + struct parm enable;
>> + struct parm reset;
>> + const struct clk_div_table *table;
>> + u8 flags;
>> +};
>> +
>> +extern const struct clk_ops meson_vclk_div_ops;
>> +
>> +#endif /* __VCLK_H */
>
>
^ permalink raw reply
* [PATCH 2/2] dt-bindings: iio: imu: add icm42688 inside inv_icm42600
From: inv.git-commit @ 2024-03-29 15:15 UTC (permalink / raw)
To: jic23, robh, krzysztof.kozlowski+dt, conor+dt
Cc: lars, linux-iio, devicetree, Jean-Baptiste Maneyrol
In-Reply-To: <20240329151535.712827-1-inv.git-commit@tdk.com>
From: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>
Add bindings for ICM-42688-P chip.
Signed-off-by: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>
---
.../devicetree/bindings/iio/imu/invensense,icm42600.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml b/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml
index 7cd05bcbee31..152aec8d82ff 100644
--- a/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml
+++ b/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml
@@ -31,6 +31,7 @@ properties:
- invensense,icm42602
- invensense,icm42605
- invensense,icm42622
+ - invensense,icm42688
- invensense,icm42631
reg:
--
2.34.1
^ permalink raw reply related
* [PATCH 1/2] iio: imu: inv_icm42600: add support of ICM-42688-P
From: inv.git-commit @ 2024-03-29 15:15 UTC (permalink / raw)
To: jic23, robh, krzysztof.kozlowski+dt, conor+dt
Cc: lars, linux-iio, devicetree, Jean-Baptiste Maneyrol
In-Reply-To: <20240329151535.712827-1-inv.git-commit@tdk.com>
From: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>
Signed-off-by: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>
---
drivers/iio/imu/inv_icm42600/inv_icm42600.h | 2 ++
drivers/iio/imu/inv_icm42600/inv_icm42600_core.c | 5 +++++
drivers/iio/imu/inv_icm42600/inv_icm42600_i2c.c | 3 +++
drivers/iio/imu/inv_icm42600/inv_icm42600_spi.c | 3 +++
4 files changed, 13 insertions(+)
diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600.h b/drivers/iio/imu/inv_icm42600/inv_icm42600.h
index 0e290c807b0f..0566340b2660 100644
--- a/drivers/iio/imu/inv_icm42600/inv_icm42600.h
+++ b/drivers/iio/imu/inv_icm42600/inv_icm42600.h
@@ -22,6 +22,7 @@ enum inv_icm42600_chip {
INV_CHIP_ICM42602,
INV_CHIP_ICM42605,
INV_CHIP_ICM42622,
+ INV_CHIP_ICM42688,
INV_CHIP_ICM42631,
INV_CHIP_NB,
};
@@ -304,6 +305,7 @@ struct inv_icm42600_state {
#define INV_ICM42600_WHOAMI_ICM42602 0x41
#define INV_ICM42600_WHOAMI_ICM42605 0x42
#define INV_ICM42600_WHOAMI_ICM42622 0x46
+#define INV_ICM42600_WHOAMI_ICM42688 0x47
#define INV_ICM42600_WHOAMI_ICM42631 0x5C
/* User bank 1 (MSB 0x10) */
diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600_core.c b/drivers/iio/imu/inv_icm42600/inv_icm42600_core.c
index a5e81906e37e..82e0a2e2ad70 100644
--- a/drivers/iio/imu/inv_icm42600/inv_icm42600_core.c
+++ b/drivers/iio/imu/inv_icm42600/inv_icm42600_core.c
@@ -87,6 +87,11 @@ static const struct inv_icm42600_hw inv_icm42600_hw[INV_CHIP_NB] = {
.name = "icm42622",
.conf = &inv_icm42600_default_conf,
},
+ [INV_CHIP_ICM42688] = {
+ .whoami = INV_ICM42600_WHOAMI_ICM42688,
+ .name = "icm42688",
+ .conf = &inv_icm42600_default_conf,
+ },
[INV_CHIP_ICM42631] = {
.whoami = INV_ICM42600_WHOAMI_ICM42631,
.name = "icm42631",
diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600_i2c.c b/drivers/iio/imu/inv_icm42600/inv_icm42600_i2c.c
index 1af559403ba6..ebb28f84ba98 100644
--- a/drivers/iio/imu/inv_icm42600/inv_icm42600_i2c.c
+++ b/drivers/iio/imu/inv_icm42600/inv_icm42600_i2c.c
@@ -84,6 +84,9 @@ static const struct of_device_id inv_icm42600_of_matches[] = {
}, {
.compatible = "invensense,icm42622",
.data = (void *)INV_CHIP_ICM42622,
+ }, {
+ .compatible = "invensense,icm42688",
+ .data = (void *)INV_CHIP_ICM42688,
}, {
.compatible = "invensense,icm42631",
.data = (void *)INV_CHIP_ICM42631,
diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600_spi.c b/drivers/iio/imu/inv_icm42600/inv_icm42600_spi.c
index 6be4ac794937..50217a10e0bb 100644
--- a/drivers/iio/imu/inv_icm42600/inv_icm42600_spi.c
+++ b/drivers/iio/imu/inv_icm42600/inv_icm42600_spi.c
@@ -80,6 +80,9 @@ static const struct of_device_id inv_icm42600_of_matches[] = {
}, {
.compatible = "invensense,icm42622",
.data = (void *)INV_CHIP_ICM42622,
+ }, {
+ .compatible = "invensense,icm42688",
+ .data = (void *)INV_CHIP_ICM42688,
}, {
.compatible = "invensense,icm42631",
.data = (void *)INV_CHIP_ICM42631,
--
2.34.1
^ permalink raw reply related
* Re: [PATCH RESEND v6 3/5] spmi: pmic-arb: Make the APID init a version operation
From: Abel Vesa @ 2024-03-29 16:32 UTC (permalink / raw)
To: Neil Armstrong
Cc: Stephen Boyd, Matthias Brugger, Bjorn Andersson, Konrad Dybcio,
Dmitry Baryshkov, AngeloGioacchino Del Regno, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Srini Kandagatla, Johan Hovold,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-mediatek,
devicetree
In-Reply-To: <9af9cfd1-38c7-4f38-a652-fd046f427f98@linaro.org>
On 24-03-28 09:51:49, Neil Armstrong wrote:
> On 26/03/2024 17:28, Abel Vesa wrote:
> > Rather than using conditionals in probe function, add the APID init
> > as a version specific operation. Due to v7, which supports multiple
> > buses, pass on the bus index to be used for sorting out the apid base
> > and count.
> >
> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> > ---
> > drivers/spmi/spmi-pmic-arb.c | 199 +++++++++++++++++++++++++++----------------
> > 1 file changed, 124 insertions(+), 75 deletions(-)
> >
> > diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c
> > index 9ed1180fe31f..38fed8a585fe 100644
> > --- a/drivers/spmi/spmi-pmic-arb.c
> > +++ b/drivers/spmi/spmi-pmic-arb.c
> > @@ -183,6 +183,7 @@ struct spmi_pmic_arb {
> > * struct pmic_arb_ver_ops - version dependent functionality.
> > *
> > * @ver_str: version string.
> > + * @init_apid: finds the apid base and count
> > * @ppid_to_apid: finds the apid for a given ppid.
> > * @non_data_cmd: on v1 issues an spmi non-data command.
> > * on v2 no HW support, returns -EOPNOTSUPP.
> > @@ -202,6 +203,7 @@ struct spmi_pmic_arb {
> > */
> > struct pmic_arb_ver_ops {
> > const char *ver_str;
> > + int (*init_apid)(struct spmi_pmic_arb *pmic_arb, int index);
> > int (*ppid_to_apid)(struct spmi_pmic_arb *pmic_arb, u16 ppid);
> > /* spmi commands (read_cmd, write_cmd, cmd) functionality */
> > int (*offset)(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
> > @@ -942,6 +944,38 @@ static int qpnpint_irq_domain_alloc(struct irq_domain *domain,
> > return 0;
> > }
> > +static int pmic_arb_init_apid_min_max(struct spmi_pmic_arb *pmic_arb)
> > +{
> > + /*
> > + * Initialize max_apid/min_apid to the opposite bounds, during
> > + * the irq domain translation, we are sure to update these
> > + */
> > + pmic_arb->max_apid = 0;
> > + pmic_arb->min_apid = pmic_arb->max_periphs - 1;
> > +
> > + return 0;
> > +}
> > +
> > +static int pmic_arb_init_apid_v1(struct spmi_pmic_arb *pmic_arb, int index)
> > +{
> > + u32 *mapping_table;
> > +
> > + if (index) {
> > + dev_err(&pmic_arb->spmic->dev, "Unsupported buses count %d detected\n",
> > + index);
> > + return -EINVAL;
> > + }
> > +
> > + mapping_table = devm_kcalloc(&pmic_arb->spmic->dev, pmic_arb->max_periphs,
> > + sizeof(*mapping_table), GFP_KERNEL);
> > + if (!mapping_table)
> > + return -ENOMEM;
> > +
> > + pmic_arb->mapping_table = mapping_table;
>
> Can you specify in the spmi_pmic_arb->mapping_table struct documentation the mapping_table
> is only used in v1 ? or even better rename it to mapping_table_v1
>
Actually the mapping_table is used on version 1 through 3.
^ permalink raw reply
* [PATCH v4 0/4] arm64: dts: imx8: add cm40 and cm40_uart
From: Frank Li @ 2024-03-29 16:37 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Frank Li,
Dong Aisheng, Alexander Stein, Alice Guo, Peng Fan
Add cm40 subsystem.
Add cm40_lpuart and lpurt1 for 8dxl evk boards.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Changes in v4:
- fixed lpcg index.
- fixed typo 'informaiton'.
- fixed fixregulator name
- Link to v3: https://lore.kernel.org/r/20240305-m4_lpuart-v3-0-592463ef1d22@nxp.com
Changes in v3:
- Add Alexander review tags
- move interrupt-parent below range.
- move interrupt-parent before interrutps at intmux node
- Link to v2: https://lore.kernel.org/r/20240302-m4_lpuart-v2-0-89a5952043b6@nxp.com
Changes in v2:
- commit message "Adding" to Add
- fixed regulator@101 warning
- remove 'modem reset'
- order nodes by access
- move interrupt-parent under top bus
- clean up other dtb check warning
- Link to v1: https://lore.kernel.org/r/20240228-m4_lpuart-v1-0-9e6947be15e7@nxp.com
---
Alice Guo (1):
arm64: dts: imx8dxl: add lpuart device in cm40 subsystem
Dong Aisheng (1):
arm64: dts: imx8: add cm40 subsystem dtsi
Frank Li (2):
arm64: dts: imx8dxl: update cm40 irq number information
dts: arm64: imx8dxl-evk: add lpuart1 and cm40 uart
arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi | 91 +++++++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 37 ++++++++++
arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 13 ++++
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 +
4 files changed, 142 insertions(+)
---
base-commit: 9acc053fc8f256959e849cb6588a054074daebcd
change-id: 20240228-m4_lpuart-30791c032f2a
Best regards,
---
Frank Li <Frank.Li@nxp.com>
^ permalink raw reply
* [PATCH v4 1/4] arm64: dts: imx8: add cm40 subsystem dtsi
From: Frank Li @ 2024-03-29 16:37 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Frank Li,
Dong Aisheng, Alexander Stein
In-Reply-To: <20240329-m4_lpuart-v4-0-c11d9ca2a317@nxp.com>
From: Dong Aisheng <aisheng.dong@nxp.com>
Add cm40 subsystem dtsi.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi | 67 +++++++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 2 +
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 +
3 files changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
new file mode 100644
index 0000000000000..10a05db06ade9
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+cm40_ipg_clk: clock-cm40-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <132000000>;
+ clock-output-names = "cm40_ipg_clk";
+};
+
+cm40_subsys: bus@34000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x34000000 0x0 0x34000000 0x4000000>;
+ interrupt-parent = <&cm40_intmux>;
+
+ cm40_i2c: i2c@37230000 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x37230000 0x1000>;
+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cm40_i2c_lpcg IMX_LPCG_CLK_0>,
+ <&cm40_i2c_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_M4_0_I2C>;
+ status = "disabled";
+ };
+
+ cm40_intmux: intmux@37400000 {
+ compatible = "fsl,imx-intmux";
+ reg = <0x37400000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&cm40_ipg_clk>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_M4_0_INTMUX>;
+ status = "disabled";
+ };
+
+ cm40_i2c_lpcg: clock-controller@37630000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x37630000 0x1000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>,
+ <&cm40_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "cm40_lpcg_i2c_clk",
+ "cm40_lpcg_i2c_ipg_clk";
+ power-domains = <&pd IMX_SC_R_M4_0_I2C>;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
index a0674c5c55766..9d49c75a26222 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/clock/imx8-clock.h>
#include <dt-bindings/dma/fsl-edma.h>
+#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -231,6 +232,7 @@ xtal24m: clock-xtal24m {
};
/* sorted in register address */
+ #include "imx8-ss-cm40.dtsi"
#include "imx8-ss-adma.dtsi"
#include "imx8-ss-conn.dtsi"
#include "imx8-ss-ddr.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 10e16d84c0c3b..0313f295de2e9 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -317,6 +317,7 @@ map0 {
/* sorted in register address */
#include "imx8-ss-img.dtsi"
#include "imx8-ss-vpu.dtsi"
+ #include "imx8-ss-cm40.dtsi"
#include "imx8-ss-gpu0.dtsi"
#include "imx8-ss-adma.dtsi"
#include "imx8-ss-conn.dtsi"
--
2.34.1
^ permalink raw reply related
* [PATCH v4 2/4] arm64: dts: imx8dxl: add lpuart device in cm40 subsystem
From: Frank Li @ 2024-03-29 16:37 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Frank Li,
Alice Guo, Peng Fan, Alexander Stein
In-Reply-To: <20240329-m4_lpuart-v4-0-c11d9ca2a317@nxp.com>
From: Alice Guo <alice.guo@nxp.com>
Add lpuart device in cm40 subsystem.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
index 10a05db06ade9..5cff052b95d18 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
@@ -20,6 +20,18 @@ cm40_subsys: bus@34000000 {
ranges = <0x34000000 0x0 0x34000000 0x4000000>;
interrupt-parent = <&cm40_intmux>;
+ cm40_lpuart: serial@37220000 {
+ compatible = "fsl,imx8qxp-lpuart";
+ reg = <0x37220000 0x1000>;
+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cm40_uart_lpcg IMX_LPCG_CLK_1>, <&cm40_uart_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "ipg", "baud";
+ assigned-clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_M4_0_UART>;
+ status = "disabled";
+ };
+
cm40_i2c: i2c@37230000 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x37230000 0x1000>;
@@ -53,6 +65,18 @@ cm40_intmux: intmux@37400000 {
status = "disabled";
};
+ cm40_uart_lpcg: clock-controller@37620000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x37620000 0x1000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>,
+ <&cm40_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>;
+ clock-output-names = "cm40_lpcg_uart_clk",
+ "cm40_lpcg_uart_ipg_clk";
+ power-domains = <&pd IMX_SC_R_M4_0_UART>;
+ };
+
cm40_i2c_lpcg: clock-controller@37630000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x37630000 0x1000>;
--
2.34.1
^ permalink raw reply related
* [PATCH v4 3/4] arm64: dts: imx8dxl: update cm40 irq number information
From: Frank Li @ 2024-03-29 16:37 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Frank Li
In-Reply-To: <20240329-m4_lpuart-v4-0-c11d9ca2a317@nxp.com>
Update cm40 irq number for imx8dxl chip.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
index 9d49c75a26222..b9d137d69f5a7 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
@@ -243,3 +243,14 @@ xtal24m: clock-xtal24m {
#include "imx8dxl-ss-conn.dtsi"
#include "imx8dxl-ss-lsio.dtsi"
#include "imx8dxl-ss-ddr.dtsi"
+
+&cm40_intmux {
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+};
--
2.34.1
^ permalink raw reply related
* [PATCH v4 4/4] dts: arm64: imx8dxl-evk: add lpuart1 and cm40 uart
From: Frank Li @ 2024-03-29 16:37 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Frank Li
In-Reply-To: <20240329-m4_lpuart-v4-0-c11d9ca2a317@nxp.com>
Add lpuart1 and cm40 uart.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 37 +++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
index 2123d431e0613..2412ab145c066 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
@@ -16,6 +16,8 @@ aliases {
mmc0 = &usdhc1;
mmc1 = &usdhc2;
serial0 = &lpuart0;
+ serial1 = &lpuart1;
+ serial6 = &cm40_lpuart;
};
chosen {
@@ -51,6 +53,16 @@ linux,cma {
};
};
+ m2_uart1_sel: regulator-m2uart1sel {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "m2_uart1_sel";
+ gpio = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
mux3_en: regulator-0 {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
@@ -340,6 +352,12 @@ &lpuart0 {
status = "okay";
};
+&lpuart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+ status = "okay";
+};
+
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
@@ -354,6 +372,16 @@ &flexcan3 {
status = "okay";
};
+&cm40_intmux {
+ status = "disabled";
+};
+
+&cm40_lpuart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_cm40_lpuart>;
+ status = "disabled";
+};
+
&lsio_gpio4 {
status = "okay";
};
@@ -595,6 +623,15 @@ IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020
>;
};
+ pinctrl_lpuart1: lpuart1grp {
+ fsl,pins = <
+ IMX8DXL_UART1_TX_ADMA_UART1_TX 0x06000020
+ IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020
+ IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020
+ IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
--
2.34.1
^ permalink raw reply related
* Re: (subset) [PATCH 0/5] Add Support for RK3326 GameForce Chi
From: Neil Armstrong @ 2024-03-29 16:37 UTC (permalink / raw)
To: linux-rockchip, Chris Morgan
Cc: dri-devel, devicetree, daniel, airlied, sam, quic_jesszhan, megi,
kernel, agx, heiko, conor+dt, krzysztof.kozlowski+dt, robh,
Chris Morgan
In-Reply-To: <20240325134959.11807-1-macroalpha82@gmail.com>
Hi,
On Mon, 25 Mar 2024 08:49:54 -0500, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Add support for the GameForce Chi [1].
>
> The GameForce Chi has the following hardware:
> Tested:
> - 3.5" dual lane 640x480 DSI display.
> - 15 GPIO based face buttons.
> - 2 ADC based face buttons.
> - 1 ADC joystick (left) connected to internal SARADC.
> - RGB LED arrays for key backlighting
> - Dual internal speakers.
> - Realtek RTL8723BS SDIO WiFi.
> - Single SDMMC slot.
>
> [...]
Thanks, Applied to https://gitlab.freedesktop.org/drm/misc/kernel.git (drm-misc-next)
[1/5] dt-bindings: vendor-prefix: Add prefix for GameForce
https://gitlab.freedesktop.org/drm/misc/kernel/-/commit/59237fc04ee1c4cdf62ad5dba18244713970e36f
[2/5] dt-bindings: display: Add GameForce Chi Panel
https://gitlab.freedesktop.org/drm/misc/kernel/-/commit/387974a21a63b1c7efcbc19c48b9930f6ef5ac63
[3/5] drm/panel: st7703: Add GameForce Chi Panel Support
https://gitlab.freedesktop.org/drm/misc/kernel/-/commit/4c4f33be7e4d476566246e7166c54ef175287e00
--
Neil
^ permalink raw reply
* Re: [PATCH v9 0/8] I3C target mode support
From: Frank Li @ 2024-03-29 16:52 UTC (permalink / raw)
To: alexandre.belloni
Cc: conor.culhane, devicetree, gregkh, ilpo.jarvinen, imx, jirislaby,
joe, krzysztof.kozlowski+dt, krzysztof.kozlowski, linux-i3c,
linux-kernel, linux-serial, miquel.raynal, robh,
zbigniew.lukwinski
In-Reply-To: <20240308162518.1615468-1-Frank.Li@nxp.com>
On Fri, Mar 08, 2024 at 11:25:10AM -0500, Frank Li wrote:
> This patch introduces support for I3C target mode, which is referenced
> with a PCIe Endpoint system. It also establishes a configuration framework
> (configfs) for the I3C target controller driver and the I3C target function
> driver
Alex:
Do you have any concern about these patches?
Frank
>
> Typic usage as
>
> The user can configure the i3c-target-tty device using configfs entry. In
> order to change the vendorid, the following commands can be used
>
> # echo 0x011b > functions/tty/func1/vendor_id
> # echo 0x1000 > functions/tty/func1/part_id
> # echo 0x6 > functions/tty/t/bcr
>
> Binding i3c-target-tty Device to target Controller
> ------------------------------------------------
>
> In order for the target function device to be useful, it has to be bound to
> a I3C target controller driver. Use the configfs to bind the function
> device to one of the controller driver present in the system::
>
> # ln -s functions/pci_epf_test/func1 controllers/44330000.i3c-target/
>
> Host side:
> cat /dev/ttyI3C0
> Taret side:
> echo abc >/dev/ttyI3C0
>
> Notes about header files.
>
> About Ilpo Järvinen's header file comments, it can pass build, some header
> should be included by other header files.
>
> I added some, but I am not sure that is all needs. There may have tools,
> which can help check, but I don't know.
>
> Chagne from v2 to v3
> - using 'mode' distingiush master and target.
> - move svc-i3c-target.c to under master,
> - built together with svc-i3c-master.c
>
> Change from v1 to v2
> - change "slave" to "target"
> - include master side tty patch
> - fixed dtbcheck problem
> - fixed kerne-doc check warning
>
> Some review comment may be lost since it is quite long time since v1. Now
> master side dependent patches already in linux-next. So sent target side
> patches with tty support again.
>
> No sure why an additional "\r\n" appended.
>
> Frank Li (8):
> i3c: add target mode support
> dt-bindings: i3c: svc: add proptery mode
> Documentation: i3c: Add I3C target mode controller and function
> i3c: svc: Add svc-i3c-main.c and svc-i3c.h
> i3c: target: add svc target controller support
> i3c: target: func: add tty driver
> i3c: add API i3c_dev_gettstatus_format1() to get target device status
> tty: i3c: add TTY over I3C master support
>
> .../bindings/i3c/silvaco,i3c-master.yaml | 11 +-
> Documentation/driver-api/i3c/index.rst | 1 +
> .../driver-api/i3c/target/i3c-target-cfs.rst | 109 +++
> .../driver-api/i3c/target/i3c-target.rst | 189 +++++
> .../driver-api/i3c/target/i3c-tty-howto.rst | 109 +++
> Documentation/driver-api/i3c/target/index.rst | 13 +
> drivers/i3c/Kconfig | 31 +-
> drivers/i3c/Makefile | 3 +
> drivers/i3c/device.c | 24 +
> drivers/i3c/func/Kconfig | 9 +
> drivers/i3c/func/Makefile | 3 +
> drivers/i3c/func/tty.c | 481 +++++++++++
> drivers/i3c/i3c-cfs.c | 389 +++++++++
> drivers/i3c/internals.h | 1 +
> drivers/i3c/master.c | 26 +
> drivers/i3c/master/Makefile | 3 +-
> drivers/i3c/master/svc-i3c-main.c | 80 ++
> drivers/i3c/master/svc-i3c-master.c | 34 +-
> drivers/i3c/master/svc-i3c-target.c | 776 ++++++++++++++++++
> drivers/i3c/master/svc-i3c.h | 15 +
> drivers/i3c/target.c | 453 ++++++++++
> drivers/tty/Kconfig | 13 +
> drivers/tty/Makefile | 1 +
> drivers/tty/i3c_tty.c | 432 ++++++++++
> include/linux/i3c/device.h | 1 +
> include/linux/i3c/target.h | 548 +++++++++++++
> 26 files changed, 3724 insertions(+), 31 deletions(-)
> create mode 100644 Documentation/driver-api/i3c/target/i3c-target-cfs.rst
> create mode 100644 Documentation/driver-api/i3c/target/i3c-target.rst
> create mode 100644 Documentation/driver-api/i3c/target/i3c-tty-howto.rst
> create mode 100644 Documentation/driver-api/i3c/target/index.rst
> create mode 100644 drivers/i3c/func/Kconfig
> create mode 100644 drivers/i3c/func/Makefile
> create mode 100644 drivers/i3c/func/tty.c
> create mode 100644 drivers/i3c/i3c-cfs.c
> create mode 100644 drivers/i3c/master/svc-i3c-main.c
> create mode 100644 drivers/i3c/master/svc-i3c-target.c
> create mode 100644 drivers/i3c/master/svc-i3c.h
> create mode 100644 drivers/i3c/target.c
> create mode 100644 drivers/tty/i3c_tty.c
> create mode 100644 include/linux/i3c/target.h
>
> --
> 2.34.1
>
^ permalink raw reply
* Re: [PATCH RFT 3/7] phy: qcom: qmp-combo: introduce QPHY_MODE
From: Vinod Koul @ 2024-03-29 16:56 UTC (permalink / raw)
To: Neil Armstrong
Cc: Bjorn Andersson, Konrad Dybcio, Kishon Vijay Abraham I,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
linux-phy, devicetree, linux-kernel
In-Reply-To: <20240229-topic-sm8x50-upstream-phy-combo-typec-mux-v1-3-07e24a231840@linaro.org>
On 29-02-24, 14:07, Neil Armstrong wrote:
> Introduce an enum for the QMP Combo PHY modes, use it in the
> QMP commmon phy init function and default to COMBO mode.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 41 +++++++++++++++++++++++++++----
> 1 file changed, 36 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> index 3721bbea9eae..ac5d528fd7a1 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> @@ -61,6 +61,12 @@
>
> #define PHY_INIT_COMPLETE_TIMEOUT 10000
>
> +enum qphy_mode {
> + QPHY_MODE_COMBO = 0,
> + QPHY_MODE_DP_ONLY,
> + QPHY_MODE_USB_ONLY,
> +};
> +
> /* set of registers with offsets different per-PHY */
> enum qphy_reg_layout {
> /* PCS registers */
> @@ -1491,6 +1497,7 @@ struct qmp_combo {
>
> struct mutex phy_mutex;
> int init_count;
> + enum qphy_mode init_mode;
>
> struct phy *usb_phy;
> enum phy_mode mode;
> @@ -2531,12 +2538,33 @@ static int qmp_combo_com_init(struct qmp_combo *qmp, bool force)
> if (qmp->orientation == TYPEC_ORIENTATION_REVERSE)
> val |= SW_PORTSELECT_VAL;
> writel(val, com + QPHY_V3_DP_COM_TYPEC_CTRL);
> - writel(USB3_MODE | DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL);
>
> - /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
> - qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
> - SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
> - SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
> + switch (qmp->init_mode) {
> + case QPHY_MODE_COMBO:
Case should be at same indent as switch :-) coding style 101
> + writel(USB3_MODE | DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL);
> +
> + /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
> + qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
> + SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
> + SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
> + break;
> +
> + case QPHY_MODE_DP_ONLY:
> + writel(DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL);
> +
> + /* bring QMP DP PHY PCS block out of reset */
> + qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
> + SW_DPPHY_RESET_MUX | SW_DPPHY_RESET);
> + break;
> +
> + case QPHY_MODE_USB_ONLY:
> + writel(USB3_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL);
> +
> + /* bring QMP USB PHY PCS block out of reset */
> + qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
> + SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
> + break;
> + }
>
> qphy_clrbits(com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
> qphy_clrbits(com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
> @@ -3545,6 +3573,9 @@ static int qmp_combo_probe(struct platform_device *pdev)
> if (ret)
> goto err_node_put;
>
> + /* Set PHY_MODE as combo by default */
> + qmp->init_mode = QPHY_MODE_COMBO;
> +
> qmp->usb_phy = devm_phy_create(dev, usb_np, &qmp_combo_usb_phy_ops);
> if (IS_ERR(qmp->usb_phy)) {
> ret = PTR_ERR(qmp->usb_phy);
>
> --
> 2.34.1
--
~Vinod
^ permalink raw reply
* [PATCH] dt-bindings: pci: altera: covert to yaml
From: matthew.gerlach @ 2024-03-29 17:00 UTC (permalink / raw)
To: joyce.ooi, bhelgaas, lpieralisi, kw, robh, krzysztof.kozlowski+dt,
conor+dt, linux-pci, devicetree, linux-kernel
Cc: Matthew Gerlach
From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Covert the device tree bindings for the Altera Root
Port controller from text to yaml.
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
---
.../devicetree/bindings/pci/altera-pcie.txt | 50 ---------
.../bindings/pci/altr,pcie-root-port.yaml | 106 ++++++++++++++++++
2 files changed, 106 insertions(+), 50 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pci/altera-pcie.txt
create mode 100644 Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt b/Documentation/devicetree/bindings/pci/altera-pcie.txt
deleted file mode 100644
index 816b244a221e..000000000000
--- a/Documentation/devicetree/bindings/pci/altera-pcie.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-* Altera PCIe controller
-
-Required properties:
-- compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0"
-- reg: a list of physical base address and length for TXS and CRA.
- For "altr,pcie-root-port-2.0", additional HIP base address and length.
-- reg-names: must include the following entries:
- "Txs": TX slave port region
- "Cra": Control register access region
- "Hip": Hard IP region (if "altr,pcie-root-port-2.0")
-- interrupts: specifies the interrupt source of the parent interrupt
- controller. The format of the interrupt specifier depends
- on the parent interrupt controller.
-- device_type: must be "pci"
-- #address-cells: set to <3>
-- #size-cells: set to <2>
-- #interrupt-cells: set to <1>
-- ranges: describes the translation of addresses for root ports and
- standard PCI regions.
-- interrupt-map-mask and interrupt-map: standard PCI properties to define the
- mapping of the PCIe interface to interrupt numbers.
-
-Optional properties:
-- msi-parent: Link to the hardware entity that serves as the MSI controller
- for this PCIe controller.
-- bus-range: PCI bus numbers covered
-
-Example
- pcie_0: pcie@c00000000 {
- compatible = "altr,pcie-root-port-1.0";
- reg = <0xc0000000 0x20000000>,
- <0xff220000 0x00004000>;
- reg-names = "Txs", "Cra";
- interrupt-parent = <&hps_0_arm_gic_0>;
- interrupts = <0 40 4>;
- interrupt-controller;
- #interrupt-cells = <1>;
- bus-range = <0x0 0xFF>;
- device_type = "pci";
- msi-parent = <&msi_to_gic_gen_0>;
- #address-cells = <3>;
- #size-cells = <2>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie_0 1>,
- <0 0 0 2 &pcie_0 2>,
- <0 0 0 3 &pcie_0 3>,
- <0 0 0 4 &pcie_0 4>;
- ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
- 0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
- };
diff --git a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
new file mode 100644
index 000000000000..8f1ad1362ad1
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (C) 2024, Intel Corporation
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/altr,pcie-root-port.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera PCIe Root Port
+
+maintainers:
+ - Matthew Gerlach <matthew.gerlach@linux.intel.com>
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - altr,pcie-root-port-1.0
+ - altr,pcie-root-port-2.0
+
+ reg:
+ minItems: 2
+ maxItems: 3
+
+ reg-names:
+ description:
+ TX slave port region (Txs)
+ Control register access region (Cra)
+ Hard IP region if altr,pcie-root-port-2.0 (Hip)
+
+ items:
+ - const: Txs
+ - const: Cra
+ - const: Hip
+ minItems: 2
+
+ device_type:
+ const: pci
+
+ "#address-cells":
+ const: 3
+
+ "#size-cells":
+ const: 2
+
+ interrupts:
+ minItems: 1
+
+ interrupt-map-mask:
+ items:
+ - const: 0
+ - const: 0
+ - const: 0
+ - const: 7
+
+ interrupt-map:
+ maxItems: 4
+
+ "#interrupt-cells":
+ const: 1
+
+ msi-parent:
+ description: Link to the hardware entity that serves as the MSI controller.
+
+ bus-range:
+ description: PCI bus numbers covered.
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - device_type
+ - "#address-cells"
+ - "#size-cells"
+ - interrupts
+ - interrupt-map
+ - interrupt-map-mask
+ - "#interrupt-cells"
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ pcie_0: pcie@c00000000 {
+ compatible = "altr,pcie-root-port-1.0";
+ reg = <0xc0000000 0x20000000>,
+ <0xff220000 0x00004000>;
+ reg-names = "Txs", "Cra";
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 40 4>;
+ #interrupt-cells = <1>;
+ bus-range = <0x0 0xFF>;
+ device_type = "pci";
+ msi-parent = <&msi_to_gic_gen_0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc 1>,
+ <0 0 0 2 &pcie_intc 2>,
+ <0 0 0 3 &pcie_intc 3>,
+ <0 0 0 4 &pcie_intc 4>;
+ ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
+ 0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
+ };
--
2.34.1
^ permalink raw reply related
* Re: [PATCH 2/4] drm/panel: simple: Add missing Innolux G121X1-L03 format, flags, connector
From: Jessica Zhang @ 2024-03-29 17:03 UTC (permalink / raw)
To: Marek Vasut, dri-devel
Cc: Conor Dooley, Daniel Vetter, David Airlie, Krzysztof Kozlowski,
Maarten Lankhorst, Maxime Ripard, Neil Armstrong, Rob Herring,
Sam Ravnborg, Thierry Reding, Thomas Zimmermann, devicetree
In-Reply-To: <20240328102746.17868-2-marex@denx.de>
On 3/28/2024 3:27 AM, Marek Vasut wrote:
> The .bpc = 6 implies .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG ,
> add the missing bus_format. Add missing connector type and bus_flags
> as well.
>
> Documentation [1] 1.4 GENERAL SPECIFICATI0NS indicates this panel is
> capable of both RGB 18bit/24bit panel, the current configuration uses
> 18bit mode, .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG , .bpc = 6.
>
> Support for the 24bit mode would require another entry in panel-simple
> with .bus_format = MEDIA_BUS_FMT_RGB666_1X7X4_SPWG and .bpc = 8, which
> is out of scope of this fix.
>
> [1] https://www.distec.de/fileadmin/pdf/produkte/TFT-Displays/Innolux/G121X1-L03_Datasheet.pdf
Hi Marek,
Acked-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Thanks,
Jessica Zhang
>
> Fixes: f8fa17ba812b ("drm/panel: simple: Add support for Innolux G121X1-L03")
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Daniel Vetter <daniel@ffwll.ch>
> Cc: David Airlie <airlied@gmail.com>
> Cc: Jessica Zhang <quic_jesszhan@quicinc.com>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Maxime Ripard <mripard@kernel.org>
> Cc: Neil Armstrong <neil.armstrong@linaro.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Sam Ravnborg <sam@ravnborg.org>
> Cc: Thierry Reding <thierry.reding@gmail.com>
> Cc: Thomas Zimmermann <tzimmermann@suse.de>
> Cc: devicetree@vger.kernel.org
> Cc: dri-devel@lists.freedesktop.org
> ---
> drivers/gpu/drm/panel/panel-simple.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> index d9ddef0e675a7..d4c30a86d15d6 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -2618,6 +2618,9 @@ static const struct panel_desc innolux_g121x1_l03 = {
> .unprepare = 200,
> .disable = 400,
> },
> + .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
> + .bus_flags = DRM_BUS_FLAG_DE_HIGH,
> + .connector_type = DRM_MODE_CONNECTOR_LVDS,
> };
>
> static const struct display_timing innolux_g156hce_l01_timings = {
> --
> 2.43.0
>
^ permalink raw reply
* Re: [PATCH 3/4] drm/panel: simple: Convert Innolux G121X1-L03 to display_timing
From: Jessica Zhang @ 2024-03-29 17:03 UTC (permalink / raw)
To: Marek Vasut, dri-devel
Cc: Conor Dooley, Daniel Vetter, David Airlie, Krzysztof Kozlowski,
Maarten Lankhorst, Maxime Ripard, Neil Armstrong, Rob Herring,
Sam Ravnborg, Thierry Reding, Thomas Zimmermann, devicetree
In-Reply-To: <20240328102746.17868-3-marex@denx.de>
On 3/28/2024 3:27 AM, Marek Vasut wrote:
> Use display_timing instead of drm_display_mode to define a range of
> possible display timings supported by this panel. This makes the panel
> support more flexible and improves compatibility. No functional change
> is expected.
>
> The settings are picked from documentation [1] section 6.1 INPUT SIGNAL
> TIMING SPECIFICATIONS.
>
> [1] https://www.distec.de/fileadmin/pdf/produkte/TFT-Displays/Innolux/G121X1-L03_Datasheet.pdf
Hi Marek,
Acked-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Thanks,
Jessica Zhang
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Daniel Vetter <daniel@ffwll.ch>
> Cc: David Airlie <airlied@gmail.com>
> Cc: Jessica Zhang <quic_jesszhan@quicinc.com>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Maxime Ripard <mripard@kernel.org>
> Cc: Neil Armstrong <neil.armstrong@linaro.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Sam Ravnborg <sam@ravnborg.org>
> Cc: Thierry Reding <thierry.reding@gmail.com>
> Cc: Thomas Zimmermann <tzimmermann@suse.de>
> Cc: devicetree@vger.kernel.org
> Cc: dri-devel@lists.freedesktop.org
> ---
> drivers/gpu/drm/panel/panel-simple.c | 26 +++++++++++++-------------
> 1 file changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> index d4c30a86d15d6..737c78b3b8a23 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -2592,22 +2592,22 @@ static const struct panel_desc innolux_g121i1_l01 = {
> .connector_type = DRM_MODE_CONNECTOR_LVDS,
> };
>
> -static const struct drm_display_mode innolux_g121x1_l03_mode = {
> - .clock = 65000,
> - .hdisplay = 1024,
> - .hsync_start = 1024 + 0,
> - .hsync_end = 1024 + 1,
> - .htotal = 1024 + 0 + 1 + 320,
> - .vdisplay = 768,
> - .vsync_start = 768 + 38,
> - .vsync_end = 768 + 38 + 1,
> - .vtotal = 768 + 38 + 1 + 0,
> - .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
> +static const struct display_timing innolux_g121x1_l03_timings = {
> + .pixelclock = { 57500000, 64900000, 74400000 },
> + .hactive = { 1024, 1024, 1024 },
> + .hfront_porch = { 90, 140, 190 },
> + .hback_porch = { 90, 140, 190 },
> + .hsync_len = { 36, 40, 60 },
> + .vactive = { 768, 768, 768 },
> + .vfront_porch = { 2, 15, 30 },
> + .vback_porch = { 2, 15, 30 },
> + .vsync_len = { 2, 8, 20 },
> + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
> };
>
> static const struct panel_desc innolux_g121x1_l03 = {
> - .modes = &innolux_g121x1_l03_mode,
> - .num_modes = 1,
> + .timings = &innolux_g121x1_l03_timings,
> + .num_timings = 1,
> .bpc = 6,
> .size = {
> .width = 246,
> --
> 2.43.0
>
^ permalink raw reply
* Re: [PATCH 4/4] drm/panel: simple: Add Innolux G121XCE-L01 LVDS display support
From: Jessica Zhang @ 2024-03-29 17:04 UTC (permalink / raw)
To: Marek Vasut, dri-devel
Cc: Conor Dooley, Daniel Vetter, David Airlie, Krzysztof Kozlowski,
Maarten Lankhorst, Maxime Ripard, Neil Armstrong, Rob Herring,
Sam Ravnborg, Thierry Reding, Thomas Zimmermann, devicetree
In-Reply-To: <20240328102746.17868-4-marex@denx.de>
On 3/28/2024 3:27 AM, Marek Vasut wrote:
> G121XCE-L01 is a Color Active Matrix Liquid Crystal Display composed of
> a TFT LCD panel, a driver circuit, and LED backlight system. The screen
> format is intended to support the 4:3, 1024(H) x 768(V) screen and either
> 262k/16.7M colors (RGB 6-bits or 8-bits) with LED backlight driver circuit.
> All input signals are LVDS interface compatible.
>
> Documentation [1] and [2] indicate that G121X1-L03 and G121XCE-L01 are
> effectively identical panels, use the former as RGB 6-bits variant and
> add the later as RGB 8-bits variant.
>
> [1] https://www.distec.de/fileadmin/pdf/produkte/TFT-Displays/Innolux/G121X1-L03_Datasheet.pdf
> [2] https://www.distec.de/fileadmin/pdf/produkte/TFT-Displays/Innolux/G121XCE-L01_Datasheet.pdf
Hi Marek,
Acked-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Thanks,
Jessica Zhang
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Daniel Vetter <daniel@ffwll.ch>
> Cc: David Airlie <airlied@gmail.com>
> Cc: Jessica Zhang <quic_jesszhan@quicinc.com>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Maxime Ripard <mripard@kernel.org>
> Cc: Neil Armstrong <neil.armstrong@linaro.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Sam Ravnborg <sam@ravnborg.org>
> Cc: Thierry Reding <thierry.reding@gmail.com>
> Cc: Thomas Zimmermann <tzimmermann@suse.de>
> Cc: devicetree@vger.kernel.org
> Cc: dri-devel@lists.freedesktop.org
> ---
> drivers/gpu/drm/panel/panel-simple.c | 21 +++++++++++++++++++++
> 1 file changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> index 737c78b3b8a23..5acc9f2941909 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -2623,6 +2623,24 @@ static const struct panel_desc innolux_g121x1_l03 = {
> .connector_type = DRM_MODE_CONNECTOR_LVDS,
> };
>
> +static const struct panel_desc innolux_g121xce_l01 = {
> + .timings = &innolux_g121x1_l03_timings,
> + .num_timings = 1,
> + .bpc = 8,
> + .size = {
> + .width = 246,
> + .height = 185,
> + },
> + .delay = {
> + .enable = 200,
> + .unprepare = 200,
> + .disable = 400,
> + },
> + .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
> + .bus_flags = DRM_BUS_FLAG_DE_HIGH,
> + .connector_type = DRM_MODE_CONNECTOR_LVDS,
> +};
> +
> static const struct display_timing innolux_g156hce_l01_timings = {
> .pixelclock = { 120000000, 141860000, 150000000 },
> .hactive = { 1920, 1920, 1920 },
> @@ -4596,6 +4614,9 @@ static const struct of_device_id platform_of_match[] = {
> }, {
> .compatible = "innolux,g121x1-l03",
> .data = &innolux_g121x1_l03,
> + }, {
> + .compatible = "innolux,g121xce-l01",
> + .data = &innolux_g121xce_l01,
> }, {
> .compatible = "innolux,g156hce-l01",
> .data = &innolux_g156hce_l01,
> --
> 2.43.0
>
^ permalink raw reply
* Re: [PATCH] dt-bindings: timer: renesas,tmu: Make interrupt-names required
From: Krzysztof Kozlowski @ 2024-03-29 17:42 UTC (permalink / raw)
To: Geert Uytterhoeven, Daniel Lezcano, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Laurent Pinchart
Cc: linux-renesas-soc, devicetree, linux-kernel
In-Reply-To: <137c184267faacdc3024f0b88e53889571165a84.1711715780.git.geert+renesas@glider.be>
On 29/03/2024 13:37, Geert Uytterhoeven wrote:
> Now all in-tree users have been updated with interrupt-names properties
> according to commit 0076a37a426b6c85 ("dt-bindings: timer: renesas,tmu:
> Document input capture interrupt"), make interrupt-names required.
Would be nice to see here *why* they should be required, e.g. "Linux
driver needs them since commit foobar").
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> Documentation/devicetree/bindings/timer/renesas,tmu.yaml | 1 +
> 1 file changed, 1 insertion(+)
Anyway:
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 06/10] dt-bindings: iio: dac: add bindings doc for AXI DAC driver
From: David Lechner @ 2024-03-29 18:46 UTC (permalink / raw)
To: nuno.sa
Cc: linux-iio, devicetree, Dragos Bogdan, Jonathan Cameron,
Lars-Peter Clausen, Michael Hennerich, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Olivier Moysan
In-Reply-To: <20240328-iio-backend-axi-dac-v1-6-afc808b3fde3@analog.com>
On Thu, Mar 28, 2024 at 8:22 AM Nuno Sa via B4 Relay
<devnull+nuno.sa.analog.com@kernel.org> wrote:
>
> From: Nuno Sa <nuno.sa@analog.com>
>
> This adds the bindings documentation for the AXI DAC driver.
>
> Signed-off-by: Nuno Sa <nuno.sa@analog.com>
> ---
> .../devicetree/bindings/iio/dac/adi,axi-dac.yaml | 62 ++++++++++++++++++++++
> MAINTAINERS | 7 +++
> 2 files changed, 69 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml
> new file mode 100644
> index 000000000000..1018fd274f04
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml
> @@ -0,0 +1,62 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iio/dac/adi,axi-dac.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Analog Devices AXI DAC IP core
> +
> +maintainers:
> + - Nuno Sa <nuno.sa@analog.com>
> +
> +description: |
> + Analog Devices Generic AXI DAC IP core for interfacing a DAC device
> + with a high speed serial (JESD204B/C) or source synchronous parallel
> + interface (LVDS/CMOS).
> + Usually, some other interface type (i.e SPI) is used as a control
> + interface for the actual DAC, while this IP core will interface
> + to the data-lines of the DAC and handle the streaming of data into
> + memory via DMA.
Isn't it the other way around for DAC, from memory to hardware?
^ permalink raw reply
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