* [PATCH v3 5/5] riscv: dts: spacemit: Add PDMA controller node for K3 SoC
From: Troy Mitchell @ 2026-03-31 8:27 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Guodong Xu, Michael Turquette,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti
Cc: dmaengine, devicetree, linux-riscv, spacemit, linux-kernel,
linux-clk, Troy Mitchell
In-Reply-To: <20260331-k3-pdma-v3-0-a4e60dd8b4b3@linux.spacemit.com>
Add the Peripheral DMA (PDMA) controller node for the SpacemiT K3 SoC.
The PDMA controller provides general-purpose DMA capabilities for various
peripheral devices across the system to offload CPU data transfers.
Unlike the previous K1 SoC, where some DMA masters had memory addressing
limitations (e.g. restricted to the 0-4GB space) requiring a dedicated dma-bus
with dma-ranges to restrict memory allocations, the K3 DMA masters have
full memory addressing capabilities. Therefore, the PDMA node is now
instantiated directly under the main soc bus.
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
---
arch/riscv/boot/dts/spacemit/k3.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
index a3a8ceddabec..cd321975fc18 100644
--- a/arch/riscv/boot/dts/spacemit/k3.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
@@ -438,6 +438,17 @@ soc: soc {
dma-noncoherent;
ranges;
+ pdma: dma-controller@d4000000 {
+ compatible = "spacemit,k3-pdma";
+ reg = <0x0 0xd4000000 0x0 0x4000>;
+ clocks = <&syscon_apmu CLK_APMU_DMA>;
+ resets = <&syscon_apmu RESET_APMU_DMA>;
+ interrupts = <72 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <16>;
+ #dma-cells = <1>;
+ status = "disabled";
+ };
+
syscon_apbc: system-controller@d4015000 {
compatible = "spacemit,k3-syscon-apbc";
reg = <0x0 0xd4015000 0x0 0x1000>;
--
2.53.0
^ permalink raw reply related
* Re: [PATCH v5 1/2] thermal/qcom/lmh: support SDM670 and its CPU clusters
From: Konrad Dybcio @ 2026-03-31 8:30 UTC (permalink / raw)
To: Richard Acayan, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Amit Kucheria, Thara Gopinath,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
linux-arm-msm, devicetree, linux-pm
In-Reply-To: <20260330165237.101045-2-mailingradian@gmail.com>
On 3/30/26 6:52 PM, Richard Acayan wrote:
> The LMh driver was made for Qualcomm SoCs with clusters of 4 CPUs, but
> some SoCs divide the CPUs into different sizes of clusters. In SDM670,
> the first 6 CPUs are in the little cluster and the next 2 are in the big
> cluster. Define the clusters in the match data and define the different
> cluster configuration for SDM670.
>
> Currently, this tolerates linking to any CPU in a given cluster.
>
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
[...]
> + if (cpu_id < 0) {
> + dev_err(dev, "Wrong CPU id associated with LMh node\n");
> + return -EINVAL;
> + }
nit: try to use 'return dev_err_probe(dev, ret, "....") in the future
Konrad
^ permalink raw reply
* Re: [PATCH 2/7] cache: andes_llcache: refactor initialization and cache operations
From: Krzysztof Kozlowski @ 2026-03-31 8:31 UTC (permalink / raw)
To: Hui Min Mina Chou
Cc: pjw, palmer, aou, alex, geert+renesas, prabhakar.mahadev-lad.rj,
magnus.damm, ben717, robh, krzk+dt, conor+dt, jonathan.cameron,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc, tim609,
alex749, az70021
In-Reply-To: <20260330102724.1012470-3-minachou@andestech.com>
On Mon, Mar 30, 2026 at 06:27:19PM +0800, Hui Min Mina Chou wrote:
> return 0;
> @@ -186,16 +181,18 @@ static const struct of_device_id andes_cache_ids[] = {
> static int __init andes_cache_init(void)
> {
> struct resource res;
> - int ret;
> + int ret = 0;
>
> struct device_node *np __free(device_node) =
> of_find_matching_node(NULL, andes_cache_ids);
> - if (!of_device_is_available(np))
> - return -ENODEV;
> + if (!of_device_is_available(np)) {
> + ret = -ENODEV;
> + goto err_ret;
> + }
You just made antipattern. Conor mentioned briefly that he does not see
commit as doing right, but let's clarify: this is absolutely wrong.
It is explicitly discouraged by cleanup.h, but even without that remarks
one simple 'return' in one line is converted to three lines with goto
and you call it "simpler"?
No way this is simpler. You made code worse.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v4 1/9] dt-bindings: mfd: mt6397: Add MT6392 PMIC
From: Luca Leonardo Scorcia @ 2026-03-31 8:36 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-mediatek, Fabien Parent, Val Packett, Dmitry Torokhov,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sen Chu,
Sean Wang, Macpaul Lin, Lee Jones, Matthias Brugger,
AngeloGioacchino Del Regno, Linus Walleij, Liam Girdwood,
Mark Brown, Louis-Alexis Eyraud, Gary Bisson, Julien Massot,
Chen Zhong, linux-input, devicetree, linux-kernel, linux-pm,
linux-arm-kernel, linux-gpio
In-Reply-To: <20260331-flawless-bronze-lorikeet-59a6ff@quoll>
> > - required:
> > - - compatible
>
> Not really, this affects existing ABI and might make the child schema
> being applied. Basically regulators node can be anything now.
>
> This is definitely not a binding we want. The syntax for parent schema
> when listing only compatibles is requiring this compatible. You cannot
> have here whatever empty node.
Hi, it felt quite strange to me too, but that's what I thought you
meant with your previous suggestion [1].
To keep the required attribute I would be happy to reintroduce the
compatible here, in the regulator schema and the pmic dtsi.
Before I do that and resubmit, could you please help me understand
what you meant before?
Thank you!
[1] https://lists.infradead.org/pipermail/linux-mediatek/2026-March/105060.html
--
Luca Leonardo Scorcia
l.scorcia@gmail.com
^ permalink raw reply
* Re: [PATCH v5 2/2] arm64: dts: qcom: sdm670: add thermal zones and thermal devices
From: Konrad Dybcio @ 2026-03-31 8:36 UTC (permalink / raw)
To: Richard Acayan, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Amit Kucheria, Thara Gopinath,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
linux-arm-msm, devicetree, linux-pm
In-Reply-To: <20260330165237.101045-3-mailingradian@gmail.com>
On 3/30/26 6:52 PM, Richard Acayan wrote:
> Add thermal zones to safeguard from overheating to high temperatures,
> along with the thermal sensors (TSENS) and CPU frequency limits (LMh).
> The temperatures are very high, but should still be safeguard for
> devices that do not specify their own thermal zones.
>
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---
[...]
> + thermal-zones {
> + aoss0-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
You can drop all polling on TSENS thermal zones - we get interrupts
for when thresholds are crossed
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* RE: [PATCH v5 2/4] iio: adc: ad4691: add initial driver for AD4691 family
From: Sabau, Radu bogdan @ 2026-03-31 8:36 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Andy Shevchenko, Lars-Peter Clausen, Hennerich, Michael,
Jonathan Cameron, David Lechner, Sa, Nuno, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Uwe Kleine-König, Liam Girdwood, Mark Brown, Linus Walleij,
Bartosz Golaszewski, Philipp Zabel, Jonathan Corbet, Shuah Khan,
linux-iio@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-doc@vger.kernel.org
In-Reply-To: <CAHp75VcUCM8aeUpNaFEXnS+Cm08Mq5j+Qp2gYqWP9vCO+9CtQA@mail.gmail.com>
> -----Original Message-----
> From: Andy Shevchenko <andy.shevchenko@gmail.com>
> Sent: Monday, March 30, 2026 8:24 PM
> To: Sabau, Radu bogdan <Radu.Sabau@analog.com>
>
> ...
>
> > > > +#include <linux/bitfield.h>
> > > > +#include <linux/bitops.h>
> > > > +#include <linux/cleanup.h>
> > > > +#include <linux/delay.h>
> > > > +#include <linux/device.h>
> > >
> > > Hmm... Is it used? Or perhaps you need only
> > > dev_printk.h
> > > device/devres.h
> > > ?
>
> > I have checked this out and it seems device.h doesn't actually need
> > to be included anyway since spi.h directly includes device.h, and since
> > this is a SPI driver that's never going away, it's covered. Will drop it!
>
> No, this is the wrong justification. IWYU principle is about exact
> match between what is used and included in a file (module). spi.h is
> not dev_*() provider and may not be considered for that.
>
You are right, my justification was incorrect. Under IWYU, relying on
spi.h's transitive pull of device.h is not valid. However, I think device.h
is still needed in this case since struct device is used directly in the code
both as local variables and in the regmap callbacks. Also dev_err_probe()
is called directly and lives in device.h.
What's your take on this?
Best Regards,
Radu
^ permalink raw reply
* Re: [PATCH v4 4/5] arm64: dts: qcom: sdm670: add lpi pinctrl
From: Konrad Dybcio @ 2026-03-31 8:38 UTC (permalink / raw)
To: Richard Acayan, Bjorn Andersson, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Srinivas Kandagatla, linux-arm-msm, linux-gpio, devicetree
In-Reply-To: <20260330164707.87441-5-mailingradian@gmail.com>
On 3/30/26 6:47 PM, Richard Acayan wrote:
> The Snapdragon 670 has a separate TLMM for audio pins. Add the device
> node for it.
>
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* Re: [PATCH v4 5/5] arm64: dts: qcom: sdm670-google: add reserved lpi gpios
From: Konrad Dybcio @ 2026-03-31 8:38 UTC (permalink / raw)
To: Richard Acayan, Bjorn Andersson, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Srinivas Kandagatla, linux-arm-msm, linux-gpio, devicetree
In-Reply-To: <20260330164707.87441-6-mailingradian@gmail.com>
On 3/30/26 6:47 PM, Richard Acayan wrote:
> Some of the GPIOs are reserved for sensors since the ADSP also handles
> sensors on SDM670. Add the reserved GPIOs for the LPI pin controller.
>
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
Technically this'd be best squashed with patch 4, as without this one
applied your phone stops booting, but it's up to you
Konrad
^ permalink raw reply
* Re: [PATCH 1/4] dt-bindings: display: waveshare,dsp2dpi: describe DSI2LVDS setup
From: Krzysztof Kozlowski @ 2026-03-31 8:40 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Neil Armstrong, Jessica Zhang, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Thierry Reding, Sam Ravnborg,
Joseph Guo, Marek Vasut, Andrzej Hajda, Robert Foss,
Laurent Pinchart, Jonas Karlman, Jernej Skrabec, dri-devel,
devicetree, linux-kernel
In-Reply-To: <20260330-ws-lcd-v1-1-309834a435c0@oss.qualcomm.com>
On Mon, Mar 30, 2026 at 04:25:50PM +0300, Dmitry Baryshkov wrote:
> Several the Waveshare DSI LCD panel kits use DSI2LVDS ICN6202 bridge
If you know the hardware bridge used, should not it be the front
compatible (with waveshare,dsi2lvds fallback)? Or even alone? Can the
waveshare kits come with different bridges? I guess yes, they could.
> together with the LVDS panels. Define new compatible for the on-kit
> bridge setup (it is not defailed and it uses Waveshare prefix since the
typo: detailed
> rest of the integration details are not known).
>
Please also update at least description:
"...converts DSI to DPI or LVDS."
or similar.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 3/4] dt-bindings: display: panel: add Waveshare LCD panels
From: Krzysztof Kozlowski @ 2026-03-31 8:40 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Neil Armstrong, Jessica Zhang, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Thierry Reding, Sam Ravnborg,
Joseph Guo, Marek Vasut, Andrzej Hajda, Robert Foss,
Laurent Pinchart, Jonas Karlman, Jernej Skrabec, dri-devel,
devicetree, linux-kernel
In-Reply-To: <20260330-ws-lcd-v1-3-309834a435c0@oss.qualcomm.com>
On Mon, Mar 30, 2026 at 04:25:52PM +0300, Dmitry Baryshkov wrote:
> Waveshare has a family of LVDS / DPI panels bundled with the DSI2DPI or
> DSI2LVDS bridge. The bridge and the rest of the logic are covered by the
> waveshare,dsi2dpi compatible. The bindings already include several
> entries for the panels from this series (waveshare,13.3inch-panel,
> waveshare,7.0inch-c-panel). Define compatible strings for the rest of
> the panels from that series.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> .../bindings/display/panel/panel-simple.yaml | 28 ++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Hawi SoC
From: Krzysztof Kozlowski @ 2026-03-31 8:42 UTC (permalink / raw)
To: Vivek Aknurwar
Cc: Georgi Djakov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-msm, linux-pm, devicetree, linux-kernel, Mike Tipton
In-Reply-To: <20260330-icc-hawi-v1-1-4b54a9e7d38c@oss.qualcomm.com>
On Mon, Mar 30, 2026 at 05:40:00PM -0700, Vivek Aknurwar wrote:
> Document the RPMh Network-On-Chip Interconnect of the Hawi platform.
Test your patches before you send, not after. I am not reviewing this.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 2/2] interconnect: qcom: add Hawi interconnect provider driver
From: Krzysztof Kozlowski @ 2026-03-31 8:45 UTC (permalink / raw)
To: Vivek Aknurwar
Cc: Georgi Djakov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-msm, linux-pm, devicetree, linux-kernel, Mike Tipton
In-Reply-To: <20260330-icc-hawi-v1-2-4b54a9e7d38c@oss.qualcomm.com>
On Mon, Mar 30, 2026 at 05:40:01PM -0700, Vivek Aknurwar wrote:
> Add driver for the Qualcomm interconnect buses found in Hawi
> based platforms. The topology consists of several NoCs that are
> controlled by a remote processor that collects the aggregated
> bandwidth for each master-slave pairs.
>
> Signed-off-by: Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com>
> ---
> drivers/interconnect/qcom/Kconfig | 9 +
> drivers/interconnect/qcom/Makefile | 2 +
> drivers/interconnect/qcom/hawi.c | 2021 ++++++++++++++++++++++++++++++++++++
Can you finally stop sending code based on downstream?
You just made same mistakes I have been fixing for more than 3 years
now.
NAK
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH v5 0/6] Enable new features for flipkart-rimob
From: Cristian Cozzolino via B4 Relay @ 2026-03-31 9:47 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: dri-devel, devicetree, linux-kernel, linux-arm-msm,
~postmarketos/upstreaming, phone-devel, Cristian Cozzolino,
Krzysztof Kozlowski, Dmitry Baryshkov, Konrad Dybcio
This series enables a set of miscellaneous features for Billion Capture+
(a handset using the MSM8953 SoC released in 2017):
- Panel and GPU
- Touchscreen
- WiFi + Bluetooth
- Hall sensor
Patches 1 and 2 provide a driver for Novatek NT35532 and its corresponding
devicetree bindings, required for enabling panel in DTS. The remaining
patches are all DTS changes, aimed to enable the features listed above.
To: Neil Armstrong <neil.armstrong@linaro.org>
To: Jessica Zhang <jesszhan0024@gmail.com>
To: David Airlie <airlied@gmail.com>
To: Simona Vetter <simona@ffwll.ch>
To: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
To: Maxime Ripard <mripard@kernel.org>
To: Thomas Zimmermann <tzimmermann@suse.de>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Bjorn Andersson <andersson@kernel.org>
To: Konrad Dybcio <konradybcio@kernel.org>
Cc: dri-devel@lists.freedesktop.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-msm@vger.kernel.org
Cc: ~postmarketos/upstreaming@lists.sr.ht
Cc: phone-devel@vger.kernel.org
Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com>
---
Changes in v5:
- Based on dts-coding-style.html ("Nodes without unit addresses shall be
ordered alpha-numerically by the node name. For a few node types, they
can be ordered by the main property, e.g. pin configuration states
ordered by value of “pins” property."), sort pinctrl states by GPIO
index (Konrad);
- Pick up tags;
- Link to v4: https://lore.kernel.org/r/20260327-rimob-new-features-v4-0-06edff9c4509@protonmail.com
Changes in v4:
- (patch 1/6): added a new compatible (since it's not possible to
identify panel vendor/id), matching user of this device and leaving
novatek,nt35532 as fallback (Dmitry);
- (patch 2/6):
- according to bindings changes, make panel driver handling multiple
panels paired with NT35532 and use specific compatible/data;
- due to changes applied to panel code, remove tag received previously
by Dmitry.
- (patch 3/6):
- use a specific panel compatible, according to bindings changes;
- remove 'output-high' property from panel pinctrl, since panel is not
reset.
- Link to v3: https://lore.kernel.org/r/20260321-rimob-new-features-v3-0-d4b8ee867de7@protonmail.com
Changes in v3:
- (patch 1/6): removed avdd, avee and vci supplies from 'required' properties;
- (patch 2/6):
- removed "select VIDEOMODE_HELPERS" from nt35532 Kconfig entry, since
its functions are not used (but this option is enabled and its code
compiled anyway) by nt35532 panel driver;
- pick up tags (Dmitry).
- (patch 3/6): replaced a506_zap.mdt with a506_zap.mbn firmware name
in gpu_zap_shader (Dmitry);
- (patch 5/6): pick up tags (Konrad);
- (patch 6/6): pick up tags (Konrad);
- Link to v2: https://lore.kernel.org/r/20260318-rimob-new-features-v2-0-c1bf8917449e@protonmail.com
Changes in v2:
- (patch 1/6): define power supplies in the bindings as per datasheet
and update example;
- (patch 2/6): add blank lines where required between mipi dsi write
sequences in nt35532_on() function and make use of names for mipi dcs
commands, instead of hex numbers, to improve readibility (Dmitry);
- (patch 3/6): move pinctrl lines ibto panel node and get rid of
sleep/reset state, since panel just uses one pinctrl state for
default/sleep (Dmitry). Also, update power supplies according to
bindings;
- (patch 4/6): pick up tags (Konrad,Dmitry);
- (patch 6/6): squash hall sensor node into gpio-keys (Dmitry);
- Link to v1: https://lore.kernel.org/r/20260308-rimob-new-features-v1-0-aa2c330572c0@protonmail.com
---
Cristian Cozzolino (6):
dt-bindings: display: panel: Add Novatek NT35532 LCD DSI
drm/panel: Add driver for Novatek NT35532
arm64: dts: qcom: msm8953-flipkart-rimob: Enable display and GPU
arm64: dts: qcom: msm8953-flipkart-rimob: Enable WiFi/Bluetooth
arm64: dts: qcom: msm8953-flipkart-rimob: Enable touchscreen
arm64: dts: qcom: msm8953-flipkart-rimob: Enable Hall sensor
.../bindings/display/panel/novatek,nt35532.yaml | 80 +++
MAINTAINERS | 6 +
.../arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts | 138 +++-
drivers/gpu/drm/panel/Kconfig | 10 +
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/panel/panel-novatek-nt35532.c | 796 +++++++++++++++++++++
6 files changed, 1030 insertions(+), 1 deletion(-)
---
base-commit: cf7c3c02fdd0dfccf4d6611714273dcb538af2cb
change-id: 20260303-rimob-new-features-037944b3a620
Best regards,
--
Cristian Cozzolino <cristian_ci@protonmail.com>
^ permalink raw reply
* [PATCH v5 1/6] dt-bindings: display: panel: Add Novatek NT35532 LCD DSI
From: Cristian Cozzolino via B4 Relay @ 2026-03-31 9:47 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: dri-devel, devicetree, linux-kernel, linux-arm-msm,
~postmarketos/upstreaming, phone-devel, Cristian Cozzolino,
Krzysztof Kozlowski
In-Reply-To: <20260331-rimob-new-features-v5-0-5fcf42a29c12@protonmail.com>
From: Cristian Cozzolino <cristian_ci@protonmail.com>
Document Novatek NT35532-based DSI display panel.
Since it's not possible to identify panel vendor nor id, add a suitable
compatible (matching the device's user, which makes use of this DDIC)
and set "novatek,nt35532" as fallback.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com>
---
.../bindings/display/panel/novatek,nt35532.yaml | 80 ++++++++++++++++++++++
MAINTAINERS | 5 ++
2 files changed, 85 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/panel/novatek,nt35532.yaml b/Documentation/devicetree/bindings/display/panel/novatek,nt35532.yaml
new file mode 100644
index 000000000000..ff6fdad7febf
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/novatek,nt35532.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/novatek,nt35532.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Novatek NT35532-based DSI display panels
+
+maintainers:
+ - Cristian Cozzolino <cristian_ci@protonmail.com>
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - flipkart,rimob-panel-nt35532-cs
+ - const: novatek,nt35532
+
+ reg:
+ maxItems: 1
+
+ backlight: true
+ reset-gpios: true
+
+ avdd-supply:
+ description: positive boost supply regulator
+
+ avee-supply:
+ description: negative boost supply regulator
+
+ vci-supply:
+ description: regulator that supplies the analog voltage
+
+ vddam-supply:
+ description: power supply for MIPI interface
+
+ vddi-supply:
+ description: regulator that supplies the I/O voltage
+
+ port: true
+
+required:
+ - compatible
+ - reg
+ - reset-gpios
+ - vddi-supply
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel@0 {
+ compatible = "flipkart,rimob-panel-nt35532-cs", "novatek,nt35532";
+ reg = <0>;
+
+ backlight = <&pmi8950_wled>;
+ reset-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
+ avdd-supply = <&lab>;
+ avee-supply = <&ibb>;
+ vci-supply = <&pm8953_l17>;
+ vddi-supply = <&pm8953_l6>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ };
+ };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index ef978bfca514..8617d830b1d2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8175,6 +8175,11 @@ T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: Documentation/devicetree/bindings/display/panel/novatek,nt35510.yaml
F: drivers/gpu/drm/panel/panel-novatek-nt35510.c
+DRM DRIVER FOR NOVATEK NT35532 PANELS
+M: Cristian Cozzolino <cristian_ci@protonmail.com>
+S: Maintained
+F: Documentation/devicetree/bindings/display/panel/novatek,nt35532.yaml
+
DRM DRIVER FOR NOVATEK NT35560 PANELS
M: Linus Walleij <linusw@kernel.org>
S: Maintained
--
2.53.0
^ permalink raw reply related
* [PATCH v5 4/6] arm64: dts: qcom: msm8953-flipkart-rimob: Enable WiFi/Bluetooth
From: Cristian Cozzolino via B4 Relay @ 2026-03-31 9:47 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: dri-devel, devicetree, linux-kernel, linux-arm-msm,
~postmarketos/upstreaming, phone-devel, Cristian Cozzolino,
Konrad Dybcio, Dmitry Baryshkov
In-Reply-To: <20260331-rimob-new-features-v5-0-5fcf42a29c12@protonmail.com>
From: Cristian Cozzolino <cristian_ci@protonmail.com>
Configure and enable the WCNSS which provides WiFi and Bluetooth on this
device using the WCN3660B chip.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com>
---
arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts
index 5a9d71d1e466..db5c9f04bf1a 100644
--- a/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts
+++ b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts
@@ -326,3 +326,18 @@ &usb3 {
&usb3_dwc3 {
dr_mode = "peripheral";
};
+
+&wcnss {
+ vddpx-supply = <&pm8953_l5>;
+
+ status = "okay";
+};
+
+&wcnss_iris {
+ compatible = "qcom,wcn3660b";
+
+ vddxo-supply = <&pm8953_l7>;
+ vddrfa-supply = <&pm8953_l19>;
+ vddpa-supply = <&pm8953_l9>;
+ vdddig-supply = <&pm8953_l5>;
+};
--
2.53.0
^ permalink raw reply related
* [PATCH v5 3/6] arm64: dts: qcom: msm8953-flipkart-rimob: Enable display and GPU
From: Cristian Cozzolino via B4 Relay @ 2026-03-31 9:47 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: dri-devel, devicetree, linux-kernel, linux-arm-msm,
~postmarketos/upstreaming, phone-devel, Cristian Cozzolino,
Konrad Dybcio, Dmitry Baryshkov
In-Reply-To: <20260331-rimob-new-features-v5-0-5fcf42a29c12@protonmail.com>
From: Cristian Cozzolino <cristian_ci@protonmail.com>
Add the description for the display panel found on this phone.
And with this done we can also enable the GPU and set the zap shader
firmware path.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com>
---
.../arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts | 73 ++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts
index ef4faf763132..5a9d71d1e466 100644
--- a/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts
+++ b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts
@@ -78,6 +78,13 @@ vph_pwr: vph-pwr-regulator {
};
};
+&gpu {
+ status = "okay";
+};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/msm8953/flipkart/rimob/a506_zap.mbn";
+};
&hsusb_phy {
vdd-supply = <&pm8953_l3>;
@@ -87,11 +94,70 @@ &hsusb_phy {
status = "okay";
};
+&ibb {
+ qcom,discharge-resistor-kohms = <32>;
+};
+
+&lab {
+ qcom,soft-start-us = <800>;
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&pm8953_s3>;
+ vddio-supply = <&pm8953_l6>;
+
+ status = "okay";
+
+ panel: panel@0 {
+ compatible = "flipkart,rimob-panel-nt35532-cs";
+ reg = <0>;
+
+ backlight = <&pmi8950_wled>;
+ reset-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
+ avdd-supply = <&lab>;
+ avee-supply = <&ibb>;
+ vci-supply = <&pm8953_l17>;
+ vddi-supply = <&pm8953_l6>;
+
+ pinctrl-0 = <&panel_default>;
+ pinctrl-names = "default";
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+ };
+};
+
+&mdss_dsi0_out {
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&panel_in>;
+};
+
+&mdss_dsi0_phy {
+ vcca-supply = <&pm8953_l3>;
+
+ status = "okay";
+};
+
&pm8953_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
+&pmi8950_wled {
+ qcom,current-limit-microamp = <10000>;
+ qcom,num-strings = <3>;
+ qcom,ovp-millivolt = <29500>;
+
+ status = "okay";
+};
+
&rpm_requests {
regulators {
compatible = "qcom,rpm-pm8953-regulators";
@@ -238,6 +304,13 @@ &sdhc_2 {
&tlmm {
gpio-reserved-ranges = <0 4>, <135 4>;
+ panel_default: panel-default-state {
+ pins = "gpio61";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
gpio_key_default: gpio-key-default-state {
pins = "gpio85";
function = "gpio";
--
2.53.0
^ permalink raw reply related
* [PATCH v5 2/6] drm/panel: Add driver for Novatek NT35532
From: Cristian Cozzolino via B4 Relay @ 2026-03-31 9:47 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: dri-devel, devicetree, linux-kernel, linux-arm-msm,
~postmarketos/upstreaming, phone-devel, Cristian Cozzolino,
Dmitry Baryshkov
In-Reply-To: <20260331-rimob-new-features-v5-0-5fcf42a29c12@protonmail.com>
From: Cristian Cozzolino <cristian_ci@protonmail.com>
Add support for Novatek NT35532-based 1080p video mode DSI panel.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com>
---
MAINTAINERS | 1 +
drivers/gpu/drm/panel/Kconfig | 10 +
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/panel/panel-novatek-nt35532.c | 796 ++++++++++++++++++++++++++
4 files changed, 808 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8617d830b1d2..3c4eef7905d1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8179,6 +8179,7 @@ DRM DRIVER FOR NOVATEK NT35532 PANELS
M: Cristian Cozzolino <cristian_ci@protonmail.com>
S: Maintained
F: Documentation/devicetree/bindings/display/panel/novatek,nt35532.yaml
+F: drivers/gpu/drm/panel/panel-novatek-nt35532.c
DRM DRIVER FOR NOVATEK NT35560 PANELS
M: Linus Walleij <linusw@kernel.org>
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index d6863b28ddc5..386fb6f1ff50 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -549,6 +549,16 @@ config DRM_PANEL_NOVATEK_NT35510
around the Novatek NT35510 display controller, such as some
Hydis panels.
+config DRM_PANEL_NOVATEK_NT35532
+ tristate "Novatek NT35532-based DSI video mode panel"
+ depends on OF
+ depends on DRM_MIPI_DSI
+ depends on BACKLIGHT_CLASS_DEVICE
+ select DRM_KMS_HELPER
+ help
+ Say Y or M here if you want to enable support for Novatek
+ NT35532-based 1080p video mode DSI panels.
+
config DRM_PANEL_NOVATEK_NT35560
tristate "Novatek NT35560 DSI command mode panel"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index a4291dc3905b..7caf60dd3f57 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_DRM_PANEL_NEC_NL8048HL11) += panel-nec-nl8048hl11.o
obj-$(CONFIG_DRM_PANEL_NEWVISION_NV3051D) += panel-newvision-nv3051d.o
obj-$(CONFIG_DRM_PANEL_NEWVISION_NV3052C) += panel-newvision-nv3052c.o
obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35510) += panel-novatek-nt35510.o
+obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35532) += panel-novatek-nt35532.o
obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35560) += panel-novatek-nt35560.o
obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35950) += panel-novatek-nt35950.o
obj-$(CONFIG_DRM_PANEL_NOVATEK_NT36523) += panel-novatek-nt36523.o
diff --git a/drivers/gpu/drm/panel/panel-novatek-nt35532.c b/drivers/gpu/drm/panel/panel-novatek-nt35532.c
new file mode 100644
index 000000000000..184f61bca7ca
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-novatek-nt35532.c
@@ -0,0 +1,796 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Generated with linux-mdss-dsi-panel-driver-generator from vendor device tree.
+ * Copyright (c) 2026 Cristian Cozzolino <cristian_ci@protonmail.com>
+ */
+
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/property.h>
+#include <linux/regulator/consumer.h>
+
+#include <video/mipi_display.h>
+
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_modes.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_probe_helper.h>
+
+struct novatek_nt35532 {
+ struct drm_panel panel;
+ struct mipi_dsi_device *dsi;
+ struct regulator_bulk_data *supplies;
+ struct gpio_desc *reset_gpio;
+ const struct nt35532_panel_desc *desc;
+};
+
+struct nt35532_panel_desc {
+ const struct drm_display_mode *mode;
+ int (*on)(struct novatek_nt35532 *ctx);
+};
+
+static const struct regulator_bulk_data nt35532_supplies[] = {
+ { .supply = "vci" },
+ { .supply = "vddi" },
+ { .supply = "avee" },
+ { .supply = "avdd" },
+};
+
+static inline struct novatek_nt35532 *to_novatek_nt35532(struct drm_panel *panel)
+{
+ return container_of_const(panel, struct novatek_nt35532, panel);
+}
+
+static void nt35532_reset(struct novatek_nt35532 *ctx)
+{
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ usleep_range(10000, 11000);
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ usleep_range(5000, 6000);
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ usleep_range(10000, 11000);
+}
+
+static int rimob_panel_on(struct novatek_nt35532 *ctx)
+{
+ struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
+
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6e, 0x80);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x68, 0x13);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x05);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd7, 0x31);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd8, 0x7e);
+
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x01, 0x55);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x04, 0x0c);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x05, 0x3a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x06, 0x50);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x07, 0xd0);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0a, 0x0f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0c, 0x06);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0d, 0x6b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0e, 0x6b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0f, 0x70);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x10, 0x63);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x11, 0x3c);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x12, 0x5c);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x15, 0x60);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x16, 0x15);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x17, 0x15);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5b, 0xca);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5c, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5d, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5f, 0x1b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x60, 0xd5);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x61, 0xf0);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6c, 0xab);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6d, 0x44);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6e, 0x80);
+
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x05);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x00, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x01, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x02, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x03, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x04, 0x38);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x05, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x06, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x07, 0x19);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x08, 0x1b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x09, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0a, 0x1d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0b, 0x17);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0c, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0d, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0e, 0x08);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0f, 0x0c);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x10, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x11, 0x10);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x12, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x13, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x14, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x15, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x16, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x17, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x18, 0x38);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x19, 0x18);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x1a, 0x1a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x1b, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x1c, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x1d, 0x1c);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x1e, 0x16);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x1f, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x20, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x21, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x22, 0x06);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x23, 0x0a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x24, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x25, 0x0e);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x26, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x27, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x54, 0x08);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x55, 0x07);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x56, 0x1a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x58, 0x19);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x59, 0x36);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5a, 0x1b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5b, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5c, 0x32);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5e, 0x27);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5f, 0x28);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x60, 0x2b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x61, 0x2c);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x62, 0x18);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x63, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x64, 0x32);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x65, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x66, 0x44);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x67, 0x11);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x68, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x69, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6a, 0x06);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6b, 0x22);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6c, 0x08);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6d, 0x08);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x78, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x79, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7e, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7f, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x80, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x81, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8d, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8e, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8f, 0xc0);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x90, 0x73);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x91, 0x10);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x92, 0x09);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x96, 0x11);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x97, 0x14);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x98, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x99, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9a, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9b, 0x61);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9c, 0x15);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9d, 0x30);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9f, 0x0f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa2, 0xb0);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa7, 0x0a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa9, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xaa, 0x70);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xab, 0xda);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xac, 0xff);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xae, 0xf4);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xaf, 0x40);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x7f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb1, 0x16);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb2, 0x53);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb3, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb4, 0x2a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb5, 0x3a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb6, 0xf0);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbc, 0x85);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbd, 0xf8);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbe, 0x3b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbf, 0x13);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc0, 0x77);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc1, 0x77);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc2, 0x77);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc3, 0x77);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc4, 0x77);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc5, 0x77);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc6, 0x77);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc7, 0x77);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc8, 0xaa);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc9, 0x2a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xca, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcb, 0xaa);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcc, 0x92);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcd, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xce, 0x18);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcf, 0x88);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd0, 0xaa);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd1, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd2, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd3, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd6, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xed, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xee, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xef, 0x70);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfa, 0x03);
+
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x75, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x76, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x77, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x78, 0x20);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x79, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7a, 0x49);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7b, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7c, 0x66);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7d, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7e, 0x7d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7f, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x80, 0x91);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x81, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x82, 0xa3);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x83, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x84, 0xb3);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x85, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x86, 0xc1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x87, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x88, 0xf1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x89, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8a, 0x18);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8b, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8c, 0x54);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8d, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8e, 0x85);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8f, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x90, 0xd1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x91, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x92, 0x0c);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x93, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x94, 0x0e);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x95, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x96, 0x43);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x97, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x98, 0x7d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x99, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9a, 0xa2);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9b, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9c, 0xd7);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9d, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9e, 0xf8);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9f, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa0, 0x2b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa2, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa3, 0x3a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa4, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa5, 0x4b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa6, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa7, 0x5d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa9, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xaa, 0x73);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xab, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xac, 0x8e);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xad, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xae, 0xae);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xaf, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0xc9);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb1, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb2, 0xcd);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb3, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb4, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb5, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb6, 0x20);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb7, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb8, 0x49);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb9, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xba, 0x66);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbb, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbc, 0x7d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbd, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbe, 0x91);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbf, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc0, 0xa3);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc1, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc2, 0xb3);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc3, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc4, 0xc1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc5, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc6, 0xf1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc7, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc8, 0x18);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc9, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xca, 0x54);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcb, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcc, 0x85);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcd, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xce, 0xd1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcf, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd0, 0x0c);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd1, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd2, 0x0e);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd3, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd4, 0x43);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd5, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd6, 0x7d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd7, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd8, 0xa2);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd9, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xda, 0xd7);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdb, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdc, 0xf8);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdd, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xde, 0x2b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdf, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe0, 0x3a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe1, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe2, 0x4b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe3, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe4, 0x5d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe5, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe6, 0x73);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe7, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe8, 0x8e);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe9, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xea, 0xae);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xeb, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xec, 0xc9);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xed, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xee, 0xcd);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xef, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf1, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf2, 0x20);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf3, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf4, 0x49);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf5, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf6, 0x66);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf7, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf8, 0x7d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf9, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfa, 0x91);
+
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x00, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x01, 0xa3);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x02, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x03, 0xb3);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x04, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x05, 0xc1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x06, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x07, 0xf1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x08, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x09, 0x18);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0a, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0b, 0x54);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0c, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0d, 0x85);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0e, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0f, 0xd1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x10, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x11, 0x0c);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x12, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x13, 0x0e);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x14, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x15, 0x43);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x16, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x17, 0x7d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x18, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x19, 0xa2);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x1a, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x1b, 0xd7);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x1c, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x1d, 0xf8);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x1e, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x1f, 0x2b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x20, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x21, 0x3a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x22, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x23, 0x4b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x24, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x25, 0x5d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x26, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x27, 0x73);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x28, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x29, 0x8e);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x2a, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x2b, 0xae);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x2d, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x2f, 0xc9);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x30, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x31, 0xcd);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x32, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x33, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x34, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x35, 0x20);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x36, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x37, 0x49);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x38, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x39, 0x66);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x3a, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x3b, 0x7d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x3d, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x3f, 0x91);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x40, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x41, 0xa3);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x42, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x43, 0xb3);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x44, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x45, 0xc1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x46, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x47, 0xf1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x48, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x49, 0x18);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x4a, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x4b, 0x54);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x4c, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x4d, 0x85);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x4e, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x4f, 0xd1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x50, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x51, 0x0c);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x52, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x53, 0x0e);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x54, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x55, 0x43);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x56, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x58, 0x7d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x59, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5a, 0xa2);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5b, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5c, 0xd7);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5d, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5e, 0xf8);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5f, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x60, 0x2b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x61, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x62, 0x3a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x63, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x64, 0x4b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x65, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x66, 0x5d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x67, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x68, 0x73);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x69, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6a, 0x8e);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6b, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6c, 0xae);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6d, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6e, 0xc9);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6f, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x70, 0xcd);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x71, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x72, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x73, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x74, 0x20);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x75, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x76, 0x49);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x77, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x78, 0x66);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x79, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7a, 0x7d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7b, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7c, 0x91);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7d, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7e, 0xa3);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7f, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x80, 0xb3);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x81, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x82, 0xc1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x83, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x84, 0xf1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x85, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x86, 0x18);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x87, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x88, 0x54);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x89, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8a, 0x85);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8b, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8c, 0xd1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8d, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8e, 0x0c);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8f, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x90, 0x0e);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x91, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x92, 0x43);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x93, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x94, 0x7d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x95, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x96, 0xa2);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x97, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x98, 0xd7);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x99, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9a, 0xf8);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9b, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9c, 0x2b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9d, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9e, 0x3a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9f, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa0, 0x4b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa2, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa3, 0x5d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa4, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa5, 0x73);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa6, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa7, 0x8e);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa9, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xaa, 0xae);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xab, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xac, 0xc9);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xad, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xae, 0xcd);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xaf, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb1, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb2, 0x20);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb3, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb4, 0x49);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb5, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb6, 0x66);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb7, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb8, 0x7d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb9, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xba, 0x91);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbb, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbc, 0xa3);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbd, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbe, 0xb3);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbf, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc0, 0xc1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc1, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc2, 0xf1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc3, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc4, 0x18);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc5, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc6, 0x54);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc7, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc8, 0x85);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc9, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xca, 0xd1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcb, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcc, 0x0c);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcd, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xce, 0x0e);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcf, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd0, 0x43);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd1, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd2, 0x7d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd3, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd4, 0xa2);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd5, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd6, 0xd7);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd7, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd8, 0xf8);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd9, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xda, 0x2b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdb, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdc, 0x3a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdd, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xde, 0x4b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdf, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe0, 0x5d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe1, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe2, 0x73);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe3, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe4, 0x8e);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe5, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe6, 0xae);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe7, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe8, 0xc9);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe9, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xea, 0xcd);
+
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0xee);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x02, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x40, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x02, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x41, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x02, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x42, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xba, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x35, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x36, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd3, 0x10);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd4, 0x0f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd5, 0x0f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd6, 0x48);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd7, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd9, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, MIPI_DCS_EXIT_SLEEP_MODE, 0x00);
+ mipi_dsi_msleep(&dsi_ctx, 120);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_DISPLAY_ON, 0x00);
+ mipi_dsi_msleep(&dsi_ctx, 50);
+
+ return dsi_ctx.accum_err;
+}
+
+static int nt35532_off(struct novatek_nt35532 *ctx)
+{
+ struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
+
+ mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
+ mipi_dsi_msleep(&dsi_ctx, 50);
+ mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
+ mipi_dsi_msleep(&dsi_ctx, 120);
+
+ return dsi_ctx.accum_err;
+}
+
+static int nt35532_prepare(struct drm_panel *panel)
+{
+ struct novatek_nt35532 *ctx = to_novatek_nt35532(panel);
+ struct device *dev = &ctx->dsi->dev;
+ int ret;
+
+ ret = regulator_bulk_enable(ARRAY_SIZE(nt35532_supplies), ctx->supplies);
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable regulators: %d\n", ret);
+ return ret;
+ }
+
+ nt35532_reset(ctx);
+
+ ret = ctx->desc->on(ctx);
+ if (ret < 0) {
+ dev_err(dev, "Failed to initialize panel: %d\n", ret);
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ regulator_bulk_disable(ARRAY_SIZE(nt35532_supplies), ctx->supplies);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int nt35532_unprepare(struct drm_panel *panel)
+{
+ struct novatek_nt35532 *ctx = to_novatek_nt35532(panel);
+ struct device *dev = &ctx->dsi->dev;
+ int ret;
+
+ ret = nt35532_off(ctx);
+ if (ret < 0)
+ dev_err(dev, "Failed to un-initialize panel: %d\n", ret);
+
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ regulator_bulk_disable(ARRAY_SIZE(nt35532_supplies), ctx->supplies);
+
+ return 0;
+}
+
+static const struct drm_display_mode rimob_panel_mode = {
+ .clock = (1080 + 100 + 6 + 94) * (1920 + 15 + 6 + 10) * 60 / 1000,
+ .hdisplay = 1080,
+ .hsync_start = 1080 + 100,
+ .hsync_end = 1080 + 100 + 6,
+ .htotal = 1080 + 100 + 6 + 94,
+ .vdisplay = 1920,
+ .vsync_start = 1920 + 15,
+ .vsync_end = 1920 + 15 + 6,
+ .vtotal = 1920 + 15 + 6 + 10,
+ .width_mm = 68,
+ .height_mm = 121,
+ .type = DRM_MODE_TYPE_DRIVER,
+};
+
+static int nt35532_get_modes(struct drm_panel *panel,
+ struct drm_connector *connector)
+{
+ struct novatek_nt35532 *ctx = to_novatek_nt35532(panel);
+ const struct drm_display_mode *mode = ctx->desc->mode;
+
+ return drm_connector_helper_get_modes_fixed(connector, mode);
+}
+
+static const struct nt35532_panel_desc rimob_panel_desc = {
+ .mode = &rimob_panel_mode,
+ .on = rimob_panel_on,
+};
+
+static const struct drm_panel_funcs novatek_nt35532_panel_funcs = {
+ .prepare = nt35532_prepare,
+ .unprepare = nt35532_unprepare,
+ .get_modes = nt35532_get_modes,
+};
+
+static int nt35532_probe(struct mipi_dsi_device *dsi)
+{
+ struct device *dev = &dsi->dev;
+ struct novatek_nt35532 *ctx;
+ int ret;
+
+ ctx = devm_drm_panel_alloc(dev, struct novatek_nt35532, panel,
+ &novatek_nt35532_panel_funcs,
+ DRM_MODE_CONNECTOR_DSI);
+ if (IS_ERR(ctx))
+ return PTR_ERR(ctx);
+
+ ctx->desc = device_get_match_data(dev);
+
+ ret = devm_regulator_bulk_get_const(dev,
+ ARRAY_SIZE(nt35532_supplies),
+ nt35532_supplies,
+ &ctx->supplies);
+ if (ret < 0)
+ return ret;
+
+ ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
+ if (IS_ERR(ctx->reset_gpio))
+ return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio),
+ "Failed to get reset-gpios\n");
+
+ ctx->dsi = dsi;
+ mipi_dsi_set_drvdata(dsi, ctx);
+
+ dsi->lanes = 4;
+ dsi->format = MIPI_DSI_FMT_RGB888;
+ dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+ MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_LPM;
+
+ ctx->panel.prepare_prev_first = true;
+
+ ret = drm_panel_of_backlight(&ctx->panel);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to get backlight\n");
+
+ drm_panel_add(&ctx->panel);
+
+ ret = mipi_dsi_attach(dsi);
+ if (ret < 0) {
+ drm_panel_remove(&ctx->panel);
+ return dev_err_probe(dev, ret, "Failed to attach to DSI host\n");
+ }
+
+ return 0;
+}
+
+static void nt35532_remove(struct mipi_dsi_device *dsi)
+{
+ struct novatek_nt35532 *ctx = mipi_dsi_get_drvdata(dsi);
+ int ret;
+
+ ret = mipi_dsi_detach(dsi);
+ if (ret < 0)
+ dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret);
+
+ drm_panel_remove(&ctx->panel);
+}
+
+static const struct of_device_id nt35532_of_match[] = {
+ { .compatible = "flipkart,rimob-panel-nt35532-cs", .data = &rimob_panel_desc },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, nt35532_of_match);
+
+static struct mipi_dsi_driver nt35532_driver = {
+ .probe = nt35532_probe,
+ .remove = nt35532_remove,
+ .driver = {
+ .name = "panel-novatek-nt35532",
+ .of_match_table = nt35532_of_match,
+ },
+};
+module_mipi_dsi_driver(nt35532_driver);
+
+MODULE_DESCRIPTION("DRM driver for Novatek NT35532-based 1080p video mode DSI panel");
+MODULE_LICENSE("GPL");
--
2.53.0
^ permalink raw reply related
* [PATCH v5 5/6] arm64: dts: qcom: msm8953-flipkart-rimob: Enable touchscreen
From: Cristian Cozzolino via B4 Relay @ 2026-03-31 9:47 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: dri-devel, devicetree, linux-kernel, linux-arm-msm,
~postmarketos/upstreaming, phone-devel, Cristian Cozzolino,
Konrad Dybcio
In-Reply-To: <20260331-rimob-new-features-v5-0-5fcf42a29c12@protonmail.com>
From: Cristian Cozzolino <cristian_ci@protonmail.com>
This device uses a Goodix GT5688 touch controller, connected to i2c_3.
Add it to the device tree.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com>
---
.../arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts | 32 ++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts
index db5c9f04bf1a..060129c72264 100644
--- a/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts
+++ b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts
@@ -94,6 +94,31 @@ &hsusb_phy {
status = "okay";
};
+&i2c_3 {
+ status = "okay";
+
+ touchscreen@5d {
+ compatible = "goodix,gt5688";
+ reg = <0x5d>;
+
+ interrupts-extended = <&tlmm 65 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-0 = <&tsp_int_rst_default>;
+ pinctrl-names = "default";
+
+ irq-gpios = <&tlmm 65 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
+
+ VDDIO-supply = <&pm8953_l6>;
+ AVDD28-supply = <&pm8953_l10>;
+
+ touchscreen-size-x = <1080>;
+ touchscreen-size-y = <1920>;
+ touchscreen-inverted-x;
+ touchscreen-inverted-y;
+ };
+};
+
&ibb {
qcom,discharge-resistor-kohms = <32>;
};
@@ -311,6 +336,13 @@ panel_default: panel-default-state {
bias-disable;
};
+ tsp_int_rst_default: tsp-int-rst-default-state {
+ pins = "gpio64", "gpio65";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
gpio_key_default: gpio-key-default-state {
pins = "gpio85";
function = "gpio";
--
2.53.0
^ permalink raw reply related
* [PATCH v5 6/6] arm64: dts: qcom: msm8953-flipkart-rimob: Enable Hall sensor
From: Cristian Cozzolino via B4 Relay @ 2026-03-31 9:47 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: dri-devel, devicetree, linux-kernel, linux-arm-msm,
~postmarketos/upstreaming, phone-devel, Cristian Cozzolino,
Konrad Dybcio, Dmitry Baryshkov
In-Reply-To: <20260331-rimob-new-features-v5-0-5fcf42a29c12@protonmail.com>
From: Cristian Cozzolino <cristian_ci@protonmail.com>
Enable the Hall effect sensor (flip cover) for Billion Capture+.
The GPIO is mapped to SW_LID events as in other qcom devices.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com>
---
arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts
index 060129c72264..978820348fa5 100644
--- a/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts
+++ b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts
@@ -47,9 +47,18 @@ framebuffer@90001000 {
gpio-keys {
compatible = "gpio-keys";
- pinctrl-0 = <&gpio_key_default>;
+ pinctrl-0 = <&gpio_hall_sensor_default>, <&gpio_key_default>;
pinctrl-names = "default";
+ event-hall-sensor {
+ label = "Hall Effect Sensor";
+ gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ linux,can-disable;
+ wakeup-source;
+ };
+
key-volume-up {
label = "Volume Up";
gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
@@ -329,6 +338,13 @@ &sdhc_2 {
&tlmm {
gpio-reserved-ranges = <0 4>, <135 4>;
+ gpio_hall_sensor_default: gpio-hall-sensor-default-state {
+ pins = "gpio46";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
panel_default: panel-default-state {
pins = "gpio61";
function = "gpio";
--
2.53.0
^ permalink raw reply related
* Re: [PATCH 2/2] interconnect: qcom: add Hawi interconnect provider driver
From: Krzysztof Kozlowski @ 2026-03-31 8:48 UTC (permalink / raw)
To: Vivek Aknurwar
Cc: Georgi Djakov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-msm, linux-pm, devicetree, linux-kernel, Mike Tipton
In-Reply-To: <20260331-sly-centipede-of-opportunity-590509@quoll>
On 31/03/2026 10:45, Krzysztof Kozlowski wrote:
> On Mon, Mar 30, 2026 at 05:40:01PM -0700, Vivek Aknurwar wrote:
>> Add driver for the Qualcomm interconnect buses found in Hawi
>> based platforms. The topology consists of several NoCs that are
>> controlled by a remote processor that collects the aggregated
>> bandwidth for each master-slave pairs.
>>
>> Signed-off-by: Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com>
>> ---
>> drivers/interconnect/qcom/Kconfig | 9 +
>> drivers/interconnect/qcom/Makefile | 2 +
>> drivers/interconnect/qcom/hawi.c | 2021 ++++++++++++++++++++++++++++++++++++
>
> Can you finally stop sending code based on downstream?
>
> You just made same mistakes I have been fixing for more than 3 years
> now.
Oh, no, I was wrong - my grep pattern was incomplete. The code is
finally fixed!
Sorry for the noise.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v15 3/3] arm64: dts: qcom: talos-evk: Add support for QCS615 talos evk board
From: tessolveupstream @ 2026-03-31 8:49 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: andersson, konradybcio, robh, krzk+dt, conor+dt, linux-arm-msm,
devicetree, linux-kernel, Konrad Dybcio
In-Reply-To: <rco6vpc2cnn7y52hyuf3btt2mo7apv46romvi3onakc5axjuef@sbghvgoknspy>
On 02-03-2026 18:43, Dmitry Baryshkov wrote:
> On Mon, Mar 02, 2026 at 05:41:59PM +0530, Sudarshan Shetty wrote:
>> Add the device tree for the QCS615-based Talos EVK platform. The
>> platform is composed of a System-on-Module following the SMARC
>> standard, and a Carrier Board.
>>
>> The Carrier Board supports several display configurations, HDMI and
>> LVDS. Both configurations use the same base hardware, with the display
>> selection controlled by a DIP switch.
>>
>> Use a DTBO file, talos-evk-lvds-auo,g133han01.dtso, which defines an
>> overlay that disables HDMI and adds LVDS. The DTs file talos-evk
>> can describe the HDMI display configurations.
>>
>> According to the hardware design and vendor guidance, the WiFi PA
>> supplies VDD_PA_A and VDD_PA_B only need to be enabled at the same time
>> as asserting WLAN_EN.
>>
>> On this platform, WiFi enablement is controlled via the WLAN_EN GPIO
>> (GPIO84), which also drives the VDD_PA_A and VDD_PA_B power enables.
>> Remove the VDD_PA_A and VDD_PA_B regulator nodes from the device tree
>> and rely on WLAN_EN to enable WiFi functionality.
>>
>> Add talos-evk-usb1-peripheral.dtso overlay to enable USB0 peripheral
>> (EDL) mode. The base DTS will keep USB0 host-only due to hardware
>> routing through the EDL DIP switch, and the overlay switches the
>> configuration for device-mode operation.
>>
>> The LVDS backlight hardware has been updated to use a simplified
>> design. The backlight enable signal is now permanently pulled up
>> to 3.3V and is no longer controlled via GPIO59.
>>
>> Remove the GPIO59 based backlight configuration from the device
>> tree, as it is no longer routed to the LVDS interface.
>>
>> The initial device tree includes support for:
>> - CPU and memory
>> - UART
>> - GPIOs
>> - Regulators
>> - PMIC
>> - Early console
>> - AT24MAC602 EEPROM
>> - MCP2515 SPI to CAN
>> - ADV7535 DSI-to-HDMI bridge
>> - DisplayPort interface
>> - SN65DSI84ZXHR DSI-to-LVDS bridge
>> - Wi-Fi/BT
>>
>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> Signed-off-by: Sudarshan Shetty <tessolveupstream@gmail.com>
>> ---
>> arch/arm64/boot/dts/qcom/Makefile | 6 +
>> .../qcom/talos-evk-lvds-auo,g133han01.dtso | 127 ++++
>> arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 614 ++++++++++++++++++
>> .../dts/qcom/talos-evk-usb1-peripheral.dtso | 10 +
>> arch/arm64/boot/dts/qcom/talos-evk.dts | 139 ++++
>> 5 files changed, 896 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/talos-evk-lvds-auo,g133han01.dtso
>> create mode 100644 arch/arm64/boot/dts/qcom/talos-evk-som.dtsi
>> create mode 100644 arch/arm64/boot/dts/qcom/talos-evk-usb1-peripheral.dtso
>> create mode 100644 arch/arm64/boot/dts/qcom/talos-evk.dts
>
>> +
>> + regulator-usb2-vbus {
>> + compatible = "regulator-fixed";
>> + regulator-name = "USB2_VBUS";
>> + gpio = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>;
>> + pinctrl-0 = <&usb2_en>;
>> + pinctrl-names = "default";
>> + enable-active-high;
>> + regulator-always-on;
>> + };
>
> Hmm. I hoped that we are past this stage. Please order the nodes.
>
Okay, will take care in the next patch series.
>> +
>> + vreg_conn_1p8: regulator-conn-1p8 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vreg_conn_1p8";
>> + startup-delay-us = <4000>;
>> + enable-active-high;
>> + gpio = <&pm8150_gpios 1 GPIO_ACTIVE_HIGH>;
>> + };
>> +
>> + vreg_conn_pa: regulator-conn-pa {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vreg_conn_pa";
>> + startup-delay-us = <4000>;
>> + enable-active-high;
>> + gpio = <&pm8150_gpios 6 GPIO_ACTIVE_HIGH>;
>> + };
>> +
>> + vreg_v3p3_can: regulator-v3p3-can {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vreg-v3p3-can";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-boot-on;
>> + regulator-always-on;
>> + };
>> +
>> + vreg_v5p0_can: regulator-v5p0-can {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vreg-v5p0-can";
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + regulator-boot-on;
>> + regulator-always-on;
>> + };
>> +
>
> [...]
>
>> +
>> +/*
>> + * USB0 routing and EDL mode:
>> + *
>> + * The USB0 controller’s HS differential pair is switched (manually)
>> + * between the Micro-USB port for EDL/ADB and the on-board USB 3.0 hub.
>> + *
>> + * During EDL (Emergency Download) mode, the HS lines are explicitly
>> + * routed to the Micro-USB port to allow the SoC to enter device mode
>> + * for flashing.
>> + *
>> + * After EDL the switch is normally toggled so the HS lines stay
>> + * connected to the hub’s Type-A downstream ports, leaving no electrical
>> + * path to the Micro-USB connector — therefore USB0 runs host-only in
>> + * normal runtime and device mode must not be advertised.
>> + *
>> + * USB0 is configured host-only in the base device tree; a separate
>> + * device-tree overlay enables the Micro-USB peripheral configuration for
>> + * ADB. For ADB to work during normal runtime the DIP switch SW1 must be
>> + * manually toggled to the off position (reconnecting the HS pair to the
>> + * Micro-USB port).
>> + */
>> +
>> +&usb_1 {
>> + status = "okay";
>> +};
>> +
>
>
>> diff --git a/arch/arm64/boot/dts/qcom/talos-evk-usb1-peripheral.dtso b/arch/arm64/boot/dts/qcom/talos-evk-usb1-peripheral.dtso
>> new file mode 100644
>> index 000000000000..2f4630a6ba66
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/talos-evk-usb1-peripheral.dtso
>> @@ -0,0 +1,10 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
>> + */
>> +/dts-v1/;
>> +/plugin/;
>
> Comment, what should be changed to make use of it.
>
Sure, will add it in the next patch series.
>> +
>> +&usb_1_dwc3 {
>> + dr_mode = "peripheral";
>> +};
>
^ permalink raw reply
* Re: [PATCH v4 1/3] dt-bindings: media: camss: Add qcom,sm6350-camss
From: Bryan O'Donoghue @ 2026-03-31 8:50 UTC (permalink / raw)
To: Luca Weiss, Robert Foss, Todor Tomov, Vladimir Zapolskiy,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bryan O'Donoghue, Bjorn Andersson,
Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm,
linux-media, devicetree, linux-kernel, Krzysztof Kozlowski
In-Reply-To: <20260216-sm6350-camss-v4-1-b9df35f87edb@fairphone.com>
On 16/02/2026 08:54, Luca Weiss wrote:
> Add bindings for the Camera Subsystem on the SM6350 SoC.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> .../bindings/media/qcom,sm6350-camss.yaml | 471 +++++++++++++++++++++
> 1 file changed, 471 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,sm6350-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm6350-camss.yaml
> new file mode 100644
> index 000000000000..96974d90d8c4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,sm6350-camss.yaml
> @@ -0,0 +1,471 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/qcom,sm6350-camss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SM6350 Camera Subsystem (CAMSS)
> +
> +maintainers:
> + - Luca Weiss <luca.weiss@fairphone.com>
> +
> +description:
> + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
> +
> +properties:
> + compatible:
> + const: qcom,sm6350-camss
> +
> + reg:
> + maxItems: 24
> +
> + reg-names:
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csid2
> + - const: csid_lite
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: csiphy3
> + - const: vfe0
> + - const: vfe1
> + - const: vfe2
> + - const: vfe_lite
> + - const: a5_csr
> + - const: a5_qgic
> + - const: a5_sierra
> + - const: bps
> + - const: camnoc
> + - const: core_top_csr_tcsr
> + - const: cpas_cdm
> + - const: cpas_top
> + - const: ipe
> + - const: jpeg_dma
> + - const: jpeg_enc
> + - const: lrme
> +
> + clocks:
> + maxItems: 39
> +
> + clock-names:
> + items:
> + - const: cam_axi
> + - const: soc_ahb
> + - const: camnoc_axi
> + - const: core_ahb
> + - const: cpas_ahb
> + - const: csiphy0
> + - const: csiphy0_timer
> + - const: csiphy1
> + - const: csiphy1_timer
> + - const: csiphy2
> + - const: csiphy2_timer
> + - const: csiphy3
> + - const: csiphy3_timer
> + - const: vfe0_axi
> + - const: vfe0
> + - const: vfe0_cphy_rx
> + - const: vfe0_csid
> + - const: vfe1_axi
> + - const: vfe1
> + - const: vfe1_cphy_rx
> + - const: vfe1_csid
> + - const: vfe2_axi
> + - const: vfe2
> + - const: vfe2_cphy_rx
> + - const: vfe2_csid
> + - const: vfe_lite
> + - const: vfe_lite_cphy_rx
> + - const: vfe_lite_csid
> + - const: bps
> + - const: bps_ahb
> + - const: bps_areg
> + - const: bps_axi
> + - const: icp
> + - const: ipe0
> + - const: ipe0_ahb
> + - const: ipe0_areg
> + - const: ipe0_axi
> + - const: jpeg
> + - const: lrme
> +
> + interrupts:
> + maxItems: 18
> +
> + interrupt-names:
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csid2
> + - const: csid_lite
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: csiphy3
> + - const: vfe0
> + - const: vfe1
> + - const: vfe2
> + - const: vfe_lite
> + - const: a5
> + - const: cpas
> + - const: cpas_cdm
> + - const: jpeg_dma
> + - const: jpeg_enc
> + - const: lrme
> +
> + interconnects:
> + maxItems: 4
> +
> + interconnect-names:
> + items:
> + - const: ahb
> + - const: hf_mnoc
> + - const: sf_mnoc
> + - const: sf_icp_mnoc
> +
> + iommus:
> + maxItems: 14
> +
> + power-domains:
> + maxItems: 6
> +
> + power-domain-names:
> + items:
> + - const: ife0
> + - const: ife1
> + - const: ife2
> + - const: top
> + - const: bps
> + - const: ipe
> +
> + vdd-csiphy0-0p9-supply:
> + description:
> + Phandle to a 0.9V regulator supply to CSIPHY0.
> +
> + vdd-csiphy0-1p25-supply:
> + description:
> + Phandle to a 1.25V regulator supply to CSIPHY0.
> +
> + vdd-csiphy1-0p9-supply:
> + description:
> + Phandle to a 0.9V regulator supply to CSIPHY1.
> +
> + vdd-csiphy1-1p25-supply:
> + description:
> + Phandle to a 1.25V regulator supply to CSIPHY1.
> +
> + vdd-csiphy2-0p9-supply:
> + description:
> + Phandle to a 0.9V regulator supply to CSIPHY2.
> +
> + vdd-csiphy2-1p25-supply:
> + description:
> + Phandle to a 1.25V regulator supply to CSIPHY2.
> +
> + vdd-csiphy3-0p9-supply:
> + description:
> + Phandle to a 0.9V regulator supply to CSIPHY3.
> +
> + vdd-csiphy3-1p25-supply:
> + description:
> + Phandle to a 1.25V regulator supply to CSIPHY3.
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + description:
> + CSI input ports.
> +
> + patternProperties:
> + "^port@[0-3]$":
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> +
> + description:
> + Input port for receiving CSI data from a CSIPHY.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + bus-type:
> + enum:
> + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
> + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
> +
> + required:
> + - data-lanes
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> + - interrupts
> + - interrupt-names
> + - interconnects
> + - interconnect-names
> + - iommus
> + - power-domains
> + - power-domain-names
> + - ports
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,gcc-sm6350.h>
> + #include <dt-bindings/clock/qcom,sm6350-camcc.h>
> + #include <dt-bindings/interconnect/qcom,icc.h>
> + #include <dt-bindings/interconnect/qcom,sm6350.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/media/video-interfaces.h>
> + #include <dt-bindings/power/qcom-rpmpd.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + isp@acb3000 {
> + compatible = "qcom,sm6350-camss";
> +
> + reg = <0x0 0x0acb3000 0x0 0x1000>,
> + <0x0 0x0acba000 0x0 0x1000>,
> + <0x0 0x0acc1000 0x0 0x1000>,
> + <0x0 0x0acc8000 0x0 0x1000>,
> + <0x0 0x0ac65000 0x0 0x1000>,
> + <0x0 0x0ac66000 0x0 0x1000>,
> + <0x0 0x0ac67000 0x0 0x1000>,
> + <0x0 0x0ac68000 0x0 0x1000>,
> + <0x0 0x0acaf000 0x0 0x4000>,
> + <0x0 0x0acb6000 0x0 0x4000>,
> + <0x0 0x0acbd000 0x0 0x4000>,
> + <0x0 0x0acc4000 0x0 0x4000>,
> + <0x0 0x0ac18000 0x0 0x3000>,
> + <0x0 0x0ac00000 0x0 0x6000>,
> + <0x0 0x0ac10000 0x0 0x8000>,
> + <0x0 0x0ac6f000 0x0 0x8000>,
> + <0x0 0x0ac42000 0x0 0x4600>,
> + <0x0 0x01fc0000 0x0 0x40000>,
> + <0x0 0x0ac48000 0x0 0x1000>,
> + <0x0 0x0ac40000 0x0 0x1000>,
> + <0x0 0x0ac87000 0x0 0xa000>,
> + <0x0 0x0ac52000 0x0 0x4000>,
> + <0x0 0x0ac4e000 0x0 0x4000>,
> + <0x0 0x0ac6b000 0x0 0xa00>;
> + reg-names = "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "vfe0",
> + "vfe1",
> + "vfe2",
> + "vfe_lite",
> + "a5_csr",
> + "a5_qgic",
> + "a5_sierra",
> + "bps",
> + "camnoc",
> + "core_top_csr_tcsr",
> + "cpas_cdm",
> + "cpas_top",
> + "ipe",
> + "jpeg_dma",
> + "jpeg_enc",
> + "lrme";
> +
> + clocks = <&gcc GCC_CAMERA_AXI_CLK>,
> + <&camcc CAMCC_SOC_AHB_CLK>,
> + <&camcc CAMCC_CAMNOC_AXI_CLK>,
> + <&camcc CAMCC_CORE_AHB_CLK>,
> + <&camcc CAMCC_CPAS_AHB_CLK>,
> + <&camcc CAMCC_CSIPHY0_CLK>,
> + <&camcc CAMCC_CSI0PHYTIMER_CLK>,
> + <&camcc CAMCC_CSIPHY1_CLK>,
> + <&camcc CAMCC_CSI1PHYTIMER_CLK>,
> + <&camcc CAMCC_CSIPHY2_CLK>,
> + <&camcc CAMCC_CSI2PHYTIMER_CLK>,
> + <&camcc CAMCC_CSIPHY3_CLK>,
> + <&camcc CAMCC_CSI3PHYTIMER_CLK>,
> + <&camcc CAMCC_IFE_0_AXI_CLK>,
> + <&camcc CAMCC_IFE_0_CLK>,
> + <&camcc CAMCC_IFE_0_CPHY_RX_CLK>,
> + <&camcc CAMCC_IFE_0_CSID_CLK>,
> + <&camcc CAMCC_IFE_1_AXI_CLK>,
> + <&camcc CAMCC_IFE_1_CLK>,
> + <&camcc CAMCC_IFE_1_CPHY_RX_CLK>,
> + <&camcc CAMCC_IFE_1_CSID_CLK>,
> + <&camcc CAMCC_IFE_2_AXI_CLK>,
> + <&camcc CAMCC_IFE_2_CLK>,
> + <&camcc CAMCC_IFE_2_CPHY_RX_CLK>,
> + <&camcc CAMCC_IFE_2_CSID_CLK>,
> + <&camcc CAMCC_IFE_LITE_CLK>,
> + <&camcc CAMCC_IFE_LITE_CPHY_RX_CLK>,
> + <&camcc CAMCC_IFE_LITE_CSID_CLK>,
> + <&camcc CAMCC_BPS_CLK>,
> + <&camcc CAMCC_BPS_AHB_CLK>,
> + <&camcc CAMCC_BPS_AREG_CLK>,
> + <&camcc CAMCC_BPS_AXI_CLK>,
> + <&camcc CAMCC_ICP_CLK>,
> + <&camcc CAMCC_IPE_0_CLK>,
> + <&camcc CAMCC_IPE_0_AHB_CLK>,
> + <&camcc CAMCC_IPE_0_AREG_CLK>,
> + <&camcc CAMCC_IPE_0_AXI_CLK>,
> + <&camcc CAMCC_JPEG_CLK>,
> + <&camcc CAMCC_LRME_CLK>;
> + clock-names = "cam_axi",
> + "soc_ahb",
> + "camnoc_axi",
> + "core_ahb",
> + "cpas_ahb",
> + "csiphy0",
> + "csiphy0_timer",
> + "csiphy1",
> + "csiphy1_timer",
> + "csiphy2",
> + "csiphy2_timer",
> + "csiphy3",
> + "csiphy3_timer",
> + "vfe0_axi",
> + "vfe0",
> + "vfe0_cphy_rx",
> + "vfe0_csid",
> + "vfe1_axi",
> + "vfe1",
> + "vfe1_cphy_rx",
> + "vfe1_csid",
> + "vfe2_axi",
> + "vfe2",
> + "vfe2_cphy_rx",
> + "vfe2_csid",
> + "vfe_lite",
> + "vfe_lite_cphy_rx",
> + "vfe_lite_csid",
> + "bps",
> + "bps_ahb",
> + "bps_areg",
> + "bps_axi",
> + "icp",
> + "ipe0",
> + "ipe0_ahb",
> + "ipe0_areg",
> + "ipe0_axi",
> + "jpeg",
> + "lrme";
> +
> + interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 717 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 473 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 461 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 718 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 472 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 459 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 474 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 476 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "vfe0",
> + "vfe1",
> + "vfe2",
> + "vfe_lite",
> + "a5",
> + "cpas",
> + "cpas_cdm",
> + "jpeg_dma",
> + "jpeg_enc",
> + "lrme";
> +
> + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
> + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
> + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS
> + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
> + <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS
> + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "ahb",
> + "hf_mnoc",
> + "sf_mnoc",
> + "sf_icp_mnoc";
> +
> + iommus = <&apps_smmu 0x820 0xc0>,
> + <&apps_smmu 0x840 0x0>,
> + <&apps_smmu 0x860 0xc0>,
> + <&apps_smmu 0x880 0x0>,
> + <&apps_smmu 0xc40 0x20>,
> + <&apps_smmu 0xc60 0x20>,
> + <&apps_smmu 0xc80 0x0>,
> + <&apps_smmu 0xca2 0x0>,
> + <&apps_smmu 0xcc0 0x20>,
> + <&apps_smmu 0xce0 0x20>,
> + <&apps_smmu 0xd00 0x20>,
> + <&apps_smmu 0xd20 0x20>,
> + <&apps_smmu 0xd40 0x20>,
> + <&apps_smmu 0xd60 0x20>;
> +
> + power-domains = <&camcc IFE_0_GDSC>,
> + <&camcc IFE_1_GDSC>,
> + <&camcc IFE_2_GDSC>,
> + <&camcc TITAN_TOP_GDSC>,
> + <&camcc BPS_GDSC>,
> + <&camcc IPE_0_GDSC>;
> + power-domain-names = "ife0",
> + "ife1",
> + "ife2",
> + "top",
> + "bps",
> + "ipe";
> +
> + vdd-csiphy0-0p9-supply = <&vreg_l18a>;
> + vdd-csiphy0-1p25-supply = <&vreg_l22a>;
> + vdd-csiphy1-0p9-supply = <&vreg_l18a>;
> + vdd-csiphy1-1p25-supply = <&vreg_l22a>;
> + vdd-csiphy2-0p9-supply = <&vreg_l18a>;
> + vdd-csiphy2-1p25-supply = <&vreg_l22a>;
> + vdd-csiphy3-0p9-supply = <&vreg_l18a>;
> + vdd-csiphy3-1p25-supply = <&vreg_l22a>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + csiphy0_ep: endpoint {
> + data-lanes = <0 1 2 3>;
> + bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
> + remote-endpoint = <&sensor_ep>;
> + };
> + };
> + };
> + };
> + };
>
> --
> 2.53.0
>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply
* Re: [PATCH v4 1/3] dt-bindings: media: camss: Add qcom,sm6350-camss
From: Bryan O'Donoghue @ 2026-03-31 8:54 UTC (permalink / raw)
To: Luca Weiss, Vladimir Zapolskiy, Robert Foss, Todor Tomov,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bryan O'Donoghue, Bjorn Andersson,
Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm,
linux-media, devicetree, linux-kernel, Krzysztof Kozlowski
In-Reply-To: <DHGREFP0IVZS.1HWJHNFTI50KZ@fairphone.com>
On 31/03/2026 07:38, Luca Weiss wrote:
> Would be nice if the camss maintainers were aligned so that contributors
> don't have to deal with mailing list conflicts over these fundamental
> things.
>
> It doesn't really make it fun to contribute if you get conflicting
> opinions from two people that you should both value the opinion of
> because they're maintainer.
Yeah you're right and very much appreciate all the very awesome work you
personally do all over Qcom and PostmarketOS, which I don't think you
get called out enough for.
FWIW if we assume the proposed method of transitioning from legacy to
new in Hamoa goes through, even bindings in the old format like this can
benefit from new sub-nodes.
---
bod
^ permalink raw reply
* Re: [PATCH v5 2/4] iio: adc: ad4691: add initial driver for AD4691 family
From: Andy Shevchenko @ 2026-03-31 8:58 UTC (permalink / raw)
To: Sabau, Radu bogdan
Cc: Andy Shevchenko, Lars-Peter Clausen, Hennerich, Michael,
Jonathan Cameron, David Lechner, Sa, Nuno, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Uwe Kleine-König, Liam Girdwood, Mark Brown, Linus Walleij,
Bartosz Golaszewski, Philipp Zabel, Jonathan Corbet, Shuah Khan,
linux-iio@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-doc@vger.kernel.org
In-Reply-To: <LV9PR03MB8414CB05EB794F6974584C2AF753A@LV9PR03MB8414.namprd03.prod.outlook.com>
On Tue, Mar 31, 2026 at 08:36:42AM +0000, Sabau, Radu bogdan wrote:
> > -----Original Message-----
> > From: Andy Shevchenko <andy.shevchenko@gmail.com>
> > Sent: Monday, March 30, 2026 8:24 PM
...
> > > > > +#include <linux/bitfield.h>
> > > > > +#include <linux/bitops.h>
> > > > > +#include <linux/cleanup.h>
> > > > > +#include <linux/delay.h>
> > > > > +#include <linux/device.h>
> > > >
> > > > Hmm... Is it used? Or perhaps you need only
> > > > dev_printk.h
> > > > device/devres.h
> > > > ?
> >
> > > I have checked this out and it seems device.h doesn't actually need
> > > to be included anyway since spi.h directly includes device.h, and since
> > > this is a SPI driver that's never going away, it's covered. Will drop it!
> >
> > No, this is the wrong justification. IWYU principle is about exact
> > match between what is used and included in a file (module). spi.h is
> > not dev_*() provider and may not be considered for that.
> >
>
> You are right, my justification was incorrect. Under IWYU, relying on
> spi.h's transitive pull of device.h is not valid. However, I think device.h
> is still needed in this case since struct device is used directly in the code
> both as local variables and in the regmap callbacks.
Really? I can't see that.
(Hint: use of the data type and use of its pointer is a huge difference.)
> Also dev_err_probe() is called directly and lives in device.h.
No, as I started with my replies. The proper header that provides it is
dev_printk.h.
> What's your take on this?
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v1 2/2] riscv: dts: spacemit: add DeepComputing FML13V05 board device tree
From: Yixun Lan @ 2026-03-31 8:59 UTC (permalink / raw)
To: Sandie Cao
Cc: Conor Dooley, Emil Renner Berthing, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Heinrich Schuchardt, Troy Mitchell, Michael Opdenacker,
Guodong Xu, Hendrik Hamerlinck, Yangyu Chen, spacemit,
linux-riscv, devicetree, linux-kernel
In-Reply-To: <20260331034616.67183-1-sandie.cao@deepcomputing.io>
Hi Sandie,
On 11:46 Tue 31 Mar , Sandie Cao wrote:
> From: sandiecao <sandie.cao@deepcomputing.io>
>
> The FML13V05 board from DeepComputing incorporates a SpacemiT K3 RISC-V
> SoC.It is a mainboard designed for the Framework Laptop 13 Chassis,
> which has (Framework) SKU FRANHQ0001.
>
> The FML13V05 board features:
> - SpacemiT K3 RISC-V SoC
> - LPDDR5 16GB or 32GB
> - eMMC 32GB ~128GB (Optional)
> - UFS 3.1 256G (Optional)
> - QSPI Flash
> - MicroSD Slot
> - PCIe-based Wi-Fi
> - 4 USB-C Ports
> - Port 1: PD 3.0 (65W Max), USB 3.2 Gen 1
> - Port 2: PD 3.0 (65W Max), USB 3.2 Gen 1, DP 1.4 (4K@60Hz)
> - Port 3 & 4: USB 3.2 Gen 1
>
> This minimal device tree enables booting into a serial console with UART
> output.
>
> Signed-off-by: sandiecao <sandie.cao@deepcomputing.io>
> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
should put your own signed-off at the end.
> ---
> arch/riscv/boot/dts/spacemit/Makefile | 1 +
> .../spacemit/k3-deepcomputing-fml13v05.dts | 28 +++++++++++++++++++
> 2 files changed, 29 insertions(+)
> create mode 100644 arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts
>
> diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile
> index 7e2b87702571..acb993c452ba 100644
> --- a/arch/riscv/boot/dts/spacemit/Makefile
> +++ b/arch/riscv/boot/dts/spacemit/Makefile
> @@ -4,4 +4,5 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb
> dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb
> dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb
> dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb
> +dtb-$(CONFIG_ARCH_SPACEMIT) += k3-deepcomputing-fml13v05.dtb
> dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb
> diff --git a/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts b/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts
> new file mode 100644
> index 000000000000..2343ae3acc2d
> --- /dev/null
> +++ b/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts
> @@ -0,0 +1,28 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2024 DeepComputing (HK) Limited
should cover current year, which is 2026 now..
> + */
> +
> +#include "k3.dtsi"
> +
> +/ {
> + model = "DeepComputing FML13V05";
> + compatible = "deepcomputing,fml13v05", "spacemit,k3";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0";
> + };
> +
> + memory@100000000 {
> + device_type = "memory";
> + reg = <0x1 0x00000000 0x4 0x00000000>;
> + };
> +};
> +
> +&uart0 {
Can you also add pinctrl data explicitly?
> + status = "okay";
> +};
> --
> 2.43.0
--
Yixun Lan (dlan)
^ permalink raw reply
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