* Re: [PATCH RFC 0/2] arm64: dts: qcom: eliza: Add display
From: Krzysztof Kozlowski @ 2026-03-31 15:06 UTC (permalink / raw)
To: Konrad Dybcio, Krzysztof Kozlowski, Bjorn Andersson,
Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Abel Vesa
In-Reply-To: <f4ee7476-74d8-4e88-b14f-64835e6e7fbc@oss.qualcomm.com>
On 31/03/2026 17:03, Konrad Dybcio wrote:
> On 3/31/26 5:01 PM, Krzysztof Kozlowski wrote:
>> On 31/03/2026 16:49, Konrad Dybcio wrote:
>>> On 3/31/26 4:02 PM, Krzysztof Kozlowski wrote:
>>>> Dependency
>>>> ==========
>>>> Depends on USB patches, which are being reviewed, therefore marking it
>>>> as RFC as it cannot be applied.
>>>> https://lore.kernel.org/all/20260331-eliza-adsp-usb-v1-0-d8a251be20c3@oss.qualcomm.com/
>>>>
>>>> Unmerged bindings used here
>>>> ===========================
>>>> dispcc: https://lore.kernel.org/all/20260319-clk-qcom-dispcc-eliza-v3-0-d1f2b19a6e6b@oss.qualcomm.com/
>>>> (DRM MDSS bindings were applied)
>>>>
>>>> Description
>>>> ===========
>>>> I did not enable DisplayPort because it does not work on my board and I
>>>> don't know why. I double checked QMP combo phy and other bits, and
>>>> everything is looking fine, but still no USB display, so maybe I miss
>>>> some other dependencies as this is early upstream.
>>>
>>> What was the furthest that you got? We can certainly try to help..
>>>
>>> Got USB Type-C mode mux events?
>>> PHY initialized and configured to 2/4-lane DP mode?
>>> Are the AUX transfers failling?
>>
>> [ 43.975329] msm_dpu ae01000.display-controller: [drm:drm_dp_dpcd_access] dpu_dp_aux: Too many retries, giving up. First error: -110
>> [ 43.975410] msm_dpu ae01000.display-controller: [drm:drm_dp_dpcd_probe] dpu_dp_aux: 0x00102 AUX -> (ret=-110)
>> [ 45.780383] msm_dpu ae01000.display-controller: [drm:drm_dp_dpcd_access] dpu_dp_aux: Too many retries, giving up. First error: -110
>> [ 45.780463] msm_dpu ae01000.display-controller: [drm:drm_dp_dpcd_probe] dpu_dp_aux: 0x00102 AUX -> (ret=-110)
>> [ 45.780521] msm_dpu ae01000.display-controller: [drm:msm_dp_pm_runtime_suspend] type=10 core_init=1 phy_init=1
>>
>> pastebin: https://pastebin.com/BVXy3Qeq
>>
>> Abel pointed me to the phy problems, so I focused on that.
>> HSR says it is exactly same programming sequence as SM8650
>> and such was used.
>>
>> Just note, that we have ADSP remoteproc up, but no audio including USB mux,
>
> Are you talking about wcd939x-mux?
Yes
>
> If so, you need that or the lanes won't be properly connected
Ha! That would explain, although I had impression that with disabled
WCD939x mux the SM8750 DP still works.
Well, I don't have that WCD939x and it is left for other team to finish
a bit later, so we can leave the USB DP for now. I will re-visit that
when audio progresses.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v8 0/6] mfd: Add support for NXP MC33978/MC34978 MSDI
From: Rob Herring @ 2026-03-31 15:13 UTC (permalink / raw)
To: Guenter Roeck
Cc: Oleksij Rempel, Krzysztof Kozlowski, Conor Dooley, Lee Jones,
Peter Rosin, Linus Walleij, kernel, linux-kernel, devicetree,
linux-hwmon, linux-gpio, David Jander
In-Reply-To: <8291919d-c5ea-42ab-b2e5-2dfa16c23698@roeck-us.net>
On Sun, Mar 29, 2026 at 08:34:31AM -0700, Guenter Roeck wrote:
> Hi Oleksij,
>
> On 3/29/26 02:05, Oleksij Rempel wrote:
> > changes v7:
> > - drop gpiolib irq fix and make pinctrl more robust against NULL point
> > dereference.
> >
> > This series adds support for the NXP MC33978/MC34978 Multiple Switch Detection
> > Interface (MSDI) via the MFD framework.
> >
> > Architecture overview:
> > * mfd: Core driver handling 2-frame pipelined SPI, regulator sequencing, and
> > linear irq_domain. Harvests status bits from SPI MISO MSB.
> > * pinctrl: Exposes 22 physical switch inputs as standard GPIOs. Proxies IRQs to
> > the MFD domain.
> > * hwmon: Exposes thermal limits, VBATP/VDDQ voltage boundaries, and dynamic
> > fault alarms.
> > * mux: Controls the 24-to-1 AMUX routing analog signals (switch voltages,
> > temperature, VBATP) to an external ADC.
> >
> > Initial pinctrl implementation by David Jander, reworked into this MFD
> > architecture.
> >
>
> I Acked the hwmon driver, but Sashiko is still not happy with several of the other
> patches in the series:
>
> https://sashiko.dev/#/patchset/20260329090601.532477-1-o.rempel%40pengutronix.de
>
> If the remaining issues are false positives, please let Roman and/or me know.
The binding issue is valid. However, it's an issue with many GPIO
controller bindings that's been on my todo to address. Generally, there
is only a reference to the provider schema when there's child nodes.
Originally, there wheren't child nodes for GPIO, but then we added hog
nodes. Changing things probably entails changes to gpio.yaml, so there's
really nothing to do on this binding yet.
I really hope this sashiko stuff gains support soon in a form I can
review first and email out rather than dropping links into threads. It
is not a great workflow as-is.
Rob
^ permalink raw reply
* Re: [PATCH v8 4/5] reset: rzv2h-usb2phy: Keep PHY clock enabled for entire device lifetime
From: Philipp Zabel @ 2026-03-31 15:14 UTC (permalink / raw)
To: Tommaso Merciai, tomm.merciai, peda
Cc: linux-renesas-soc, biju.das.jz, Fabrizio Castro, Lad Prabhakar,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Ulf Hansson, Greg Kroah-Hartman,
Josua Mayer, Arnd Bergmann, devicetree, linux-kernel, stable
In-Reply-To: <6584aed8dc4fddb28c2184c83b92b4f3b419bc31.1773319566.git.tommaso.merciai.xr@bp.renesas.com>
On Do, 2026-03-12 at 15:50 +0100, Tommaso Merciai wrote:
> The driver was disabling the USB2 PHY clock immediately after register
> initialization in probe() and after each reset operation. This left the
> PHY unclocked even though it must remain active for USB functionality.
>
> The behavior appeared to work only when another driver
> (e.g., USB controller) had already enabled the clock, making operation
> unreliable and hardware-dependent. In configurations where this driver
> is the sole clock user, USB functionality would fail.
>
> Fix this by:
> - Enabling the clock once in probe() via pm_runtime_resume_and_get()
> - Removing all pm_runtime_put() calls from assert/deassert/status
> - Registering a devm cleanup action to release the clock at removal
> - Removed rzv2h_usbphy_assert_helper() and its call in
> rzv2h_usb2phy_reset_probe()
>
> This ensures the PHY clock remains enabled for the entire device lifetime,
> preventing instability and aligning with hardware requirements.
>
> Cc: stable@vger.kernel.org
> Fixes: e3911d7f865b ("reset: Add USB2PHY port reset driver for Renesas RZ/V2H(P)")
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Applied patch 4 to reset/next, thanks!
[4/5] reset: rzv2h-usb2phy: Keep PHY clock enabled for entire device lifetime
https://git.pengutronix.de/cgit/pza/linux/commit/?id=8889b289ce1b
regards
Philipp
^ permalink raw reply
* Re: [PATCH V3 0/9] Add Invensense ICM42607
From: Chris Morgan @ 2026-03-31 15:15 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Chris Morgan, linux-iio, andy, nuno.sa, dlechner, jic23,
jean-baptiste.maneyrol, linux-rockchip, devicetree, heiko,
conor+dt, krzk+dt, robh
In-Reply-To: <acuvQr0UVyGIQ7fo@ashevche-desk.local>
On Tue, Mar 31, 2026 at 02:25:54PM +0300, Andy Shevchenko wrote:
> On Mon, Mar 30, 2026 at 02:58:44PM -0500, Chris Morgan wrote:
>
> > Add support for the ICM42607 IMU. This sensor shares the same
> > functionality but a different register layout with the existing
> > ICM42600.
> >
> > This driver should work with the ICM42607 and ICM42607P over both I2C
> > and SPI, however only the ICM42607P over I2C could be tested.
> >
> > Changes Since V1:
> > - Instead of creating a new driver, merged with the existing inv_icm42600
> > driver. This necessitated adding some code to the existing driver to
> > permit using a different register layout for the same functionality.
> > - Split changes up a bit more to decrease the size of the individual
> > patches. Note that patch 0004 is still pretty hefty; if I need to split
> > further I may need to create some temporary stub functions.
> > - Used guard() and PM_RUNTIME_ACQUIRE_AUTOSUSPEND() on the new functions
> > per Jonathan's recommendations.
> >
> > Changes Since V2:
> > - Went back to using a new driver on advice from Invensense engineer.
>
> Okay, but this should be elaborated in the cover letter. If I followed
> previous discussion correctly, the problem is the indirect subset of
> registers that are absent on the 42600 series. But would be nice to have
> the summary of what vendor engineers told you.
Sorry, I should have elaborated you are correct. The information the
engineer said was that the 42607 chips use an indirect register access
method using IREG specific registers. As a result it did not make sense
to have the 42600 and 42607 drivers combined.
That said, the driver in question here does not use any of those specific
IREG registers (but it's possible other future 42607 devices could).
Specifically, I only have the 42607P (via I2C) to test with, which does
not have those registers only ones that can be directly accessed.
I hope this clears that up, I'll try to include that information in the
next patch. I also want to make sure with this revision that I'm "in the
ballpark" for breaking this down into digestable chunks.
Thank you,
Chris
>
> > - Further split changes up into smaller chunks of functionality. Note
> > still that the largest patch is approximately 900 lines, and that while
> > the driver compiles cleanly at each commit it is not able to drive the
> > hardware until the commit that adds the Interrupt (as it also adds the
> > Makefile).
> > - Change the error to a warning when the devicetree binding does not match
> > the hardware ID.
> > - Dropped the ack on the devicetree bindings, as I am creating a new file
> > (for a new driver) instead of modifying the existing one.
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
^ permalink raw reply
* Re: [PATCH v2 6/7] dt-bindings: PCI: intel,lgm-pcie: Make atu resource mandatory
From: Rob Herring @ 2026-03-31 15:21 UTC (permalink / raw)
To: Florian Eckert
Cc: Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, Johan Hovold, Sajid Dalvi,
Ajay Agarwal, Krzysztof Kozlowski, Conor Dooley, Rahul Tanwar,
linux-pci, linux-kernel, devicetree, Eckert.Florian, ms
In-Reply-To: <20260330-pcie-intel-gw-v2-6-8bd07367a298@dev.tdt.de>
On Mon, Mar 30, 2026 at 11:07:16AM +0200, Florian Eckert wrote:
> The ATU information is already set in the dwc core if it is specified in
> the DTS. The driver uses its own value here [1]. This information is
> hardware specific and should therefore be maintained in the DTS rather
> than in the source.
>
> Backwards compatibility is not an issue here [5], as the driver is
> exclusively used by Maxlinear.
>
> Old DTS entry for PCIe:
>
> reg = <0xd1000000 0x1000>,
> <0xd3000000 0x20000>,
> <0xd0c41000.0x1000>;
> reg-names = "dbi", "config", "app";
>
> New DTS entry for PCIe:
>
> reg = <0xd1000000 0x1000>,
> <0xd10c0000 0x1000>,
> <0xd3000000 0x20000>,
> <0xd0c41000.0x1000>;
> reg-names = "dbi", "atu", "config", "app";
>
> [1] https://elixir.bootlin.com/linux/v6.19.10/source/drivers/pci/controller/dwc/pcie-intel-gw.c#L301
> [2] https://lore.kernel.org/all/BY3PR19MB507667CE7531D863E1E5F8AEBDD82@BY3PR19MB5076.namprd19.prod.outlook.com/
>
> Signed-off-by: Florian Eckert <fe@dev.tdt.de>
> ---
> Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
> index 54e2890ae6314ac6847fc23f49440d05d66d87d4..e4b781f57e8ae84a3ffc33635a421e1a5761587e 100644
> --- a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
> @@ -29,12 +29,14 @@ properties:
> reg:
> items:
> - description: Controller control and status registers.
> + - description: Internal Address Translation Unit (iATU) registers.
> - description: PCIe configuration registers.
> - description: Controller application registers.
>
> reg-names:
> items:
> - const: dbi
> + - const: atu
Put this at the end and add 'minItems: 3' and you avoid any ABI issues.
> - const: config
> - const: app
>
^ permalink raw reply
* Re: [PATCH RFC 0/2] arm64: dts: qcom: eliza: Add display
From: Konrad Dybcio @ 2026-03-31 15:23 UTC (permalink / raw)
To: Krzysztof Kozlowski, Krzysztof Kozlowski, Bjorn Andersson,
Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Abel Vesa
In-Reply-To: <918785e7-ab35-4d54-a613-ca56de78cf86@kernel.org>
On 3/31/26 5:06 PM, Krzysztof Kozlowski wrote:
> On 31/03/2026 17:03, Konrad Dybcio wrote:
>> On 3/31/26 5:01 PM, Krzysztof Kozlowski wrote:
>>> On 31/03/2026 16:49, Konrad Dybcio wrote:
>>>> On 3/31/26 4:02 PM, Krzysztof Kozlowski wrote:
>>>>> Dependency
>>>>> ==========
>>>>> Depends on USB patches, which are being reviewed, therefore marking it
>>>>> as RFC as it cannot be applied.
>>>>> https://lore.kernel.org/all/20260331-eliza-adsp-usb-v1-0-d8a251be20c3@oss.qualcomm.com/
>>>>>
>>>>> Unmerged bindings used here
>>>>> ===========================
>>>>> dispcc: https://lore.kernel.org/all/20260319-clk-qcom-dispcc-eliza-v3-0-d1f2b19a6e6b@oss.qualcomm.com/
>>>>> (DRM MDSS bindings were applied)
>>>>>
>>>>> Description
>>>>> ===========
>>>>> I did not enable DisplayPort because it does not work on my board and I
>>>>> don't know why. I double checked QMP combo phy and other bits, and
>>>>> everything is looking fine, but still no USB display, so maybe I miss
>>>>> some other dependencies as this is early upstream.
>>>>
>>>> What was the furthest that you got? We can certainly try to help..
>>>>
>>>> Got USB Type-C mode mux events?
>>>> PHY initialized and configured to 2/4-lane DP mode?
>>>> Are the AUX transfers failling?
>>>
>>> [ 43.975329] msm_dpu ae01000.display-controller: [drm:drm_dp_dpcd_access] dpu_dp_aux: Too many retries, giving up. First error: -110
>>> [ 43.975410] msm_dpu ae01000.display-controller: [drm:drm_dp_dpcd_probe] dpu_dp_aux: 0x00102 AUX -> (ret=-110)
>>> [ 45.780383] msm_dpu ae01000.display-controller: [drm:drm_dp_dpcd_access] dpu_dp_aux: Too many retries, giving up. First error: -110
>>> [ 45.780463] msm_dpu ae01000.display-controller: [drm:drm_dp_dpcd_probe] dpu_dp_aux: 0x00102 AUX -> (ret=-110)
>>> [ 45.780521] msm_dpu ae01000.display-controller: [drm:msm_dp_pm_runtime_suspend] type=10 core_init=1 phy_init=1
>>>
>>> pastebin: https://pastebin.com/BVXy3Qeq
>>>
>>> Abel pointed me to the phy problems, so I focused on that.
>>> HSR says it is exactly same programming sequence as SM8650
>>> and such was used.
>>>
>>> Just note, that we have ADSP remoteproc up, but no audio including USB mux,
>>
>> Are you talking about wcd939x-mux?
>
> Yes
>
>>
>> If so, you need that or the lanes won't be properly connected
>
> Ha! That would explain, although I had impression that with disabled
> WCD939x mux the SM8750 DP still works.
I don't know what's the power-on-reset setup, but there is a nonzero
chance that if your recollections are correct, flipping the cable may
make it work. But that'd be pure luck.
> Well, I don't have that WCD939x and it is left for other team to finish
> a bit later, so we can leave the USB DP for now. I will re-visit that
> when audio progresses.
But.. can't you just copy-paste the sm8750-mtp node and fix up the reset
pin?
Konrad
^ permalink raw reply
* Re: [PATCH 1/2] reset: amlogic: t7: Fix null reset ops
From: Philipp Zabel @ 2026-03-31 15:25 UTC (permalink / raw)
To: Ronald Claveau, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-kernel, linux-amlogic, linux-kernel, devicetree
In-Reply-To: <20260331-fix-aml-t7-null-reset-v1-1-eb95b625234c@aliel.fr>
On Di, 2026-03-31 at 16:24 +0200, Ronald Claveau wrote:
> Fix missing reset ops causing kernel null pointer dereference.
> This SOC's reset is currently not used yet.
>
> Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr>
Applied to reset/fixes, thanks!
[1/2] reset: amlogic: t7: Fix null reset ops
https://git.pengutronix.de/cgit/pza/linux/commit/?id=9797524ef2b6
regards
Philipp
^ permalink raw reply
* [PATCH 0/4] timers: Add support for RZ/N1 SoCs timers
From: Herve Codina (Schneider Electric) @ 2026-03-31 15:26 UTC (permalink / raw)
To: Wolfram Sang, Herve Codina, Daniel Lezcano, Thomas Gleixner,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm
Cc: linux-renesas-soc, linux-kernel, devicetree, Pascal Eberhard,
Miquel Raynal, Thomas Petazzoni
The Renesas RZ/N1 SoCs family has two timers block controller
available.
Each controller is charge of 8 timers (six 16-bit timers + two 32-bit
timers).
Each timer has its own interrupt, its own prescaler that can be used to
device the clock by 25 (timers block are fed with a 25 MHz clock) and
all timers can work in either one-shot or periodic mode.
This series adds support for those timers blocks.
Best regards,
Hervé
Herve Codina (Schneider Electric) (4):
dt-bindings: timer: Add the Renesas RZ/N1 timer
clocksource/drivers: Add support for the Renesas RZ/N1 timers
ARM: dts: r9a06g032: Add support for timers
MAINTAINERS: Add the Renesas RZ/N1 timers driver entry
.../bindings/timer/renesas,rzn1-timer.yaml | 75 +++
MAINTAINERS | 7 +
arch/arm/boot/dts/renesas/r9a06g032.dtsi | 34 ++
drivers/clocksource/Kconfig | 10 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-rzn1.c | 442 ++++++++++++++++++
6 files changed, 569 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/renesas,rzn1-timer.yaml
create mode 100644 drivers/clocksource/timer-rzn1.c
--
2.53.0
^ permalink raw reply
* [PATCH 1/4] dt-bindings: timer: Add the Renesas RZ/N1 timer
From: Herve Codina (Schneider Electric) @ 2026-03-31 15:26 UTC (permalink / raw)
To: Wolfram Sang, Herve Codina, Daniel Lezcano, Thomas Gleixner,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm
Cc: linux-renesas-soc, linux-kernel, devicetree, Pascal Eberhard,
Miquel Raynal, Thomas Petazzoni
In-Reply-To: <20260331152616.197031-1-herve.codina@bootlin.com>
The Renesas RZ/N1 timer block controller is the controller in charge of
timers available in the Renesas RZ/N1 SoCs family.
This controller handles 8 timers:
- 6 16-bit timers
- 2 32-bit timers
Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
---
.../bindings/timer/renesas,rzn1-timer.yaml | 75 +++++++++++++++++++
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/renesas,rzn1-timer.yaml
diff --git a/Documentation/devicetree/bindings/timer/renesas,rzn1-timer.yaml b/Documentation/devicetree/bindings/timer/renesas,rzn1-timer.yaml
new file mode 100644
index 000000000000..b9a725837d7c
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/renesas,rzn1-timer.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/renesas,rzn1-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/N1 timers
+
+maintainers:
+ - Herve Codina <herve.codina@bootlin.com>
+
+description: |
+ The Renesas RZ/N1 SoCs timers block controller is composed of 8 independent
+ timers.
+ - 6 are 16-bit timers
+ - 2 are 32-bit timers
+
+ Each timer has its own interrupt line and can work in either one-shot or
+ periodic mode.
+
+properties:
+ compatible:
+ items:
+ - const: renesas,r9a06g032-timer # RZ/N1D
+ - const: renesas,rzn1-timer
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: APB internal bus clock
+
+ clock-names:
+ items:
+ - const: pclk
+
+ power-domains:
+ maxItems: 1
+
+ interrupts:
+ minItems: 8
+ maxItems: 8
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - power-domains
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/r9a06g032-sysctrl.h>
+
+ timer@51001000 {
+ compatible = "renesas,r9a06g032-timer", "renesas,rzn1-timer";
+ reg = <0x51001000 0x400>;
+ clocks = <&sysctrl R9A06G032_HCLK_TIMER0>;
+ clock-names = "pclk";
+ power-domains = <&sysctrl>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ };
+...
--
2.53.0
^ permalink raw reply related
* [PATCH 2/4] clocksource/drivers: Add support for the Renesas RZ/N1 timers
From: Herve Codina (Schneider Electric) @ 2026-03-31 15:26 UTC (permalink / raw)
To: Wolfram Sang, Herve Codina, Daniel Lezcano, Thomas Gleixner,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm
Cc: linux-renesas-soc, linux-kernel, devicetree, Pascal Eberhard,
Miquel Raynal, Thomas Petazzoni
In-Reply-To: <20260331152616.197031-1-herve.codina@bootlin.com>
The Renesas RZ/N1 timer block controller is the controller in charge of
timers available in the Renesas RZ/N1 SoCs family.
This controller handles 8 timers:
- 6 16-bit timers
- 2 32-bit timers
Each timer has its own interrupt, its own prescaler that can be used to
device the clock by 25 and all of them can work in either one-shot or
periodic mode.
Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
---
drivers/clocksource/Kconfig | 10 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-rzn1.c | 442 +++++++++++++++++++++++++++++++
3 files changed, 453 insertions(+)
create mode 100644 drivers/clocksource/timer-rzn1.c
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index fd9112706545..31cf40880ece 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -152,6 +152,16 @@ config REALTEK_OTTO_TIMER
RT8391, RTL8392, RTL8393 and RTL8396 and chips of the RTL930x series
such as RTL9301, RTL9302 or RTL9303.
+config RZN1_TIMER
+ bool "Renesas RZ/N1 Timer"
+ depends on HAS_IOMEM && COMMON_CLK && (ARCH_RZN1 || COMPILE_TEST)
+ help
+ Enables support for RZ/N1 SoC timers.
+ A timers block in RZ/N1 SoCs is composed of 8 timers
+ - 6 16-bit timers
+ - 2 32-bit timers
+ Two timers blocks are available in RZ/N1 SoCs.
+
config SUN4I_TIMER
bool "Sun4i timer driver" if COMPILE_TEST
depends on HAS_IOMEM
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index b46376af6b49..464ec6690ab6 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -96,3 +96,4 @@ obj-$(CONFIG_EP93XX_TIMER) += timer-ep93xx.o
obj-$(CONFIG_RALINK_TIMER) += timer-ralink.o
obj-$(CONFIG_NXP_STM_TIMER) += timer-nxp-stm.o
obj-$(CONFIG_RTK_SYSTIMER) += timer-realtek.o
+obj-$(CONFIG_RZN1_TIMER) += timer-rzn1.o
diff --git a/drivers/clocksource/timer-rzn1.c b/drivers/clocksource/timer-rzn1.c
new file mode 100644
index 000000000000..1b95b0b5cd3b
--- /dev/null
+++ b/drivers/clocksource/timer-rzn1.c
@@ -0,0 +1,442 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/N1 timers driver
+ *
+ * Copyright (C) 2026 Schneider-Electric
+ *
+ * Author: Herve Codina <herve.codina@bootlin.com>
+ */
+
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/cpuhotplug.h>
+#include <linux/interrupt.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/sched_clock.h>
+
+/* Per-timer register offsets */
+#define RZN1_TIMER_LOAD_COUNT_REG 0x00
+#define RZN1_TIMER_CURRENT_COUNT_REG 0x04
+#define RZN1_TIMER_CONTROL_REG 0x08
+#define RZN1_TIMER_CONTROL_INT_UNMASK BIT(3)
+#define RZN1_TIMER_CONTROL_ENABLE BIT(2)
+#define RZN1_TIMER_CONTROL_AUTORELOAD BIT(1)
+#define RZN1_TIMER_CONTROL_PRESCALER_DIV25 BIT(0)
+#define RZN1_TIMER_CLEAR_INT_REG 0x0c
+#define RZN1_TIMER_STATUS_INT0_REG 0x10
+#define RZN1_TIMER_STATUS_INT1_REG 0x14
+
+/*
+ * 8 timers are available. Among those 8 timers, the first 6 timers are 16-bit
+ * timers and the last two ones are 32-bit timers.
+ */
+#define RZN1_TIMER_BASE_INDEX_16BIT_TIMERS 0
+#define RZN1_TIMER_NB_16BIT_TIMERS 6
+
+#define RZN1_TIMER_BASE_INDEX_32BIT_TIMER 6
+#define RZN1_TIMER_NB_32BIT_TIMERS 2
+
+#define RZN1_TIMER_IS_16BIT_TIMER(_i) ((_i) < RZN1_TIMER_BASE_INDEX_32BIT_TIMER)
+
+/* Total numbers of timers */
+#define RZN1_TIMER_NB_TIMERS (RZN1_TIMER_NB_16BIT_TIMERS + \
+ RZN1_TIMER_NB_32BIT_TIMERS)
+
+/* Offset of registers related to the timer number _i in the timers regs area */
+#define RZN1_TIMER_REGS_OFFSET(_i) (0x20 * (_i))
+
+struct rzn1_timer {
+ void __iomem *base;
+ unsigned int width;
+ unsigned long rate;
+ unsigned long hz_period;
+ struct clock_event_device ced;
+};
+
+static int rzn1_timer_config(struct rzn1_timer *timer, u32 period, bool is_periodic)
+{
+ u32 ctrl;
+
+ ctrl = readl(timer->base + RZN1_TIMER_CONTROL_REG);
+
+ /* Disable the timer */
+ writel(ctrl & ~RZN1_TIMER_CONTROL_ENABLE,
+ timer->base + RZN1_TIMER_CONTROL_REG);
+
+ /* Set the new period */
+ writel(period, timer->base + RZN1_TIMER_LOAD_COUNT_REG);
+
+ /* Prepare the timer mode */
+ if (is_periodic)
+ ctrl |= RZN1_TIMER_CONTROL_AUTORELOAD;
+ else
+ ctrl &= ~RZN1_TIMER_CONTROL_AUTORELOAD;
+
+ /*
+ * Enable the timer.
+ *
+ * This automatically resets the CURRENT_COUNT register.
+ */
+ ctrl |= RZN1_TIMER_CONTROL_ENABLE;
+ writel(ctrl, timer->base + RZN1_TIMER_CONTROL_REG);
+
+ return 0;
+}
+
+static void rzn1_timer_disable(struct rzn1_timer *timer)
+{
+ u32 ctrl;
+
+ ctrl = readl(timer->base + RZN1_TIMER_CONTROL_REG);
+ ctrl &= ~RZN1_TIMER_CONTROL_ENABLE;
+ writel(ctrl, timer->base + RZN1_TIMER_CONTROL_REG);
+}
+
+static void rzn1_timer_int_enable(struct rzn1_timer *timer)
+{
+ u32 ctrl;
+
+ ctrl = readl(timer->base + RZN1_TIMER_CONTROL_REG);
+ ctrl |= RZN1_TIMER_CONTROL_INT_UNMASK;
+ writel(ctrl, timer->base + RZN1_TIMER_CONTROL_REG);
+}
+
+static irqreturn_t rzn1_timer_interrupt(int irq, void *dev_id)
+{
+ struct rzn1_timer *timer = dev_id;
+
+ /* Ack the interrupt */
+ readl(timer->base + RZN1_TIMER_CLEAR_INT_REG);
+
+ timer->ced.event_handler(&timer->ced);
+ return IRQ_HANDLED;
+}
+
+static int rzn1_clkevt_set_next_event(unsigned long cycles,
+ struct clock_event_device *evt)
+{
+ struct rzn1_timer *timer = container_of(evt, struct rzn1_timer, ced);
+
+ return rzn1_timer_config(timer, cycles, false);
+}
+
+static int rzn1_clkevt_shutdown(struct clock_event_device *evt)
+{
+ struct rzn1_timer *timer = container_of(evt, struct rzn1_timer, ced);
+
+ rzn1_timer_disable(timer);
+ return 0;
+}
+
+static int rzn1_clkevt_set_periodic(struct clock_event_device *evt)
+{
+ struct rzn1_timer *timer = container_of(evt, struct rzn1_timer, ced);
+
+ rzn1_timer_config(timer, timer->hz_period, true);
+ return 0;
+}
+
+/*
+ * This global lock is used to prevent race conditions during global timers
+ * test and set operation in case the driver is using the async probe option.
+ */
+static DEFINE_MUTEX(rzn1_global_timers_lock);
+
+static int rzn1_timer_instance;
+
+/* scheduler and clocksource */
+static struct rzn1_timer *rzn1_sched_clock;
+
+static u64 notrace rzn1_sched_read(void)
+{
+ return readl_relaxed(rzn1_sched_clock->base + RZN1_TIMER_CURRENT_COUNT_REG);
+}
+
+static u64 rzn1_clksrc_read(struct clocksource *cs)
+{
+ return readl_relaxed(rzn1_sched_clock->base + RZN1_TIMER_CURRENT_COUNT_REG);
+}
+
+static struct clocksource rzn1_clocksource = {
+ .name = "rzn1_timer_clocksource",
+ .rating = 200,
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
+ .read = rzn1_clksrc_read,
+};
+
+/* Timers table where 32-bit timers will be assigned per-cpu */
+static struct rzn1_timer *rzn1_tab_timers;
+
+static int rzn1_local_timer_starting_cpu(unsigned int cpu)
+{
+ struct rzn1_timer *timer;
+
+ if (cpu > RZN1_TIMER_NB_32BIT_TIMERS)
+ return -EINVAL;
+
+ timer = &rzn1_tab_timers[cpu + RZN1_TIMER_BASE_INDEX_32BIT_TIMER];
+
+ timer->ced.cpumask = cpumask_of(cpu);
+ irq_force_affinity(timer->ced.irq, cpumask_of(cpu));
+ clockevents_config_and_register(&timer->ced, timer->rate, 1,
+ GENMASK(timer->width - 1, 0));
+
+ return 0;
+}
+
+static void rzn1_timer_init(struct rzn1_timer *timer, unsigned int index,
+ void __iomem *timers_base, unsigned long clock_rate)
+{
+ timer->base = timers_base + RZN1_TIMER_REGS_OFFSET(index);
+
+ /* Disable the timer */
+ writel(0, timer->base + RZN1_TIMER_CONTROL_REG);
+
+ /* Clear potential interrupts */
+ readl(timer->base + RZN1_TIMER_CLEAR_INT_REG);
+
+ if (RZN1_TIMER_IS_16BIT_TIMER(index)) {
+ timer->width = 16;
+ /*
+ * Enable pre-scaler for 16-bit timers.
+ *
+ * Timers are fed by a 25MHz clock. With this pre-scaler (1/25)
+ * enabled, the 16-bit timers resolution is 1 microsecond.
+ */
+ writel(RZN1_TIMER_CONTROL_PRESCALER_DIV25,
+ timer->base + RZN1_TIMER_CONTROL_REG);
+ timer->rate = clock_rate / 25;
+ } else {
+ timer->width = 32;
+ timer->rate = clock_rate;
+ }
+ timer->hz_period = DIV_ROUND_UP(timer->rate, HZ);
+}
+
+static void rzn1_timer_clkevt_init_ced(struct rzn1_timer *timer, const char *name,
+ int irq)
+{
+ timer->ced.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
+ timer->ced.set_next_event = rzn1_clkevt_set_next_event;
+ timer->ced.set_state_shutdown = rzn1_clkevt_shutdown;
+ timer->ced.set_state_periodic = rzn1_clkevt_set_periodic;
+ timer->ced.cpumask = cpu_possible_mask;
+
+ /*
+ * 32-bit timers are fed with a 25 MHz clock directly derived from the
+ * main PLL (1 GHz). The arch timer, ARMv7 CP15 in RZ/N1 SoCs, is fed
+ * with to a 6.25 MHz clock.
+ *
+ * The clock of the RZ/N1 timers block is a stable one and the RZ/N1
+ * timers have a higher resolution than the ARM CP15 one.
+ *
+ * Also those 32-bit RZ/N1 timers are assigned per-cpu.
+ *
+ * Use a high rating for the 32-bit RZ/N1 timers in order to have them
+ * chosen by the system.
+ */
+ timer->ced.rating = timer->width == 16 ? 200 : 460;
+ timer->ced.owner = THIS_MODULE;
+ timer->ced.name = name;
+ timer->ced.irq = irq;
+}
+
+static int rzn1_timer_probe_first(struct platform_device *pdev, struct rzn1_timer *tab_timers,
+ void __iomem *base, unsigned long clock_rate)
+{
+ struct device *dev = &pdev->dev;
+ struct rzn1_timer *timer;
+ unsigned int i;
+ char *name;
+ int irq;
+ int ret;
+
+ /*
+ * Probe the first instance. In that case, timers are assigned as
+ * follow:
+ * - First 16-bit timer: clocksource and sched_clock
+ * - Other 16-bit timers: clock events for all possible CPUs
+ * - 32-bit timers: clock events per CPU
+ *
+ * First step, perform all operation that could fail without calling
+ * clockevents_config_and_register(), sched_clock_register() nor
+ * cpuhp_setup_state(). Those operation don't have unregister nor
+ * teardown counterparts and so, once called, we cannot remove the
+ * related resource.
+ */
+
+ /*
+ * First step for 16-bit timers except the first one and all 32-bit
+ * timers.
+ */
+ for (i = RZN1_TIMER_BASE_INDEX_16BIT_TIMERS + 1; i < RZN1_TIMER_NB_TIMERS; i++) {
+ timer = &tab_timers[i];
+
+ rzn1_timer_init(timer, i, base, clock_rate);
+
+ irq = platform_get_irq(pdev, i);
+ if (irq < 0)
+ return irq;
+
+ name = devm_kasprintf(dev, GFP_KERNEL, "%s-%u", dev_name(dev), i);
+ if (!name)
+ return -ENOMEM;
+
+ rzn1_timer_clkevt_init_ced(timer, name, irq);
+
+ ret = devm_request_irq(dev, timer->ced.irq, rzn1_timer_interrupt,
+ IRQF_TIMER, timer->ced.name, timer);
+ if (ret < 0)
+ return dev_err_probe(dev, irq, "timer%d: Failed to request IRQ\n", i);
+
+ rzn1_timer_int_enable(timer);
+ }
+
+ /*
+ * Second step, almost all operations that can fail have been called.
+ * Timers are ready to work. Start with the last operation that can fail,
+ * installing and invoking hotplug callbacks
+ */
+ rzn1_tab_timers = tab_timers;
+ ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
+ "clockevents/rzn1/global_timer:starting",
+ rzn1_local_timer_starting_cpu, NULL);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Setup CPU hotplug state failed\n");
+
+ /*
+ * At this point, no more operations can fail. Perform remaining
+ * operations. Starting by handling the first 16-bit timer
+ */
+ timer = &tab_timers[RZN1_TIMER_BASE_INDEX_16BIT_TIMERS];
+
+ rzn1_timer_init(timer, RZN1_TIMER_BASE_INDEX_16BIT_TIMERS, base, clock_rate);
+ rzn1_timer_config(timer, GENMASK(timer->width - 1, 0), true);
+
+ rzn1_sched_clock = timer;
+
+ sched_clock_register(rzn1_sched_read, rzn1_sched_clock->width, rzn1_sched_clock->rate);
+
+ rzn1_clocksource.mask = CLOCKSOURCE_MASK(rzn1_sched_clock->width);
+ clocksource_register_hz(&rzn1_clocksource, rzn1_sched_clock->rate);
+
+ /*
+ * Register clockevents only for 16-bit timers. 32-bit timers clockevents
+ * are registered by CPU hotplug startup function set previously by the
+ * cpuhp_setup_state() call.
+ */
+ for (i = RZN1_TIMER_BASE_INDEX_16BIT_TIMERS + 1; i < RZN1_TIMER_NB_16BIT_TIMERS; i++) {
+ timer = &tab_timers[i];
+ clockevents_config_and_register(&timer->ced, timer->rate,
+ 1, GENMASK(timer->width - 1, 0));
+ }
+
+ return 0;
+}
+
+static int rzn1_timer_probe_other(struct platform_device *pdev, struct rzn1_timer *tab_timers,
+ void __iomem *base, unsigned long clock_rate)
+{
+ struct device *dev = &pdev->dev;
+ struct rzn1_timer *timer;
+ unsigned int i;
+ char *name;
+ int irq;
+ int ret;
+
+ /*
+ * Probe other instance(s), i.e. not the first one. In that case,
+ * all timers are used as clock events and available for all possible
+ * CPUs
+ *
+ * First step, perform all operation that could fail without calling
+ * clockevents_config_and_register(). Unregister counterpart does not
+ * exist and so, once called, we cannot remove the related resource.
+ */
+ for (i = 0; i < RZN1_TIMER_NB_TIMERS; i++) {
+ timer = &tab_timers[i];
+
+ rzn1_timer_init(timer, i, base, clock_rate);
+
+ irq = platform_get_irq(pdev, i);
+ if (irq < 0)
+ return irq;
+
+ name = devm_kasprintf(dev, GFP_KERNEL, "%s-%u", dev_name(dev), i);
+ if (!name)
+ return -ENOMEM;
+
+ rzn1_timer_clkevt_init_ced(timer, name, irq);
+
+ ret = devm_request_irq(dev, timer->ced.irq, rzn1_timer_interrupt,
+ IRQF_TIMER, timer->ced.name, timer);
+ if (ret < 0)
+ return dev_err_probe(dev, irq, "timer%d: Failed to request IRQ\n", i);
+
+ rzn1_timer_int_enable(timer);
+ }
+
+ /*
+ * Second step, all operation that can fail have been called. We can
+ * register our timers
+ */
+
+ for (i = 0; i < RZN1_TIMER_NB_TIMERS; i++) {
+ timer = &tab_timers[i];
+ clockevents_config_and_register(&timer->ced, timer->rate,
+ 1, GENMASK(timer->width - 1, 0));
+ }
+
+ return 0;
+}
+
+static int rzn1_timer_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct rzn1_timer *tab_timers;
+ unsigned long clock_rate;
+ void __iomem *base;
+ struct clk *clk;
+ int ret;
+
+ tab_timers = devm_kcalloc(dev, RZN1_TIMER_NB_TIMERS, sizeof(*tab_timers),
+ GFP_KERNEL);
+ if (!tab_timers)
+ return -ENOMEM;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ clk = devm_clk_get_enabled(dev, "pclk");
+ if (IS_ERR(clk))
+ return dev_err_probe(dev, PTR_ERR(clk), "Failed to get pclk\n");
+
+ clock_rate = clk_get_rate(clk);
+
+ scoped_guard(mutex, &rzn1_global_timers_lock) {
+ ret = !rzn1_timer_instance ?
+ rzn1_timer_probe_first(pdev, tab_timers, base, clock_rate) :
+ rzn1_timer_probe_other(pdev, tab_timers, base, clock_rate);
+ if (!ret)
+ rzn1_timer_instance++;
+ }
+
+ return ret;
+}
+
+static const struct of_device_id rzn1_timer_of_match[] = {
+ { .compatible = "renesas,rzn1-timer", },
+ { /* sentinel */ }
+};
+
+static struct platform_driver rzn1_timer_driver = {
+ .driver = {
+ .name = "rzn1_timer",
+ .of_match_table = rzn1_timer_of_match,
+ },
+};
+builtin_platform_driver_probe(rzn1_timer_driver, rzn1_timer_probe);
--
2.53.0
^ permalink raw reply related
* [PATCH 3/4] ARM: dts: r9a06g032: Add support for timers
From: Herve Codina (Schneider Electric) @ 2026-03-31 15:26 UTC (permalink / raw)
To: Wolfram Sang, Herve Codina, Daniel Lezcano, Thomas Gleixner,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm
Cc: linux-renesas-soc, linux-kernel, devicetree, Pascal Eberhard,
Miquel Raynal, Thomas Petazzoni
In-Reply-To: <20260331152616.197031-1-herve.codina@bootlin.com>
In the Renesas RZ/N1 SoCs family, two timers block are available.
Each block contains 8 timers composed of 6 16-bits timers and 2 32-bits
timers.
Each timer has its own interrupt line.
Describe those timers blocks.
Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
---
arch/arm/boot/dts/renesas/r9a06g032.dtsi | 34 ++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
index f4f760aff28b..7d736e1e835a 100644
--- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
@@ -674,6 +674,40 @@ gpioirqmux: interrupt-controller@51000480 {
status = "disabled";
};
+ timer0: timer@51001000 {
+ compatible = "renesas,r9a06g032-timer", "renesas,rzn1-timer";
+ reg = <0x51001000 0x400>;
+ clocks = <&sysctrl R9A06G032_HCLK_TIMER0>;
+ clock-names = "pclk";
+ power-domains = <&sysctrl>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ timer1: timer@51002000 {
+ compatible = "renesas,r9a06g032-timer", "renesas,rzn1-timer";
+ reg = <0x51002000 0x400>;
+ clocks = <&sysctrl R9A06G032_HCLK_TIMER1>;
+ clock-names = "pclk";
+ power-domains = <&sysctrl>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
can0: can@52104000 {
compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000";
reg = <0x52104000 0x800>;
--
2.53.0
^ permalink raw reply related
* [PATCH 4/4] MAINTAINERS: Add the Renesas RZ/N1 timers driver entry
From: Herve Codina (Schneider Electric) @ 2026-03-31 15:26 UTC (permalink / raw)
To: Wolfram Sang, Herve Codina, Daniel Lezcano, Thomas Gleixner,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm
Cc: linux-renesas-soc, linux-kernel, devicetree, Pascal Eberhard,
Miquel Raynal, Thomas Petazzoni
In-Reply-To: <20260331152616.197031-1-herve.codina@bootlin.com>
After contributing the driver, add myself as the maintainer for the
Renesas RZ/N1 timers driver.
Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 55af015174a5..5655d8b0c89e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22512,6 +22512,13 @@ S: Maintained
F: Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml
F: drivers/rtc/rtc-rzn1.c
+RENESAS RZ/N1 TIMERS DRIVER
+M: Herve Codina <herve.codina@bootlin.com>
+L: linux-renesas-soc@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/timer/renesas,rzn1-timer.yaml
+F: drivers/clocksource/timer-rzn1.c
+
RENESAS RZ/N1 USBF CONTROLLER DRIVER
M: Herve Codina <herve.codina@bootlin.com>
L: linux-renesas-soc@vger.kernel.org
--
2.53.0
^ permalink raw reply related
* Re: [PATCH RFC 0/2] arm64: dts: qcom: eliza: Add display
From: Krzysztof Kozlowski @ 2026-03-31 15:27 UTC (permalink / raw)
To: Konrad Dybcio, Krzysztof Kozlowski, Bjorn Andersson,
Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Abel Vesa
In-Reply-To: <77ea76fe-7f8c-47d7-a697-3e2fcfd8a8e9@oss.qualcomm.com>
On 31/03/2026 17:23, Konrad Dybcio wrote:
>>> If so, you need that or the lanes won't be properly connected
>>
>> Ha! That would explain, although I had impression that with disabled
>> WCD939x mux the SM8750 DP still works.
>
> I don't know what's the power-on-reset setup, but there is a nonzero
> chance that if your recollections are correct, flipping the cable may
> make it work. But that'd be pure luck.
>
>> Well, I don't have that WCD939x and it is left for other team to finish
>> a bit later, so we can leave the USB DP for now. I will re-visit that
>> when audio progresses.
>
> But.. can't you just copy-paste the sm8750-mtp node and fix up the reset
> pin?
I just wanted to avoid doing concurrent work, but sure, I can try. I'll
test it before sending v2.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 0/4] drm/panel: simple: add Waveshare LCD panels
From: Dmitry Baryshkov @ 2026-03-31 15:36 UTC (permalink / raw)
To: Marek Vasut
Cc: Neil Armstrong, Jessica Zhang, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Thierry Reding, Sam Ravnborg,
Joseph Guo, Marek Vasut, Andrzej Hajda, Robert Foss,
Laurent Pinchart, Jonas Karlman, Jernej Skrabec, dri-devel,
devicetree, linux-kernel
In-Reply-To: <982c4d97-695f-46b0-b819-a0b3d016b12b@mailbox.org>
On Tue, Mar 31, 2026 at 05:11:43AM +0200, Marek Vasut wrote:
> On 3/31/26 3:22 AM, Dmitry Baryshkov wrote:
> > On Tue, 31 Mar 2026 at 00:07, Marek Vasut <marek.vasut@mailbox.org> wrote:
> > >
> > > On 3/30/26 3:25 PM, Dmitry Baryshkov wrote:
> > > > Waveshare have a serie of DSI panel kits with the DPI or LVDS panel
> > > > being attached to the DSI2DPI or DSI2LVDS bridge. Commit 80b0eb11f8e0
> > > > ("dt-bindings: display: panel: Add waveshare DPI panel support")
> > > > described two of them in the bindings and commit 46be11b678e0
> > > > ("drm/panel: simple: Add Waveshare 13.3" panel support") added
> > > > definitions for one of those panels. Add support for the rest of them.
> > > Can we by any chance use the icn6211 driver in tree for this ?
> >
> > As far as I can see, no. Waveshare kits have an extra ASIC in front of
> > ICN6211 / ICN6202, which completely hides all programming. So far the
> > interface is really better expressed by the waveshare,dsi2dpi /
> > dsi2lvds: this way, even if they decide to change the actual
> > implementation (like they did for DPI -> LVDS), we won't have to worry
> > about it for as long as their programming interface remains stable.
> Hmmm, I've seen this before, but I don't think this is extra ASIC. The
> ICN6211 pulls its register settings from EEPROM, does it not ?
The kits that I have at hand don't have I2C EEPROMs. They have 25Q8
QSPI. Also note that neither ICN6211 nor ICN6202 datasheets describe I2C
master interface. It is defined as a purely I2C slave.
The kits have WSVTH01 chip (CPLD?) and 25Q8 QSPI NOR. I assume the
bridge settings are loaded from by the WSVTH01 and programmed into the
ICN bridge.
> But no matter how the ICN loads its configuration, this is not waveshare
> specific. I have another display from another manufacturer here which is
> also ICN6211 that is preprogrammed. Can we instead have some generic-dsi
> display , because I don't think these proprogrammed DSI displays are going
> to be only ICN6211 based and only made by waveshare ?
If it was just about the bridge config, I would completely agree with
you. However if you check the waveshare-dsi.c, you'd notice that it is
not directly related to either of ICN bridges. It controls backlight
and panel regulators.
For the reference, *technically* the signal sequence should be:
DSI host -> ICN6202 -> WSVTH01 -> panel. But describing it this way
would require additional changes to the bridge driver to stop it from
programming the bridge (over the DSI). As such I really assume that it's
easier to omit the ICN bridges from the picture.
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v7 2/5] platform: arm64: Add driver for EC found on Qualcomm reference devices
From: Akhil P Oommen @ 2026-03-31 15:37 UTC (permalink / raw)
To: Anvesh Jain P, Sibi Sankar, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Hans de Goede, Ilpo Järvinen,
Bryan O'Donoghue, Bjorn Andersson, Konrad Dybcio,
Randy Dunlap
Cc: linux-arm-msm, devicetree, linux-kernel, platform-driver-x86,
Maya Matuszczyk, Dmitry Baryshkov, Konrad Dybcio
In-Reply-To: <20260327-add-driver-for-ec-v7-2-7684c915e42c@oss.qualcomm.com>
On 3/27/2026 3:38 PM, Anvesh Jain P wrote:
> From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
>
> Add Embedded controller driver support for Hamoa/Purwa/Glymur qualcomm
> reference boards. It handles fan control, temperature sensors, access
> to EC state changes and supports reporting suspend entry/exit to the
> EC.
>
> Co-developed-by: Maya Matuszczyk <maccraft123mc@gmail.com>
> Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com>
> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Co-developed-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
> Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
> ---
> MAINTAINERS | 8 +
> drivers/platform/arm64/Kconfig | 12 +
> drivers/platform/arm64/Makefile | 1 +
> drivers/platform/arm64/qcom-hamoa-ec.c | 451 +++++++++++++++++++++++++++++++++
> 4 files changed, 472 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 30ca84404976..536dfd9adff4 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -21804,6 +21804,14 @@ F: Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml
> F: drivers/misc/fastrpc.c
> F: include/uapi/misc/fastrpc.h
>
> +QUALCOMM HAMOA EMBEDDED CONTROLLER DRIVER
> +M: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
> +M: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> +L: linux-arm-msm@vger.kernel.org
> +S: Maintained
> +F: Documentation/devicetree/bindings/embedded-controller/qcom,hamoa-ec.yaml
> +F: drivers/platform/arm64/qcom-hamoa-ec.c
> +
> QUALCOMM HEXAGON ARCHITECTURE
> M: Brian Cain <brian.cain@oss.qualcomm.com>
> L: linux-hexagon@vger.kernel.org
> diff --git a/drivers/platform/arm64/Kconfig b/drivers/platform/arm64/Kconfig
> index 10f905d7d6bf..025cdf091f9e 100644
> --- a/drivers/platform/arm64/Kconfig
> +++ b/drivers/platform/arm64/Kconfig
> @@ -90,4 +90,16 @@ config EC_LENOVO_THINKPAD_T14S
>
> Say M or Y here to include this support.
>
> +config EC_QCOM_HAMOA
Enable this in arm64 defconfig?
Anyway, for the whole series:
Tested-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Nice work. I have been looking for a way to force fan always ON since
Hamoa. :)
-Akhil.
> + tristate "Embedded Controller driver for Qualcomm Hamoa/Glymur reference devices"
> + depends on ARCH_QCOM || COMPILE_TEST
> + depends on I2C
> + help
> + Say M or Y here to enable the Embedded Controller driver for Qualcomm
> + Snapdragon-based Hamoa/Glymur reference devices. The driver handles fan
> + control, temperature sensors, access to EC state changes and supports
> + reporting suspend entry/exit to the EC.
> +
> + This driver currently supports Hamoa/Purwa/Glymur reference devices.
> +
> endif # ARM64_PLATFORM_DEVICES
> diff --git a/drivers/platform/arm64/Makefile b/drivers/platform/arm64/Makefile
> index 60c131cff6a1..7681be4a46e9 100644
> --- a/drivers/platform/arm64/Makefile
> +++ b/drivers/platform/arm64/Makefile
> @@ -9,3 +9,4 @@ obj-$(CONFIG_EC_ACER_ASPIRE1) += acer-aspire1-ec.o
> obj-$(CONFIG_EC_HUAWEI_GAOKUN) += huawei-gaokun-ec.o
> obj-$(CONFIG_EC_LENOVO_YOGA_C630) += lenovo-yoga-c630.o
> obj-$(CONFIG_EC_LENOVO_THINKPAD_T14S) += lenovo-thinkpad-t14s.o
> +obj-$(CONFIG_EC_QCOM_HAMOA) += qcom-hamoa-ec.o
> diff --git a/drivers/platform/arm64/qcom-hamoa-ec.c b/drivers/platform/arm64/qcom-hamoa-ec.c
> new file mode 100644
> index 000000000000..0f883130ac9a
> --- /dev/null
> +++ b/drivers/platform/arm64/qcom-hamoa-ec.c
> @@ -0,0 +1,451 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2024 Maya Matuszczyk <maccraft123mc@gmail.com>
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/bits.h>
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/i2c.h>
> +#include <linux/interrupt.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/pm.h>
> +#include <linux/slab.h>
> +#include <linux/thermal.h>
> +
> +#define EC_SCI_EVT_READ_CMD 0x05
> +#define EC_FW_VERSION_CMD 0x0e
> +#define EC_MODERN_STANDBY_CMD 0x23
> +#define EC_FAN_DBG_CONTROL_CMD 0x30
> +#define EC_SCI_EVT_CONTROL_CMD 0x35
> +#define EC_THERMAL_CAP_CMD 0x42
> +
> +#define EC_FW_VERSION_RESP_LEN 4
> +#define EC_THERMAL_CAP_RESP_LEN 3
> +#define EC_FAN_DEBUG_CMD_LEN 6
> +#define EC_FAN_SPEED_DATA_SIZE 4
> +
> +#define EC_MODERN_STANDBY_ENTER 0x01
> +#define EC_MODERN_STANDBY_EXIT 0x00
> +
> +#define EC_FAN_DEBUG_MODE_OFF 0
> +#define EC_FAN_DEBUG_MODE_ON BIT(0)
> +#define EC_FAN_ON BIT(1)
> +#define EC_FAN_DEBUG_TYPE_PWM BIT(2)
> +#define EC_MAX_FAN_CNT 2
> +#define EC_FAN_NAME_SIZE 20
> +#define EC_FAN_MAX_PWM 255
> +
> +enum qcom_ec_sci_events {
> + EC_FAN1_STATUS_CHANGE_EVT = 0x30,
> + EC_FAN2_STATUS_CHANGE_EVT,
> + EC_FAN1_SPEED_CHANGE_EVT,
> + EC_FAN2_SPEED_CHANGE_EVT,
> + EC_NEW_LUT_SET_EVT,
> + EC_FAN_PROFILE_SWITCH_EVT,
> + EC_THERMISTOR_1_THRESHOLD_CROSS_EVT,
> + EC_THERMISTOR_2_THRESHOLD_CROSS_EVT,
> + EC_THERMISTOR_3_THRESHOLD_CROSS_EVT,
> + /* Reserved: 0x39 - 0x3c/0x3f */
> + EC_RECOVERED_FROM_RESET_EVT = 0x3d,
> +};
> +
> +struct qcom_ec_version {
> + u8 main_version;
> + u8 sub_version;
> + u8 test_version;
> +};
> +
> +struct qcom_ec_thermal_cap {
> +#define EC_THERMAL_FAN_CNT(x) (FIELD_GET(GENMASK(1, 0), (x)))
> +#define EC_THERMAL_FAN_TYPE(x) (FIELD_GET(GENMASK(4, 2), (x)))
> +#define EC_THERMAL_THERMISTOR_MASK(x) (FIELD_GET(GENMASK(7, 0), (x)))
> + u8 fan_cnt;
> + u8 fan_type;
> + u8 thermistor_mask;
> +};
> +
> +struct qcom_ec_cooling_dev {
> + struct thermal_cooling_device *cdev;
> + struct device *parent_dev;
> + u8 fan_id;
> + u8 state;
> +};
> +
> +struct qcom_ec {
> + struct qcom_ec_cooling_dev *ec_cdev;
> + struct qcom_ec_thermal_cap thermal_cap;
> + struct qcom_ec_version version;
> + struct i2c_client *client;
> +};
> +
> +static int qcom_ec_read(struct qcom_ec *ec, u8 cmd, u8 resp_len, u8 *resp)
> +{
> + int ret;
> +
> + ret = i2c_smbus_read_i2c_block_data(ec->client, cmd, resp_len, resp);
> +
> + if (ret < 0)
> + return ret;
> + else if (ret == 0 || ret == 0xff)
> + return -EOPNOTSUPP;
> +
> + if (resp[0] >= resp_len)
> + return -EINVAL;
> +
> + return 0;
> +}
> +
> +/*
> + * EC Device Firmware Version:
> + *
> + * Read Response:
> + * ----------------------------------------------------------------------
> + * | Offset | Name | Description |
> + * ----------------------------------------------------------------------
> + * | 0x00 | Byte count | Number of bytes in response |
> + * | | | (excluding byte count) |
> + * ----------------------------------------------------------------------
> + * | 0x01 | Test-version | Test-version of EC firmware |
> + * ----------------------------------------------------------------------
> + * | 0x02 | Sub-version | Sub-version of EC firmware |
> + * ----------------------------------------------------------------------
> + * | 0x03 | Main-version | Main-version of EC firmware |
> + * ----------------------------------------------------------------------
> + *
> + */
> +static int qcom_ec_read_fw_version(struct device *dev)
> +{
> + struct i2c_client *client = to_i2c_client(dev);
> + struct qcom_ec *ec = i2c_get_clientdata(client);
> + struct qcom_ec_version *version = &ec->version;
> + u8 resp[EC_FW_VERSION_RESP_LEN];
> + int ret;
> +
> + ret = qcom_ec_read(ec, EC_FW_VERSION_CMD, EC_FW_VERSION_RESP_LEN, resp);
> + if (ret < 0)
> + return ret;
> +
> + version->main_version = resp[3];
> + version->sub_version = resp[2];
> + version->test_version = resp[1];
> +
> + dev_dbg(dev, "EC Version %d.%d.%d\n",
> + version->main_version, version->sub_version, version->test_version);
> +
> + return 0;
> +}
> +
> +/*
> + * EC Device Thermal Capabilities:
> + *
> + * Read Response:
> + * ------------------------------------------------------------------------------
> + * | Offset | Name | Description |
> + * ------------------------------------------------------------------------------
> + * | 0x00 | Byte count | Number of bytes in response |
> + * | | | (excluding byte count) |
> + * ------------------------------------------------------------------------------
> + * | 0x02 (LSB) | EC Thermal | Bit 0-1: Number of fans |
> + * | 0x3 | Capabilities | Bit 2-4: Type of fan |
> + * | | | Bit 5-6: Reserved |
> + * | | | Bit 7: Data Valid/Invalid |
> + * | | | (Valid - 1, Invalid - 0) |
> + * | | | Bit 8-15: Thermistor 0 - 7 presence |
> + * | | | (1 present, 0 absent) |
> + * ------------------------------------------------------------------------------
> + *
> + */
> +static int qcom_ec_thermal_capabilities(struct device *dev)
> +{
> + struct i2c_client *client = to_i2c_client(dev);
> + struct qcom_ec *ec = i2c_get_clientdata(client);
> + struct qcom_ec_thermal_cap *cap = &ec->thermal_cap;
> + u8 resp[EC_THERMAL_CAP_RESP_LEN];
> + int ret;
> +
> + ret = qcom_ec_read(ec, EC_THERMAL_CAP_CMD, EC_THERMAL_CAP_RESP_LEN, resp);
> + if (ret < 0)
> + return ret;
> +
> + cap->fan_cnt = min(EC_MAX_FAN_CNT, EC_THERMAL_FAN_CNT(resp[1]));
> + cap->fan_type = EC_THERMAL_FAN_TYPE(resp[1]);
> + cap->thermistor_mask = EC_THERMAL_THERMISTOR_MASK(resp[2]);
> +
> + dev_dbg(dev, "Fan count: %d Fan Type: %d Thermistor Mask: %x\n",
> + cap->fan_cnt, cap->fan_type, cap->thermistor_mask);
> +
> + return 0;
> +}
> +
> +static irqreturn_t qcom_ec_irq(int irq, void *data)
> +{
> + struct qcom_ec *ec = data;
> + struct device *dev = &ec->client->dev;
> + int val;
> +
> + val = i2c_smbus_read_byte_data(ec->client, EC_SCI_EVT_READ_CMD);
> + if (val < 0) {
> + dev_err_ratelimited(dev, "Failed to read EC SCI Event: %d\n", val);
> + return IRQ_HANDLED;
> + }
> +
> + switch (val) {
> + case EC_FAN1_STATUS_CHANGE_EVT:
> + dev_dbg_ratelimited(dev, "Fan1 status changed\n");
> + break;
> + case EC_FAN2_STATUS_CHANGE_EVT:
> + dev_dbg_ratelimited(dev, "Fan2 status changed\n");
> + break;
> + case EC_FAN1_SPEED_CHANGE_EVT:
> + dev_dbg_ratelimited(dev, "Fan1 speed crossed low/high trip point\n");
> + break;
> + case EC_FAN2_SPEED_CHANGE_EVT:
> + dev_dbg_ratelimited(dev, "Fan2 speed crossed low/high trip point\n");
> + break;
> + case EC_NEW_LUT_SET_EVT:
> + dev_dbg_ratelimited(dev, "New LUT set\n");
> + break;
> + case EC_FAN_PROFILE_SWITCH_EVT:
> + dev_dbg_ratelimited(dev, "FAN Profile switched\n");
> + break;
> + case EC_THERMISTOR_1_THRESHOLD_CROSS_EVT:
> + dev_dbg_ratelimited(dev, "Thermistor 1 threshold crossed\n");
> + break;
> + case EC_THERMISTOR_2_THRESHOLD_CROSS_EVT:
> + dev_dbg_ratelimited(dev, "Thermistor 2 threshold crossed\n");
> + break;
> + case EC_THERMISTOR_3_THRESHOLD_CROSS_EVT:
> + dev_dbg_ratelimited(dev, "Thermistor 3 threshold crossed\n");
> + break;
> + case EC_RECOVERED_FROM_RESET_EVT:
> + dev_dbg_ratelimited(dev, "EC recovered from reset\n");
> + break;
> + default:
> + dev_notice_ratelimited(dev, "Unknown EC event: %d\n", val);
> + break;
> + }
> +
> + return IRQ_HANDLED;
> +}
> +
> +static int qcom_ec_sci_evt_control(struct device *dev, bool enable)
> +{
> + struct i2c_client *client = to_i2c_client(dev);
> +
> + return i2c_smbus_write_byte_data(client, EC_SCI_EVT_CONTROL_CMD, !!enable);
> +}
> +
> +static int qcom_ec_fan_get_max_state(struct thermal_cooling_device *cdev, unsigned long *state)
> +{
> + *state = EC_FAN_MAX_PWM;
> +
> + return 0;
> +}
> +
> +static int qcom_ec_fan_get_cur_state(struct thermal_cooling_device *cdev, unsigned long *state)
> +{
> + struct qcom_ec_cooling_dev *ec_cdev = cdev->devdata;
> +
> + *state = ec_cdev->state;
> +
> + return 0;
> +}
> +
> +/*
> + * Fan Debug control command:
> + *
> + * Command Payload:
> + * --------------------------------------------------------------------------------------
> + * | Offset | Name | Description |
> + * --------------------------------------------------------------------------------------
> + * | 0x00 | Command | Fan control command |
> + * --------------------------------------------------------------------------------------
> + * | 0x01 | Fan ID | 0x1 : Fan 1 |
> + * | | | 0x2 : Fan 2 |
> + * --------------------------------------------------------------------------------------
> + * | 0x02 | Byte count = 4| Size of data to set fan speed |
> + * --------------------------------------------------------------------------------------
> + * | 0x03 | Mode | Bit 0: Debug Mode On/Off (0 - OFF, 1 - ON ) |
> + * | | | Bit 1: Fan On/Off (0 - Off, 1 - ON) |
> + * | | | Bit 2: Debug Type (0 - RPM, 1 - PWM) |
> + * --------------------------------------------------------------------------------------
> + * | 0x04 (LSB) | Speed in RPM | RPM value, if mode selected is RPM |
> + * | 0x05 | | |
> + * --------------------------------------------------------------------------------------
> + * | 0x06 | Speed in PWM | PWM value, if mode selected is PWM (0 - 255) |
> + * ______________________________________________________________________________________
> + *
> + */
> +static int qcom_ec_fan_debug_mode_off(struct qcom_ec_cooling_dev *ec_cdev)
> +{
> + struct device *dev = ec_cdev->parent_dev;
> + struct i2c_client *client = to_i2c_client(dev);
> + u8 request[6] = { ec_cdev->fan_id, EC_FAN_SPEED_DATA_SIZE,
> + EC_FAN_DEBUG_MODE_OFF, 0, 0, 0 };
> + int ret;
> +
> + ret = i2c_smbus_write_i2c_block_data(client, EC_FAN_DBG_CONTROL_CMD,
> + sizeof(request), request);
> + if (ret) {
> + dev_err(dev, "Failed to turn off fan%d debug mode: %d\n",
> + ec_cdev->fan_id, ret);
> + }
> +
> + return ret;
> +}
> +
> +static int qcom_ec_fan_set_cur_state(struct thermal_cooling_device *cdev, unsigned long state)
> +{
> + struct qcom_ec_cooling_dev *ec_cdev = cdev->devdata;
> + struct device *dev = ec_cdev->parent_dev;
> + struct i2c_client *client = to_i2c_client(dev);
> + u8 request[6] = { ec_cdev->fan_id, EC_FAN_SPEED_DATA_SIZE,
> + EC_FAN_DEBUG_MODE_ON | EC_FAN_ON | EC_FAN_DEBUG_TYPE_PWM,
> + 0, 0, state };
> + int ret;
> +
> + ret = i2c_smbus_write_i2c_block_data(client, EC_FAN_DBG_CONTROL_CMD,
> + sizeof(request), request);
> + if (ret) {
> + dev_err(dev, "Failed to set fan pwm: %d\n", ret);
> + return ret;
> + }
> +
> + ec_cdev->state = state;
> +
> + return 0;
> +}
> +
> +static const struct thermal_cooling_device_ops qcom_ec_thermal_ops = {
> + .get_max_state = qcom_ec_fan_get_max_state,
> + .get_cur_state = qcom_ec_fan_get_cur_state,
> + .set_cur_state = qcom_ec_fan_set_cur_state,
> +};
> +
> +static int qcom_ec_resume(struct device *dev)
> +{
> + struct i2c_client *client = to_i2c_client(dev);
> +
> + return i2c_smbus_write_byte_data(client, EC_MODERN_STANDBY_CMD,
> + EC_MODERN_STANDBY_ENTER);
> +}
> +
> +static int qcom_ec_suspend(struct device *dev)
> +{
> + struct i2c_client *client = to_i2c_client(dev);
> +
> + return i2c_smbus_write_byte_data(client, EC_MODERN_STANDBY_CMD,
> + EC_MODERN_STANDBY_EXIT);
> +}
> +
> +static int qcom_ec_probe(struct i2c_client *client)
> +{
> + struct device *dev = &client->dev;
> + struct qcom_ec *ec;
> + unsigned int i;
> + int ret;
> +
> + ec = devm_kzalloc(dev, sizeof(*ec), GFP_KERNEL);
> + if (!ec)
> + return -ENOMEM;
> +
> + ec->client = client;
> +
> + ret = devm_request_threaded_irq(dev, client->irq, NULL, qcom_ec_irq,
> + IRQF_ONESHOT, "qcom_ec", ec);
> + if (ret < 0)
> + return ret;
> +
> + i2c_set_clientdata(client, ec);
> +
> + ret = qcom_ec_read_fw_version(dev);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "Failed to read EC firmware version\n");
> +
> + ret = qcom_ec_sci_evt_control(dev, true);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "Failed to enable SCI events\n");
> +
> + ret = qcom_ec_thermal_capabilities(dev);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "Failed to read thermal capabilities\n");
> +
> + if (ec->thermal_cap.fan_cnt == 0) {
> + dev_warn(dev, FW_BUG "Failed to get fan count, firmware update required\n");
> + return 0;
> + }
> +
> + ec->ec_cdev = devm_kcalloc(dev, ec->thermal_cap.fan_cnt, sizeof(*ec->ec_cdev), GFP_KERNEL);
> + if (!ec->ec_cdev)
> + return -ENOMEM;
> +
> + for (i = 0; i < ec->thermal_cap.fan_cnt; i++) {
> + struct qcom_ec_cooling_dev *ec_cdev = &ec->ec_cdev[i];
> + char name[EC_FAN_NAME_SIZE];
> +
> + scnprintf(name, sizeof(name), "qcom_ec_fan_%u", i);
> + ec_cdev->fan_id = i + 1;
> + ec_cdev->parent_dev = dev;
> +
> + ec_cdev->cdev = devm_thermal_of_cooling_device_register(dev, NULL, name, ec_cdev,
> + &qcom_ec_thermal_ops);
> + if (IS_ERR(ec_cdev->cdev)) {
> + return dev_err_probe(dev, PTR_ERR(ec_cdev->cdev),
> + "Failed to register fan%d cooling device\n", i);
> + }
> + }
> +
> + return 0;
> +}
> +
> +static void qcom_ec_remove(struct i2c_client *client)
> +{
> + struct qcom_ec *ec = i2c_get_clientdata(client);
> + struct device *dev = &client->dev;
> + int ret;
> +
> + ret = qcom_ec_sci_evt_control(dev, false);
> + if (ret < 0)
> + dev_err(dev, "Failed to disable SCI events: %d\n", ret);
> +
> + for (int i = 0; i < ec->thermal_cap.fan_cnt; i++) {
> + struct qcom_ec_cooling_dev *ec_cdev = &ec->ec_cdev[i];
> +
> + qcom_ec_fan_debug_mode_off(ec_cdev);
> + }
> +}
> +
> +static const struct of_device_id qcom_ec_of_match[] = {
> + { .compatible = "qcom,hamoa-crd-ec" },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, qcom_ec_of_match);
> +
> +static const struct i2c_device_id qcom_ec_i2c_id_table[] = {
> + { "qcom-hamoa-ec", },
> + {}
> +};
> +MODULE_DEVICE_TABLE(i2c, qcom_ec_i2c_id_table);
> +
> +static DEFINE_SIMPLE_DEV_PM_OPS(qcom_ec_pm_ops,
> + qcom_ec_suspend,
> + qcom_ec_resume);
> +
> +static struct i2c_driver qcom_ec_i2c_driver = {
> + .driver = {
> + .name = "qcom-hamoa-ec",
> + .of_match_table = qcom_ec_of_match,
> + .pm = &qcom_ec_pm_ops
> + },
> + .probe = qcom_ec_probe,
> + .remove = qcom_ec_remove,
> + .id_table = qcom_ec_i2c_id_table,
> +};
> +module_i2c_driver(qcom_ec_i2c_driver);
> +
> +MODULE_DESCRIPTION("QCOM Hamoa Embedded Controller");
> +MODULE_LICENSE("GPL");
>
^ permalink raw reply
* [PATCH v6 00/11] Add support for the TI BQ25792 battery charger
From: Alexey Charkov @ 2026-03-31 15:43 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chris Morgan, Liam Girdwood, Mark Brown, Sebastian Reichel
Cc: devicetree, linux-kernel, Sebastian Reichel, linux-pm,
Alexey Charkov, Krzysztof Kozlowski, stable
This adds support for the TI BQ25792 battery charger, which is similar in
overall logic to the BQ25703A, but has a different register layout and
slightly different lower-level programming logic.
The series is organized as follows:
- Patch 1 adds the new variant to the existing DT binding, including the
changes in electrical characteristics
- Patches 2-4 are minor cleanups to the existing BQ25703A OTG regulator
driver, slimming down the code and making it more reusable for the new
BQ25792 variant
- Patch 5 is a logical fix to the BQ25703A clamping logic for VSYSMIN
(this is a standalone fix which can be applied independently and may be
backported to stable)
- Patches 6-8 are slight refactoring of the existing BQ25703A charger
driver to make it more reusable for the new BQ25792 variant
- Patch 9 adds platform data to distinguish between the two variants in
the parent MFD driver, and binds it to the new compatible string
- Patches 10-11 add variant-specific code to support the new BQ25792
variant in the regulator part and the charger part respectively,
selected by the platform data added in patch 9
Signed-off-by: Alexey Charkov <alchark@flipper.net>
---
Changes in v6:
- Changed -EINVAL to -ENODEV for non-match cases in the MFD driver, to stay
in line with what other drivers do in similar situations (Lee Jones)
- Link to v5: https://lore.kernel.org/r/20260324-bq25792-v5-0-0a2eb58cf11d@flipper.net
Changes in v5:
- Added non-OF match data and switched to i2c_get_match_data() to support
non-OF platforms (Lee Jones)
- Shifted the types in the enum to start at 1 to avoid confusion with
zero-initialized data and non-match cases (Lee Jones)
- Reinstated the const qualifier on the MFD cell array (Lee Jones)
- Link to v4: https://lore.kernel.org/r/20260311-bq25792-v4-0-7213415d9eec@flipper.net
Changes in v4:
- Avoid additional data structures and pass 'type' within the existing
struct bq257xx_device instead (Lee Jones)
- Move comments for new struct fields to the patches where those fields
are added (Sebastian Reichel)
- Collect tags from Sebastian Reichel (thanks!)
- Link to v3: https://lore.kernel.org/r/20260310-bq25792-v3-0-02f8e232d63b@flipper.net
Changes in v3:
- Move MFD cell definitions back out of the probe function (Lee Jones)
- Collect tags from Mark Brown, Krzysztof Kozlowski and Chris Morgan (thanks!)
- Enable ship FET functionality at init for BQ25792
- Link to v2: https://lore.kernel.org/r/20260306-bq25792-v2-0-6595249d6e6f@flipper.net
Changes in v2:
- Fix an error in DT schema (thanks Rob's bot)
- Ensure the broadest constraints for all variants remain in the common
part of the schema, per writing-schema doc (thanks Krzysztof)
- Link to v1: https://lore.kernel.org/r/20260303-bq25792-v1-0-e6e5e0033458@flipper.net
---
Alexey Charkov (11):
dt-bindings: mfd: ti,bq25703a: Expand to include BQ25792
regulator: bq257xx: Remove reference to the parent MFD's dev
regulator: bq257xx: Drop the regulator_dev from the driver data
regulator: bq257xx: Make OTG enable GPIO really optional
power: supply: bq257xx: Fix VSYSMIN clamping logic
power: supply: bq257xx: Make the default current limit a per-chip attribute
power: supply: bq257xx: Consistently use indirect get/set helpers
power: supply: bq257xx: Add fields for 'charging' and 'overvoltage' states
mfd: bq257xx: Add BQ25792 support
regulator: bq257xx: Add support for BQ25792
power: supply: bq257xx: Add support for BQ25792
.../devicetree/bindings/mfd/ti,bq25703a.yaml | 73 ++-
drivers/mfd/bq257xx.c | 54 ++-
drivers/power/supply/bq257xx_charger.c | 534 ++++++++++++++++++++-
drivers/regulator/bq257xx-regulator.c | 121 ++++-
include/linux/mfd/bq257xx.h | 412 ++++++++++++++++
5 files changed, 1156 insertions(+), 38 deletions(-)
---
base-commit: 36ece9697e89016181e5ae87510e40fb31d86f2b
change-id: 20260303-bq25792-0132ac86846d
Best regards,
--
Alexey Charkov <alchark@flipper.net>
^ permalink raw reply
* [PATCH v6 01/11] dt-bindings: mfd: ti,bq25703a: Expand to include BQ25792
From: Alexey Charkov @ 2026-03-31 15:43 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chris Morgan, Liam Girdwood, Mark Brown, Sebastian Reichel
Cc: devicetree, linux-kernel, Sebastian Reichel, linux-pm,
Alexey Charkov, Krzysztof Kozlowski
In-Reply-To: <20260331-bq25792-v6-0-0278fba33eb9@flipper.net>
TI BQ25792 is similar in operation to BQ25703A, but has a different
register layout and different current/voltage capabilities.
Expand the existing BQ25703A binding to include BQ25792, and move the
voltage and current limits into per-variant conditional statements.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Tested-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Alexey Charkov <alchark@flipper.net>
---
.../devicetree/bindings/mfd/ti,bq25703a.yaml | 73 +++++++++++++++++++---
1 file changed, 63 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/mfd/ti,bq25703a.yaml b/Documentation/devicetree/bindings/mfd/ti,bq25703a.yaml
index ba14663c9266..cdce83f05804 100644
--- a/Documentation/devicetree/bindings/mfd/ti,bq25703a.yaml
+++ b/Documentation/devicetree/bindings/mfd/ti,bq25703a.yaml
@@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/mfd/ti,bq25703a.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: BQ25703A Charger Manager/Buck/Boost Converter
+title: BQ257xx Charger Manager/Buck/Boost Converter
maintainers:
- Chris Morgan <macromorgan@hotmail.com>
-allOf:
- - $ref: /schemas/power/supply/power-supply.yaml#
-
properties:
compatible:
- const: ti,bq25703a
+ enum:
+ - ti,bq25703a
+ - ti,bq25792
reg:
const: 0x6b
@@ -25,7 +24,6 @@ properties:
powering the device.
minimum: 50000
maximum: 6400000
- default: 3250000
interrupts:
maxItems: 1
@@ -57,11 +55,11 @@ properties:
minimum: 0
maximum: 6350000
regulator-min-microvolt:
- minimum: 4480000
- maximum: 20800000
+ minimum: 2800000
+ maximum: 22000000
regulator-max-microvolt:
- minimum: 4480000
- maximum: 20800000
+ minimum: 2800000
+ maximum: 22000000
enable-gpios:
description:
The BQ25703 may require both a register write and a GPIO
@@ -74,6 +72,61 @@ properties:
- regulator-min-microvolt
- regulator-max-microvolt
+allOf:
+ - $ref: /schemas/power/supply/power-supply.yaml#
+ - if:
+ properties:
+ compatible:
+ const: ti,bq25703a
+ then:
+ properties:
+ input-current-limit-microamp:
+ minimum: 50000
+ maximum: 6400000
+ default: 3250000
+ regulators:
+ properties:
+ vbus:
+ properties:
+ regulator-min-microamp:
+ minimum: 0
+ maximum: 6350000
+ regulator-max-microamp:
+ minimum: 0
+ maximum: 6350000
+ regulator-min-microvolt:
+ minimum: 4480000
+ maximum: 20800000
+ regulator-max-microvolt:
+ minimum: 4480000
+ maximum: 20800000
+ - if:
+ properties:
+ compatible:
+ const: ti,bq25792
+ then:
+ properties:
+ input-current-limit-microamp:
+ minimum: 100000
+ maximum: 3300000
+ default: 3000000
+ regulators:
+ properties:
+ vbus:
+ properties:
+ regulator-min-microamp:
+ minimum: 0
+ maximum: 3320000
+ regulator-max-microamp:
+ minimum: 0
+ maximum: 3320000
+ regulator-min-microvolt:
+ minimum: 2800000
+ maximum: 22000000
+ regulator-max-microvolt:
+ minimum: 2800000
+ maximum: 22000000
+
unevaluatedProperties: false
required:
--
2.52.0
^ permalink raw reply related
* [PATCH v6 02/11] regulator: bq257xx: Remove reference to the parent MFD's dev
From: Alexey Charkov @ 2026-03-31 15:43 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chris Morgan, Liam Girdwood, Mark Brown, Sebastian Reichel
Cc: devicetree, linux-kernel, Sebastian Reichel, linux-pm,
Alexey Charkov
In-Reply-To: <20260331-bq25792-v6-0-0278fba33eb9@flipper.net>
Drop the ->bq field from the platform data of the bq257xx regulator driver,
which was only used to get the regmap of the parent MFD device, and use the
regmap from the regulator_dev instead, slimming down the code a bit.
Acked-by: Mark Brown <broonie@kernel.org>
Tested-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Alexey Charkov <alchark@flipper.net>
---
drivers/regulator/bq257xx-regulator.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/regulator/bq257xx-regulator.c b/drivers/regulator/bq257xx-regulator.c
index dab8f1ab4450..812938e565e3 100644
--- a/drivers/regulator/bq257xx-regulator.c
+++ b/drivers/regulator/bq257xx-regulator.c
@@ -15,7 +15,6 @@
#include <linux/regulator/of_regulator.h>
struct bq257xx_reg_data {
- struct bq257xx_device *bq;
struct regulator_dev *bq257xx_reg;
struct gpio_desc *otg_en_gpio;
struct regulator_desc desc;
@@ -23,11 +22,11 @@ struct bq257xx_reg_data {
static int bq25703_vbus_get_cur_limit(struct regulator_dev *rdev)
{
- struct bq257xx_reg_data *pdata = rdev_get_drvdata(rdev);
+ struct regmap *regmap = rdev_get_regmap(rdev);
int ret;
unsigned int reg;
- ret = regmap_read(pdata->bq->regmap, BQ25703_OTG_CURRENT, ®);
+ ret = regmap_read(regmap, BQ25703_OTG_CURRENT, ®);
if (ret)
return ret;
return FIELD_GET(BQ25703_OTG_CUR_MASK, reg) * BQ25703_OTG_CUR_STEP_UA;
@@ -40,7 +39,7 @@ static int bq25703_vbus_get_cur_limit(struct regulator_dev *rdev)
static int bq25703_vbus_set_cur_limit(struct regulator_dev *rdev,
int min_uA, int max_uA)
{
- struct bq257xx_reg_data *pdata = rdev_get_drvdata(rdev);
+ struct regmap *regmap = rdev_get_regmap(rdev);
unsigned int reg;
if ((min_uA > BQ25703_OTG_CUR_MAX_UA) || (max_uA < 0))
@@ -52,7 +51,7 @@ static int bq25703_vbus_set_cur_limit(struct regulator_dev *rdev,
if ((reg * BQ25703_OTG_CUR_STEP_UA) < min_uA)
return -EINVAL;
- return regmap_write(pdata->bq->regmap, BQ25703_OTG_CURRENT,
+ return regmap_write(regmap, BQ25703_OTG_CURRENT,
FIELD_PREP(BQ25703_OTG_CUR_MASK, reg));
}
@@ -137,7 +136,6 @@ static void bq257xx_reg_dt_parse_gpio(struct platform_device *pdev)
static int bq257xx_regulator_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
- struct bq257xx_device *bq = dev_get_drvdata(pdev->dev.parent);
struct bq257xx_reg_data *pdata;
struct device_node *np = dev->of_node;
struct regulator_config cfg = {};
@@ -149,7 +147,6 @@ static int bq257xx_regulator_probe(struct platform_device *pdev)
if (!pdata)
return -ENOMEM;
- pdata->bq = bq;
pdata->desc = bq25703_vbus_desc;
platform_set_drvdata(pdev, pdata);
--
2.52.0
^ permalink raw reply related
* [PATCH v6 03/11] regulator: bq257xx: Drop the regulator_dev from the driver data
From: Alexey Charkov @ 2026-03-31 15:43 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chris Morgan, Liam Girdwood, Mark Brown, Sebastian Reichel
Cc: devicetree, linux-kernel, Sebastian Reichel, linux-pm,
Alexey Charkov
In-Reply-To: <20260331-bq25792-v6-0-0278fba33eb9@flipper.net>
The field was not used anywhere in the driver, so just drop it. This helps
further slim down the platform data structure.
Acked-by: Mark Brown <broonie@kernel.org>
Tested-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Alexey Charkov <alchark@flipper.net>
---
drivers/regulator/bq257xx-regulator.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/regulator/bq257xx-regulator.c b/drivers/regulator/bq257xx-regulator.c
index 812938e565e3..674dae6109e9 100644
--- a/drivers/regulator/bq257xx-regulator.c
+++ b/drivers/regulator/bq257xx-regulator.c
@@ -15,7 +15,6 @@
#include <linux/regulator/of_regulator.h>
struct bq257xx_reg_data {
- struct regulator_dev *bq257xx_reg;
struct gpio_desc *otg_en_gpio;
struct regulator_desc desc;
};
@@ -139,6 +138,7 @@ static int bq257xx_regulator_probe(struct platform_device *pdev)
struct bq257xx_reg_data *pdata;
struct device_node *np = dev->of_node;
struct regulator_config cfg = {};
+ struct regulator_dev *rdev;
pdev->dev.of_node = pdev->dev.parent->of_node;
pdev->dev.of_node_reused = true;
@@ -159,9 +159,9 @@ static int bq257xx_regulator_probe(struct platform_device *pdev)
if (!cfg.regmap)
return -ENODEV;
- pdata->bq257xx_reg = devm_regulator_register(dev, &pdata->desc, &cfg);
- if (IS_ERR(pdata->bq257xx_reg)) {
- return dev_err_probe(&pdev->dev, PTR_ERR(pdata->bq257xx_reg),
+ rdev = devm_regulator_register(dev, &pdata->desc, &cfg);
+ if (IS_ERR(rdev)) {
+ return dev_err_probe(&pdev->dev, PTR_ERR(rdev),
"error registering bq257xx regulator");
}
--
2.52.0
^ permalink raw reply related
* [PATCH v6 04/11] regulator: bq257xx: Make OTG enable GPIO really optional
From: Alexey Charkov @ 2026-03-31 15:43 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chris Morgan, Liam Girdwood, Mark Brown, Sebastian Reichel
Cc: devicetree, linux-kernel, Sebastian Reichel, linux-pm,
Alexey Charkov
In-Reply-To: <20260331-bq25792-v6-0-0278fba33eb9@flipper.net>
The bindings describe the OTG enable GPIO as optional, but the driver
gets upset if it's not provided in the device tree.
Make the driver accept the absence of the GPIO, and just use register
writes to handle OTG mode in that case, skipping the error message for
-ENOENT.
Acked-by: Mark Brown <broonie@kernel.org>
Tested-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Alexey Charkov <alchark@flipper.net>
---
drivers/regulator/bq257xx-regulator.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/regulator/bq257xx-regulator.c b/drivers/regulator/bq257xx-regulator.c
index 674dae6109e9..0bb58ab4b8d4 100644
--- a/drivers/regulator/bq257xx-regulator.c
+++ b/drivers/regulator/bq257xx-regulator.c
@@ -126,6 +126,12 @@ static void bq257xx_reg_dt_parse_gpio(struct platform_device *pdev)
of_node_put(subchild);
if (IS_ERR(pdata->otg_en_gpio)) {
+ if (PTR_ERR(pdata->otg_en_gpio) == -ENOENT) {
+ /* No GPIO, will only use register writes for OTG */
+ pdata->otg_en_gpio = NULL;
+ return;
+ }
+
dev_err(&pdev->dev, "Error getting enable gpio: %ld\n",
PTR_ERR(pdata->otg_en_gpio));
return;
--
2.52.0
^ permalink raw reply related
* [PATCH v6 05/11] power: supply: bq257xx: Fix VSYSMIN clamping logic
From: Alexey Charkov @ 2026-03-31 15:43 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chris Morgan, Liam Girdwood, Mark Brown, Sebastian Reichel
Cc: devicetree, linux-kernel, Sebastian Reichel, linux-pm,
Alexey Charkov, stable
In-Reply-To: <20260331-bq25792-v6-0-0278fba33eb9@flipper.net>
The minimal system voltage (VSYSMIN) is meant to protect the battery from
dangerous over-discharge. When the device tree provides a value for the
minimum design voltage of the battery, the user should not be allowed to
set a lower VSYSMIN, as that would defeat the purpose of this protection.
Flip the clamping logic when setting VSYSMIN to ensure that battery design
voltage is respected.
Cc: stable@vger.kernel.org
Fixes: 1cc017b7f9c7 ("power: supply: bq257xx: Add support for BQ257XX charger")
Tested-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Alexey Charkov <alchark@flipper.net>
---
drivers/power/supply/bq257xx_charger.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/power/supply/bq257xx_charger.c b/drivers/power/supply/bq257xx_charger.c
index 02c7d8b61e82..7ca4ae610902 100644
--- a/drivers/power/supply/bq257xx_charger.c
+++ b/drivers/power/supply/bq257xx_charger.c
@@ -128,9 +128,8 @@ static int bq25703_get_min_vsys(struct bq257xx_chg *pdata, int *intval)
* @vsys: voltage value to set in uV.
*
* This function takes a requested minimum system voltage value, clamps
- * it between the minimum supported value by the charger and a user
- * defined minimum system value, and then writes the value to the
- * appropriate register.
+ * it between the user defined minimum system value and the maximum supported
+ * value by the charger, and then writes the value to the appropriate register.
*
* Return: Returns 0 on success or error if an error occurs.
*/
@@ -139,7 +138,7 @@ static int bq25703_set_min_vsys(struct bq257xx_chg *pdata, int vsys)
unsigned int reg;
int vsys_min = pdata->vsys_min;
- vsys = clamp(vsys, BQ25703_MINVSYS_MIN_UV, vsys_min);
+ vsys = clamp(vsys, vsys_min, BQ25703_MINVSYS_MAX_UV);
reg = ((vsys - BQ25703_MINVSYS_MIN_UV) / BQ25703_MINVSYS_STEP_UV);
reg = FIELD_PREP(BQ25703_MINVSYS_MASK, reg);
--
2.52.0
^ permalink raw reply related
* [PATCH v6 06/11] power: supply: bq257xx: Make the default current limit a per-chip attribute
From: Alexey Charkov @ 2026-03-31 15:43 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chris Morgan, Liam Girdwood, Mark Brown, Sebastian Reichel
Cc: devicetree, linux-kernel, Sebastian Reichel, linux-pm,
Alexey Charkov
In-Reply-To: <20260331-bq25792-v6-0-0278fba33eb9@flipper.net>
Add a field for the default current limit to the bq257xx_info structure and
use it instead of the hardcoded value in the probe function.
This prepares the driver for allowing different electrical constraints for
different chip variants.
Tested-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Alexey Charkov <alchark@flipper.net>
---
drivers/power/supply/bq257xx_charger.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/power/supply/bq257xx_charger.c b/drivers/power/supply/bq257xx_charger.c
index 7ca4ae610902..39718223c3f9 100644
--- a/drivers/power/supply/bq257xx_charger.c
+++ b/drivers/power/supply/bq257xx_charger.c
@@ -18,6 +18,7 @@ struct bq257xx_chg;
/**
* struct bq257xx_chip_info - chip specific routines
+ * @default_iindpm_uA: default input current limit in microamps
* @bq257xx_hw_init: init function for hw
* @bq257xx_hw_shutdown: shutdown function for hw
* @bq257xx_get_state: get and update state of hardware
@@ -26,6 +27,7 @@ struct bq257xx_chg;
* @bq257xx_set_iindpm: set maximum input current (in uA)
*/
struct bq257xx_chip_info {
+ int default_iindpm_uA;
int (*bq257xx_hw_init)(struct bq257xx_chg *pdata);
void (*bq257xx_hw_shutdown)(struct bq257xx_chg *pdata);
int (*bq257xx_get_state)(struct bq257xx_chg *pdata);
@@ -627,6 +629,7 @@ static const struct power_supply_desc bq257xx_power_supply_desc = {
};
static const struct bq257xx_chip_info bq25703_chip_info = {
+ .default_iindpm_uA = BQ25703_IINDPM_DEFAULT_UA,
.bq257xx_hw_init = &bq25703_hw_init,
.bq257xx_hw_shutdown = &bq25703_hw_shutdown,
.bq257xx_get_state = &bq25703_get_state,
@@ -675,7 +678,7 @@ static int bq257xx_parse_dt(struct bq257xx_chg *pdata,
"input-current-limit-microamp",
&pdata->iindpm_max);
if (ret)
- pdata->iindpm_max = BQ25703_IINDPM_DEFAULT_UA;
+ pdata->iindpm_max = pdata->chip->default_iindpm_uA;
return 0;
}
--
2.52.0
^ permalink raw reply related
* [PATCH v6 07/11] power: supply: bq257xx: Consistently use indirect get/set helpers
From: Alexey Charkov @ 2026-03-31 15:43 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chris Morgan, Liam Girdwood, Mark Brown, Sebastian Reichel
Cc: devicetree, linux-kernel, Sebastian Reichel, linux-pm,
Alexey Charkov
In-Reply-To: <20260331-bq25792-v6-0-0278fba33eb9@flipper.net>
Move the remaining get/set helper functions to indirect calls via the
per-chip bq257xx_chip_info struct.
This improves the consistency of the code and prepares the driver to
support multiple chip variants with different register layouts and bit
definitions.
Tested-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Alexey Charkov <alchark@flipper.net>
---
drivers/power/supply/bq257xx_charger.c | 30 ++++++++++++++++++++++++------
1 file changed, 24 insertions(+), 6 deletions(-)
diff --git a/drivers/power/supply/bq257xx_charger.c b/drivers/power/supply/bq257xx_charger.c
index 39718223c3f9..0765673728e4 100644
--- a/drivers/power/supply/bq257xx_charger.c
+++ b/drivers/power/supply/bq257xx_charger.c
@@ -22,18 +22,30 @@ struct bq257xx_chg;
* @bq257xx_hw_init: init function for hw
* @bq257xx_hw_shutdown: shutdown function for hw
* @bq257xx_get_state: get and update state of hardware
+ * @bq257xx_get_ichg: get maximum charge current (in uA)
* @bq257xx_set_ichg: set maximum charge current (in uA)
+ * @bq257xx_get_vbatreg: get maximum charge voltage (in uV)
* @bq257xx_set_vbatreg: set maximum charge voltage (in uV)
+ * @bq257xx_get_iindpm: get maximum input current (in uA)
* @bq257xx_set_iindpm: set maximum input current (in uA)
+ * @bq257xx_get_cur: get battery current from ADC (in uA)
+ * @bq257xx_get_vbat: get battery voltage from ADC (in uV)
+ * @bq257xx_get_min_vsys: get minimum system voltage (in uV)
*/
struct bq257xx_chip_info {
int default_iindpm_uA;
int (*bq257xx_hw_init)(struct bq257xx_chg *pdata);
void (*bq257xx_hw_shutdown)(struct bq257xx_chg *pdata);
int (*bq257xx_get_state)(struct bq257xx_chg *pdata);
+ int (*bq257xx_get_ichg)(struct bq257xx_chg *pdata, int *intval);
int (*bq257xx_set_ichg)(struct bq257xx_chg *pdata, int ichg);
+ int (*bq257xx_get_vbatreg)(struct bq257xx_chg *pdata, int *intval);
int (*bq257xx_set_vbatreg)(struct bq257xx_chg *pdata, int vbatreg);
+ int (*bq257xx_get_iindpm)(struct bq257xx_chg *pdata, int *intval);
int (*bq257xx_set_iindpm)(struct bq257xx_chg *pdata, int iindpm);
+ int (*bq257xx_get_cur)(struct bq257xx_chg *pdata, int *intval);
+ int (*bq257xx_get_vbat)(struct bq257xx_chg *pdata, int *intval);
+ int (*bq257xx_get_min_vsys)(struct bq257xx_chg *pdata, int *intval);
};
/**
@@ -490,22 +502,22 @@ static int bq257xx_get_charger_property(struct power_supply *psy,
break;
case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT:
- return bq25703_get_iindpm(pdata, &val->intval);
+ return pdata->chip->bq257xx_get_iindpm(pdata, &val->intval);
case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX:
- return bq25703_get_chrg_volt(pdata, &val->intval);
+ return pdata->chip->bq257xx_get_vbatreg(pdata, &val->intval);
case POWER_SUPPLY_PROP_CURRENT_NOW:
- return bq25703_get_cur(pdata, &val->intval);
+ return pdata->chip->bq257xx_get_cur(pdata, &val->intval);
case POWER_SUPPLY_PROP_VOLTAGE_NOW:
- return bq25703_get_vbat(pdata, &val->intval);
+ return pdata->chip->bq257xx_get_vbat(pdata, &val->intval);
case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX:
- return bq25703_get_ichg_cur(pdata, &val->intval);
+ return pdata->chip->bq257xx_get_ichg(pdata, &val->intval);
case POWER_SUPPLY_PROP_VOLTAGE_MIN:
- return bq25703_get_min_vsys(pdata, &val->intval);
+ return pdata->chip->bq257xx_get_min_vsys(pdata, &val->intval);
case POWER_SUPPLY_PROP_USB_TYPE:
val->intval = pdata->usb_type;
@@ -633,9 +645,15 @@ static const struct bq257xx_chip_info bq25703_chip_info = {
.bq257xx_hw_init = &bq25703_hw_init,
.bq257xx_hw_shutdown = &bq25703_hw_shutdown,
.bq257xx_get_state = &bq25703_get_state,
+ .bq257xx_get_ichg = &bq25703_get_ichg_cur,
.bq257xx_set_ichg = &bq25703_set_ichg_cur,
+ .bq257xx_get_vbatreg = &bq25703_get_chrg_volt,
.bq257xx_set_vbatreg = &bq25703_set_chrg_volt,
+ .bq257xx_get_iindpm = &bq25703_get_iindpm,
.bq257xx_set_iindpm = &bq25703_set_iindpm,
+ .bq257xx_get_cur = &bq25703_get_cur,
+ .bq257xx_get_vbat = &bq25703_get_vbat,
+ .bq257xx_get_min_vsys = &bq25703_get_min_vsys,
};
/**
--
2.52.0
^ permalink raw reply related
* [PATCH v6 08/11] power: supply: bq257xx: Add fields for 'charging' and 'overvoltage' states
From: Alexey Charkov @ 2026-03-31 15:43 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chris Morgan, Liam Girdwood, Mark Brown, Sebastian Reichel
Cc: devicetree, linux-kernel, Sebastian Reichel, linux-pm,
Alexey Charkov
In-Reply-To: <20260331-bq25792-v6-0-0278fba33eb9@flipper.net>
The driver currently reports the 'charging' and 'overvoltage' states based
on a logical expression in the get_charger_property() wrapper function.
This doesn't scale well to other chip variants, which may have a different
number and type of hardware reported conditions which fall into these
broad power supply states.
Move the logic for determining 'charging' and 'overvoltage' states into
chip-specific accessors, which can be overridden by each variant as
needed.
This helps keep the get_charger_property() wrapper function chip-agnostic
while allowing for new chip variants to be added bringing their own logic.
Tested-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Alexey Charkov <alchark@flipper.net>
---
drivers/power/supply/bq257xx_charger.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/power/supply/bq257xx_charger.c b/drivers/power/supply/bq257xx_charger.c
index 0765673728e4..9c082865e745 100644
--- a/drivers/power/supply/bq257xx_charger.c
+++ b/drivers/power/supply/bq257xx_charger.c
@@ -54,8 +54,10 @@ struct bq257xx_chip_info {
* @bq: parent MFD device
* @charger: power supply device
* @online: charger input is present
+ * @charging: charger is actively charging the battery
* @fast_charge: charger is in fast charge mode
* @pre_charge: charger is in pre-charge mode
+ * @overvoltage: overvoltage fault detected
* @ov_fault: charger reports over voltage fault
* @batoc_fault: charger reports battery over current fault
* @oc_fault: charger reports over current fault
@@ -71,8 +73,10 @@ struct bq257xx_chg {
struct bq257xx_device *bq;
struct power_supply *charger;
bool online;
+ bool charging;
bool fast_charge;
bool pre_charge;
+ bool overvoltage;
bool ov_fault;
bool batoc_fault;
bool oc_fault;
@@ -106,8 +110,10 @@ static int bq25703_get_state(struct bq257xx_chg *pdata)
pdata->online = reg & BQ25703_STS_AC_STAT;
pdata->fast_charge = reg & BQ25703_STS_IN_FCHRG;
pdata->pre_charge = reg & BQ25703_STS_IN_PCHRG;
+ pdata->charging = pdata->fast_charge || pdata->pre_charge;
pdata->ov_fault = reg & BQ25703_STS_FAULT_ACOV;
pdata->batoc_fault = reg & BQ25703_STS_FAULT_BATOC;
+ pdata->overvoltage = pdata->ov_fault || pdata->batoc_fault;
pdata->oc_fault = reg & BQ25703_STS_FAULT_ACOC;
return 0;
@@ -478,14 +484,14 @@ static int bq257xx_get_charger_property(struct power_supply *psy,
case POWER_SUPPLY_PROP_STATUS:
if (!pdata->online)
val->intval = POWER_SUPPLY_STATUS_DISCHARGING;
- else if (pdata->fast_charge || pdata->pre_charge)
+ else if (pdata->charging)
val->intval = POWER_SUPPLY_STATUS_CHARGING;
else
val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING;
break;
case POWER_SUPPLY_PROP_HEALTH:
- if (pdata->ov_fault || pdata->batoc_fault)
+ if (pdata->overvoltage)
val->intval = POWER_SUPPLY_HEALTH_OVERVOLTAGE;
else if (pdata->oc_fault)
val->intval = POWER_SUPPLY_HEALTH_OVERCURRENT;
--
2.52.0
^ permalink raw reply related
* [PATCH v6 09/11] mfd: bq257xx: Add BQ25792 support
From: Alexey Charkov @ 2026-03-31 15:43 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chris Morgan, Liam Girdwood, Mark Brown, Sebastian Reichel
Cc: devicetree, linux-kernel, Sebastian Reichel, linux-pm,
Alexey Charkov
In-Reply-To: <20260331-bq25792-v6-0-0278fba33eb9@flipper.net>
Add register definitions and a new 'type' enum to be passed via MFD
private data to support the BQ25792, which is a newer variant of the
BQ257xx family.
BQ25792 shares similar logic of operation with the already supported
BQ25703A but has a completely different register map and different
electrical constraints.
Tested-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Alexey Charkov <alchark@flipper.net>
---
drivers/mfd/bq257xx.c | 54 +++++-
include/linux/mfd/bq257xx.h | 412 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 463 insertions(+), 3 deletions(-)
diff --git a/drivers/mfd/bq257xx.c b/drivers/mfd/bq257xx.c
index e9d49dac0a16..054342c60b73 100644
--- a/drivers/mfd/bq257xx.c
+++ b/drivers/mfd/bq257xx.c
@@ -39,6 +39,39 @@ static const struct regmap_config bq25703_regmap_config = {
.val_format_endian = REGMAP_ENDIAN_LITTLE,
};
+static const struct regmap_range bq25792_writeable_reg_ranges[] = {
+ regmap_reg_range(BQ25792_REG00_MIN_SYS_VOLTAGE,
+ BQ25792_REG18_NTC_CONTROL_1),
+ regmap_reg_range(BQ25792_REG28_CHARGER_MASK_0,
+ BQ25792_REG30_ADC_FUNCTION_DISABLE_1),
+};
+
+static const struct regmap_access_table bq25792_writeable_regs = {
+ .yes_ranges = bq25792_writeable_reg_ranges,
+ .n_yes_ranges = ARRAY_SIZE(bq25792_writeable_reg_ranges),
+};
+
+static const struct regmap_range bq25792_volatile_reg_ranges[] = {
+ regmap_reg_range(BQ25792_REG19_ICO_CURRENT_LIMIT,
+ BQ25792_REG27_FAULT_FLAG_1),
+ regmap_reg_range(BQ25792_REG31_IBUS_ADC,
+ BQ25792_REG47_DPDM_DRIVER),
+};
+
+static const struct regmap_access_table bq25792_volatile_regs = {
+ .yes_ranges = bq25792_volatile_reg_ranges,
+ .n_yes_ranges = ARRAY_SIZE(bq25792_volatile_reg_ranges),
+};
+
+static const struct regmap_config bq25792_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = BQ25792_REG48_PART_INFORMATION,
+ .cache_type = REGCACHE_MAPLE,
+ .wr_table = &bq25792_writeable_regs,
+ .volatile_table = &bq25792_volatile_regs,
+};
+
static const struct mfd_cell cells[] = {
MFD_CELL_NAME("bq257xx-regulator"),
MFD_CELL_NAME("bq257xx-charger"),
@@ -46,6 +79,7 @@ static const struct mfd_cell cells[] = {
static int bq257xx_probe(struct i2c_client *client)
{
+ const struct regmap_config *rcfg;
struct bq257xx_device *ddata;
int ret;
@@ -53,9 +87,21 @@ static int bq257xx_probe(struct i2c_client *client)
if (!ddata)
return -ENOMEM;
+ ddata->type = (uintptr_t)i2c_get_match_data(client);
ddata->client = client;
- ddata->regmap = devm_regmap_init_i2c(client, &bq25703_regmap_config);
+ switch (ddata->type) {
+ case BQ25703A:
+ rcfg = &bq25703_regmap_config;
+ break;
+ case BQ25792:
+ rcfg = &bq25792_regmap_config;
+ break;
+ default:
+ return dev_err_probe(&client->dev, -ENODEV, "Unsupported device type\n");
+ }
+
+ ddata->regmap = devm_regmap_init_i2c(client, rcfg);
if (IS_ERR(ddata->regmap)) {
return dev_err_probe(&client->dev, PTR_ERR(ddata->regmap),
"Failed to allocate register map\n");
@@ -73,13 +119,15 @@ static int bq257xx_probe(struct i2c_client *client)
}
static const struct i2c_device_id bq257xx_i2c_ids[] = {
- { "bq25703a" },
+ { "bq25703a", BQ25703A },
+ { "bq25792", BQ25792 },
{}
};
MODULE_DEVICE_TABLE(i2c, bq257xx_i2c_ids);
static const struct of_device_id bq257xx_of_match[] = {
- { .compatible = "ti,bq25703a" },
+ { .compatible = "ti,bq25703a", .data = (void *)BQ25703A },
+ { .compatible = "ti,bq25792", .data = (void *)BQ25792 },
{}
};
MODULE_DEVICE_TABLE(of, bq257xx_of_match);
diff --git a/include/linux/mfd/bq257xx.h b/include/linux/mfd/bq257xx.h
index 1d6ddc7fb09f..4ec72eb920f2 100644
--- a/include/linux/mfd/bq257xx.h
+++ b/include/linux/mfd/bq257xx.h
@@ -98,7 +98,419 @@
#define BQ25703_EN_OTG_MASK BIT(12)
+#define BQ25792_REG00_MIN_SYS_VOLTAGE 0x00
+#define BQ25792_REG01_CHARGE_VOLTAGE_LIMIT 0x01
+#define BQ25792_REG03_CHARGE_CURRENT_LIMIT 0x03
+#define BQ25792_REG05_INPUT_VOLTAGE_LIMIT 0x05
+#define BQ25792_REG06_INPUT_CURRENT_LIMIT 0x06
+#define BQ25792_REG08_PRECHARGE_CONTROL 0x08
+#define BQ25792_REG09_TERMINATION_CONTROL 0x09
+#define BQ25792_REG0A_RECHARGE_CONTROL 0x0a
+#define BQ25792_REG0B_VOTG_REGULATION 0x0b
+#define BQ25792_REG0D_IOTG_REGULATION 0x0d
+#define BQ25792_REG0E_TIMER_CONTROL 0x0e
+#define BQ25792_REG0F_CHARGER_CONTROL_0 0x0f
+#define BQ25792_REG10_CHARGER_CONTROL_1 0x10
+#define BQ25792_REG11_CHARGER_CONTROL_2 0x11
+#define BQ25792_REG12_CHARGER_CONTROL_3 0x12
+#define BQ25792_REG13_CHARGER_CONTROL_4 0x13
+#define BQ25792_REG14_CHARGER_CONTROL_5 0x14
+/* REG15 reserved */
+#define BQ25792_REG16_TEMPERATURE_CONTROL 0x16
+#define BQ25792_REG17_NTC_CONTROL_0 0x17
+#define BQ25792_REG18_NTC_CONTROL_1 0x18
+#define BQ25792_REG19_ICO_CURRENT_LIMIT 0x19
+#define BQ25792_REG1B_CHARGER_STATUS_0 0x1b
+#define BQ25792_REG1C_CHARGER_STATUS_1 0x1c
+#define BQ25792_REG1D_CHARGER_STATUS_2 0x1d
+#define BQ25792_REG1E_CHARGER_STATUS_3 0x1e
+#define BQ25792_REG1F_CHARGER_STATUS_4 0x1f
+#define BQ25792_REG20_FAULT_STATUS_0 0x20
+#define BQ25792_REG21_FAULT_STATUS_1 0x21
+#define BQ25792_REG22_CHARGER_FLAG_0 0x22
+#define BQ25792_REG23_CHARGER_FLAG_1 0x23
+#define BQ25792_REG24_CHARGER_FLAG_2 0x24
+#define BQ25792_REG25_CHARGER_FLAG_3 0x25
+#define BQ25792_REG26_FAULT_FLAG_0 0x26
+#define BQ25792_REG27_FAULT_FLAG_1 0x27
+#define BQ25792_REG28_CHARGER_MASK_0 0x28
+#define BQ25792_REG29_CHARGER_MASK_1 0x29
+#define BQ25792_REG2A_CHARGER_MASK_2 0x2a
+#define BQ25792_REG2B_CHARGER_MASK_3 0x2b
+#define BQ25792_REG2C_FAULT_MASK_0 0x2c
+#define BQ25792_REG2D_FAULT_MASK_1 0x2d
+#define BQ25792_REG2E_ADC_CONTROL 0x2e
+#define BQ25792_REG2F_ADC_FUNCTION_DISABLE_0 0x2f
+#define BQ25792_REG30_ADC_FUNCTION_DISABLE_1 0x30
+#define BQ25792_REG31_IBUS_ADC 0x31
+#define BQ25792_REG33_IBAT_ADC 0x33
+#define BQ25792_REG35_VBUS_ADC 0x35
+#define BQ25792_REG37_VAC1_ADC 0x37
+#define BQ25792_REG39_VAC2_ADC 0x39
+#define BQ25792_REG3B_VBAT_ADC 0x3b
+#define BQ25792_REG3D_VSYS_ADC 0x3d
+#define BQ25792_REG3F_TS_ADC 0x3f
+#define BQ25792_REG41_TDIE_ADC 0x41
+#define BQ25792_REG43_DP_ADC 0x43
+#define BQ25792_REG45_DM_ADC 0x45
+#define BQ25792_REG47_DPDM_DRIVER 0x47
+#define BQ25792_REG48_PART_INFORMATION 0x48
+
+/* Minimal System Voltage */
+#define BQ25792_REG00_VSYSMIN_MASK GENMASK(5, 0)
+
+#define BQ25792_MINVSYS_MIN_UV 2500000
+#define BQ25792_MINVSYS_STEP_UV 250000
+#define BQ25792_MINVSYS_MAX_UV 16000000
+
+/* Charge Voltage Limit */
+#define BQ25792_REG01_VREG_MASK GENMASK(10, 0)
+
+#define BQ25792_VBATREG_MIN_UV 3000000
+#define BQ25792_VBATREG_STEP_UV 10000
+#define BQ25792_VBATREG_MAX_UV 18800000
+
+/* Charge Current Limit */
+#define BQ25792_REG03_ICHG_MASK GENMASK(8, 0)
+
+#define BQ25792_ICHG_MIN_UA 50000
+#define BQ25792_ICHG_STEP_UA 10000
+#define BQ25792_ICHG_MAX_UA 5000000
+
+/* Input Voltage Limit */
+#define BQ25792_REG05_VINDPM_MASK GENMASK(7, 0)
+
+/* Input Current Limit */
+#define BQ25792_REG06_IINDPM_MASK GENMASK(8, 0)
+#define BQ25792_IINDPM_DEFAULT_UA 3000000
+#define BQ25792_IINDPM_STEP_UA 10000
+#define BQ25792_IINDPM_MIN_UA 100000
+#define BQ25792_IINDPM_MAX_UA 3300000
+
+/* Precharge Control */
+#define BQ25792_REG08_VBAT_LOWV_MASK GENMASK(7, 6)
+#define BQ25792_REG08_IPRECHG_MASK GENMASK(5, 0)
+
+/* Termination Control */
+#define BQ25792_REG09_REG_RST BIT(6)
+#define BQ25792_REG09_ITERM_MASK GENMASK(4, 0)
+
+/* Re-charge Control */
+#define BQ25792_REG0A_CELL_MASK GENMASK(7, 6)
+#define BQ25792_REG0A_TRECHG_MASK GENMASK(5, 4)
+#define BQ25792_REG0A_VRECHG_MASK GENMASK(3, 0)
+
+/* VOTG regulation */
+#define BQ25792_REG0B_VOTG_MASK GENMASK(10, 0)
+
+#define BQ25792_OTG_VOLT_MIN_UV 2800000
+#define BQ25792_OTG_VOLT_STEP_UV 10000
+#define BQ25792_OTG_VOLT_MAX_UV 22000000
+#define BQ25792_OTG_VOLT_NUM_VOLT ((BQ25792_OTG_VOLT_MAX_UV \
+ - BQ25792_OTG_VOLT_MIN_UV) \
+ / BQ25792_OTG_VOLT_STEP_UV + 1)
+
+/* IOTG regulation */
+#define BQ25792_REG0D_PRECHG_TMR BIT(7)
+#define BQ25792_REG0D_IOTG_MASK GENMASK(6, 0)
+
+#define BQ25792_OTG_CUR_MIN_UA 120000
+#define BQ25792_OTG_CUR_STEP_UA 40000
+#define BQ25792_OTG_CUR_MAX_UA 3320000
+
+/* Timer Control */
+#define BQ25792_REG0E_TOPOFF_TMR_MASK GENMASK(7, 6)
+#define BQ25792_REG0E_EN_TRICHG_TMR BIT(5)
+#define BQ25792_REG0E_EN_PRECHG_TMR BIT(4)
+#define BQ25792_REG0E_EN_CHG_TMR BIT(3)
+#define BQ25792_REG0E_CHG_TMR_MASK GENMASK(2, 1)
+#define BQ25792_REG0E_TMR2X_EN BIT(0)
+
+/* Charger Control 0 */
+#define BQ25792_REG0F_EN_AUTO_IBATDIS BIT(7)
+#define BQ25792_REG0F_FORCE_IBATDIS BIT(6)
+#define BQ25792_REG0F_EN_CHG BIT(5)
+#define BQ25792_REG0F_EN_ICO BIT(4)
+#define BQ25792_REG0F_FORCE_ICO BIT(3)
+#define BQ25792_REG0F_EN_HIZ BIT(2)
+#define BQ25792_REG0F_EN_TERM BIT(1)
+/* bit0 reserved */
+
+/* Charger Control 1 */
+#define BQ25792_REG10_VAC_OVP_MASK GENMASK(5, 4)
+#define BQ25792_REG10_WD_RST BIT(3)
+#define BQ25792_REG10_WATCHDOG_MASK GENMASK(2, 0)
+
+/* Charger Control 2 */
+#define BQ25792_REG11_FORCE_INDET BIT(7)
+#define BQ25792_REG11_AUTO_INDET_EN BIT(6)
+#define BQ25792_REG11_EN_12V BIT(5)
+#define BQ25792_REG11_EN_9V BIT(4)
+#define BQ25792_REG11_HVDCP_EN BIT(3)
+#define BQ25792_REG11_SDRV_CTRL_MASK GENMASK(2, 1)
+#define BQ25792_REG11_SDRV_DLY BIT(0)
+
+/* Charger Control 3 */
+#define BQ25792_REG12_DIS_ACDRV BIT(7)
+#define BQ25792_REG12_EN_OTG BIT(6)
+#define BQ25792_REG12_PFM_OTG_DIS BIT(5)
+#define BQ25792_REG12_PFM_FWD_DIS BIT(4)
+#define BQ25792_REG12_WKUP_DLY BIT(3)
+#define BQ25792_REG12_DIS_LDO BIT(2)
+#define BQ25792_REG12_DIS_OTG_OOA BIT(1)
+#define BQ25792_REG12_DIS_FWD_OOA BIT(0)
+
+/* Charger Control 4 */
+#define BQ25792_REG13_EN_ACDRV2 BIT(7)
+#define BQ25792_REG13_EN_ACDRV1 BIT(6)
+#define BQ25792_REG13_PWM_FREQ BIT(5)
+#define BQ25792_REG13_DIS_STAT BIT(4)
+#define BQ25792_REG13_DIS_VSYS_SHORT BIT(3)
+#define BQ25792_REG13_DIS_VOTG_UVP BIT(2)
+#define BQ25792_REG13_FORCE_VINDPM_DET BIT(1)
+#define BQ25792_REG13_EN_IBUS_OCP BIT(0)
+
+/* Charger Control 5 */
+#define BQ25792_REG14_SFET_PRESENT BIT(7)
+/* bit6 reserved */
+#define BQ25792_REG14_EN_IBAT BIT(5)
+#define BQ25792_REG14_IBAT_REG_MASK GENMASK(4, 3)
+#define BQ25792_REG14_EN_IINDPM BIT(2)
+#define BQ25792_REG14_EN_EXTILIM BIT(1)
+#define BQ25792_REG14_EN_BATOC BIT(0)
+
+#define BQ25792_IBAT_3A FIELD_PREP(BQ25792_REG14_IBAT_REG_MASK, 0)
+#define BQ25792_IBAT_4A FIELD_PREP(BQ25792_REG14_IBAT_REG_MASK, 1)
+#define BQ25792_IBAT_5A FIELD_PREP(BQ25792_REG14_IBAT_REG_MASK, 2)
+#define BQ25792_IBAT_UNLIM FIELD_PREP(BQ25792_REG14_IBAT_REG_MASK, 3)
+
+/* Temperature Control */
+#define BQ25792_REG16_TREG_MASK GENMASK(7, 6)
+#define BQ25792_REG16_TSHUT_MASK GENMASK(5, 4)
+#define BQ25792_REG16_VBUS_PD_EN BIT(3)
+#define BQ25792_REG16_VAC1_PD_EN BIT(2)
+#define BQ25792_REG16_VAC2_PD_EN BIT(1)
+
+/* NTC Control 0 */
+#define BQ25792_REG17_JEITA_VSET_MASK GENMASK(7, 5)
+#define BQ25792_REG17_JEITA_ISETH_MASK GENMASK(4, 3)
+#define BQ25792_REG17_JEITA_ISETC_MASK GENMASK(2, 1)
+
+/* NTC Control 1 */
+#define BQ25792_REG18_TS_COOL_MASK GENMASK(7, 6)
+#define BQ25792_REG18_TS_WARM_MASK GENMASK(5, 4)
+#define BQ25792_REG18_BHOT_MASK GENMASK(3, 2)
+#define BQ25792_REG18_BCOLD BIT(1)
+#define BQ25792_REG18_TS_IGNORE BIT(0)
+
+/* ICO Current Limit */
+#define BQ25792_REG19_ICO_ILIM_MASK GENMASK(8, 0)
+
+/* Charger Status 0 */
+#define BQ25792_REG1B_IINDPM_STAT BIT(7)
+#define BQ25792_REG1B_VINDPM_STAT BIT(6)
+#define BQ25792_REG1B_WD_STAT BIT(5)
+#define BQ25792_REG1B_POORSRC_STAT BIT(4)
+#define BQ25792_REG1B_PG_STAT BIT(3)
+#define BQ25792_REG1B_AC2_PRESENT_STAT BIT(2)
+#define BQ25792_REG1B_AC1_PRESENT_STAT BIT(1)
+#define BQ25792_REG1B_VBUS_PRESENT_STAT BIT(0)
+
+/* Charger Status 1 */
+#define BQ25792_REG1C_CHG_STAT_MASK GENMASK(7, 5)
+#define BQ25792_REG1C_VBUS_STAT_MASK GENMASK(4, 1)
+#define BQ25792_REG1C_BC12_DONE_STAT BIT(0)
+
+/* Charger Status 2 */
+#define BQ25792_REG1D_ICO_STAT_MASK GENMASK(7, 6)
+#define BQ25792_REG1D_TREG_STAT BIT(2)
+#define BQ25792_REG1D_DPDM_STAT BIT(1)
+#define BQ25792_REG1D_VBAT_PRESENT_STAT BIT(0)
+
+/* Charger Status 3 */
+#define BQ25792_REG1E_ACRB2_STAT BIT(7)
+#define BQ25792_REG1E_ACRB1_STAT BIT(6)
+#define BQ25792_REG1E_ADC_DONE_STAT BIT(5)
+#define BQ25792_REG1E_VSYS_STAT BIT(4)
+#define BQ25792_REG1E_CHG_TMR_STAT BIT(3)
+#define BQ25792_REG1E_TRICHG_TMR_STAT BIT(2)
+#define BQ25792_REG1E_PRECHG_TMR_STAT BIT(1)
+
+/* Charger Status 4 */
+#define BQ25792_REG1F_VBATOTG_LOW_STAT BIT(4)
+#define BQ25792_REG1F_TS_COLD_STAT BIT(3)
+#define BQ25792_REG1F_TS_COOL_STAT BIT(2)
+#define BQ25792_REG1F_TS_WARM_STAT BIT(1)
+#define BQ25792_REG1F_TS_HOT_STAT BIT(0)
+
+/* FAULT Status 0 */
+#define BQ25792_REG20_IBAT_REG_STAT BIT(7)
+#define BQ25792_REG20_VBUS_OVP_STAT BIT(6)
+#define BQ25792_REG20_VBAT_OVP_STAT BIT(5)
+#define BQ25792_REG20_IBUS_OCP_STAT BIT(4)
+#define BQ25792_REG20_IBAT_OCP_STAT BIT(3)
+#define BQ25792_REG20_CONV_OCP_STAT BIT(2)
+#define BQ25792_REG20_VAC2_OVP_STAT BIT(1)
+#define BQ25792_REG20_VAC1_OVP_STAT BIT(0)
+
+#define BQ25792_REG20_OVERVOLTAGE_MASK (BQ25792_REG20_VBAT_OVP_STAT | \
+ BQ25792_REG20_VAC2_OVP_STAT | \
+ BQ25792_REG20_VAC1_OVP_STAT)
+#define BQ25792_REG20_OVERCURRENT_MASK (BQ25792_REG20_IBAT_OCP_STAT | \
+ BQ25792_REG20_CONV_OCP_STAT)
+
+/* FAULT Status 1 */
+#define BQ25792_REG21_VSYS_SHORT_STAT BIT(7)
+#define BQ25792_REG21_VSYS_OVP_STAT BIT(6)
+#define BQ25792_REG21_OTG_OVP_STAT BIT(5)
+#define BQ25792_REG21_OTG_UVP_STAT BIT(4)
+#define BQ25792_REG21_TSHUT_STAT BIT(2)
+
+
+/* Charger Flag 0 */
+#define BQ25792_REG22_IINDPM_FLAG BIT(7)
+#define BQ25792_REG22_VINDPM_FLAG BIT(6)
+#define BQ25792_REG22_WD_FLAG BIT(5)
+#define BQ25792_REG22_POORSRC_FLAG BIT(4)
+#define BQ25792_REG22_PG_FLAG BIT(3)
+#define BQ25792_REG22_AC2_PRESENT_FLAG BIT(2)
+#define BQ25792_REG22_AC1_PRESENT_FLAG BIT(1)
+#define BQ25792_REG22_VBUS_PRESENT_FLAG BIT(0)
+
+/* Charger Flag 1 */
+#define BQ25792_REG23_CHG_FLAG BIT(7)
+#define BQ25792_REG23_ICO_FLAG BIT(6)
+#define BQ25792_REG23_VBUS_FLAG BIT(4)
+#define BQ25792_REG23_TREG_FLAG BIT(2)
+#define BQ25792_REG23_VBAT_PRESENT_FLAG BIT(1)
+#define BQ25792_REG23_BC12_DONE_FLAG BIT(0)
+
+/* Charger Flag 2 */
+#define BQ25792_REG24_DPDM_DONE_FLAG BIT(6)
+#define BQ25792_REG24_ADC_DONE_FLAG BIT(5)
+#define BQ25792_REG24_VSYS_FLAG BIT(4)
+#define BQ25792_REG24_CHG_TMR_FLAG BIT(3)
+#define BQ25792_REG24_TRICHG_TMR_FLAG BIT(2)
+#define BQ25792_REG24_PRECHG_TMR_FLAG BIT(1)
+#define BQ25792_REG24_TOPOFF_TMR_FLAG BIT(0)
+
+/* Charger Flag 3 */
+#define BQ25792_REG25_VBATOTG_LOW_FLAG BIT(4)
+#define BQ25792_REG25_TS_COLD_FLAG BIT(3)
+#define BQ25792_REG25_TS_COOL_FLAG BIT(2)
+#define BQ25792_REG25_TS_WARM_FLAG BIT(1)
+#define BQ25792_REG25_TS_HOT_FLAG BIT(0)
+
+/* FAULT Flag 0 */
+#define BQ25792_REG26_IBAT_REG_FLAG BIT(7)
+#define BQ25792_REG26_VBUS_OVP_FLAG BIT(6)
+#define BQ25792_REG26_VBAT_OVP_FLAG BIT(5)
+#define BQ25792_REG26_IBUS_OCP_FLAG BIT(4)
+#define BQ25792_REG26_IBAT_OCP_FLAG BIT(3)
+#define BQ25792_REG26_CONV_OCP_FLAG BIT(2)
+#define BQ25792_REG26_VAC2_OVP_FLAG BIT(1)
+#define BQ25792_REG26_VAC1_OVP_FLAG BIT(0)
+
+/* FAULT Flag 1 */
+#define BQ25792_REG27_VSYS_SHORT_FLAG BIT(7)
+#define BQ25792_REG27_VSYS_OVP_FLAG BIT(6)
+#define BQ25792_REG27_OTG_OVP_FLAG BIT(5)
+#define BQ25792_REG27_OTG_UVP_FLAG BIT(4)
+#define BQ25792_REG27_TSHUT_FLAG BIT(2)
+
+/* Charger Mask 0 */
+#define BQ25792_REG28_IINDPM_MASK BIT(7)
+#define BQ25792_REG28_VINDPM_MASK BIT(6)
+#define BQ25792_REG28_WD_MASK BIT(5)
+#define BQ25792_REG28_POORSRC_MASK BIT(4)
+#define BQ25792_REG28_PG_MASK BIT(3)
+#define BQ25792_REG28_AC2_PRESENT_MASK BIT(2)
+#define BQ25792_REG28_AC1_PRESENT_MASK BIT(1)
+#define BQ25792_REG28_VBUS_PRESENT_MASK BIT(0)
+
+/* Charger Mask 1 */
+#define BQ25792_REG29_CHG_MASK BIT(7)
+#define BQ25792_REG29_ICO_MASK BIT(6)
+#define BQ25792_REG29_VBUS_MASK BIT(4)
+#define BQ25792_REG29_TREG_MASK BIT(2)
+#define BQ25792_REG29_VBAT_PRESENT_MASK BIT(1)
+#define BQ25792_REG29_BC12_DONE_MASK BIT(0)
+
+/* Charger Mask 2 */
+#define BQ25792_REG2A_DPDM_DONE_MASK BIT(6)
+#define BQ25792_REG2A_ADC_DONE_MASK BIT(5)
+#define BQ25792_REG2A_VSYS_MASK BIT(4)
+#define BQ25792_REG2A_CHG_TMR_MASK BIT(3)
+#define BQ25792_REG2A_TRICHG_TMR_MASK BIT(2)
+#define BQ25792_REG2A_PRECHG_TMR_MASK BIT(1)
+#define BQ25792_REG2A_TOPOFF_TMR_MASK BIT(0)
+
+/* Charger Mask 3 */
+#define BQ25792_REG2B_VBATOTG_LOW_MASK BIT(4)
+#define BQ25792_REG2B_TS_COLD_MASK BIT(3)
+#define BQ25792_REG2B_TS_COOL_MASK BIT(2)
+#define BQ25792_REG2B_TS_WARM_MASK BIT(1)
+#define BQ25792_REG2B_TS_HOT_MASK BIT(0)
+
+/* FAULT Mask 0 */
+#define BQ25792_REG2C_IBAT_REG_MASK BIT(7)
+#define BQ25792_REG2C_VBUS_OVP_MASK BIT(6)
+#define BQ25792_REG2C_VBAT_OVP_MASK BIT(5)
+#define BQ25792_REG2C_IBUS_OCP_MASK BIT(4)
+#define BQ25792_REG2C_IBAT_OCP_MASK BIT(3)
+#define BQ25792_REG2C_CONV_OCP_MASK BIT(2)
+#define BQ25792_REG2C_VAC2_OVP_MASK BIT(1)
+#define BQ25792_REG2C_VAC1_OVP_MASK BIT(0)
+
+/* FAULT Mask 1 */
+#define BQ25792_REG2D_VSYS_SHORT_MASK BIT(7)
+#define BQ25792_REG2D_VSYS_OVP_MASK BIT(6)
+#define BQ25792_REG2D_OTG_OVP_MASK BIT(5)
+#define BQ25792_REG2D_OTG_UVP_MASK BIT(4)
+#define BQ25792_REG2D_TSHUT_MASK BIT(2)
+
+/* ADC Control */
+#define BQ25792_REG2E_ADC_EN BIT(7)
+#define BQ25792_REG2E_ADC_RATE BIT(6)
+#define BQ25792_REG2E_ADC_SAMPLE_MASK GENMASK(5, 4)
+#define BQ25792_REG2E_ADC_AVG BIT(3)
+#define BQ25792_REG2E_ADC_AVG_INIT BIT(2)
+
+/* ADC Function Disable 0 */
+#define BQ25792_REG2F_IBUS_ADC_DIS BIT(7)
+#define BQ25792_REG2F_IBAT_ADC_DIS BIT(6)
+#define BQ25792_REG2F_VBUS_ADC_DIS BIT(5)
+#define BQ25792_REG2F_VBAT_ADC_DIS BIT(4)
+#define BQ25792_REG2F_VSYS_ADC_DIS BIT(3)
+#define BQ25792_REG2F_TS_ADC_DIS BIT(2)
+#define BQ25792_REG2F_TDIE_ADC_DIS BIT(1)
+
+/* ADC Function Disable 1 */
+#define BQ25792_REG30_DP_ADC_DIS BIT(7)
+#define BQ25792_REG30_DM_ADC_DIS BIT(6)
+#define BQ25792_REG30_VAC2_ADC_DIS BIT(5)
+#define BQ25792_REG30_VAC1_ADC_DIS BIT(4)
+
+/* 0x31-0x45: ADC result registers (16-bit, RO): single full-width field */
+
+#define BQ25792_ADCVSYSVBAT_STEP_UV 1000
+#define BQ25792_ADCIBAT_STEP_UA 1000
+
+/* DPDM Driver */
+#define BQ25792_REG47_DPLUS_DAC_MASK GENMASK(7, 5)
+#define BQ25792_REG47_DMINUS_DAC_MASK GENMASK(4, 2)
+
+/* Part Information */
+#define BQ25792_REG48_PN_MASK GENMASK(5, 3)
+#define BQ25792_REG48_DEV_REV_MASK GENMASK(2, 0)
+
+enum bq257xx_type {
+ BQ25703A = 1,
+ BQ25792,
+};
+
struct bq257xx_device {
struct i2c_client *client;
struct regmap *regmap;
+ enum bq257xx_type type;
};
--
2.52.0
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