* [PATCH v1 4/5] dt-bindings: riscv: Add StarFive JHB100 SoC
From: Changhuang Liang @ 2026-04-02 8:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Samuel Holland, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Daniel Lezcano, Emil Renner Berthing
Cc: Yixun Lan, Joel Stanley, Drew Fustini, Darshan Prajapati,
Guodong Xu, Michal Simek, Junhui Liu, Heinrich Schuchardt,
E Shattow, Icenowy Zheng, Anup Patel, linux-kernel, devicetree,
linux-riscv, Ji Sheng Teoh, Hal Feng, Ley Foon Tan,
Changhuang Liang, Michael Zhu
In-Reply-To: <20260402084019.440708-1-changhuang.liang@starfivetech.com>
From: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Add device tree bindings for the StarFive JHB100 RISC-V SoC.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
Documentation/devicetree/bindings/riscv/starfive.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
index 8ba0e10b529a..277618efff6e 100644
--- a/Documentation/devicetree/bindings/riscv/starfive.yaml
+++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
@@ -43,6 +43,11 @@ properties:
- const: starfive,jh7110s
- const: starfive,jh7110
+ - items:
+ - enum:
+ - starfive,jhb100-evb1
+ - const: starfive,jhb100
+
additionalProperties: true
...
--
2.25.1
^ permalink raw reply related
* [PATCH v1 5/5] riscv: dts: starfive: jhb100: Add JHB100 base DT
From: Changhuang Liang @ 2026-04-02 8:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Samuel Holland, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Daniel Lezcano, Emil Renner Berthing
Cc: Yixun Lan, Joel Stanley, Drew Fustini, Darshan Prajapati,
Guodong Xu, Michal Simek, Junhui Liu, Heinrich Schuchardt,
E Shattow, Icenowy Zheng, Anup Patel, linux-kernel, devicetree,
linux-riscv, Ji Sheng Teoh, Hal Feng, Ley Foon Tan,
Changhuang Liang, Michael Zhu
In-Reply-To: <20260402084019.440708-1-changhuang.liang@starfivetech.com>
From: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Add JHB100 base dtsi and dts. Consist of 4 Dubhe-70 cores, CLINT, PLIC,
PMU, UART and 1GB DDR.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
MAINTAINERS | 6 +
arch/riscv/boot/dts/starfive/Makefile | 2 +
.../boot/dts/starfive/jhb100-evb1-eth.dts | 6 +
arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi | 32 ++
arch/riscv/boot/dts/starfive/jhb100.dtsi | 326 ++++++++++++++++++
5 files changed, 372 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
create mode 100644 arch/riscv/boot/dts/starfive/jhb100.dtsi
diff --git a/MAINTAINERS b/MAINTAINERS
index 7d10988cbc62..b1892a480c31 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25306,6 +25306,12 @@ S: Supported
F: Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml
F: drivers/irqchip/irq-starfive-jh8100-intc.c
+STARFIVE JHB100 DEVICETREES
+M: Changhuang Liang <changhuang.liang@starfivetech.com>
+L: linux-riscv@lists.infradead.org
+S: Maintained
+F: arch/riscv/boot/dts/starfive/jhb100*
+
STATIC BRANCH/CALL
M: Peter Zijlstra <peterz@infradead.org>
M: Josh Poimboeuf <jpoimboe@kernel.org>
diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index 3dd1f05283f7..7cdb75788053 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -18,3 +18,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite-emmc.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
+
+dtb-$(CONFIG_ARCH_STARFIVE) += jhb100-evb1-eth.dtb
diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts b/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
new file mode 100644
index 000000000000..62cd046e1224
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2024-2026 StarFive Technology Co., Ltd.
+ */
+
+#include "jhb100-evb1.dtsi"
diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi b/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
new file mode 100644
index 000000000000..462b6fb7953b
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2024-2026 StarFive Technology Co., Ltd.
+ */
+
+#include "jhb100.dtsi"
+
+/ {
+ model = "StarFive JHB100 EVB-1";
+ compatible = "starfive,jhb100-evb1", "starfive,jhb100";
+
+ aliases {
+ serial6 = &uart6;
+ };
+
+ chosen {
+ stdout-path = "serial6:115200n8";
+ };
+
+ cpus {
+ timebase-frequency = <5000000>;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x0 0x40000000>; /* 1GB */
+ };
+};
+
+&uart6 {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/dts/starfive/jhb100.dtsi
new file mode 100644
index 000000000000..4d03470f78ab
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi
@@ -0,0 +1,326 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2024-2026 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+
+/ {
+ compatible = "starfive,jhb100";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "starfive,dubhe-70", "riscv";
+ riscv,isa = "rv64imafdcbh";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", "zba", "zbb",
+ "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr",
+ "zicond", "zicsr", "zifencei", "zihintpause",
+ "zihpm", "svinval", "svnapot", "sscofpmf";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <512>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <16>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <512>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <24>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <&l2c0>;
+ reg = <0x0>;
+ tlb-split;
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu1: cpu@1 {
+ compatible = "starfive,dubhe-70", "riscv";
+ riscv,isa = "rv64imafdcbh";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", "zba", "zbb",
+ "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr",
+ "zicond", "zicsr", "zifencei", "zihintpause",
+ "zihpm", "svinval", "svnapot", "sscofpmf";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <512>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <16>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <512>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <24>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <&l2c1>;
+ reg = <0x1>;
+ tlb-split;
+
+ cpu1_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu2: cpu@2 {
+ compatible = "starfive,dubhe-70", "riscv";
+ riscv,isa = "rv64imafdcbh";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", "zba", "zbb",
+ "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr",
+ "zicond", "zicsr", "zifencei", "zihintpause",
+ "zihpm", "svinval", "svnapot", "sscofpmf";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <512>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <16>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <512>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <24>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <&l2c2>;
+ reg = <0x2>;
+ tlb-split;
+
+ cpu2_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu3: cpu@3 {
+ compatible = "starfive,dubhe-70", "riscv";
+ riscv,isa = "rv64imafdcbh";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", "zba", "zbb",
+ "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr",
+ "zicond", "zicsr", "zifencei", "zihintpause",
+ "zihpm", "svinval", "svnapot", "sscofpmf";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <512>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <16>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <512>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <24>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <&l2c3>;
+ reg = <0x3>;
+ tlb-split;
+
+ cpu3_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu1>;
+ };
+ };
+
+ cluster2 {
+ core0 {
+ cpu = <&cpu2>;
+ };
+ };
+
+ cluster3 {
+ core0 {
+ cpu = <&cpu3>;
+ };
+ };
+ };
+
+ l2c0: cache-controller-0 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <2048>;
+ cache-size = <0x20000>;
+ cache-unified;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2c1: cache-controller-1 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <2048>;
+ cache-size = <0x20000>;
+ cache-unified;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2c2: cache-controller-2 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <2048>;
+ cache-size = <0x20000>;
+ cache-unified;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2c3: cache-controller-3 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <2048>;
+ cache-size = <0x20000>;
+ cache-unified;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l3_cache: cache-controller-4 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <3>;
+ cache-sets = <1024>;
+ cache-size = <0x20000>;
+ cache-unified;
+ };
+ };
+
+ pmu {
+ compatible = "riscv,pmu";
+ interrupts-extended = <&cpu0_intc 13>, <&cpu1_intc 13>,
+ <&cpu2_intc 13>, <&cpu3_intc 13>;
+
+ riscv,event-to-mhpmevent = <0x00005 0x0000 0xA>,
+ <0x00006 0x0000 0xB>,
+ <0x00008 0x0000 0x10>,
+ <0x00009 0x0000 0xF>,
+ <0x10000 0x0000 0x19>,
+ <0x10001 0x0000 0x1A>,
+ <0x10002 0x0000 0x1B>,
+ <0x10003 0x0000 0x1C>,
+ <0x10008 0x0000 0x8>,
+ <0x10009 0x0000 0x9>,
+ <0x1000C 0x0000 0x9E>,
+ <0x1000D 0x0000 0x9F>,
+ <0x10010 0x0000 0x1D>,
+ <0x10011 0x0000 0x1E>,
+ <0x10012 0x0000 0x1F>,
+ <0x10013 0x0000 0x20>,
+ <0x10014 0x0000 0x21>,
+ <0x10018 0x0000 0x17>,
+ <0x10019 0x0000 0x18>,
+ <0x10020 0x0000 0x8>,
+ <0x10021 0x0000 0x7>;
+
+ riscv,event-to-mhpmcounters = <0x00005 0x00006 0x00007FF8>,
+ <0x00008 0x00009 0x00007FF8>,
+ <0x10000 0x10003 0x00007FF8>,
+ <0x10008 0x10009 0x00007FF8>,
+ <0x1000C 0x1000D 0x00007FF8>,
+ <0x10010 0x10014 0x00007FF8>,
+ <0x10018 0x10019 0x00007FF8>,
+ <0x10020 0x10021 0x00007FF8>;
+
+ riscv,raw-event-to-mhpmcounters =
+ <0x00 0x00 0xFFFFFFFF 0xFFFFFFE0 0x00007FF8>, /* Event ID 1-31 */
+ <0x00 0x20 0xFFFFFFFF 0xFFFFFFFE 0x00007FF8>, /* Event ID 32-33 */
+ <0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>; /* Event ID 34 */
+ };
+
+ clk_uart: clk-uart {
+ compatible = "fixed-clock"; /* Initial clock handler for UART */
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&plic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clint: timer@2000000 {
+ compatible = "starfive,jhb100-clint", "sifive,clint0";
+ reg = <0x0 0x02000000 0x0 0x10000>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+ <&cpu1_intc 3>, <&cpu1_intc 7>,
+ <&cpu2_intc 3>, <&cpu2_intc 7>,
+ <&cpu3_intc 3>, <&cpu3_intc 7>;
+ };
+
+ plic: interrupt-controller@c000000 {
+ compatible = "starfive,jhb100-plic", "sifive,plic-1.0.0";
+ reg = <0x0 0x0c000000 0x0 0x4000000>;
+ riscv,ndev = <400>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>,
+ <&cpu2_intc 11>, <&cpu2_intc 9>,
+ <&cpu3_intc 11>, <&cpu3_intc 9>;
+ };
+
+ bus_nioc: bus_nioc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-noncoherent;
+ dma-ranges = <0x4 0x00000000 0x0 0x40000000 0x2 0x0>,
+ <0x4 0x00000000 0x4 0x00000000 0x2 0x0>;
+ ranges;
+
+ uart6: serial@11982000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x11982000 0x0 0x400>;
+ clocks = <&clk_uart>, <&clk_uart>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+ };
+ };
+};
--
2.25.1
^ permalink raw reply related
* Re: [PATCH v4 2/5] arm64: dts: sophgo: add initial Milk-V Duo S board support
From: Joshua Milas @ 2026-04-02 12:14 UTC (permalink / raw)
To: Michael Opdenacker
Cc: tglx, robh, krzk+dt, conor+dt, pjw, samuel.holland, unicorn_wang,
inochiama, daniel.lezcano, palmer, aou, alex, liujingqi,
alexander.sverdlin, rabenda.cn, dlan, chao.wei, anup,
linux-kernel, devicetree, linux-riscv, sophgo, hanguidong02
In-Reply-To: <11e7fcc9-c8dd-4bf5-a600-3d130407bb82@rootcommit.com>
Hi Michael,
Just fixed in my latest set and will post v5 after debugging your eth0 issue.
Thanks,
- Joshua Milas
^ permalink raw reply
* Re: [PATCH v1 22/22] riscv: dts: starfive: jhb100: Add clocks and resets nodes
From: Conor Dooley @ 2026-04-02 12:14 UTC (permalink / raw)
To: Changhuang Liang
Cc: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran, linux-clk, linux-kernel,
devicetree, linux-riscv, linux-hardening, netdev, Sia Jee Heng,
Hal Feng, Ley Foon Tan
In-Reply-To: <20260402105523.447523-23-changhuang.liang@starfivetech.com>
[-- Attachment #1: Type: text/plain, Size: 2110 bytes --]
On Thu, Apr 02, 2026 at 03:55:23AM -0700, Changhuang Liang wrote:
> Add clocks and resets nodes for JHB100 RISC-V BMC SoC. They contain
> sys0crg/sys1crg/sys2crg/per0crg/per1crg/per2crg/per3crg.
>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> ---
> arch/riscv/boot/dts/starfive/jhb100.dtsi | 198 ++++++++++++++++++++++-
> 1 file changed, 195 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/dts/starfive/jhb100.dtsi
> index 4d03470f78ab..700d00f800bc 100644
> --- a/arch/riscv/boot/dts/starfive/jhb100.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi
> @@ -4,6 +4,8 @@
> */
>
> /dts-v1/;
> +#include <dt-bindings/clock/starfive,jhb100-crg.h>
> +#include <dt-bindings/reset/starfive,jhb100-crg.h>
>
> / {
> compatible = "starfive,jhb100";
> @@ -268,12 +270,96 @@ pmu {
> <0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>; /* Event ID 34 */
> };
>
> - clk_uart: clk-uart {
> - compatible = "fixed-clock"; /* Initial clock handler for UART */
> + osc: osc {
> + compatible = "fixed-clock";
> #clock-cells = <0>;
> clock-frequency = <25000000>;
> };
Is this really on the SoC?
>
> + pll0: pll0 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <2400000000>;
> + };
What's providing all of these PLLs? Are they all fixed-frequency on-chip
PLLs without an off-chip reference? I find that somewhat unlikely.
Since devicetrees are now being imported into U-Boot, it's important to
make sure that I'm not merging fixed-clocks that later get replaced by
dedicated drivers that U-Boot won't have.
To that end, I won't apply the series this depends on without this patch
being applied at the same time.
> +
> + pll1: pll1 {
Also, none of these follow the preferred naming scheme for
fixed-frequency clocks. Go look at the binding for how they should be,
if they are too be kept.
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <1000000000>;
> + };
Cheers,
Conor.
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^ permalink raw reply
* [PATCH v1 1/5] dt-bindings: riscv: Add StarFive Dubhe-70 compatibles
From: Changhuang Liang @ 2026-04-02 8:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Samuel Holland, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Daniel Lezcano, Emil Renner Berthing
Cc: Yixun Lan, Joel Stanley, Drew Fustini, Darshan Prajapati,
Guodong Xu, Michal Simek, Junhui Liu, Heinrich Schuchardt,
E Shattow, Icenowy Zheng, Anup Patel, linux-kernel, devicetree,
linux-riscv, Ji Sheng Teoh, Hal Feng, Ley Foon Tan,
Changhuang Liang, Michael Zhu
In-Reply-To: <20260402084019.440708-1-changhuang.liang@starfivetech.com>
From: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
Add new compatible string for Dubhe-70.
Dubhe-70 is a low power RISC-V cpu core from StarFive Technology.
Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 5feeb2203050..e7eda7a9c345 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -63,6 +63,7 @@ properties:
- sifive,u74-mc
- spacemit,x100
- spacemit,x60
+ - starfive,dubhe-70
- thead,c906
- thead,c908
- thead,c910
--
2.25.1
^ permalink raw reply related
* [PATCH v1 2/5] dt-bindings: timer: Add StarFive JHB100 clint
From: Changhuang Liang @ 2026-04-02 8:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Samuel Holland, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Daniel Lezcano, Emil Renner Berthing
Cc: Yixun Lan, Joel Stanley, Drew Fustini, Darshan Prajapati,
Guodong Xu, Michal Simek, Junhui Liu, Heinrich Schuchardt,
E Shattow, Icenowy Zheng, Anup Patel, linux-kernel, devicetree,
linux-riscv, Ji Sheng Teoh, Hal Feng, Ley Foon Tan,
Changhuang Liang, Michael Zhu
In-Reply-To: <20260402084019.440708-1-changhuang.liang@starfivetech.com>
From: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Add compatible string for the StarFive JHB100 clint.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index 3bab40500df9..387086bc6b5e 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -37,6 +37,7 @@ properties:
- starfive,jh7100-clint # StarFive JH7100
- starfive,jh7110-clint # StarFive JH7110
- starfive,jh8100-clint # StarFive JH8100
+ - starfive,jhb100-clint # StarFive JHB100
- tenstorrent,blackhole-clint # Tenstorrent Blackhole
- const: sifive,clint0 # SiFive CLINT v0 IP block
- items:
--
2.25.1
^ permalink raw reply related
* [PATCH v6 3/3] hwmon: emc2305: Support configurable fan PWM at shutdown
From: florin.leotescu @ 2026-04-02 12:25 UTC (permalink / raw)
To: Guenter Roeck, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Michael Shych, linux-hwmon, devicetree, linux-kernel
Cc: daniel.baluta, viorel.suman, linux-arm-kernel, imx, festevam,
Florin Leotescu
In-Reply-To: <20260402122514.1811737-1-florin.leotescu@oss.nxp.com>
From: Florin Leotescu <florin.leotescu@nxp.com>
Some systems require fans to enter in a defined safe state during system
shutdown or reboot handoff.
Add support for the optional Device Tree property "fan-shutdown-percent"
to configure the shutdown PWM duty cycle per fan output.
If the property is present for a fan channel, the driver converts the
configured percentage value to the corresponding PWM duty cycle and
applies it during driver shutdown.
If the property is not present, the fan state remains unchanged.
Signed-off-by: Florin Leotescu <florin.leotescu@nxp.com>
---
drivers/hwmon/emc2305.c | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/drivers/hwmon/emc2305.c b/drivers/hwmon/emc2305.c
index 0b42b82c8e22..dec3a79933c1 100644
--- a/drivers/hwmon/emc2305.c
+++ b/drivers/hwmon/emc2305.c
@@ -32,6 +32,7 @@
#define EMC2305_REG_DRIVE_PWM_OUT 0x2b
#define EMC2305_OPEN_DRAIN 0x0
#define EMC2305_PUSH_PULL 0x1
+#define EMC2305_PWM_SHUTDOWN_UNSET -1
#define EMC2305_PWM_DUTY2STATE(duty, max_state, pwm_max) \
DIV_ROUND_CLOSEST((duty) * (max_state), (pwm_max))
@@ -104,6 +105,7 @@ struct emc2305_cdev_data {
* @pwm_output_mask: PWM output mask
* @pwm_polarity_mask: PWM polarity mask
* @pwm_separate: separate PWM settings for every channel
+ * @pwm_shutdown: Set shutdown PWM.
* @pwm_min: array of minimum PWM per channel
* @pwm_freq: array of PWM frequency per channel
* @cdev_data: array of cooling devices data
@@ -116,6 +118,7 @@ struct emc2305_data {
u8 pwm_output_mask;
u8 pwm_polarity_mask;
bool pwm_separate;
+ s16 pwm_shutdown[EMC2305_PWM_MAX];
u8 pwm_min[EMC2305_PWM_MAX];
u16 pwm_freq[EMC2305_PWM_MAX];
struct emc2305_cdev_data cdev_data[EMC2305_PWM_MAX];
@@ -539,6 +542,7 @@ static int emc2305_of_parse_pwm_child(struct device *dev,
struct device_node *child,
struct emc2305_data *data)
{ u32 ch;
+ u32 pwm_shutdown_percent;
int ret;
struct of_phandle_args args;
@@ -585,6 +589,16 @@ static int emc2305_of_parse_pwm_child(struct device *dev,
}
of_node_put(args.np);
+
+ ret = of_property_read_u32(child, "fan-shutdown-percent",
+ &pwm_shutdown_percent);
+
+ if (!ret) {
+ pwm_shutdown_percent = clamp(pwm_shutdown_percent, 0, 100);
+ data->pwm_shutdown[ch] =
+ DIV_ROUND_CLOSEST(pwm_shutdown_percent * EMC2305_FAN_MAX, 100);
+ }
+
return 0;
}
@@ -637,6 +651,9 @@ static int emc2305_probe(struct i2c_client *client)
if (ret)
return ret;
+ for (i = 0; i < EMC2305_PWM_MAX; i++)
+ data->pwm_shutdown[i] = EMC2305_PWM_SHUTDOWN_UNSET;
+
pwm_childs = emc2305_probe_childs_from_dt(dev);
pdata = dev_get_platdata(&client->dev);
@@ -720,6 +737,23 @@ static int emc2305_probe(struct i2c_client *client)
return 0;
}
+static void emc2305_shutdown(struct i2c_client *client)
+{
+ int i;
+ int ret;
+ struct emc2305_data *data = i2c_get_clientdata(client);
+
+ for (i = 0; i < data->pwm_num; i++) {
+ if (data->pwm_shutdown[i] != EMC2305_PWM_SHUTDOWN_UNSET) {
+ ret = i2c_smbus_write_byte_data(client, EMC2305_REG_FAN_DRIVE(i),
+ data->pwm_shutdown[i]);
+ if (ret < 0)
+ dev_warn(&client->dev,
+ "Failed to set shutdown PWM for ch %d\n", i);
+ }
+ }
+}
+
static const struct of_device_id of_emc2305_match_table[] = {
{ .compatible = "microchip,emc2305", },
{},
@@ -732,6 +766,7 @@ static struct i2c_driver emc2305_driver = {
.of_match_table = of_emc2305_match_table,
},
.probe = emc2305_probe,
+ .shutdown = emc2305_shutdown,
.id_table = emc2305_ids,
};
--
2.34.1
^ permalink raw reply related
* [PATCH v6 2/3] dt-bindings: hwmon: emc2305: Add fan-shutdown-percent property
From: florin.leotescu @ 2026-04-02 12:25 UTC (permalink / raw)
To: Guenter Roeck, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Michael Shych, linux-hwmon, devicetree, linux-kernel
Cc: daniel.baluta, viorel.suman, linux-arm-kernel, imx, festevam,
Florin Leotescu
In-Reply-To: <20260402122514.1811737-1-florin.leotescu@oss.nxp.com>
From: Florin Leotescu <florin.leotescu@nxp.com>
The EMC2305 fan controller supports multiple independent PWM fan
outputs. Some systems require fans to enter a defined safe state
during system shutdown or reboot handoff, until firmware or the next
boot stage reconfigures the controller.
Add an optional "fan-shutdown-percent" property to fan child nodes
allowing the PWM duty cycle applied during shutdown to be configured
per fan output.
Signed-off-by: Florin Leotescu <florin.leotescu@nxp.com>
---
.../devicetree/bindings/hwmon/microchip,emc2305.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml b/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml
index d3f06ebc19fa..8c2548539d7f 100644
--- a/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml
+++ b/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml
@@ -54,6 +54,12 @@ patternProperties:
The fan number used to determine the associated PWM channel.
maxItems: 1
+ fan-shutdown-percent:
+ description:
+ PWM duty cycle in percent applied to the fan during shutdown.
+ minimum: 0
+ maximum: 100
+
required:
- reg
@@ -80,12 +86,14 @@ examples:
fan@0 {
reg = <0x0>;
pwms = <&fan_controller 26000 PWM_POLARITY_INVERTED 1>;
+ fan-shutdown-percent = <100>;
#cooling-cells = <2>;
};
fan@1 {
reg = <0x1>;
pwms = <&fan_controller 26000 0 1>;
+ fan-shutdown-percent = <50>;
#cooling-cells = <2>;
};
--
2.34.1
^ permalink raw reply related
* [PATCH v6 1/3] hwmon: emc2305: Validate fan channel index
From: florin.leotescu @ 2026-04-02 12:25 UTC (permalink / raw)
To: Guenter Roeck, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Michael Shych, linux-hwmon, devicetree, linux-kernel
Cc: daniel.baluta, viorel.suman, linux-arm-kernel, imx, festevam,
Florin Leotescu
In-Reply-To: <20260402122514.1811737-1-florin.leotescu@oss.nxp.com>
From: Florin Leotescu <florin.leotescu@nxp.com>
The fan channel index is used to access per-channel data structures.
Validate the index agains the number of available channels
before use to prevent out-of-bounds access if an invalid
value is provided.
Signed-off-by: Florin Leotescu <florin.leotescu@nxp.com>
---
drivers/hwmon/emc2305.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/hwmon/emc2305.c b/drivers/hwmon/emc2305.c
index 64b213e1451e..0b42b82c8e22 100644
--- a/drivers/hwmon/emc2305.c
+++ b/drivers/hwmon/emc2305.c
@@ -548,6 +548,12 @@ static int emc2305_of_parse_pwm_child(struct device *dev,
return ret;
}
+ if (ch >= data->pwm_num) {
+ dev_err(dev, "invalid reg %u for node %pOF (valid range 0-%u)\n", ch, child,
+ data->pwm_num - 1);
+ return -EINVAL;
+ }
+
ret = of_parse_phandle_with_args(child, "pwms", "#pwm-cells", 0, &args);
if (ret)
--
2.34.1
^ permalink raw reply related
* [PATCH v6 0/3] hwmon: emc2305: Support configurable fan PWM at shutdown
From: florin.leotescu @ 2026-04-02 12:25 UTC (permalink / raw)
To: Guenter Roeck, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Michael Shych, linux-hwmon, devicetree, linux-kernel
Cc: daniel.baluta, viorel.suman, linux-arm-kernel, imx, festevam,
Florin Leotescu
From: Florin Leotescu <florin.leotescu@nxp.com>
This series adds support for configuring the fan PWM duty cycle applied
during system shutdown for the EMC2305 fan controller.
Some platforms require fans to transition to a predefined safe state
during shutdown or reboot handoff until firmware or the next boot stage
reconfigures the controller.
The new optional Device Tree property "fan-shutdown-percent" allows the
shutdown PWM duty cycle to be configured per fan output.
Changes in v6:
- Split fan channel index validation into a separate patch.
Validate fan channel index agains the number of available channels.
- Refine dt-binding commit message to refer to PWM duty cycle
instead of fan speed.
Changes in v5:
- Add fan channel index bound check after reg property read
to prevent out-of-bounds access.
- Refine fan-shutdown-percent description.
Changes in v4:
- Initialize pwm_shudown array to EMC2305_PWM_SHUTDOWN_UNSET in probe,
to avoid treating unconfigured channels as valid and written 0
during shutdown
Changes in v3:
- Rebased on current upstream
- Dropped already upstreamed of_node_put(child) fix
Changes in v2:
- Address feedback from Guenter Roeck
- Make shutdown behavior configurable via Device Tree
- Add optional fan-shutdown-percent property
- Apply shutdown PWM only for channels defining the property
Florin Leotescu (3):
hwmon: emc2305: Validate fan channel index
dt-bindings: hwmon: emc2305: Add fan-shutdown-percent property
hwmon: emc2305: Support configurable fan PWM at shutdown
.../bindings/hwmon/microchip,emc2305.yaml | 8 ++++
drivers/hwmon/emc2305.c | 41 +++++++++++++++++++
2 files changed, 49 insertions(+)
--
2.34.1
^ permalink raw reply
* Re: [PATCH v2 00/24] ASoC: rsnd: Add audio support for the Renesas RZ/G3E SoC
From: Mark Brown @ 2026-04-02 11:55 UTC (permalink / raw)
To: John Madieu
Cc: Geert Uytterhoeven, Kuninori Morimoto, Vinod Koul, Rob Herring,
Krzysztof Kozlowski, Michael Turquette, Stephen Boyd,
Conor Dooley, Frank Li, Liam Girdwood, Magnus Damm,
Thomas Gleixner, Jaroslav Kysela, Takashi Iwai, Philipp Zabel,
Claudiu Beznea, Biju Das, Fabrizio Castro, Lad Prabhakar,
John Madieu, linux-renesas-soc, linux-clk, devicetree,
linux-kernel, dmaengine, linux-sound
In-Reply-To: <20260402090524.9137-1-john.madieu.xa@bp.renesas.com>
[-- Attachment #1: Type: text/plain, Size: 1121 bytes --]
On Thu, Apr 02, 2026 at 11:04:59AM +0200, John Madieu wrote:
> This series adds audio support for the Renesas RZ/G3E SoC and enables
> it on the SMARC EVK board with the Dialog DA7212 codec.
> The RZ/G3E audio subsystem is based on R-Car Sound IP but has several
> differences requiring dedicated handling:
> - SSI operates exclusively in BUSIF mode (no PIO)
> - 2 BUSIF channels per SSI instead of 4/8 on R-Car
> - Different register offsets for SCU, ADG, SSIU, and SSI
> - Per-SSI ADG and SSIF supply clocks
> - DMA ACK signal routing through ICU
>
> This series includes:
> - Clock driver support for audio clocks and resets
> - DT bindings update for DMA ACK signal field
> - IRQ chip extension for DMA ACK signal routing
> - RZ-DMAC driver updates for ACK signal support
> - R-Car Sound driver updates for RZ/G3E support
> - System suspend/resume support
> - Device tree nodes for RZ/G3E SMARC EVK
You said you were going to separate out the serieses:
https://lore.kernel.org/all/TY6PR01MB173779BDE4BE11739D3B7DAACFF4FA@TY6PR01MB17377.jpnprd01.prod.outlook.com/
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^ permalink raw reply
* [PATCH 8/7] dt-bindings: display/msm: qcom,eliza-mdss: Correct DPU and DP ranges in example
From: Krzysztof Kozlowski @ 2026-04-02 11:54 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, dri-devel,
freedreno, devicetree, linux-kernel
Cc: Krzysztof Kozlowski
In-Reply-To: <20260402-dts-qcom-display-regs-v1-0-daa54ab448a3@oss.qualcomm.com>
VBIF register range is 0x3000 long. DisplayPort block has few too short
ranges and misses four more address spaces. Similarly first part of DSI
space should be 0x300 long.
No practical impact, except when existing code is being re-used in new
contributions.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
I forgot about this one, so patch numbering is a bit odd 8/7 :)
.../bindings/display/msm/qcom,eliza-mdss.yaml | 20 +++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,eliza-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,eliza-mdss.yaml
index 47938d13d1ca..bd4ba91a171f 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,eliza-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,eliza-mdss.yaml
@@ -119,7 +119,7 @@ examples:
mdss_mdp: display-controller@ae01000 {
compatible = "qcom,eliza-dpu";
reg = <0x0ae01000 0x93000>,
- <0x0aeb0000 0x2008>;
+ <0x0aeb0000 0x3000>;
reg-names = "mdp",
"vbif";
@@ -304,7 +304,7 @@ examples:
mdss_dsi0_phy: phy@ae95000 {
compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm";
reg = <0x0ae95000 0x200>,
- <0x0ae95200 0x280>,
+ <0x0ae95200 0x300>,
<0x0ae95500 0x400>;
reg-names = "dsi_phy",
"dsi_phy_lane",
@@ -388,7 +388,7 @@ examples:
mdss_dsi1_phy: phy@ae97000 {
compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm";
reg = <0x0ae97000 0x200>,
- <0x0ae97200 0x280>,
+ <0x0ae97200 0x300>,
<0x0ae97500 0x400>;
reg-names = "dsi_phy",
"dsi_phy_lane",
@@ -407,11 +407,15 @@ examples:
displayport-controller@af54000 {
compatible = "qcom,eliza-dp", "qcom,sm8650-dp";
- reg = <0xaf54000 0x104>,
- <0xaf54200 0xc0>,
- <0xaf55000 0x770>,
- <0xaf56000 0x9c>,
- <0xaf57000 0x9c>;
+ reg = <0x0af54000 0x200>,
+ <0x0af54200 0x200>,
+ <0x0af55000 0xc00>,
+ <0x0af56000 0x400>,
+ <0x0af57000 0x400>,
+ <0x0af58000 0x400>,
+ <0x0af59000 0x400>,
+ <0x0af5a000 0x600>,
+ <0x0af5b000 0x600>;
interrupts-extended = <&mdss 12>;
--
2.51.0
^ permalink raw reply related
* Re: [PATCH v2 3/5] dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller
From: Thierry Reding @ 2026-04-02 11:54 UTC (permalink / raw)
To: Rob Herring (Arm)
Cc: Krzysztof Wilczyński, devicetree, linux-tegra, linux-pci,
Bjorn Helgaas, Krzysztof Kozlowski, Lorenzo Pieralisi, Jon Hunter,
Mikko Perttunen, Conor Dooley, Manivannan Sadhasivam
In-Reply-To: <177440189257.2451552.18196101830235626115.robh@kernel.org>
[-- Attachment #1: Type: text/plain, Size: 1397 bytes --]
On Tue, Mar 24, 2026 at 08:24:53PM -0500, Rob Herring (Arm) wrote:
>
> On Fri, 20 Mar 2026 23:54:35 +0100, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> >
> > The six PCIe controllers found on Tegra264 are of two types: one is used
> > for the internal GPU and therefore is not connected to a UPHY and the
> > remaining five controllers are typically routed to a PCI slot and have
> > additional controls for the physical link.
> >
> > While these controllers can be switched into endpoint mode, this binding
> > describes the root complex mode only.
> >
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> > Changes in v2:
> > - move ECAM region first and unify C0 vs. C1-C5
> > - move unevaluatedProperties to right before the examples
> > - add description to clarify the two types of controllers
> > - add examples for C0 and C1-C5
> >
> > .../bindings/pci/nvidia,tegra264-pcie.yaml | 149 ++++++++++++++++++
> > 1 file changed, 149 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
> >
>
> Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Unfortunately making the ECAM region the first entry causes the DTC to
emit a couple of simple_bus_reg warnings, as seen in some more pedantic
build tests. I'll revert this back to the oneOf construct from v1.
Thierry
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^ permalink raw reply
* Re: [PATCH v12 00/15] arm64/riscv: Add support for crashkernel CMA reservation
From: Jinjie Ruan @ 2026-04-02 11:47 UTC (permalink / raw)
To: Borislav Petkov
Cc: corbet, skhan, catalin.marinas, will, chenhuacai, kernel, maddy,
mpe, npiggin, chleroy, pjw, palmer, aou, alex, tglx, mingo,
dave.hansen, hpa, robh, saravanak, akpm, bhe, vgoyal, dyoung,
rdunlap, peterz, pawan.kumar.gupta, feng.tang, dapeng1.mi, kees,
elver, paulmck, lirongqing, rppt, leitao, ardb, jbohac, cfsworks,
tangyouling, sourabhjain, ritesh.list, hbathini, eajames, guoren,
songshuaishuai, kevin.brodsky, vishal.moola, junhui.liu, coxu,
fuqiang.wang, liaoyuanhong, takahiro.akashi, james.morse,
lizhengyu3, x86, linux-doc, linux-kernel, linux-arm-kernel,
loongarch, linuxppc-dev, linux-riscv, devicetree, kexec
In-Reply-To: <20260402113137.GAac5Tmc5b7SL98KdY@fat_crate.local>
On 2026/4/2 19:31, Borislav Petkov wrote:
> On Thu, Apr 02, 2026 at 03:26:46PM +0800, Jinjie Ruan wrote:
>> The crash memory allocation, and the exclude of crashk_res, crashk_low_res
>> and crashk_cma memory are almost identical across different architectures,
>> This patch set handle them in crash core in a general way, which eliminate
>> a lot of duplication code.
>
> From: Documentation/process/submitting-patches.rst
>
> "Don't get discouraged - or impatient
> ------------------------------------
>
> After you have submitted your change, be patient and wait. Reviewers are
> busy people and may not get to your patch right away.
>
> Once upon a time, patches used to disappear into the void without comment,
> but the development process works more smoothly than that now. You should
> receive comments within a week or so; if that does not happen, make sure
> that you have sent your patches to the right place. Wait for a minimum of
> ^^^^^^^^^^^^^^^^^^^^^
>
> one week before resubmitting or pinging reviewers - possibly longer during
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>
> busy times like merge windows."
>
> You need to be patient and send once a week and not spam people:
Thank you for the reminder and for your patience. I apologize for the
frequent updates; I am becoming more familiar with the community's
workflow. I will follow your advice, limit my follow-ups to once a week,
and avoid resending during busy periods like the merge window. I'll wait
for further feedback before taking the next step.
>
> Feb 04 Jinjie Ruan ( :1.0K|) [PATCH v3 0/3] arm64/riscv: Add support for crashkernel CMA reservation
> Feb 09 Jinjie Ruan ( :1.5K|) [PATCH v4 0/3] arm64/riscv: Add support for crashkernel CMA reservation
> Feb 12 Jinjie Ruan ( :2.1K|) [PATCH v5 0/4] arm64/riscv: Add support for crashkernel CMA reservation
> Feb 24 Jinjie Ruan ( :2.3K|) [PATCH v6 0/5] arm64/riscv: Add support for crashkernel CMA reservation
> Feb 26 Jinjie Ruan ( :2.5K|) [PATCH v7 0/5] arm64/riscv: Add support for crashkernel CMA reservation
> Mar 02 Jinjie Ruan ( :2.8K|) [PATCH v8 0/5] arm64/riscv: Add support for crashkernel CMA reservation
> Mar 23 Jinjie Ruan ( :2.9K|) [PATCH v9 0/5] arm64/riscv: Add support for crashkernel CMA reservation
> Mar 25 Jinjie Ruan ( :3.7K|) [PATCH v10 0/8] arm64/riscv: Add support for crashkernel CMA reservation
> Mar 28 Jinjie Ruan ( :4.3K|) [PATCH v11 00/11] arm64/riscv: Add support for crashkernel CMA reservation
> Apr 02 Jinjie Ruan ( :4.5K|) [PATCH v12 00/15] arm64/riscv: Add support for crashkernel CMA reservation
>
^ permalink raw reply
* Re: [PATCH 0/7] qcom: display / dts: Few corrections of address spaces.
From: Krzysztof Kozlowski @ 2026-04-02 11:47 UTC (permalink / raw)
To: Krzysztof Kozlowski, Rob Clark, Dmitry Baryshkov, Abhinav Kumar,
Jessica Zhang, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kuogee Hsieh, Neil Armstrong, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
In-Reply-To: <20260402-dts-qcom-display-regs-v1-0-daa54ab448a3@oss.qualcomm.com>
On 02/04/2026 13:45, Krzysztof Kozlowski wrote:
> These do not have practical impact currently, but make hardware
> description correct.
>
> Patchset can go via separate trees, but DTS should wait for bindings to
> avoid new dtbs_check warnings.
>
> Best regards,
> Krzysztof
>
> ---
> Krzysztof Kozlowski (7):
> dt-bindings: display/msm: dp-controller: Correct SM8650 IO range
> dt-bindings: display/msm: dp-controller: Allow DAI on SM8650
> dt-bindings: display/msm: sm8650: Correct VBIF range in example
> dt-bindings: display/msm: qcom,sm8750-mdss: Correct DPU and DP ranges in example
Uh, 2 seconds after hitting send I understood I forgot about Eliza
bindings which were merged. <crapity crapity crap>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [DMARC error]Re: [PATCH 0/2] Add PWM support Amlogic S7 S7D S6
From: George Stark @ 2026-04-02 11:46 UTC (permalink / raw)
To: Xianwei Zhao, Martin Blumenstingl
Cc: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiner Kallweit, Neil Armstrong, Kevin Hilman,
Jerome Brunet, linux-pwm, devicetree, linux-kernel,
linux-arm-kernel, linux-amlogic, Junyi Zhao
In-Reply-To: <78e05060-6f25-4d78-8b0d-35b8fca0cecb@amlogic.com>
Hello Xianwei Zhao
On 3/31/26 10:59, Xianwei Zhao wrote:
> Hi George,
>
> On 2026/3/31 15:33, George Stark wrote:
>> Hello Martin, Xianwei
>>
>>
>> On 3/31/26 10:10, Xianwei Zhao wrote:
>>> Hi Martin,
>>> I confirmed with Junyi Zhao that the current implementation counts
>>> from zero, so this submission is correct.
>>> We agree this should be fixed and will address it in a follow-up patch.
>>> Thanks for pointing it out.
>>>
>>> On 2026/3/31 05:54, Martin Blumenstingl wrote:
>>>> Hi Xianwei Zhao,
>>>>
>>>> thanks for your contribution!
>>>>
>>>> On Thu, Mar 26, 2026 at 7:35 AM Xianwei Zhao via B4 Relay
>>>> <devnull+xianwei.zhao.amlogic.com@kernel.org> wrote:
>>>>> Add bindings and driver support Amlogic S7/S7D/S6 SoCs.
>>>> There is an old report that got lost, stating that the current
>>
>> Xianwei Zhao thanks for the confirmation.
>> I am the author of the old report and the corresponding patch and it's
>> not lost. So if the patch is correct I'll be glad to add relevant
>> tested-by tags.
>>
>
> I will use your patch and won't send a separate one.
> Do you mean I should add a Tested-by tag to your patch?
Yes since you've confirmed the problem exists then your tested-by tag
would be appropriate. And I'm ok if you resend the patch. Thanks.
>>>> pwm-meson driver has an off-by-one error with the hi and lo fields:
>>>> [0]
>>>> Since you are working on bringing up a new platform: is this something
>>>> you can verify in your lab?
>>>> To be clear: I'm not expecting you to work on this ad-hoc or bring a
>>>> patch into this series. However, it would be great if you could verify
>>>> if the findings from [0] are correct and send an updated patch in
>>>> future.
>>>>
>>>> Thank you and best regards
>>>> Martin
--
Best regards
George
^ permalink raw reply
* [PATCH 7/7] arm64: dts: qcom: sm8750: Correct DPU VBIF address space size
From: Krzysztof Kozlowski @ 2026-04-02 11:45 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kuogee Hsieh, Neil Armstrong,
Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Krzysztof Kozlowski, Krzysztof Kozlowski
In-Reply-To: <20260402-dts-qcom-display-regs-v1-0-daa54ab448a3@oss.qualcomm.com>
VBIF register range is 0x3000 long, so correct the code even though
missing part seems without practical impact.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8750.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index aefe517e0669..f4b8703ef856 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -3041,7 +3041,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
mdss_mdp: display-controller@ae01000 {
compatible = "qcom,sm8750-dpu";
reg = <0x0 0x0ae01000 0x0 0x93000>,
- <0x0 0x0aeb0000 0x0 0x2008>;
+ <0x0 0x0aeb0000 0x0 0x3000>;
reg-names = "mdp",
"vbif";
--
2.51.0
^ permalink raw reply related
* [PATCH 6/7] arm64: dts: qcom: sm8750: Correct and complete DP address spaces
From: Krzysztof Kozlowski @ 2026-04-02 11:45 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kuogee Hsieh, Neil Armstrong,
Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Krzysztof Kozlowski, Krzysztof Kozlowski
In-Reply-To: <20260402-dts-qcom-display-regs-v1-0-daa54ab448a3@oss.qualcomm.com>
DisplayPort block on Qualcomm SM8750 has few too short address space
ranges and misses four more spaces. Complete the hardware description,
which in the future might be important for full feature support.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
dtbs_check success depends on the binding change (first commit).
---
arch/arm64/boot/dts/qcom/sm8750.dtsi | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 18fb52c14acd..aefe517e0669 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -3325,11 +3325,15 @@ mdss_dsi1_phy: phy@ae97000 {
mdss_dp0: displayport-controller@af54000 {
compatible = "qcom,sm8750-dp", "qcom,sm8650-dp";
- reg = <0x0 0xaf54000 0x0 0x104>,
- <0x0 0xaf54200 0x0 0xc0>,
- <0x0 0xaf55000 0x0 0x770>,
- <0x0 0xaf56000 0x0 0x9c>,
- <0x0 0xaf57000 0x0 0x9c>;
+ reg = <0x0 0x0af54000 0x0 0x200>,
+ <0x0 0x0af54200 0x0 0x200>,
+ <0x0 0x0af55000 0x0 0xc00>,
+ <0x0 0x0af56000 0x0 0x400>,
+ <0x0 0x0af57000 0x0 0x400>,
+ <0x0 0x0af58000 0x0 0x400>,
+ <0x0 0x0af59000 0x0 0x400>,
+ <0x0 0x0af5a000 0x0 0x600>,
+ <0x0 0x0af5b000 0x0 0x600>;
interrupts-extended = <&mdss 12>;
--
2.51.0
^ permalink raw reply related
* [PATCH 5/7] arm64: dts: qcom: sm8650: Correct and complete DP address spaces
From: Krzysztof Kozlowski @ 2026-04-02 11:45 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kuogee Hsieh, Neil Armstrong,
Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Krzysztof Kozlowski, Krzysztof Kozlowski
In-Reply-To: <20260402-dts-qcom-display-regs-v1-0-daa54ab448a3@oss.qualcomm.com>
DisplayPort block on Qualcomm SM8650 has few too short address space
ranges and misses four more spaces. Complete the hardware description,
which in the future might be important for full feature support.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
dtbs_check success depends on the binding change (first commit).
---
arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 1604bc8cff37..bc420a44f0b8 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -5868,11 +5868,15 @@ mdss_dsi1_phy: phy@ae97000 {
mdss_dp0: displayport-controller@af54000 {
compatible = "qcom,sm8650-dp";
- reg = <0 0xaf54000 0 0x104>,
- <0 0xaf54200 0 0xc0>,
- <0 0xaf55000 0 0x770>,
- <0 0xaf56000 0 0x9c>,
- <0 0xaf57000 0 0x9c>;
+ reg = <0x0 0x0af54000 0x0 0x200>,
+ <0x0 0x0af54200 0x0 0x200>,
+ <0x0 0x0af55000 0x0 0xc00>,
+ <0x0 0x0af56000 0x0 0x400>,
+ <0x0 0x0af57000 0x0 0x400>,
+ <0x0 0x0af58000 0x0 0x400>,
+ <0x0 0x0af59000 0x0 0x400>,
+ <0x0 0x0af5a000 0x0 0x600>,
+ <0x0 0x0af5b000 0x0 0x600>;
interrupts-extended = <&mdss 12>;
--
2.51.0
^ permalink raw reply related
* [PATCH 4/7] dt-bindings: display/msm: qcom,sm8750-mdss: Correct DPU and DP ranges in example
From: Krzysztof Kozlowski @ 2026-04-02 11:45 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kuogee Hsieh, Neil Armstrong,
Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Krzysztof Kozlowski, Krzysztof Kozlowski
In-Reply-To: <20260402-dts-qcom-display-regs-v1-0-daa54ab448a3@oss.qualcomm.com>
VBIF register range is 0x3000 long. DisplayPort block has few too short
ranges and misses four more address spaces.
No practical impact, except when existing code is being re-used in new
contributions.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
.../bindings/display/msm/qcom,sm8750-mdss.yaml | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml
index a38c2261ef1a..46dc0d28da29 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml
@@ -117,7 +117,7 @@ examples:
display-controller@ae01000 {
compatible = "qcom,sm8750-dpu";
reg = <0x0ae01000 0x93000>,
- <0x0aeb0000 0x2008>;
+ <0x0aeb0000 0x3000>;
reg-names = "mdp",
"vbif";
@@ -389,11 +389,15 @@ examples:
displayport-controller@af54000 {
compatible = "qcom,sm8750-dp", "qcom,sm8650-dp";
- reg = <0xaf54000 0x104>,
- <0xaf54200 0xc0>,
- <0xaf55000 0x770>,
- <0xaf56000 0x9c>,
- <0xaf57000 0x9c>;
+ reg = <0x0af54000 0x200>,
+ <0x0af54200 0x200>,
+ <0x0af55000 0xc00>,
+ <0x0af56000 0x400>,
+ <0x0af57000 0x400>,
+ <0x0af58000 0x400>,
+ <0x0af59000 0x400>,
+ <0x0af5a000 0x600>,
+ <0x0af5b000 0x600>;
interrupts-extended = <&mdss 12>;
--
2.51.0
^ permalink raw reply related
* [PATCH 3/7] dt-bindings: display/msm: sm8650: Correct VBIF range in example
From: Krzysztof Kozlowski @ 2026-04-02 11:45 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kuogee Hsieh, Neil Armstrong,
Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Krzysztof Kozlowski, Krzysztof Kozlowski
In-Reply-To: <20260402-dts-qcom-display-regs-v1-0-daa54ab448a3@oss.qualcomm.com>
VBIF register range is 0x3000 long, so correct the example. No
practical impact, except when existing code is being re-used in new
contributions.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml | 2 +-
Documentation/devicetree/bindings/display/msm/qcom,sm8650-mdss.yaml | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml
index dccac525d202..134321b50897 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml
@@ -70,7 +70,7 @@ examples:
display-controller@ae01000 {
compatible = "qcom,sm8650-dpu";
reg = <0x0ae01000 0x8f000>,
- <0x0aeb0000 0x2008>;
+ <0x0aeb0000 0x3000>;
reg-names = "mdp", "vbif";
clocks = <&gcc_axi_clk>,
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-mdss.yaml
index a1c53e191033..0f7f79527748 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-mdss.yaml
@@ -112,7 +112,7 @@ examples:
display-controller@ae01000 {
compatible = "qcom,sm8650-dpu";
reg = <0x0ae01000 0x8f000>,
- <0x0aeb0000 0x2008>;
+ <0x0aeb0000 0x3000>;
reg-names = "mdp", "vbif";
clocks = <&gcc_axi_clk>,
--
2.51.0
^ permalink raw reply related
* [PATCH 2/7] dt-bindings: display/msm: dp-controller: Allow DAI on SM8650
From: Krzysztof Kozlowski @ 2026-04-02 11:45 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kuogee Hsieh, Neil Armstrong,
Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Krzysztof Kozlowski, Krzysztof Kozlowski
In-Reply-To: <20260402-dts-qcom-display-regs-v1-0-daa54ab448a3@oss.qualcomm.com>
DisplayPort on Qualcomm SM8650 (and compatible SM8750) supports audio
and there is DTS already having cells and sound-name-prefix. Add SM8650
to the list of SoCs referencing the dai-common.yaml schema to solve
dtbs_check warnings like:
sm8650-hdk-display-card-rear-camera-card.dtb:
displayport-controller@af54000 (qcom,sm8650-dp): Unevaluated properties are not allowed ('sound-name-prefix' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
index e4f17d29343b..f8daaee8d065 100644
--- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -210,6 +210,7 @@ allOf:
enum:
- qcom,glymur-dp
- qcom,sa8775p-dp
+ - qcom,sm8650-dp
- qcom,x1e80100-dp
then:
$ref: /schemas/sound/dai-common.yaml#
--
2.51.0
^ permalink raw reply related
* [PATCH 1/7] dt-bindings: display/msm: dp-controller: Correct SM8650 IO range
From: Krzysztof Kozlowski @ 2026-04-02 11:45 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kuogee Hsieh, Neil Armstrong,
Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Krzysztof Kozlowski, Krzysztof Kozlowski
In-Reply-To: <20260402-dts-qcom-display-regs-v1-0-daa54ab448a3@oss.qualcomm.com>
DP on Qualcomm SM8650 come with nine address ranges, so describe the
remaining ones as optional to keep ABI backwards compatible. Driver
also does not need them to operate correctly.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
.../bindings/display/msm/dp-controller.yaml | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
index 8239adb7f7d3..e4f17d29343b 100644
--- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -277,7 +277,6 @@ allOf:
- qcom,sc8180x-dp
- qcom,sdm845-dp
- qcom,sm8350-dp
- - qcom,sm8650-dp
then:
properties:
reg:
@@ -290,6 +289,24 @@ allOf:
minItems: 6
maxItems: 6
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8650-dp
+ then:
+ properties:
+ reg:
+ minItems: 5
+ maxItems: 9
+ clocks:
+ minItems: 6
+ maxItems: 6
+ clocks-names:
+ minItems: 6
+ maxItems: 6
+
- if:
properties:
compatible:
--
2.51.0
^ permalink raw reply related
* [PATCH 0/7] qcom: display / dts: Few corrections of address spaces.
From: Krzysztof Kozlowski @ 2026-04-02 11:45 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kuogee Hsieh, Neil Armstrong,
Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Krzysztof Kozlowski, Krzysztof Kozlowski
These do not have practical impact currently, but make hardware
description correct.
Patchset can go via separate trees, but DTS should wait for bindings to
avoid new dtbs_check warnings.
Best regards,
Krzysztof
---
Krzysztof Kozlowski (7):
dt-bindings: display/msm: dp-controller: Correct SM8650 IO range
dt-bindings: display/msm: dp-controller: Allow DAI on SM8650
dt-bindings: display/msm: sm8650: Correct VBIF range in example
dt-bindings: display/msm: qcom,sm8750-mdss: Correct DPU and DP ranges in example
arm64: dts: qcom: sm8650: Correct and complete DP address spaces
arm64: dts: qcom: sm8750: Correct and complete DP address spaces
arm64: dts: qcom: sm8750: Correct DPU VBIF address space size
.../bindings/display/msm/dp-controller.yaml | 20 +++++++++++++++++++-
.../bindings/display/msm/qcom,sm8650-dpu.yaml | 2 +-
.../bindings/display/msm/qcom,sm8650-mdss.yaml | 2 +-
.../bindings/display/msm/qcom,sm8750-mdss.yaml | 16 ++++++++++------
arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 +++++++++-----
arch/arm64/boot/dts/qcom/sm8750.dtsi | 16 ++++++++++------
6 files changed, 50 insertions(+), 20 deletions(-)
---
base-commit: 36ece9697e89016181e5ae87510e40fb31d86f2b
change-id: 20260402-dts-qcom-display-regs-11d61816e172
Best regards,
--
Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH v12 00/15] arm64/riscv: Add support for crashkernel CMA reservation
From: Borislav Petkov @ 2026-04-02 11:31 UTC (permalink / raw)
To: Jinjie Ruan
Cc: corbet, skhan, catalin.marinas, will, chenhuacai, kernel, maddy,
mpe, npiggin, chleroy, pjw, palmer, aou, alex, tglx, mingo,
dave.hansen, hpa, robh, saravanak, akpm, bhe, vgoyal, dyoung,
rdunlap, peterz, pawan.kumar.gupta, feng.tang, dapeng1.mi, kees,
elver, paulmck, lirongqing, rppt, leitao, ardb, jbohac, cfsworks,
tangyouling, sourabhjain, ritesh.list, hbathini, eajames, guoren,
songshuaishuai, kevin.brodsky, vishal.moola, junhui.liu, coxu,
fuqiang.wang, liaoyuanhong, takahiro.akashi, james.morse,
lizhengyu3, x86, linux-doc, linux-kernel, linux-arm-kernel,
loongarch, linuxppc-dev, linux-riscv, devicetree, kexec
In-Reply-To: <20260402072701.628293-1-ruanjinjie@huawei.com>
On Thu, Apr 02, 2026 at 03:26:46PM +0800, Jinjie Ruan wrote:
> The crash memory allocation, and the exclude of crashk_res, crashk_low_res
> and crashk_cma memory are almost identical across different architectures,
> This patch set handle them in crash core in a general way, which eliminate
> a lot of duplication code.
From: Documentation/process/submitting-patches.rst
"Don't get discouraged - or impatient
------------------------------------
After you have submitted your change, be patient and wait. Reviewers are
busy people and may not get to your patch right away.
Once upon a time, patches used to disappear into the void without comment,
but the development process works more smoothly than that now. You should
receive comments within a week or so; if that does not happen, make sure
that you have sent your patches to the right place. Wait for a minimum of
^^^^^^^^^^^^^^^^^^^^^
one week before resubmitting or pinging reviewers - possibly longer during
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
busy times like merge windows."
You need to be patient and send once a week and not spam people:
Feb 04 Jinjie Ruan ( :1.0K|) [PATCH v3 0/3] arm64/riscv: Add support for crashkernel CMA reservation
Feb 09 Jinjie Ruan ( :1.5K|) [PATCH v4 0/3] arm64/riscv: Add support for crashkernel CMA reservation
Feb 12 Jinjie Ruan ( :2.1K|) [PATCH v5 0/4] arm64/riscv: Add support for crashkernel CMA reservation
Feb 24 Jinjie Ruan ( :2.3K|) [PATCH v6 0/5] arm64/riscv: Add support for crashkernel CMA reservation
Feb 26 Jinjie Ruan ( :2.5K|) [PATCH v7 0/5] arm64/riscv: Add support for crashkernel CMA reservation
Mar 02 Jinjie Ruan ( :2.8K|) [PATCH v8 0/5] arm64/riscv: Add support for crashkernel CMA reservation
Mar 23 Jinjie Ruan ( :2.9K|) [PATCH v9 0/5] arm64/riscv: Add support for crashkernel CMA reservation
Mar 25 Jinjie Ruan ( :3.7K|) [PATCH v10 0/8] arm64/riscv: Add support for crashkernel CMA reservation
Mar 28 Jinjie Ruan ( :4.3K|) [PATCH v11 00/11] arm64/riscv: Add support for crashkernel CMA reservation
Apr 02 Jinjie Ruan ( :4.5K|) [PATCH v12 00/15] arm64/riscv: Add support for crashkernel CMA reservation
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
^ permalink raw reply
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