* [PATCH 08/11] media: iris: Add power sequence for Glymur
From: Vishnu Reddy @ 2026-04-14 5:00 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joerg Roedel, Will Deacon,
Robin Murphy, Bjorn Andersson, Konrad Dybcio, Stefan Schmidt,
Hans Verkuil
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, iommu,
Vishnu Reddy
In-Reply-To: <20260414-glymur-v1-0-7d3d1cf57b16@oss.qualcomm.com>
Add power sequence hooks for controller, vcodec and vcodec1. reuse the
existing code where ever is possible. add vcodec1 power on and off code
separately which has different power domains and clocks.
Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
---
.../platform/qcom/iris/iris_platform_common.h | 9 ++
drivers/media/platform/qcom/iris/iris_vpu3x.c | 123 +++++++++++++++++++++
drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 +
.../platform/qcom/iris/iris_vpu_register_defines.h | 7 ++
4 files changed, 140 insertions(+)
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index 30e9d4d288c6..e3c1aff770dd 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -61,6 +61,9 @@ enum platform_clk_type {
IRIS_VPP0_HW_CLK,
IRIS_VPP1_HW_CLK,
IRIS_APV_HW_CLK,
+ IRIS_AXI_VCODEC1_CLK,
+ IRIS_VCODEC1_CLK,
+ IRIS_VCODEC1_FREERUN_CLK,
};
struct platform_clk_data {
@@ -208,6 +211,12 @@ enum platform_pm_domain_type {
IRIS_CTRL_POWER_DOMAIN,
IRIS_VCODEC_POWER_DOMAIN,
IRIS_VPP0_HW_POWER_DOMAIN,
+ /*
+ * On Glymur, vcodec1 power domain is at the same index in pd_devs[]
+ * as IRIS_VPP0_HW_POWER_DOMAIN. Alias it so that the Glymur power
+ * domain table is indexed correctly.
+ */
+ IRIS_VCODEC1_POWER_DOMAIN = IRIS_VPP0_HW_POWER_DOMAIN,
IRIS_VPP1_HW_POWER_DOMAIN,
IRIS_APV_HW_POWER_DOMAIN,
};
diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c
index 1f0a3a47d87f..3f269f242b36 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu3x.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c
@@ -27,6 +27,16 @@ static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core)
return pwr_status ? false : true;
}
+static bool iris_vpu36_hw1_power_collapsed(struct iris_core *core)
+{
+ u32 value, pwr_status;
+
+ value = readl(core->reg_base + WRAPPER_CORE_POWER_STATUS);
+ pwr_status = value & BIT(4);
+
+ return pwr_status ? false : true;
+}
+
static void iris_vpu3_power_off_hardware(struct iris_core *core)
{
u32 reg_val = 0, value, i;
@@ -261,6 +271,111 @@ static void iris_vpu35_power_off_hw(struct iris_core *core)
iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);
}
+static int iris_vpu36_power_on_hw1(struct iris_core *core)
+{
+ int ret;
+
+ ret = iris_enable_power_domains(core,
+ core->pmdomain_tbl->pd_devs[IRIS_VCODEC1_POWER_DOMAIN]);
+ if (ret)
+ return ret;
+
+ ret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC1_CLK);
+ if (ret)
+ goto err_disable_hw1_power;
+
+ ret = iris_prepare_enable_clock(core, IRIS_VCODEC1_FREERUN_CLK);
+ if (ret)
+ goto err_disable_axi1_clk;
+
+ ret = iris_prepare_enable_clock(core, IRIS_VCODEC1_CLK);
+ if (ret)
+ goto err_disable_hw1_free_clk;
+
+ ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC1_POWER_DOMAIN], true);
+ if (ret)
+ goto err_disable_hw1_clk;
+
+ return 0;
+
+err_disable_hw1_clk:
+ iris_disable_unprepare_clock(core, IRIS_VCODEC1_CLK);
+err_disable_hw1_free_clk:
+ iris_disable_unprepare_clock(core, IRIS_VCODEC1_FREERUN_CLK);
+err_disable_axi1_clk:
+ iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC1_CLK);
+err_disable_hw1_power:
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC1_POWER_DOMAIN]);
+
+ return ret;
+}
+
+static int iris_vpu36_power_on_hw(struct iris_core *core)
+{
+ int ret;
+
+ ret = iris_vpu35_power_on_hw(core);
+ if (ret)
+ return ret;
+
+ ret = iris_vpu36_power_on_hw1(core);
+ if (ret)
+ goto err_power_off_hw;
+
+ return 0;
+
+err_power_off_hw:
+ iris_vpu35_power_off_hw(core);
+
+ return ret;
+}
+
+static void iris_vpu36_power_off_hw1(struct iris_core *core)
+{
+ u32 value, i;
+ int ret;
+
+ if (iris_vpu36_hw1_power_collapsed(core))
+ goto disable_power;
+
+ value = readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG);
+ if (value)
+ writel(CORE_CLK_RUN, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG);
+
+ for (i = 0; i < core->iris_platform_data->num_vpp_pipe; i++) {
+ ret = readl_poll_timeout(core->reg_base + VCODEC1_SS_IDLE_STATUSN + 4 * i,
+ value, value & DMA_NOC_IDLE, 2000, 20000);
+ if (ret)
+ goto disable_power;
+ }
+
+ writel(REQ_VCODEC1_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
+ ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS,
+ value, value & NOC_LPI_VCODEC1_STATUS_DONE, 2000, 20000);
+ if (ret)
+ goto disable_power;
+
+ writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
+
+ writel(VCODEC1_BRIDGE_SW_RESET | VCODEC1_BRIDGE_HW_RESET_DISABLE, core->reg_base +
+ CPU_CS_AHB_BRIDGE_SYNC_RESET);
+ writel(VCODEC1_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
+ writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
+
+disable_power:
+ dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC1_POWER_DOMAIN], false);
+ iris_disable_unprepare_clock(core, IRIS_VCODEC1_CLK);
+ iris_disable_unprepare_clock(core, IRIS_VCODEC1_FREERUN_CLK);
+ iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC1_CLK);
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC1_POWER_DOMAIN]);
+}
+
+static void iris_vpu36_power_off_hw(struct iris_core *core)
+{
+ iris_vpu35_power_off_hw(core);
+ iris_vpu36_power_off_hw1(core);
+}
+
const struct vpu_ops iris_vpu3_ops = {
.power_off_hw = iris_vpu3_power_off_hardware,
.power_on_hw = iris_vpu_power_on_hw,
@@ -285,3 +400,11 @@ const struct vpu_ops iris_vpu35_ops = {
.program_bootup_registers = iris_vpu35_vpu4x_program_bootup_registers,
.calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
};
+
+const struct vpu_ops iris_vpu36_ops = {
+ .power_off_hw = iris_vpu36_power_off_hw,
+ .power_on_hw = iris_vpu36_power_on_hw,
+ .power_off_controller = iris_vpu35_vpu4x_power_off_controller,
+ .power_on_controller = iris_vpu35_vpu4x_power_on_controller,
+ .calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
+};
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h
index f6dffc613b82..99e75fb4b10d 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.h
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h
@@ -12,6 +12,7 @@ extern const struct vpu_ops iris_vpu2_ops;
extern const struct vpu_ops iris_vpu3_ops;
extern const struct vpu_ops iris_vpu33_ops;
extern const struct vpu_ops iris_vpu35_ops;
+extern const struct vpu_ops iris_vpu36_ops;
extern const struct vpu_ops iris_vpu4x_ops;
struct vpu_ops {
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
index 72168b9ffa73..37f234484f1b 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
+++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
@@ -7,6 +7,7 @@
#define __IRIS_VPU_REGISTER_DEFINES_H__
#define VCODEC_BASE_OFFS 0x00000000
+#define VCODEC1_BASE_OFFS 0x00040000
#define AON_MVP_NOC_RESET 0x0001F000
#define CPU_BASE_OFFS 0x000A0000
#define WRAPPER_BASE_OFFS 0x000B0000
@@ -14,6 +15,8 @@
#define AON_BASE_OFFS 0x000E0000
#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70)
+#define VCODEC1_SS_IDLE_STATUSN (VCODEC1_BASE_OFFS + 0x70)
+#define DMA_NOC_IDLE BIT(22)
#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000)
#define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1))
@@ -35,6 +38,8 @@
#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160)
#define CORE_BRIDGE_SW_RESET BIT(0)
#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1)
+#define VCODEC1_BRIDGE_SW_RESET BIT(2)
+#define VCODEC1_BRIDGE_HW_RESET_DISABLE BIT(3)
#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
@@ -52,11 +57,13 @@
#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
#define REQ_POWER_DOWN_PREP BIT(0)
+#define REQ_VCODEC1_POWER_DOWN_PREP BIT(1)
#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */
#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */
#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */
+#define NOC_LPI_VCODEC1_STATUS_DONE BIT(8)
#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78)
#define WRAPPER_CORE_POWER_STATUS (WRAPPER_BASE_OFFS + 0x80)
--
2.34.1
^ permalink raw reply related
* [PATCH 07/11] media: iris: Rename clock and power domain macros to use vcodec prefix
From: Vishnu Reddy @ 2026-04-14 5:00 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joerg Roedel, Will Deacon,
Robin Murphy, Bjorn Andersson, Konrad Dybcio, Stefan Schmidt,
Hans Verkuil
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, iommu,
Vishnu Reddy
In-Reply-To: <20260414-glymur-v1-0-7d3d1cf57b16@oss.qualcomm.com>
The current clock and power domain enum names are too generic. Rename
them with a vcodec prefix to make the names more meaningful and to easily
accommodate vcodec1 enums for the secondary core in the following patches.
This patch only renames the macros and does not introduce any functional
changes.
Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
---
.../platform/qcom/iris/iris_platform_common.h | 12 ++++----
.../media/platform/qcom/iris/iris_platform_gen1.c | 6 ++--
.../media/platform/qcom/iris/iris_platform_gen2.c | 6 ++--
.../platform/qcom/iris/iris_platform_sc7280.h | 10 +++----
.../platform/qcom/iris/iris_platform_sm8750.h | 12 ++++----
drivers/media/platform/qcom/iris/iris_vpu3x.c | 25 ++++++++--------
drivers/media/platform/qcom/iris/iris_vpu4x.c | 30 ++++++++++---------
drivers/media/platform/qcom/iris/iris_vpu_common.c | 35 +++++++++++-----------
8 files changed, 70 insertions(+), 66 deletions(-)
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index 55ff6137d9a9..30e9d4d288c6 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -49,14 +49,14 @@ extern const struct iris_platform_data sm8650_data;
extern const struct iris_platform_data sm8750_data;
enum platform_clk_type {
- IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */
+ IRIS_AXI_VCODEC_CLK,
IRIS_CTRL_CLK,
IRIS_AHB_CLK,
- IRIS_HW_CLK,
- IRIS_HW_AHB_CLK,
- IRIS_AXI1_CLK,
+ IRIS_VCODEC_CLK,
+ IRIS_VCODEC_AHB_CLK,
+ IRIS_AXI_CTRL_CLK,
IRIS_CTRL_FREERUN_CLK,
- IRIS_HW_FREERUN_CLK,
+ IRIS_VCODEC_FREERUN_CLK,
IRIS_BSE_HW_CLK,
IRIS_VPP0_HW_CLK,
IRIS_VPP1_HW_CLK,
@@ -206,7 +206,7 @@ struct icc_vote_data {
enum platform_pm_domain_type {
IRIS_CTRL_POWER_DOMAIN,
- IRIS_HW_POWER_DOMAIN,
+ IRIS_VCODEC_POWER_DOMAIN,
IRIS_VPP0_HW_POWER_DOMAIN,
IRIS_VPP1_HW_POWER_DOMAIN,
IRIS_APV_HW_POWER_DOMAIN,
diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c
index df8e6bf9430e..be6a631f8ede 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c
@@ -284,9 +284,9 @@ static const char * const sm8250_pmdomain_table[] = { "venus", "vcodec0" };
static const char * const sm8250_opp_pd_table[] = { "mx" };
static const struct platform_clk_data sm8250_clk_table[] = {
- {IRIS_AXI_CLK, "iface" },
- {IRIS_CTRL_CLK, "core" },
- {IRIS_HW_CLK, "vcodec0_core" },
+ {IRIS_AXI_VCODEC_CLK, "iface" },
+ {IRIS_CTRL_CLK, "core" },
+ {IRIS_VCODEC_CLK, "vcodec0_core" },
};
static const char * const sm8250_opp_clk_table[] = {
diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
index 5da90d47f9c6..47c6b650f0b4 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
@@ -780,9 +780,9 @@ static const char * const sm8550_pmdomain_table[] = { "venus", "vcodec0" };
static const char * const sm8550_opp_pd_table[] = { "mxc", "mmcx" };
static const struct platform_clk_data sm8550_clk_table[] = {
- {IRIS_AXI_CLK, "iface" },
- {IRIS_CTRL_CLK, "core" },
- {IRIS_HW_CLK, "vcodec0_core" },
+ {IRIS_AXI_VCODEC_CLK, "iface" },
+ {IRIS_CTRL_CLK, "core" },
+ {IRIS_VCODEC_CLK, "vcodec0_core" },
};
static const char * const sm8550_opp_clk_table[] = {
diff --git a/drivers/media/platform/qcom/iris/iris_platform_sc7280.h b/drivers/media/platform/qcom/iris/iris_platform_sc7280.h
index 0ec8f334df67..6b783e524b81 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_sc7280.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_sc7280.h
@@ -16,11 +16,11 @@ static const struct bw_info sc7280_bw_table_dec[] = {
static const char * const sc7280_opp_pd_table[] = { "cx" };
static const struct platform_clk_data sc7280_clk_table[] = {
- {IRIS_CTRL_CLK, "core" },
- {IRIS_AXI_CLK, "iface" },
- {IRIS_AHB_CLK, "bus" },
- {IRIS_HW_CLK, "vcodec_core" },
- {IRIS_HW_AHB_CLK, "vcodec_bus" },
+ {IRIS_CTRL_CLK, "core" },
+ {IRIS_AXI_VCODEC_CLK, "iface" },
+ {IRIS_AHB_CLK, "bus" },
+ {IRIS_VCODEC_CLK, "vcodec_core" },
+ {IRIS_VCODEC_AHB_CLK, "vcodec_bus" },
};
static const char * const sc7280_opp_clk_table[] = {
diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8750.h b/drivers/media/platform/qcom/iris/iris_platform_sm8750.h
index 719056656a5b..f843f13251c5 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_sm8750.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_sm8750.h
@@ -11,12 +11,12 @@ static const char * const sm8750_clk_reset_table[] = {
};
static const struct platform_clk_data sm8750_clk_table[] = {
- {IRIS_AXI_CLK, "iface" },
- {IRIS_CTRL_CLK, "core" },
- {IRIS_HW_CLK, "vcodec0_core" },
- {IRIS_AXI1_CLK, "iface1" },
- {IRIS_CTRL_FREERUN_CLK, "core_freerun" },
- {IRIS_HW_FREERUN_CLK, "vcodec0_core_freerun" },
+ {IRIS_AXI_VCODEC_CLK, "iface" },
+ {IRIS_CTRL_CLK, "core" },
+ {IRIS_VCODEC_CLK, "vcodec0_core" },
+ {IRIS_AXI_CTRL_CLK, "iface1" },
+ {IRIS_CTRL_FREERUN_CLK, "core_freerun" },
+ {IRIS_VCODEC_FREERUN_CLK, "vcodec0_core_freerun" },
};
#endif
diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c
index fe4423b951b1..1f0a3a47d87f 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu3x.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c
@@ -209,7 +209,7 @@ static int iris_vpu33_power_off_controller(struct iris_core *core)
disable_power:
iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
- iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
+ iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);
return 0;
}
@@ -218,36 +218,37 @@ static int iris_vpu35_power_on_hw(struct iris_core *core)
{
int ret;
- ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+ ret = iris_enable_power_domains(core,
+ core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);
if (ret)
return ret;
- ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK);
+ ret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC_CLK);
if (ret)
goto err_disable_power;
- ret = iris_prepare_enable_clock(core, IRIS_HW_FREERUN_CLK);
+ ret = iris_prepare_enable_clock(core, IRIS_VCODEC_FREERUN_CLK);
if (ret)
goto err_disable_axi_clk;
- ret = iris_prepare_enable_clock(core, IRIS_HW_CLK);
+ ret = iris_prepare_enable_clock(core, IRIS_VCODEC_CLK);
if (ret)
goto err_disable_hw_free_clk;
- ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], true);
+ ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], true);
if (ret)
goto err_disable_hw_clk;
return 0;
err_disable_hw_clk:
- iris_disable_unprepare_clock(core, IRIS_HW_CLK);
+ iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK);
err_disable_hw_free_clk:
- iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK);
+ iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK);
err_disable_axi_clk:
- iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
+ iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);
err_disable_power:
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);
return ret;
}
@@ -256,8 +257,8 @@ static void iris_vpu35_power_off_hw(struct iris_core *core)
{
iris_vpu33_power_off_hardware(core);
- iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK);
- iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
+ iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK);
+ iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);
}
const struct vpu_ops iris_vpu3_ops = {
diff --git a/drivers/media/platform/qcom/iris/iris_vpu4x.c b/drivers/media/platform/qcom/iris/iris_vpu4x.c
index a8db02ce5c5e..4082d331d2f3 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu4x.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu4x.c
@@ -27,7 +27,8 @@ static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode, u32
{
int ret;
- ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], hw_mode);
+ ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN],
+ hw_mode);
if (ret)
return ret;
@@ -63,7 +64,7 @@ static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode, u32
dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP0_HW_POWER_DOMAIN],
!hw_mode);
restore_hw_domain_mode:
- dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], !hw_mode);
+ dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], !hw_mode);
return ret;
}
@@ -162,15 +163,15 @@ static int iris_vpu4x_enable_hardware_clocks(struct iris_core *core, u32 efuse_v
{
int ret;
- ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK);
+ ret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC_CLK);
if (ret)
return ret;
- ret = iris_prepare_enable_clock(core, IRIS_HW_FREERUN_CLK);
+ ret = iris_prepare_enable_clock(core, IRIS_VCODEC_FREERUN_CLK);
if (ret)
goto disable_axi_clock;
- ret = iris_prepare_enable_clock(core, IRIS_HW_CLK);
+ ret = iris_prepare_enable_clock(core, IRIS_VCODEC_CLK);
if (ret)
goto disable_hw_free_run_clock;
@@ -198,11 +199,11 @@ static int iris_vpu4x_enable_hardware_clocks(struct iris_core *core, u32 efuse_v
disable_bse_hw_clock:
iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK);
disable_hw_clock:
- iris_disable_unprepare_clock(core, IRIS_HW_CLK);
+ iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK);
disable_hw_free_run_clock:
- iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK);
+ iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK);
disable_axi_clock:
- iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
+ iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);
return ret;
}
@@ -216,9 +217,9 @@ static void iris_vpu4x_disable_hardware_clocks(struct iris_core *core, u32 efuse
iris_disable_unprepare_clock(core, IRIS_VPP0_HW_CLK);
iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK);
- iris_disable_unprepare_clock(core, IRIS_HW_CLK);
- iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK);
- iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
+ iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK);
+ iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK);
+ iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);
}
static int iris_vpu4x_power_on_hardware(struct iris_core *core)
@@ -226,7 +227,8 @@ static int iris_vpu4x_power_on_hardware(struct iris_core *core)
u32 efuse_value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR);
int ret;
- ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+ ret = iris_enable_power_domains(core,
+ core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);
if (ret)
return ret;
@@ -278,7 +280,7 @@ static int iris_vpu4x_power_on_hardware(struct iris_core *core)
iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs
[IRIS_VPP0_HW_POWER_DOMAIN]);
disable_hw_power_domain:
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);
return ret;
}
@@ -356,7 +358,7 @@ static void iris_vpu4x_power_off_hardware(struct iris_core *core)
iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs
[IRIS_VPP0_HW_POWER_DOMAIN]);
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);
}
const struct vpu_ops iris_vpu4x_ops = {
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
index bfd1e762c38e..006fd3ffc752 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
@@ -213,7 +213,7 @@ int iris_vpu_power_off_controller(struct iris_core *core)
disable_power:
iris_disable_unprepare_clock(core, IRIS_AHB_CLK);
iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
- iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
+ iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);
iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
return 0;
@@ -221,10 +221,10 @@ int iris_vpu_power_off_controller(struct iris_core *core)
void iris_vpu_power_off_hw(struct iris_core *core)
{
- dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], false);
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
- iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK);
- iris_disable_unprepare_clock(core, IRIS_HW_CLK);
+ dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], false);
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);
+ iris_disable_unprepare_clock(core, IRIS_VCODEC_AHB_CLK);
+ iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK);
}
void iris_vpu_power_off(struct iris_core *core)
@@ -251,7 +251,7 @@ int iris_vpu_power_on_controller(struct iris_core *core)
if (ret)
goto err_disable_power;
- ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK);
+ ret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC_CLK);
if (ret)
goto err_disable_power;
@@ -268,7 +268,7 @@ int iris_vpu_power_on_controller(struct iris_core *core)
err_disable_ctrl_clock:
iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
err_disable_axi_clock:
- iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
+ iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);
err_disable_power:
iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
@@ -279,30 +279,31 @@ int iris_vpu_power_on_hw(struct iris_core *core)
{
int ret;
- ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+ ret = iris_enable_power_domains(core,
+ core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);
if (ret)
return ret;
- ret = iris_prepare_enable_clock(core, IRIS_HW_CLK);
+ ret = iris_prepare_enable_clock(core, IRIS_VCODEC_CLK);
if (ret)
goto err_disable_power;
- ret = iris_prepare_enable_clock(core, IRIS_HW_AHB_CLK);
+ ret = iris_prepare_enable_clock(core, IRIS_VCODEC_AHB_CLK);
if (ret && ret != -ENOENT)
goto err_disable_hw_clock;
- ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], true);
+ ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], true);
if (ret)
goto err_disable_hw_ahb_clock;
return 0;
err_disable_hw_ahb_clock:
- iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK);
+ iris_disable_unprepare_clock(core, IRIS_VCODEC_AHB_CLK);
err_disable_hw_clock:
- iris_disable_unprepare_clock(core, IRIS_HW_CLK);
+ iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK);
err_disable_power:
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);
return ret;
}
@@ -362,7 +363,7 @@ int iris_vpu35_vpu4x_power_off_controller(struct iris_core *core)
disable_power:
iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK);
- iris_disable_unprepare_clock(core, IRIS_AXI1_CLK);
+ iris_disable_unprepare_clock(core, IRIS_AXI_CTRL_CLK);
iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
@@ -379,7 +380,7 @@ int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core)
if (ret)
return ret;
- ret = iris_prepare_enable_clock(core, IRIS_AXI1_CLK);
+ ret = iris_prepare_enable_clock(core, IRIS_AXI_CTRL_CLK);
if (ret)
goto err_disable_power;
@@ -396,7 +397,7 @@ int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core)
err_disable_ctrl_free_clk:
iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK);
err_disable_axi1_clk:
- iris_disable_unprepare_clock(core, IRIS_AXI1_CLK);
+ iris_disable_unprepare_clock(core, IRIS_AXI_CTRL_CLK);
err_disable_power:
iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
--
2.34.1
^ permalink raw reply related
* [PATCH 06/11] media: iris: Fix VM count passed to firmware
From: Vishnu Reddy @ 2026-04-14 5:00 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joerg Roedel, Will Deacon,
Robin Murphy, Bjorn Andersson, Konrad Dybcio, Stefan Schmidt,
Hans Verkuil
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, iommu,
Vishnu Reddy, stable
In-Reply-To: <20260414-glymur-v1-0-7d3d1cf57b16@oss.qualcomm.com>
On Glymur, firmware interprets the value written to CPU_CS_SCIACMDARG3 as
the number of virtual machines (VMs) and internally adds 1 to it. Writing
1 causes firmware to treat it as 2 VMs. Since only one VM is required,
remove this write to leave the register at its reset value of 0. This does
not affect other platforms as only Glymur firmware uses this register,
earlier platform firmwares ignore it.
Fixes: abf5bac63f68a ("media: iris: implement the boot sequence of the firmware")
Cc: stable@vger.kernel.org
Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_vpu_common.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
index 548e5f1727fd..bfd1e762c38e 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
@@ -78,7 +78,6 @@ int iris_vpu_boot_firmware(struct iris_core *core)
iris_vpu_setup_ucregion_memory_map(core);
writel(ctrl_init, core->reg_base + CTRL_INIT);
- writel(0x1, core->reg_base + CPU_CS_SCIACMDARG3);
while (!ctrl_status && count < max_tries) {
ctrl_status = readl(core->reg_base + CTRL_STATUS);
--
2.34.1
^ permalink raw reply related
* [PATCH 05/11] media: iris: Enable Secure PAS support with IOMMU managed by Linux
From: Vishnu Reddy @ 2026-04-14 5:00 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joerg Roedel, Will Deacon,
Robin Murphy, Bjorn Andersson, Konrad Dybcio, Stefan Schmidt,
Hans Verkuil
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, iommu,
Vishnu Reddy, Mukesh Ojha
In-Reply-To: <20260414-glymur-v1-0-7d3d1cf57b16@oss.qualcomm.com>
From: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Most Qualcomm platforms feature a proprietary hypervisor (such as Gunyah
or QHEE), which typically handles IOMMU configuration. This includes
mapping memory regions and device memory resources for remote processors
by intercepting qcom_scm_pas_auth_and_reset() calls. These mappings are
later removed during teardown. Additionally, SHM bridge setup is required
to enable memory protection for both remoteproc metadata and its memory
regions.
When the hypervisor is absent, the operating system must perform these
configurations instead.
Support for handling IOMMU and SHM setup in the absence of a hypervisor
is now in place. Extend the Iris driver to enable this functionality on
platforms where IOMMU is managed by Linux (i.e., non-Gunyah, non-QHEE).
Additionally, the Iris driver must map the firmware and its required
resources to the firmware SID, which is now specified via iommu-map in
the device tree.
Co-developed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_core.h | 4 ++
drivers/media/platform/qcom/iris/iris_firmware.c | 71 +++++++++++++++++++++---
2 files changed, 66 insertions(+), 9 deletions(-)
diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h
index fb194c967ad4..aa7abef6f0e0 100644
--- a/drivers/media/platform/qcom/iris/iris_core.h
+++ b/drivers/media/platform/qcom/iris/iris_core.h
@@ -34,6 +34,8 @@ enum domain_type {
* struct iris_core - holds core parameters valid for all instances
*
* @dev: reference to device structure
+ * @dev_fw: reference to the context bank device used for firmware load
+ * @ctx_fw: SCM PAS context for authenticated firmware load and shutdown
* @reg_base: IO memory base address
* @irq: iris irq
* @v4l2_dev: a holder for v4l2 device structure
@@ -77,6 +79,8 @@ enum domain_type {
struct iris_core {
struct device *dev;
+ struct device *dev_fw;
+ struct qcom_scm_pas_context *ctx_fw;
void __iomem *reg_base;
int irq;
struct v4l2_device v4l2_dev;
diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/media/platform/qcom/iris/iris_firmware.c
index 5f408024e967..93d77996c83f 100644
--- a/drivers/media/platform/qcom/iris/iris_firmware.c
+++ b/drivers/media/platform/qcom/iris/iris_firmware.c
@@ -5,6 +5,7 @@
#include <linux/firmware.h>
#include <linux/firmware/qcom/qcom_scm.h>
+#include <linux/iommu.h>
#include <linux/of_address.h>
#include <linux/of_reserved_mem.h>
#include <linux/soc/qcom/mdt_loader.h>
@@ -13,12 +14,15 @@
#include "iris_firmware.h"
#define MAX_FIRMWARE_NAME_SIZE 128
+#define IRIS_FW_START_ADDR 0
static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name)
{
+ struct device *dev = core->dev_fw ? core->dev_fw : core->dev;
u32 pas_id = core->iris_platform_data->pas_id;
const struct firmware *firmware = NULL;
- struct device *dev = core->dev;
+ struct qcom_scm_pas_context *ctx_fw;
+ struct iommu_domain *domain;
struct resource res;
phys_addr_t mem_phys;
size_t res_size;
@@ -29,13 +33,17 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name)
if (strlen(fw_name) >= MAX_FIRMWARE_NAME_SIZE - 4)
return -EINVAL;
- ret = of_reserved_mem_region_to_resource(dev->of_node, 0, &res);
+ ret = of_reserved_mem_region_to_resource(core->dev->of_node, 0, &res);
if (ret)
return ret;
mem_phys = res.start;
res_size = resource_size(&res);
+ ctx_fw = devm_qcom_scm_pas_context_alloc(dev, pas_id, mem_phys, res_size);
+ if (IS_ERR(ctx_fw))
+ return PTR_ERR(ctx_fw);
+
ret = request_firmware(&firmware, fw_name, dev);
if (ret)
return ret;
@@ -52,9 +60,27 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name)
goto err_release_fw;
}
- ret = qcom_mdt_load(dev, firmware, fw_name,
- pas_id, mem_virt, mem_phys, res_size, NULL);
+ ctx_fw->use_tzmem = !!core->dev_fw;
+ ret = qcom_mdt_pas_load(ctx_fw, firmware, fw_name, mem_virt, NULL);
+ if (ret)
+ goto err_mem_unmap;
+
+ if (ctx_fw->use_tzmem) {
+ domain = iommu_get_domain_for_dev(core->dev_fw);
+ if (!domain) {
+ ret = -ENODEV;
+ goto err_mem_unmap;
+ }
+
+ ret = iommu_map(domain, IRIS_FW_START_ADDR, mem_phys, res_size,
+ IOMMU_READ | IOMMU_WRITE | IOMMU_PRIV, GFP_KERNEL);
+ if (ret)
+ goto err_mem_unmap;
+ }
+ core->ctx_fw = ctx_fw;
+
+err_mem_unmap:
memunmap(mem_virt);
err_release_fw:
release_firmware(firmware);
@@ -62,6 +88,19 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name)
return ret;
}
+static void iris_fw_iommu_unmap(struct iris_core *core)
+{
+ bool use_tzmem = core->ctx_fw->use_tzmem;
+ struct iommu_domain *domain;
+
+ if (!use_tzmem)
+ return;
+
+ domain = iommu_get_domain_for_dev(core->dev_fw);
+ if (domain)
+ iommu_unmap(domain, IRIS_FW_START_ADDR, core->ctx_fw->mem_size);
+}
+
int iris_fw_load(struct iris_core *core)
{
const struct tz_cp_config *cp_config;
@@ -79,10 +118,10 @@ int iris_fw_load(struct iris_core *core)
return -ENOMEM;
}
- ret = qcom_scm_pas_auth_and_reset(core->iris_platform_data->pas_id);
+ ret = qcom_scm_pas_prepare_and_auth_reset(core->ctx_fw);
if (ret) {
dev_err(core->dev, "auth and reset failed: %d\n", ret);
- return ret;
+ goto err_unmap;
}
for (i = 0; i < core->iris_platform_data->tz_cp_config_data_size; i++) {
@@ -93,17 +132,31 @@ int iris_fw_load(struct iris_core *core)
cp_config->cp_nonpixel_size);
if (ret) {
dev_err(core->dev, "qcom_scm_mem_protect_video_var failed: %d\n", ret);
- qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
- return ret;
+ goto err_pas_shutdown;
}
}
+ return 0;
+
+err_pas_shutdown:
+ qcom_scm_pas_shutdown(core->ctx_fw->pas_id);
+err_unmap:
+ iris_fw_iommu_unmap(core);
+
return ret;
}
int iris_fw_unload(struct iris_core *core)
{
- return qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
+ int ret;
+
+ ret = qcom_scm_pas_shutdown(core->ctx_fw->pas_id);
+ if (ret)
+ return ret;
+
+ iris_fw_iommu_unmap(core);
+
+ return ret;
}
int iris_set_hw_state(struct iris_core *core, bool resume)
--
2.34.1
^ permalink raw reply related
* [PATCH 04/11] media: iris: Add helper to create a context bank device on iris vpu bus
From: Vishnu Reddy @ 2026-04-14 5:00 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joerg Roedel, Will Deacon,
Robin Murphy, Bjorn Andersson, Konrad Dybcio, Stefan Schmidt,
Hans Verkuil
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, iommu,
Vishnu Reddy
In-Reply-To: <20260414-glymur-v1-0-7d3d1cf57b16@oss.qualcomm.com>
From: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
Add a helper function to allocate and register context bank (CB) device
on the iris vpu bus. The function ID associated with the CB is specified
from the platform data, allowing the bus dma_configure callback to apply
correct stream ID mapping when device is registered.
Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_resources.c | 33 +++++++++++++++++++++++
drivers/media/platform/qcom/iris/iris_resources.h | 1 +
2 files changed, 34 insertions(+)
diff --git a/drivers/media/platform/qcom/iris/iris_resources.c b/drivers/media/platform/qcom/iris/iris_resources.c
index 773f6548370a..a25e0f2e9d26 100644
--- a/drivers/media/platform/qcom/iris/iris_resources.c
+++ b/drivers/media/platform/qcom/iris/iris_resources.c
@@ -6,6 +6,7 @@
#include <linux/clk.h>
#include <linux/devfreq.h>
#include <linux/interconnect.h>
+#include <linux/iris_vpu_bus.h>
#include <linux/pm_domain.h>
#include <linux/pm_opp.h>
#include <linux/pm_runtime.h>
@@ -141,3 +142,35 @@ int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk_type
return 0;
}
+
+static void iris_release_cb_dev(struct device *dev)
+{
+ kfree(dev);
+}
+
+struct device *iris_create_cb_dev(struct iris_core *core, const char *name, const u32 *f_id)
+{
+ struct device *dev;
+ int ret;
+
+ dev = kzalloc_obj(*dev);
+ if (!dev)
+ return ERR_PTR(-ENOMEM);
+
+ dev->release = iris_release_cb_dev;
+ dev->bus = &iris_vpu_bus_type;
+ dev->parent = core->dev;
+ dev->coherent_dma_mask = core->iris_platform_data->dma_mask;
+ dev->dma_mask = &dev->coherent_dma_mask;
+
+ dev_set_name(dev, "%s", name);
+ dev_set_drvdata(dev, (void *)f_id);
+
+ ret = device_register(dev);
+ if (ret) {
+ put_device(dev);
+ return ERR_PTR(ret);
+ }
+
+ return dev;
+}
diff --git a/drivers/media/platform/qcom/iris/iris_resources.h b/drivers/media/platform/qcom/iris/iris_resources.h
index 6bfbd2dc6db0..4a494627ff23 100644
--- a/drivers/media/platform/qcom/iris/iris_resources.h
+++ b/drivers/media/platform/qcom/iris/iris_resources.h
@@ -15,5 +15,6 @@ int iris_unset_icc_bw(struct iris_core *core);
int iris_set_icc_bw(struct iris_core *core, unsigned long icc_bw);
int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk_type clk_type);
int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_type clk_type);
+struct device *iris_create_cb_dev(struct iris_core *core, const char *name, const u32 *f_id);
#endif
--
2.34.1
^ permalink raw reply related
* [PATCH 03/11] media: iris: Add context bank hooks for platform specific initialization
From: Vishnu Reddy @ 2026-04-14 4:59 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joerg Roedel, Will Deacon,
Robin Murphy, Bjorn Andersson, Konrad Dybcio, Stefan Schmidt,
Hans Verkuil
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, iommu,
Vishnu Reddy
In-Reply-To: <20260414-glymur-v1-0-7d3d1cf57b16@oss.qualcomm.com>
Add init and deinit hooks in the platform data for context bank setup.
These hooks allow platform specific code to initialize and tear down
context banks.
The Glymur platform requires a dedicated firmware context bank device
which is mapped to the firmware stream ID to load the firmware.
Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
---
.../platform/qcom/iris/iris_platform_common.h | 2 ++
drivers/media/platform/qcom/iris/iris_probe.c | 23 +++++++++++++++++++++-
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index 5a489917580e..55ff6137d9a9 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -219,6 +219,8 @@ struct iris_platform_data {
u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type buffer_type);
const struct vpu_ops *vpu_ops;
void (*set_preset_registers)(struct iris_core *core);
+ int (*init_cb_devs)(struct iris_core *core);
+ void (*deinit_cb_devs)(struct iris_core *core);
const struct icc_info *icc_tbl;
unsigned int icc_tbl_size;
const struct bw_info *bw_tbl_dec;
diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c
index ddaacda523ec..34751912f871 100644
--- a/drivers/media/platform/qcom/iris/iris_probe.c
+++ b/drivers/media/platform/qcom/iris/iris_probe.c
@@ -142,6 +142,20 @@ static int iris_init_resources(struct iris_core *core)
return iris_init_resets(core);
}
+static int iris_init_cb_devs(struct iris_core *core)
+{
+ if (core->iris_platform_data->init_cb_devs)
+ return core->iris_platform_data->init_cb_devs(core);
+
+ return 0;
+}
+
+static void iris_deinit_cb_devs(struct iris_core *core)
+{
+ if (core->iris_platform_data->deinit_cb_devs)
+ core->iris_platform_data->deinit_cb_devs(core);
+}
+
static int iris_register_video_device(struct iris_core *core, enum domain_type type)
{
struct video_device *vdev;
@@ -193,6 +207,7 @@ static void iris_remove(struct platform_device *pdev)
return;
iris_core_deinit(core);
+ iris_deinit_cb_devs(core);
video_unregister_device(core->vdev_dec);
video_unregister_device(core->vdev_enc);
@@ -259,11 +274,15 @@ static int iris_probe(struct platform_device *pdev)
if (ret)
return ret;
+ ret = iris_init_cb_devs(core);
+ if (ret)
+ return ret;
+
iris_session_init_caps(core);
ret = v4l2_device_register(dev, &core->v4l2_dev);
if (ret)
- return ret;
+ goto err_deinit_cb;
ret = iris_register_video_device(core, DECODER);
if (ret)
@@ -298,6 +317,8 @@ static int iris_probe(struct platform_device *pdev)
video_unregister_device(core->vdev_dec);
err_v4l2_unreg:
v4l2_device_unregister(&core->v4l2_dev);
+err_deinit_cb:
+ iris_deinit_cb_devs(core);
return ret;
}
--
2.34.1
^ permalink raw reply related
* [PATCH 02/11] media: iris: Add iris vpu bus support and register it with iommu_buses
From: Vishnu Reddy @ 2026-04-14 4:59 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joerg Roedel, Will Deacon,
Robin Murphy, Bjorn Andersson, Konrad Dybcio, Stefan Schmidt,
Hans Verkuil
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, iommu,
Vishnu Reddy
In-Reply-To: <20260414-glymur-v1-0-7d3d1cf57b16@oss.qualcomm.com>
From: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
Add a dedicated iris VPU bus type and register it into the iommu_buses
list. Iris devices require their own bus so that each device can run its
own dma_configure() logic.
Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
---
drivers/iommu/iommu.c | 4 ++++
drivers/media/platform/qcom/iris/Makefile | 4 ++++
drivers/media/platform/qcom/iris/iris_vpu_bus.c | 32 +++++++++++++++++++++++++
include/linux/iris_vpu_bus.h | 13 ++++++++++
4 files changed, 53 insertions(+)
diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
index 61c12ba78206..d8ed6ef70ecd 100644
--- a/drivers/iommu/iommu.c
+++ b/drivers/iommu/iommu.c
@@ -13,6 +13,7 @@
#include <linux/bug.h>
#include <linux/types.h>
#include <linux/init.h>
+#include <linux/iris_vpu_bus.h>
#include <linux/export.h>
#include <linux/slab.h>
#include <linux/errno.h>
@@ -179,6 +180,9 @@ static const struct bus_type * const iommu_buses[] = {
#ifdef CONFIG_CDX_BUS
&cdx_bus_type,
#endif
+#if IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS)
+ &iris_vpu_bus_type,
+#endif
};
/*
diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile
index 2abbd3aeb4af..6f4052b98491 100644
--- a/drivers/media/platform/qcom/iris/Makefile
+++ b/drivers/media/platform/qcom/iris/Makefile
@@ -31,3 +31,7 @@ qcom-iris-objs += iris_platform_gen1.o
endif
obj-$(CONFIG_VIDEO_QCOM_IRIS) += qcom-iris.o
+
+ifdef CONFIG_VIDEO_QCOM_IRIS
+obj-y += iris_vpu_bus.o
+endif
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_bus.c b/drivers/media/platform/qcom/iris/iris_vpu_bus.c
new file mode 100644
index 000000000000..b51bb4b82b0e
--- /dev/null
+++ b/drivers/media/platform/qcom/iris/iris_vpu_bus.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/device.h>
+#include <linux/of_device.h>
+
+#include "iris_platform_common.h"
+
+static int iris_vpu_bus_dma_configure(struct device *dev)
+{
+ const u32 *f_id = dev_get_drvdata(dev);
+
+ if (!f_id)
+ return -ENODEV;
+
+ return of_dma_configure_id(dev, dev->parent->of_node, true, f_id);
+}
+
+const struct bus_type iris_vpu_bus_type = {
+ .name = "iris-vpu-bus",
+ .dma_configure = iris_vpu_bus_dma_configure,
+};
+EXPORT_SYMBOL_GPL(iris_vpu_bus_type);
+
+static int __init iris_vpu_bus_init(void)
+{
+ return bus_register(&iris_vpu_bus_type);
+}
+
+postcore_initcall(iris_vpu_bus_init);
diff --git a/include/linux/iris_vpu_bus.h b/include/linux/iris_vpu_bus.h
new file mode 100644
index 000000000000..5704b226f7d6
--- /dev/null
+++ b/include/linux/iris_vpu_bus.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef __IRIS_VPU_BUS_H__
+#define __IRIS_VPU_BUS_H__
+
+#if IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS)
+extern const struct bus_type iris_vpu_bus_type;
+#endif
+
+#endif /* __IRIS_VPU_BUS_H__ */
--
2.34.1
^ permalink raw reply related
* [PATCH 01/11] dt-bindings: media: qcom,glymur-iris: Add glymur video codec
From: Vishnu Reddy @ 2026-04-14 4:59 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joerg Roedel, Will Deacon,
Robin Murphy, Bjorn Andersson, Konrad Dybcio, Stefan Schmidt,
Hans Verkuil
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, iommu,
Vishnu Reddy
In-Reply-To: <20260414-glymur-v1-0-7d3d1cf57b16@oss.qualcomm.com>
Add device tree binding for the Qualcomm Glymur Iris video codec. Glymur
is a new generation of video IP that introduces a dual-core architecture.
The second core brings its own power domain, clocks, and reset lines,
requiring additional power domains and clocks in the power sequence.
Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
---
.../bindings/media/qcom,glymur-iris.yaml | 220 +++++++++++++++++++++
include/dt-bindings/media/qcom,glymur-iris.h | 11 ++
2 files changed, 231 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml b/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml
new file mode 100644
index 000000000000..10ee02cd1a7d
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml
@@ -0,0 +1,220 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,glymur-iris.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Glymur SoC Iris video encoder and decoder
+
+maintainers:
+ - Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
+
+description:
+ The Iris video processing unit on Qualcomm Glymur SoC is a video encode and
+ decode accelerator.
+
+properties:
+ compatible:
+ const: qcom,glymur-iris
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 9
+
+ clock-names:
+ items:
+ - const: iface
+ - const: core
+ - const: vcodec0_core
+ - const: iface_ctrl
+ - const: core_freerun
+ - const: vcodec0_core_freerun
+ - const: iface1
+ - const: vcodec1_core
+ - const: vcodec1_core_freerun
+
+ dma-coherent: true
+
+ firmware-name:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: cpu-cfg
+ - const: video-mem
+
+ interrupts:
+ maxItems: 1
+
+ iommus:
+ maxItems: 4
+
+ iommu-map:
+ maxItems: 1
+
+ memory-region:
+ maxItems: 1
+
+ operating-points-v2: true
+ opp-table:
+ type: object
+
+ power-domains:
+ maxItems: 5
+
+ power-domain-names:
+ items:
+ - const: venus
+ - const: vcodec0
+ - const: mxc
+ - const: mmcx
+ - const: vcodec1
+
+ resets:
+ maxItems: 6
+
+ reset-names:
+ items:
+ - const: bus0
+ - const: bus_ctrl
+ - const: core
+ - const: vcodec0_core
+ - const: bus1
+ - const: vcodec1_core
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - dma-coherent
+ - interconnects
+ - interconnect-names
+ - interrupts
+ - iommus
+ - memory-region
+ - power-domains
+ - power-domain-names
+ - resets
+ - reset-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/media/qcom,glymur-iris.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ video-codec@aa00000 {
+ compatible = "qcom,glymur-iris";
+ reg = <0x0aa00000 0xf0000>;
+
+ clocks = <&gcc_video_axi0_clk>,
+ <&videocc_mvs0c_clk>,
+ <&videocc_mvs0_clk>,
+ <&gcc_video_axi0c_clk>,
+ <&videocc_mvs0c_freerun_clk>,
+ <&videocc_mvs0_freerun_clk>,
+ <&gcc_video_axi1_clk>,
+ <&videocc_mvs1_clk>,
+ <&videocc_mvs1_freerun_clk>;
+ clock-names = "iface",
+ "core",
+ "vcodec0_core",
+ "iface_ctrl",
+ "core_freerun",
+ "vcodec0_core_freerun",
+ "iface1",
+ "vcodec1_core",
+ "vcodec1_core_freerun";
+
+ dma-coherent;
+
+ interconnects = <&hsc_noc_master_appss_proc &config_noc_slave_venus_cfg>,
+ <&mmss_noc_master_video &mc_virt_slave_ebi1>;
+ interconnect-names = "cpu-cfg",
+ "video-mem";
+
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&apps_smmu 0x1940 0x0>,
+ <&apps_smmu 0x1943 0x0>,
+ <&apps_smmu 0x1944 0x0>,
+ <&apps_smmu 0x19e0 0x0>;
+
+ iommu-map = <IRIS_FIRMWARE &apps_smmu 0x19e2 0x1>;
+
+ memory-region = <&video_mem>;
+
+ operating-points-v2 = <&iris_opp_table>;
+
+ power-domains = <&videocc_mvs0c_gdsc>,
+ <&videocc_mvs0_gdsc>,
+ <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&videocc_mvs1_gdsc>;
+ power-domain-names = "venus",
+ "vcodec0",
+ "mxc",
+ "mmcx",
+ "vcodec1";
+
+ resets = <&gcc_video_axi0_clk_ares>,
+ <&gcc_video_axi0c_clk_ares>,
+ <&videocc_mvs0c_freerun_clk_ares>,
+ <&videocc_mvs0_freerun_clk_ares>,
+ <&gcc_video_axi1_clk_ares>,
+ <&videocc_mvs1_freerun_clk_ares>;
+ reset-names = "bus0",
+ "bus_ctrl",
+ "core",
+ "vcodec0_core",
+ "bus1",
+ "vcodec1_core";
+
+ iris_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-240000000 {
+ opp-hz = /bits/ 64 <240000000 240000000 360000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-338000000 {
+ opp-hz = /bits/ 64 <338000000 338000000 507000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs>;
+ };
+
+ opp-366000000 {
+ opp-hz = /bits/ 64 <366000000 366000000 549000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-444000000 {
+ opp-hz = /bits/ 64 <444000000 444000000 666000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_nom>;
+ };
+
+ opp-533333334 {
+ opp-hz = /bits/ 64 <533333334 533333334 800000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_turbo>;
+ };
+
+ opp-655000000 {
+ opp-hz = /bits/ 64 <655000000 655000000 982000000>;
+ required-opps = <&rpmhpd_opp_nom>,
+ <&rpmhpd_opp_turbo_l1>;
+ };
+ };
+ };
diff --git a/include/dt-bindings/media/qcom,glymur-iris.h b/include/dt-bindings/media/qcom,glymur-iris.h
new file mode 100644
index 000000000000..5766db0b9247
--- /dev/null
+++ b/include/dt-bindings/media/qcom,glymur-iris.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_MEDIA_QCOM_GLYMUR_IRIS_H_
+#define _DT_BINDINGS_MEDIA_QCOM_GLYMUR_IRIS_H_
+
+#define IRIS_FIRMWARE 0
+
+#endif
--
2.34.1
^ permalink raw reply related
* [PATCH 00/11] media: iris: Add support for glymur platform
From: Vishnu Reddy @ 2026-04-14 4:59 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joerg Roedel, Will Deacon,
Robin Murphy, Bjorn Andersson, Konrad Dybcio, Stefan Schmidt,
Hans Verkuil
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, iommu,
Vishnu Reddy, Mukesh Ojha, stable
Glymur is a new generation video codec that supports dual hardware cores
along with additional power domains and clocks.
This series adds platform specific support in the iris driver to handle
the extra cores, power domains, and clock requirements introduced by
glymur. add support for firmware loading through context bank firmware
device.
Patch[11] is dependent on the below patch.
https://lore.kernel.org/all/20260410-glymur_mmcc_dt_config_v2-v3-1-acce9d106e72@oss.qualcomm.com/
v4l2-compliance report for decoder including streaming tests:
v4l2-compliance 1.33.0-5441, 64 bits, 64-bit time_t
v4l2-compliance SHA: 4310f15610f4 2026-01-18 22:09:17
Compliance test for iris_driver device /dev/video0:
Driver Info:
Driver name : iris_driver
Card type : Iris Decoder
Bus info : platform:aa00000.video-codec
Driver version : 7.0.0
Capabilities : 0x84204000
Video Memory-to-Memory Multiplanar
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04204000
Video Memory-to-Memory Multiplanar
Streaming
Extended Pix Format
Detected Stateful Decoder
Required ioctls:
test VIDIOC_QUERYCAP: OK
test invalid ioctls: OK
Allow for multiple opens:
test second /dev/video0 open: OK
test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
test for unlimited opens: OK
Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
test VIDIOC_QUERYCTRL: OK
test VIDIOC_G/S_CTRL: OK
test VIDIOC_G/S/TRY_EXT_CTRLS: OK
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 12 Private Controls: 0
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
test VIDIOC_G/S_PARM: OK (Not Supported)
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK
test VIDIOC_TRY_FMT: OK
test VIDIOC_S_FMT: OK
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK
test Composing: OK
test Scaling: OK (Not Supported)
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
test CREATE_BUFS maximum buffers: OK
test VIDIOC_REMOVE_BUFS: OK
test VIDIOC_EXPBUF: OK
test Requests: OK (Not Supported)
test blocking wait: OK
Test input 0:
Streaming ioctls:
test read/write: OK (Not Supported)
the input file is smaller than 7077888 bytes
Video Capture Multiplanar: Captured 465 buffers
test MMAP (select, REQBUFS): OK
the input file is smaller than 7077888 bytes
Video Capture Multiplanar: Captured 465 buffers
test MMAP (epoll, REQBUFS): OK
the input file is smaller than 7077888 bytes
Video Capture Multiplanar: Captured 465 buffers
test MMAP (select, CREATE_BUFS): OK
the input file is smaller than 7077888 bytes
Video Capture Multiplanar: Captured 465 buffers
test MMAP (epoll, CREATE_BUFS): OK
test USERPTR (select): OK (Not Supported)
test DMABUF: Cannot test, specify --expbuf-device
Total for iris_driver device /dev/video0: 54, Succeeded: 54, Failed: 0, Warnings: 0
v4l2-compliance report for encoder including streaming tests:
v4l2-compliance 1.33.0-5441, 64 bits, 64-bit time_t
v4l2-compliance SHA: 4310f15610f4 2026-01-18 22:09:17
Compliance test for iris_driver device /dev/video1:
Driver Info:
Driver name : iris_driver
Card type : Iris Encoder
Bus info : platform:aa00000.video-codec
Driver version : 7.0.0
Capabilities : 0x84204000
Video Memory-to-Memory Multiplanar
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04204000
Video Memory-to-Memory Multiplanar
Streaming
Extended Pix Format
Detected Stateful Encoder
Required ioctls:
test VIDIOC_QUERYCAP: OK
test invalid ioctls: OK
Allow for multiple opens:
test second /dev/video1 open: OK
test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
test for unlimited opens: OK
Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
test VIDIOC_QUERYCTRL: OK
test VIDIOC_G/S_CTRL: OK
test VIDIOC_G/S/TRY_EXT_CTRLS: OK
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 43 Private Controls: 0
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
test VIDIOC_G/S_PARM: OK
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK
test VIDIOC_TRY_FMT: OK
test VIDIOC_S_FMT: OK
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK
test Composing: OK (Not Supported)
test Scaling: OK (Not Supported)
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
test CREATE_BUFS maximum buffers: OK
test VIDIOC_REMOVE_BUFS: OK
test VIDIOC_EXPBUF: OK
test Requests: OK (Not Supported)
test blocking wait: OK
Test input 0:
Streaming ioctls:
test read/write: OK (Not Supported)
Video Capture Multiplanar: Captured 61 buffers
test MMAP (select, REQBUFS): OK
Video Capture Multiplanar: Captured 61 buffers
test MMAP (epoll, REQBUFS): OK
Video Capture Multiplanar: Captured 61 buffers
test MMAP (select, CREATE_BUFS): OK
Video Capture Multiplanar: Captured 61 buffers
test MMAP (epoll, CREATE_BUFS): OK
test USERPTR (select): OK (Not Supported)
test DMABUF: Cannot test, specify --expbuf-device
Total for iris_driver device /dev/video1: 54, Succeeded: 54, Failed: 0, Warnings: 0
Fluster test report:
77/135 while testing JVT-AVC_V1 with
GStreamer-H.264-V4L2-Gst1.0.JVT-AVC_V1
The failing tests are:
- 52 test vectors failed due to interlaced clips: Interlaced decoding
is not supported.
- cabac_mot_fld0_full
- cabac_mot_mbaff0_full
- cabac_mot_picaff0_full
- CABREF3_Sand_D
- CAFI1_SVA_C
- CAMA1_Sony_C
- CAMA1_TOSHIBA_B
- cama1_vtc_c
- cama2_vtc_b
- CAMA3_Sand_E
- cama3_vtc_b
- CAMACI3_Sony_C
- CAMANL1_TOSHIBA_B
- CAMANL2_TOSHIBA_B
- CAMANL3_Sand_E
- CAMASL3_Sony_B
- CAMP_MOT_MBAFF_L30
- CAMP_MOT_MBAFF_L31
- CANLMA2_Sony_C
- CANLMA3_Sony_C
- CAPA1_TOSHIBA_B
- CAPAMA3_Sand_F
- cavlc_mot_fld0_full_B
- cavlc_mot_mbaff0_full_B
- cavlc_mot_picaff0_full_B
- CVCANLMA2_Sony_C
- CVFI1_Sony_D
- CVFI1_SVA_C
- CVFI2_Sony_H
- CVFI2_SVA_C
- CVMA1_Sony_D
- CVMA1_TOSHIBA_B
- CVMANL1_TOSHIBA_B
- CVMANL2_TOSHIBA_B
- CVMAPAQP3_Sony_E
- CVMAQP2_Sony_G
- CVMAQP3_Sony_D
- CVMP_MOT_FLD_L30_B
- CVNLFI1_Sony_C
- CVNLFI2_Sony_H
- CVPA1_TOSHIBA_B
- FI1_Sony_E
- MR6_BT_B
- MR7_BT_B
- MR8_BT_B
- MR9_BT_B
- Sharp_MP_Field_1_B
- Sharp_MP_Field_2_B
- Sharp_MP_Field_3_B
- Sharp_MP_PAFF_1r2
- Sharp_MP_PAFF_2r
- CVMP_MOT_FRM_L31_B
3 test case failed due to unsupported bitstream.
num_slice_groups_minus1 greater than zero is not supported.
- FM1_BT_B
- FM1_FT_E
- FM2_SVA_C
2 test case failed because SP_SLICE type is not supported.
- SP1_BT_A
- sp2_bt_b
1 test case failed due to unsupported profile.
- BA3_SVA_C
131/147 testcases passed while testing JCT-VC-HEVC_V1 with
GStreamer-H.265-V4L2-Gst1.0
10 testcases failed due to unsupported 10 bit format.
- DBLK_A_MAIN10_VIXS_4
- INITQP_B_Main10_Sony_1
- TSUNEQBD_A_MAIN10_Technicolor_2
- WP_A_MAIN10_Toshiba_3
- WP_MAIN10_B_Toshiba_3
- WPP_A_ericsson_MAIN10_2
- WPP_B_ericsson_MAIN10_2
- WPP_C_ericsson_MAIN10_2
- WPP_E_ericsson_MAIN10_2
- WPP_F_ericsson_MAIN10_2
4 testcase failed due to unsupported resolution.
- PICSIZE_A_Bossen_1
- PICSIZE_B_Bossen_1
- WPP_D_ericsson_MAIN10_2
- WPP_D_ericsson_MAIN_2
2 testcase failed due to CRC mismatch.
- VPSSPSPPS_A_MainConcept_1
This fails with software decoder as well. Refer the below link for the
discussion happened for earlier platform.
https://lore.kernel.org/all/63ca375440c4ff2f55ea0aa4e19458f775552d88.camel@ndufresne.ca/
- RAP_A_docomo_6
This was discussed on bug report
https://gitlab.freedesktop.org/gstreamer/gstreamer/-/issues/4392
Based on above discussion, the initial error frames need to be dropped in
the firmware or driver. Discussion ongoing with video firmware team on a
way to handle such case. This issue is not specific to this platform, and
its there on other platforms also.
235/305 testcases passed while testing VP9-TEST-VECTORS with GStreamer-VP9-V4L2-Gst1.0
64 testcases failed due to unsupported resolution
- vp90-2-02-size-08x08.webm
- vp90-2-02-size-08x10.webm
- vp90-2-02-size-08x16.webm
- vp90-2-02-size-08x18.webm
- vp90-2-02-size-08x32.webm
- vp90-2-02-size-08x34.webm
- vp90-2-02-size-08x64.webm
- vp90-2-02-size-08x66.webm
- vp90-2-02-size-10x08.webm
- vp90-2-02-size-10x10.webm
- vp90-2-02-size-10x16.webm
- vp90-2-02-size-10x18.webm
- vp90-2-02-size-10x32.webm
- vp90-2-02-size-10x34.webm
- vp90-2-02-size-10x64.webm
- vp90-2-02-size-10x66.webm
- vp90-2-02-size-16x08.webm
- vp90-2-02-size-16x10.webm
- vp90-2-02-size-16x16.webm
- vp90-2-02-size-16x18.webm
- vp90-2-02-size-16x32.webm
- vp90-2-02-size-16x34.webm
- vp90-2-02-size-16x64.webm
- vp90-2-02-size-16x66.webm
- vp90-2-02-size-18x08.webm
- vp90-2-02-size-18x10.webm
- vp90-2-02-size-18x16.webm
- vp90-2-02-size-18x18.webm
- vp90-2-02-size-18x32.webm
- vp90-2-02-size-18x34.webm
- vp90-2-02-size-18x64.webm
- vp90-2-02-size-18x66.webm
- vp90-2-02-size-32x08.webm
- vp90-2-02-size-32x10.webm
- vp90-2-02-size-32x16.webm
- vp90-2-02-size-32x18.webm
- vp90-2-02-size-32x32.webm
- vp90-2-02-size-32x34.webm
- vp90-2-02-size-32x64.webm
- vp90-2-02-size-32x66.webm
- vp90-2-02-size-34x08.webm
- vp90-2-02-size-34x10.webm
- vp90-2-02-size-34x16.webm
- vp90-2-02-size-34x18.webm
- vp90-2-02-size-34x32.webm
- vp90-2-02-size-34x34.webm
- vp90-2-02-size-34x64.webm
- vp90-2-02-size-34x66.webm
- vp90-2-02-size-64x08.webm
- vp90-2-02-size-64x10.webm
- vp90-2-02-size-64x16.webm
- vp90-2-02-size-64x18.webm
- vp90-2-02-size-64x32.webm
- vp90-2-02-size-64x34.webm
- vp90-2-02-size-64x64.webm
- vp90-2-02-size-64x66.webm
- vp90-2-02-size-66x08.webm
- vp90-2-02-size-66x10.webm
- vp90-2-02-size-66x16.webm
- vp90-2-02-size-66x18.webm
- vp90-2-02-size-66x32.webm
- vp90-2-02-size-66x34.webm
- vp90-2-02-size-66x64.webm
- vp90-2-02-size-66x66.webm
2 testcases failed due to unsupported format.
- vp91-2-04-yuv422.webm
- vp91-2-04-yuv444.webm
2 testcase failed due to unsupported resolution after DRC.
- vp90-2-21-resize_inter_320x180_5_1-2.webm
- vp90-2-21-resize_inter_320x180_7_1-2.webm
1 testcase failed with CRC mismatch.
- vp90-2-22-svc_1280x720_3.ivf
This VP9 bitstream contains 20 superframes, and each superframe consists
of three subframes in the following order:
• 180p subframe
• 360p subframe
• 720p subframe
Each superframe is submitted to the driver and firmware as a single input
buffer, with one common timestamp attached to it. For every such input
buffer, the hardware decoder produces three corresponding output buffers,
one for each resolution (180p, 360p, and 720p), and all three output
buffers carry the same timestamp. When these output buffers are returned
to the client (GStreamer, in this case), the first buffer returned is
displayed, while the remaining two buffers are dropped due to having
identical timestamps. As a result, only one frame per superframe is
rendered. Here the expectation of the test result is with 720p, last
decoded frame in each super frame.
Discussion ongoing with firmware team and gst maintainer on how to handle
this case. This is not specific to glymur, and its there for the other
platforms also.
1 testcase failed due to unsupported stream.
- vp90-2-16-intra-only.webm
Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
---
Mukesh Ojha (1):
media: iris: Enable Secure PAS support with IOMMU managed by Linux
Vikash Garodia (2):
media: iris: Add iris vpu bus support and register it with iommu_buses
media: iris: Add helper to create a context bank device on iris vpu bus
Vishnu Reddy (8):
dt-bindings: media: qcom,glymur-iris: Add glymur video codec
media: iris: Add context bank hooks for platform specific initialization
media: iris: Fix VM count passed to firmware
media: iris: Rename clock and power domain macros to use vcodec prefix
media: iris: Add power sequence for Glymur
media: iris: Add support to select core for dual core platforms
media: iris: Add platform data for glymur
arm64: dts: qcom: glymur: Add iris video node
.../bindings/media/qcom,glymur-iris.yaml | 220 +++++++++++++++++++++
arch/arm64/boot/dts/qcom/glymur-crd.dts | 4 +
arch/arm64/boot/dts/qcom/glymur.dtsi | 118 +++++++++++
drivers/iommu/iommu.c | 4 +
drivers/media/platform/qcom/iris/Makefile | 5 +
drivers/media/platform/qcom/iris/iris_common.c | 7 +
drivers/media/platform/qcom/iris/iris_core.h | 4 +
drivers/media/platform/qcom/iris/iris_firmware.c | 71 ++++++-
drivers/media/platform/qcom/iris/iris_hfi_common.h | 1 +
.../platform/qcom/iris/iris_hfi_gen2_command.c | 19 ++
.../platform/qcom/iris/iris_hfi_gen2_defines.h | 1 +
drivers/media/platform/qcom/iris/iris_instance.h | 2 +
.../platform/qcom/iris/iris_platform_common.h | 25 ++-
.../media/platform/qcom/iris/iris_platform_gen1.c | 6 +-
.../media/platform/qcom/iris/iris_platform_gen2.c | 106 +++++++++-
.../platform/qcom/iris/iris_platform_glymur.c | 93 +++++++++
.../platform/qcom/iris/iris_platform_glymur.h | 17 ++
.../platform/qcom/iris/iris_platform_sc7280.h | 10 +-
.../platform/qcom/iris/iris_platform_sm8750.h | 12 +-
drivers/media/platform/qcom/iris/iris_probe.c | 27 ++-
drivers/media/platform/qcom/iris/iris_resources.c | 33 ++++
drivers/media/platform/qcom/iris/iris_resources.h | 1 +
drivers/media/platform/qcom/iris/iris_utils.c | 68 +++++--
drivers/media/platform/qcom/iris/iris_vpu3x.c | 148 ++++++++++++--
drivers/media/platform/qcom/iris/iris_vpu4x.c | 30 +--
drivers/media/platform/qcom/iris/iris_vpu_bus.c | 32 +++
drivers/media/platform/qcom/iris/iris_vpu_common.c | 36 ++--
drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 +
.../platform/qcom/iris/iris_vpu_register_defines.h | 7 +
include/dt-bindings/media/qcom,glymur-iris.h | 11 ++
include/linux/iris_vpu_bus.h | 13 ++
31 files changed, 1039 insertions(+), 93 deletions(-)
---
base-commit: 1c7cc4904160c6fc6377564140062d68a3dc93a0
change-id: 20260409-glymur-140ab7ca0910
Best regards,
--
Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH v5 4/5] remoteproc: qcom: pas: Add late attach support for subsystems
From: Jingyi Wang @ 2026-04-14 4:56 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Mathieu Poirier, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Manivannan Sadhasivam, Luca Weiss, Bartosz Golaszewski,
Konrad Dybcio, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
Gokul Krishna Krishnakumar
In-Reply-To: <adm37MruBfXAjLpZ@baldur>
On 4/11/2026 10:59 AM, Bjorn Andersson wrote:
> On Thu, Apr 09, 2026 at 01:52:27AM -0700, Jingyi Wang wrote:
>> Subsystems can be brought out of reset by entities such as bootloaders.
>> As the irq enablement could be later than subsystem bring up, the state
>> of subsystem should be checked by reading SMP2P bits and performing ping
>> test.
>>
Hi Bjorn,
>
> I still don't understand.
>
> Are you saying that devm_request_threaded_irq() will succeed and then
> calling irq_get_irqchip_state() will not work? Or are you saying that
> SMP2P driver isn't reliable and we're loosing the ready or fatal bits?
>
This says the ready state is getting from irq_get_irqchip_state()
instead of q6v5_ready_interrupt(like what rproc start do)
>
> In the reply to v4 you replied to me with "it's a downstream feature".
> That isn't a reason for performing this extra dance, either downstream
> or upstream.
>
I think the "downtream feature" in v4 means, if getting ready state
from SMP2P bits fail, no more waiting. And this has been removed in
this version.
>> A new qcom_pas_attach() function is introduced. if a crash state is
>> detected for the subsystem, rproc_report_crash() is called. If the
>> subsystem is ready and the ping is successful, it will be marked as
>> "attached". If ready irq is not received, it could be the early boot
>> feature is not supported by other entities. In this case, the state will
>> be marked as RPROC_OFFLINE so that the PAS driver can load the firmware
>> and start the remoteproc.
>>
>> Co-developed-by: Gokul Krishna Krishnakumar <gokul.krishnakumar@oss.qualcomm.com>
>> Signed-off-by: Gokul Krishna Krishnakumar <gokul.krishnakumar@oss.qualcomm.com>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>> drivers/remoteproc/qcom_q6v5.c | 69 ++++++++++++++++++++++++++++++++
>> drivers/remoteproc/qcom_q6v5.h | 6 +++
>> drivers/remoteproc/qcom_q6v5_pas.c | 80 ++++++++++++++++++++++++++++++++++++--
>> 3 files changed, 152 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/remoteproc/qcom_q6v5.c b/drivers/remoteproc/qcom_q6v5.c
>> index 58d5b85e58cd..52247c17c38a 100644
>> --- a/drivers/remoteproc/qcom_q6v5.c
>> +++ b/drivers/remoteproc/qcom_q6v5.c
>> @@ -20,6 +20,7 @@
>>
>> #define Q6V5_LOAD_STATE_MSG_LEN 64
>> #define Q6V5_PANIC_DELAY_MS 200
>> +#define Q6V5_PING_TIMEOUT_MS 500
>
> Changelog says you removed 5 second timeout, but you only removed 4.5
> seconds.
>
EARLY_ATTACH_TIMEOUT_MS has been removed and Q6V5_PING_TIMEOUT_MS is used for
soccp ping-pong.
Thanks,
Jingyi
> Regards,
> Bjorn
>
>>
>> static int q6v5_load_state_toggle(struct qcom_q6v5 *q6v5, bool enable)
>> {
>> @@ -234,6 +235,74 @@ unsigned long qcom_q6v5_panic(struct qcom_q6v5 *q6v5)
>> }
>> EXPORT_SYMBOL_GPL(qcom_q6v5_panic);
>>
>> +static irqreturn_t q6v5_pong_interrupt(int irq, void *data)
>> +{
>> + struct qcom_q6v5 *q6v5 = data;
>> +
>> + complete(&q6v5->ping_done);
>> +
>> + return IRQ_HANDLED;
>> +}
>> +
>> +int qcom_q6v5_ping_subsystem(struct qcom_q6v5 *q6v5)
>> +{
>> + int ret;
>> + int ping_failed = 0;
>> +
>> + reinit_completion(&q6v5->ping_done);
>> +
>> + /* Set master kernel Ping bit */
>> + ret = qcom_smem_state_update_bits(q6v5->ping_state,
>> + BIT(q6v5->ping_bit), BIT(q6v5->ping_bit));
>> + if (ret) {
>> + dev_err(q6v5->dev, "Failed to update ping bits\n");
>> + return ret;
>> + }
>> +
>> + ret = wait_for_completion_timeout(&q6v5->ping_done, msecs_to_jiffies(Q6V5_PING_TIMEOUT_MS));
>> + if (!ret) {
>> + ping_failed = -ETIMEDOUT;
>> + dev_err(q6v5->dev, "Failed to get back pong\n");
>> + }
>> +
>> + /* Clear ping bit master kernel */
>> + ret = qcom_smem_state_update_bits(q6v5->ping_state, BIT(q6v5->ping_bit), 0);
>> + if (ret) {
>> + dev_err(q6v5->dev, "Failed to clear master kernel bits\n");
>> + return ret;
>> + }
>> +
>> + return ping_failed;
>> +}
>> +EXPORT_SYMBOL_GPL(qcom_q6v5_ping_subsystem);
>> +
>> +int qcom_q6v5_ping_subsystem_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev)
>> +{
>> + int ret = -ENODEV;
>> +
>> + q6v5->ping_state = devm_qcom_smem_state_get(&pdev->dev, "ping", &q6v5->ping_bit);
>> + if (IS_ERR(q6v5->ping_state)) {
>> + dev_err(&pdev->dev, "Failed to acquire smem state %ld\n",
>> + PTR_ERR(q6v5->ping_state));
>> + return PTR_ERR(q6v5->ping_state);
>> + }
>> +
>> + init_completion(&q6v5->ping_done);
>> +
>> + q6v5->pong_irq = platform_get_irq_byname(pdev, "pong");
>> + if (q6v5->pong_irq < 0)
>> + return q6v5->pong_irq;
>> +
>> + ret = devm_request_threaded_irq(&pdev->dev, q6v5->pong_irq, NULL,
>> + q6v5_pong_interrupt, IRQF_TRIGGER_RISING | IRQF_ONESHOT,
>> + "q6v5 pong", q6v5);
>> + if (ret)
>> + dev_err(&pdev->dev, "Failed to acquire pong IRQ\n");
>> +
>> + return ret;
>> +}
>> +EXPORT_SYMBOL_GPL(qcom_q6v5_ping_subsystem_init);
>> +
>> /**
>> * qcom_q6v5_init() - initializer of the q6v5 common struct
>> * @q6v5: handle to be initialized
>> diff --git a/drivers/remoteproc/qcom_q6v5.h b/drivers/remoteproc/qcom_q6v5.h
>> index 5a859c41896e..5025ffc4dbe8 100644
>> --- a/drivers/remoteproc/qcom_q6v5.h
>> +++ b/drivers/remoteproc/qcom_q6v5.h
>> @@ -17,22 +17,26 @@ struct qcom_q6v5 {
>> struct rproc *rproc;
>>
>> struct qcom_smem_state *state;
>> + struct qcom_smem_state *ping_state;
>> struct qmp *qmp;
>>
>> struct icc_path *path;
>>
>> unsigned stop_bit;
>> + unsigned int ping_bit;
>>
>> int wdog_irq;
>> int fatal_irq;
>> int ready_irq;
>> int handover_irq;
>> int stop_irq;
>> + int pong_irq;
>>
>> bool handover_issued;
>>
>> struct completion start_done;
>> struct completion stop_done;
>> + struct completion ping_done;
>>
>> int crash_reason;
>>
>> @@ -52,5 +56,7 @@ int qcom_q6v5_unprepare(struct qcom_q6v5 *q6v5);
>> int qcom_q6v5_request_stop(struct qcom_q6v5 *q6v5, struct qcom_sysmon *sysmon);
>> int qcom_q6v5_wait_for_start(struct qcom_q6v5 *q6v5, int timeout);
>> unsigned long qcom_q6v5_panic(struct qcom_q6v5 *q6v5);
>> +int qcom_q6v5_ping_subsystem(struct qcom_q6v5 *q6v5);
>> +int qcom_q6v5_ping_subsystem_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev);
>>
>> #endif
>> diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c
>> index da27d1d3c9da..34b54cf832d0 100644
>> --- a/drivers/remoteproc/qcom_q6v5_pas.c
>> +++ b/drivers/remoteproc/qcom_q6v5_pas.c
>> @@ -60,6 +60,7 @@ struct qcom_pas_data {
>> int region_assign_count;
>> bool region_assign_shared;
>> int region_assign_vmid;
>> + bool early_boot;
>> };
>>
>> struct qcom_pas {
>> @@ -423,9 +424,15 @@ static int qcom_pas_stop(struct rproc *rproc)
>>
>> qcom_pas_unmap_carveout(rproc, pas->mem_phys, pas->mem_size);
>>
>> - handover = qcom_q6v5_unprepare(&pas->q6v5);
>> - if (handover)
>> - qcom_pas_handover(&pas->q6v5);
>> + /*
>> + * qcom_q6v5_prepare is not called in qcom_pas_attach, skip unprepare to
>> + * avoid mismatch.
>> + */
>> + if (pas->rproc->state != RPROC_ATTACHED) {
>> + handover = qcom_q6v5_unprepare(&pas->q6v5);
>> + if (handover)
>> + qcom_pas_handover(&pas->q6v5);
>> + }
>>
>> if (pas->smem_host_id)
>> ret = qcom_smem_bust_hwspin_lock_by_host(pas->smem_host_id);
>> @@ -510,6 +517,63 @@ static unsigned long qcom_pas_panic(struct rproc *rproc)
>> return qcom_q6v5_panic(&pas->q6v5);
>> }
>>
>> +static int qcom_pas_attach(struct rproc *rproc)
>> +{
>> + int ret;
>> + struct qcom_pas *pas = rproc->priv;
>> + bool ready_state;
>> + bool crash_state;
>> +
>> + pas->q6v5.running = true;
>> + ret = irq_get_irqchip_state(pas->q6v5.fatal_irq,
>> + IRQCHIP_STATE_LINE_LEVEL, &crash_state);
>> +
>> + if (ret)
>> + goto disable_running;
>> +
>> + if (crash_state) {
>> + dev_err(pas->dev, "Subsystem has crashed before driver probe\n");
>> + rproc_report_crash(rproc, RPROC_FATAL_ERROR);
>> + ret = -EINVAL;
>> + goto disable_running;
>> + }
>> +
>> + ret = irq_get_irqchip_state(pas->q6v5.ready_irq,
>> + IRQCHIP_STATE_LINE_LEVEL, &ready_state);
>> +
>> + if (ret)
>> + goto disable_running;
>> +
>> + if (unlikely(!ready_state)) {
>> + /*
>> + * The bootloader may not support early boot, mark the state as
>> + * RPROC_OFFLINE so that the PAS driver can load the firmware and
>> + * start the remoteproc.
>> + */
>> + dev_err(pas->dev, "Failed to get subsystem ready interrupt\n");
>> + pas->rproc->state = RPROC_OFFLINE;
>> + ret = -EINVAL;
>> + goto disable_running;
>> + }
>> +
>> + ret = qcom_q6v5_ping_subsystem(&pas->q6v5);
>> +
>> + if (ret) {
>> + dev_err(pas->dev, "Failed to ping subsystem, assuming device crashed\n");
>> + rproc_report_crash(rproc, RPROC_FATAL_ERROR);
>> + goto disable_running;
>> + }
>> +
>> + pas->q6v5.handover_issued = true;
>> +
>> + return 0;
>> +
>> +disable_running:
>> + pas->q6v5.running = false;
>> +
>> + return ret;
>> +}
>> +
>> static const struct rproc_ops qcom_pas_ops = {
>> .unprepare = qcom_pas_unprepare,
>> .start = qcom_pas_start,
>> @@ -518,6 +582,7 @@ static const struct rproc_ops qcom_pas_ops = {
>> .parse_fw = qcom_pas_parse_firmware,
>> .load = qcom_pas_load,
>> .panic = qcom_pas_panic,
>> + .attach = qcom_pas_attach,
>> };
>>
>> static const struct rproc_ops qcom_pas_minidump_ops = {
>> @@ -855,6 +920,15 @@ static int qcom_pas_probe(struct platform_device *pdev)
>>
>> pas->pas_ctx->use_tzmem = rproc->has_iommu;
>> pas->dtb_pas_ctx->use_tzmem = rproc->has_iommu;
>> +
>> + if (desc->early_boot) {
>> + ret = qcom_q6v5_ping_subsystem_init(&pas->q6v5, pdev);
>> + if (ret)
>> + dev_warn(&pdev->dev, "Falling back to firmware load\n");
>> + else
>> + pas->rproc->state = RPROC_DETACHED;
>> + }
>> +
>> ret = rproc_add(rproc);
>> if (ret)
>> goto remove_ssr_sysmon;
>>
>> --
>> 2.34.1
>>
^ permalink raw reply
* [PATCH 1/2] dt-bindings: hwmon: pmbus: add max20830
From: Alexis Czezar Torreno @ 2026-04-14 4:28 UTC (permalink / raw)
To: Guenter Roeck, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jonathan Corbet, Shuah Khan
Cc: linux-hwmon, devicetree, linux-kernel, linux-doc,
Alexis Czezar Torreno
In-Reply-To: <20260414-dev_max20830-v1-0-210d3f82c571@analog.com>
Add device tree documentation for MAX20830 step-down DC-DC switching
regulator with PMBus interface.
Signed-off-by: Alexis Czezar Torreno <alexisczezar.torreno@analog.com>
---
.../bindings/hwmon/pmbus/adi,max20830.yaml | 58 ++++++++++++++++++++++
MAINTAINERS | 7 +++
2 files changed, 65 insertions(+)
diff --git a/Documentation/devicetree/bindings/hwmon/pmbus/adi,max20830.yaml b/Documentation/devicetree/bindings/hwmon/pmbus/adi,max20830.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..b20f3be176615895e70e74bfb2a534d82d124a15
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/pmbus/adi,max20830.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/pmbus/adi,max20830.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices MAX20830 Step-Down Switching Regulator with PMBus
+
+maintainers:
+ - Alexis Czezar Torreno <alexisczezar.torreno@analog.com>
+
+description: |
+ The MAX20830 is a fully integrated step-down DC-DC switching regulator with
+ PMBus interface. It provides 2.7V to 16V input, 0.4V to 5.8V adjustable
+ output, and up to 30A output current. It allows monitoring of input/output
+ voltage, output current and temperature through the PMBus serial interface.
+ Datasheet:
+ https://www.analog.com/en/products/max20830.html
+
+properties:
+ compatible:
+ const: adi,max20830
+
+ reg:
+ maxItems: 1
+
+ vddh-supply:
+ description:
+ Phandle to the regulator that provides the VDDH power supply.
+
+ avdd-supply:
+ description:
+ Phandle to the regulator that provides the AVDD power supply.
+
+ ldoin-supply:
+ description:
+ Optional 2.5V to 5.5V LDO input supply.
+
+required:
+ - compatible
+ - reg
+ - vddh-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hwmon@30 {
+ compatible = "adi,max20830";
+ reg = <0x30>;
+ vddh-supply = <&vddh>;
+ };
+ };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 0a3991c10ade20dd79cc7d1bf2a1d307ba6bd19d..031c743e979521a92ed9ac67915c178ce31727bd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15579,6 +15579,13 @@ F: Documentation/devicetree/bindings/hwmon/pmbus/adi,max17616.yaml
F: Documentation/hwmon/max17616.rst
F: drivers/hwmon/pmbus/max17616.c
+MAX20830 HARDWARE MONITOR DRIVER
+M: Alexis Czezar Torreno <alexisczezar.torreno@analog.com>
+L: linux-hwmon@vger.kernel.org
+S: Supported
+W: https://ez.analog.com/linux-software-drivers
+F: Documentation/devicetree/bindings/hwmon/pmbus/adi,max20830.yaml
+
MAX2175 SDR TUNER DRIVER
M: Ramesh Shanmugasundaram <rashanmu@gmail.com>
L: linux-media@vger.kernel.org
--
2.34.1
^ permalink raw reply related
* [PATCH 2/2] hwmon: (pmbus/max20830) add driver for max20830
From: Alexis Czezar Torreno @ 2026-04-14 4:28 UTC (permalink / raw)
To: Guenter Roeck, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jonathan Corbet, Shuah Khan
Cc: linux-hwmon, devicetree, linux-kernel, linux-doc,
Alexis Czezar Torreno
In-Reply-To: <20260414-dev_max20830-v1-0-210d3f82c571@analog.com>
Add support for MAX20830 step-down DC-DC switching regulator with
PMBus interface. It allows monitoring of input/output voltage,
output current and temperature through the PMBus serial interface.
Signed-off-by: Alexis Czezar Torreno <alexisczezar.torreno@analog.com>
---
Documentation/hwmon/index.rst | 1 +
Documentation/hwmon/max20830.rst | 48 ++++++++++++++++++++++++++
MAINTAINERS | 2 ++
drivers/hwmon/pmbus/Kconfig | 9 +++++
drivers/hwmon/pmbus/Makefile | 1 +
drivers/hwmon/pmbus/max20830.c | 74 ++++++++++++++++++++++++++++++++++++++++
6 files changed, 135 insertions(+)
diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst
index 8b655e5d6b68b90c697a52c7bf526e81d370caf7..56f7eb761be76dd627a2f34135abad05203b0582 100644
--- a/Documentation/hwmon/index.rst
+++ b/Documentation/hwmon/index.rst
@@ -158,6 +158,7 @@ Hardware Monitoring Kernel Drivers
max197
max20730
max20751
+ max20830
max31722
max31730
max31760
diff --git a/Documentation/hwmon/max20830.rst b/Documentation/hwmon/max20830.rst
new file mode 100644
index 0000000000000000000000000000000000000000..b9dffb76059781932d383ed798cecff69e738873
--- /dev/null
+++ b/Documentation/hwmon/max20830.rst
@@ -0,0 +1,48 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+Kernel driver max20830
+======================
+
+Supported chips:
+
+ * Analog Devices MAX20830
+
+ Prefix: 'max20830'
+
+ Addresses scanned: -
+
+ Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/max20830.pdf
+
+Author:
+
+ - Alexis Czezar Torreno <alexisczezar.torreno@analog.com>
+
+
+Description
+-----------
+
+This driver supports hardware monitoring for Analog Devices MAX20830
+Step-Down Switching Regulator with PMBus Interface.
+
+The MAX20830 is a 2.7V to 16V, 30A fully integrated step-down DC-DC switching
+regulator. Through the PMBus interface, the device can monitor input/output
+voltages, output current and temperature.
+
+The driver is a client driver to the core PMBus driver. Please see
+Documentation/hwmon/pmbus.rst for details on PMBus client drivers.
+
+Sysfs entries
+-------------
+
+================= ========================================
+in1_label "vin"
+in1_input Measured input voltage
+in1_alarm Input voltage alarm
+in2_label "vout1"
+in2_input Measured output voltage
+curr1_label "iout1"
+curr1_input Measured output current
+curr1_alarm Output current alarm
+temp1_input Measured temperature
+temp1_alarm Chip temperature alarm
+================= ========================================
diff --git a/MAINTAINERS b/MAINTAINERS
index 031c743e979521a92ed9ac67915c178ce31727bd..d6a6745e2dae29c3b8f80bbe61c54a2f5ecd9f47 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15585,6 +15585,8 @@ L: linux-hwmon@vger.kernel.org
S: Supported
W: https://ez.analog.com/linux-software-drivers
F: Documentation/devicetree/bindings/hwmon/pmbus/adi,max20830.yaml
+F: Documentation/hwmon/max20830.rst
+F: drivers/hwmon/pmbus/max20830.c
MAX2175 SDR TUNER DRIVER
M: Ramesh Shanmugasundaram <rashanmu@gmail.com>
diff --git a/drivers/hwmon/pmbus/Kconfig b/drivers/hwmon/pmbus/Kconfig
index 8f4bff375ecbc355f5ed3400855c2852ec2aa5ef..987705bf45b75b7b91ccc469247909f3c3f53d77 100644
--- a/drivers/hwmon/pmbus/Kconfig
+++ b/drivers/hwmon/pmbus/Kconfig
@@ -365,6 +365,15 @@ config SENSORS_MAX20751
This driver can also be built as a module. If so, the module will
be called max20751.
+config SENSORS_MAX20830
+ tristate "Analog Devices MAX20830"
+ help
+ If you say yes here you get hardware monitoring support for Analog
+ Devices MAX20830.
+
+ This driver can also be built as a module. If so, the module will
+ be called max20830.
+
config SENSORS_MAX31785
tristate "Maxim MAX31785 and compatibles"
help
diff --git a/drivers/hwmon/pmbus/Makefile b/drivers/hwmon/pmbus/Makefile
index 7129b62bc00f8a2e98de14004997752a856dfda2..bc52f930e0825a902a0dd1c9e2b44f2e8d577c35 100644
--- a/drivers/hwmon/pmbus/Makefile
+++ b/drivers/hwmon/pmbus/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_SENSORS_MAX16601) += max16601.o
obj-$(CONFIG_SENSORS_MAX17616) += max17616.o
obj-$(CONFIG_SENSORS_MAX20730) += max20730.o
obj-$(CONFIG_SENSORS_MAX20751) += max20751.o
+obj-$(CONFIG_SENSORS_MAX20830) += max20830.o
obj-$(CONFIG_SENSORS_MAX31785) += max31785.o
obj-$(CONFIG_SENSORS_MAX34440) += max34440.o
obj-$(CONFIG_SENSORS_MAX8688) += max8688.o
diff --git a/drivers/hwmon/pmbus/max20830.c b/drivers/hwmon/pmbus/max20830.c
new file mode 100644
index 0000000000000000000000000000000000000000..bcf60fd948e3437f47267747547142704ae96378
--- /dev/null
+++ b/drivers/hwmon/pmbus/max20830.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Hardware monitoring driver for Analog Devices MAX20830
+ *
+ * Copyright (C) 2026 Analog Devices, Inc.
+ */
+
+#include <linux/i2c.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include "pmbus.h"
+
+static struct pmbus_driver_info max20830_info = {
+ .pages = 1,
+ .format[PSC_VOLTAGE_IN] = linear,
+ .format[PSC_VOLTAGE_OUT] = linear,
+ .format[PSC_CURRENT_OUT] = linear,
+ .format[PSC_TEMPERATURE] = linear,
+ .func[0] = PMBUS_HAVE_VIN | PMBUS_HAVE_VOUT | PMBUS_HAVE_IOUT |
+ PMBUS_HAVE_TEMP |
+ PMBUS_HAVE_STATUS_VOUT | PMBUS_HAVE_STATUS_IOUT |
+ PMBUS_HAVE_STATUS_INPUT | PMBUS_HAVE_STATUS_TEMP,
+};
+
+static int max20830_probe(struct i2c_client *client)
+{
+ u8 buf[I2C_SMBUS_BLOCK_MAX + 1];
+ int ret;
+
+ if (!i2c_check_functionality(client->adapter,
+ I2C_FUNC_SMBUS_READ_I2C_BLOCK))
+ return -ENODEV;
+
+ ret = i2c_smbus_read_i2c_block_data(client, PMBUS_IC_DEVICE_ID,
+ I2C_SMBUS_BLOCK_MAX, buf);
+ if (ret < 0)
+ return dev_err_probe(&client->dev, ret,
+ "Failed to read IC_DEVICE_ID\n");
+
+ buf[ret] = '\0';
+ if (ret < 9 || strncmp(buf + 1, "MAX20830", 8))
+ return dev_err_probe(&client->dev, -ENODEV,
+ "Unsupported device: '%s'\n", buf);
+
+ return pmbus_do_probe(client, &max20830_info);
+}
+
+static const struct i2c_device_id max20830_id[] = {
+ {"max20830"},
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, max20830_id);
+
+static const struct of_device_id max20830_of_match[] = {
+ { .compatible = "adi,max20830" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, max20830_of_match);
+
+static struct i2c_driver max20830_driver = {
+ .driver = {
+ .name = "max20830",
+ .of_match_table = max20830_of_match,
+ },
+ .probe = max20830_probe,
+ .id_table = max20830_id,
+};
+
+module_i2c_driver(max20830_driver);
+
+MODULE_AUTHOR("Alexis Czezar Torreno <alexisczezar.torreno@analog.com>");
+MODULE_DESCRIPTION("PMBus driver for Analog Devices MAX20830");
+MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS(PMBUS);
--
2.34.1
^ permalink raw reply related
* [PATCH 0/2] Add support for MAX20830 PMBUS
From: Alexis Czezar Torreno @ 2026-04-14 4:28 UTC (permalink / raw)
To: Guenter Roeck, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jonathan Corbet, Shuah Khan
Cc: linux-hwmon, devicetree, linux-kernel, linux-doc,
Alexis Czezar Torreno
This series adds support for the Analog Devices MAX20830 step-down
switching regulator with PMBus interface.
The MAX20830 provides 2.7V to 16V input, 0.4V to 5.8V output, and up
to 30A output current. It supports monitoring of input/output voltage,
output current, and temperature via PMBus.
Datasheet: https://www.analog.com/en/products/max20830.html
Signed-off-by: Alexis Czezar Torreno <alexisczezar.torreno@analog.com>
---
Alexis Czezar Torreno (2):
dt-bindings: hwmon: pmbus: add max20830
hwmon: (pmbus/max20830) add driver for max20830
.../bindings/hwmon/pmbus/adi,max20830.yaml | 58 +++++++++++++++++
Documentation/hwmon/index.rst | 1 +
Documentation/hwmon/max20830.rst | 48 ++++++++++++++
MAINTAINERS | 9 +++
drivers/hwmon/pmbus/Kconfig | 9 +++
drivers/hwmon/pmbus/Makefile | 1 +
drivers/hwmon/pmbus/max20830.c | 74 ++++++++++++++++++++++
7 files changed, 200 insertions(+)
---
base-commit: fb447217c59a13b2fff22d94de2498c185cd9032
change-id: 20260414-dev_max20830-9460b92cf6aa
Best regards,
--
Alexis Czezar Torreno <alexisczezar.torreno@analog.com>
^ permalink raw reply
* [PATCH 3/3] pmdomain: qcom: rpmhpd: Add power domains for Nord SoC
From: Shawn Guo @ 2026-04-14 3:59 UTC (permalink / raw)
To: Ulf Hansson
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio, Kamal Wadhwa, Taniya Das, Bartosz Golaszewski,
Deepti Jaggi, linux-arm-msm, linux-pm, devicetree, linux-kernel,
Shawn Guo
In-Reply-To: <20260414035909.652992-1-shengchao.guo@oss.qualcomm.com>
From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Add RPMh power domains required for Nord SoC. This includes
new definitions for power domains supplying GFX1 and NSP3 subsystem.
Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
drivers/pmdomain/qcom/rpmhpd.c | 35 ++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/drivers/pmdomain/qcom/rpmhpd.c b/drivers/pmdomain/qcom/rpmhpd.c
index ba0cf4694435..63120e703923 100644
--- a/drivers/pmdomain/qcom/rpmhpd.c
+++ b/drivers/pmdomain/qcom/rpmhpd.c
@@ -122,6 +122,11 @@ static struct rpmhpd gfx = {
.res_name = "gfx.lvl",
};
+static struct rpmhpd gfx1 = {
+ .pd = { .name = "gfx1", },
+ .res_name = "gfx1.lvl",
+};
+
static struct rpmhpd lcx = {
.pd = { .name = "lcx", },
.res_name = "lcx.lvl",
@@ -217,6 +222,11 @@ static struct rpmhpd nsp2 = {
.res_name = "nsp2.lvl",
};
+static struct rpmhpd nsp3 = {
+ .pd = { .name = "nsp3", },
+ .res_name = "nsp3.lvl",
+};
+
static struct rpmhpd qphy = {
.pd = { .name = "qphy", },
.res_name = "qphy.lvl",
@@ -308,6 +318,30 @@ static const struct rpmhpd_desc sa8775p_desc = {
.num_pds = ARRAY_SIZE(sa8775p_rpmhpds),
};
+/* Nord RPMH powerdomains */
+static struct rpmhpd *nord_rpmhpds[] = {
+ [RPMHPD_CX] = &cx,
+ [RPMHPD_CX_AO] = &cx_ao,
+ [RPMHPD_EBI] = &ebi,
+ [RPMHPD_GFX] = &gfx,
+ [RPMHPD_GFX1] = &gfx1,
+ [RPMHPD_MX] = &mx,
+ [RPMHPD_MX_AO] = &mx_ao,
+ [RPMHPD_MMCX] = &mmcx,
+ [RPMHPD_MMCX_AO] = &mmcx_ao,
+ [RPMHPD_MXC] = &mxc,
+ [RPMHPD_MXC_AO] = &mxc_ao,
+ [RPMHPD_NSP0] = &nsp0,
+ [RPMHPD_NSP1] = &nsp1,
+ [RPMHPD_NSP2] = &nsp2,
+ [RPMHPD_NSP3] = &nsp3,
+};
+
+static const struct rpmhpd_desc nord_desc = {
+ .rpmhpds = nord_rpmhpds,
+ .num_pds = ARRAY_SIZE(nord_rpmhpds),
+};
+
/* SAR2130P RPMH powerdomains */
static struct rpmhpd *sar2130p_rpmhpds[] = {
[RPMHPD_CX] = &cx,
@@ -856,6 +890,7 @@ static const struct of_device_id rpmhpd_match_table[] = {
{ .compatible = "qcom,hawi-rpmhpd", .data = &hawi_desc },
{ .compatible = "qcom,kaanapali-rpmhpd", .data = &kaanapali_desc },
{ .compatible = "qcom,milos-rpmhpd", .data = &milos_desc },
+ { .compatible = "qcom,nord-rpmhpd", .data = &nord_desc },
{ .compatible = "qcom,qcs615-rpmhpd", .data = &qcs615_desc },
{ .compatible = "qcom,qcs8300-rpmhpd", .data = &qcs8300_desc },
{ .compatible = "qcom,qdu1000-rpmhpd", .data = &qdu1000_desc },
--
2.43.0
^ permalink raw reply related
* [PATCH 2/3] dt-bindings: power: qcom,rpmhpd: Add RPMh power domain for Nord SoC
From: Shawn Guo @ 2026-04-14 3:59 UTC (permalink / raw)
To: Ulf Hansson
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio, Kamal Wadhwa, Taniya Das, Bartosz Golaszewski,
Deepti Jaggi, linux-arm-msm, linux-pm, devicetree, linux-kernel,
Shawn Guo
In-Reply-To: <20260414035909.652992-1-shengchao.guo@oss.qualcomm.com>
From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Document the RPMh power domain for Nord SoC, and add definitions for
the new power domains present on Nord SoC.
- RPMHPD_NSP3: power domain for the 4th NSP subsystem
- RPMHPD_GFX1: power domain for the 2nd GFX subsystem
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 +
include/dt-bindings/power/qcom,rpmhpd.h | 2 ++
2 files changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
index 0bf1e13a9964..779380cc7e44 100644
--- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
+++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
@@ -35,6 +35,7 @@ properties:
- qcom,msm8994-rpmpd
- qcom,msm8996-rpmpd
- qcom,msm8998-rpmpd
+ - qcom,nord-rpmhpd
- qcom,qcm2290-rpmpd
- qcom,qcs404-rpmpd
- qcom,qcs615-rpmhpd
diff --git a/include/dt-bindings/power/qcom,rpmhpd.h b/include/dt-bindings/power/qcom,rpmhpd.h
index 74e910150956..07bd2a7b0150 100644
--- a/include/dt-bindings/power/qcom,rpmhpd.h
+++ b/include/dt-bindings/power/qcom,rpmhpd.h
@@ -30,6 +30,8 @@
#define RPMHPD_GMXC 20
#define RPMHPD_DCX 21
#define RPMHPD_GBX 22
+#define RPMHPD_NSP3 23
+#define RPMHPD_GFX1 24
/* RPMh Power Domain performance levels */
#define RPMH_REGULATOR_LEVEL_RETENTION 16
--
2.43.0
^ permalink raw reply related
* [PATCH 1/3] dt-bindings: power: qcom,rpmhpd: Fix whitespace in RPMHPD defines
From: Shawn Guo @ 2026-04-14 3:59 UTC (permalink / raw)
To: Ulf Hansson
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio, Kamal Wadhwa, Taniya Das, Bartosz Golaszewski,
Deepti Jaggi, linux-arm-msm, linux-pm, devicetree, linux-kernel,
Shawn Guo
In-Reply-To: <20260414035909.652992-1-shengchao.guo@oss.qualcomm.com>
Some RPMHPD_* defines in the Generic RPMH Power Domain Indexes section
were using spaces instead of tabs for alignment. Fix them to be
consistent with the rest of the file.
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
include/dt-bindings/power/qcom,rpmhpd.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/include/dt-bindings/power/qcom,rpmhpd.h b/include/dt-bindings/power/qcom,rpmhpd.h
index 67e2634fdc99..74e910150956 100644
--- a/include/dt-bindings/power/qcom,rpmhpd.h
+++ b/include/dt-bindings/power/qcom,rpmhpd.h
@@ -7,7 +7,7 @@
#define _DT_BINDINGS_POWER_QCOM_RPMHPD_H
/* Generic RPMH Power Domain Indexes */
-#define RPMHPD_CX 0
+#define RPMHPD_CX 0
#define RPMHPD_CX_AO 1
#define RPMHPD_EBI 2
#define RPMHPD_GFX 3
@@ -19,14 +19,14 @@
#define RPMHPD_MX_AO 9
#define RPMHPD_MXC 10
#define RPMHPD_MXC_AO 11
-#define RPMHPD_MSS 12
+#define RPMHPD_MSS 12
#define RPMHPD_NSP 13
-#define RPMHPD_NSP0 14
-#define RPMHPD_NSP1 15
-#define RPMHPD_QPHY 16
-#define RPMHPD_DDR 17
-#define RPMHPD_XO 18
-#define RPMHPD_NSP2 19
+#define RPMHPD_NSP0 14
+#define RPMHPD_NSP1 15
+#define RPMHPD_QPHY 16
+#define RPMHPD_DDR 17
+#define RPMHPD_XO 18
+#define RPMHPD_NSP2 19
#define RPMHPD_GMXC 20
#define RPMHPD_DCX 21
#define RPMHPD_GBX 22
--
2.43.0
^ permalink raw reply related
* [PATCH 0/3] pmdomain: qcom: rpmhpd: Add power domains for Nord SoC
From: Shawn Guo @ 2026-04-14 3:59 UTC (permalink / raw)
To: Ulf Hansson
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio, Kamal Wadhwa, Taniya Das, Bartosz Golaszewski,
Deepti Jaggi, linux-arm-msm, linux-pm, devicetree, linux-kernel,
Shawn Guo
This series adds RPMh power domain support for the Qualcomm Nord SoC.
The Nord SoC introduces two new power domains beyond the existing set: GFX1
for the second GFX subsystem and NSP3 for the fourth NSP subsystem. Patch 1
is a preparatory cleanup that fixes inconsistent whitespace in the RPMHPD
define block before the new entries are added. Patches 2-3 add the DT
bindings and driver support for Nord respectively.
Kamal Wadhwa (2):
dt-bindings: power: qcom,rpmhpd: Add RPMh power domain for Nord SoC
pmdomain: qcom: rpmhpd: Add power domains for Nord SoC
Shawn Guo (1):
dt-bindings: power: qcom,rpmhpd: Fix whitespace in RPMHPD defines
.../devicetree/bindings/power/qcom,rpmpd.yaml | 1 +
drivers/pmdomain/qcom/rpmhpd.c | 35 +++++++++++++++++++
include/dt-bindings/power/qcom,rpmhpd.h | 18 +++++-----
3 files changed, 46 insertions(+), 8 deletions(-)
--
2.43.0
^ permalink raw reply
* [PATCH v4] ASoC: dt-bindings: ti,pcm3060: add descriptions and rename binding
From: Padmashree S S @ 2026-04-14 3:48 UTC (permalink / raw)
To: k.marinushkin, lgirdwood
Cc: broonie, robh, krzk+dt, conor+dt, linux-sound, devicetree,
linux-kernel, padmashreess2006
In-Reply-To: <20260327121919.603768-1-padmashreess2006@gmail.com>
Add description to reg property and overall binding mentioning that this
driver supports both I2C and SPI. Rename binding to match compatible
naming convention.
Signed-off-by: Padmashree S S <padmashreess2006@gmail.com>
---
Changes in v4:
- Rename binding from pcm3060 to ti,pcm3060
- Add binding description
- Add description to 'reg' property
- Remove unused label in example
Changes in v3:
- Remove description from 'reg' property
---
.../bindings/sound/{pcm3060.yaml => ti,pcm3060.yaml} | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
rename Documentation/devicetree/bindings/sound/{pcm3060.yaml => ti,pcm3060.yaml} (74%)
diff --git a/Documentation/devicetree/bindings/sound/pcm3060.yaml b/Documentation/devicetree/bindings/sound/ti,pcm3060.yaml
similarity index 74%
rename from Documentation/devicetree/bindings/sound/pcm3060.yaml
rename to Documentation/devicetree/bindings/sound/ti,pcm3060.yaml
index ceb6f044b196..5a402d8b7daa 100644
--- a/Documentation/devicetree/bindings/sound/pcm3060.yaml
+++ b/Documentation/devicetree/bindings/sound/ti,pcm3060.yaml
@@ -1,11 +1,13 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
-$id: http://devicetree.org/schemas/sound/pcm3060.yaml#
+$id: http://devicetree.org/schemas/sound/ti,pcm3060.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: PCM3060 audio CODEC
+description: This driver supports both I2C and SPI.
+
maintainers:
- Kirill Marinushkin <k.marinushkin@gmail.com>
@@ -21,9 +23,7 @@ properties:
ti,out-single-ended:
type: boolean
- description: |
- If present, the output is single-ended.
- If absent, the output is differential.
+ description: If present, the output is single-ended. If absent, the output is differential.
required:
- compatible
@@ -37,7 +37,7 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
- pcm3060: audio-codec@46 {
+ audio-codec@46 {
compatible = "ti,pcm3060";
reg = <0x46>;
ti,out-single-ended;
--
2.43.0
^ permalink raw reply related
* Re: [PATCH v2 1/4] riscv: add UltraRISC SoC family Kconfig support
From: Jia Wang @ 2026-04-14 3:27 UTC (permalink / raw)
To: Conor Dooley
Cc: Jia Wang, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Jingoo Han,
Xincheng Zhang, Krzysztof Kozlowski, Conor Dooley, linux-riscv,
linux-kernel, linux-pci, devicetree
In-Reply-To: <20260408-wise-dividers-ec8a057d4bd2@spud>
On 2026-04-08 18:10 +0100, Conor Dooley wrote:
> On Wed, Apr 08, 2026 at 09:47:04AM +0800, Jia Wang wrote:
> > On 2026-04-07 17:29 +0100, Conor Dooley wrote:
> > > On Tue, Apr 07, 2026 at 10:40:52AM +0800, Jia Wang wrote:
> > > > The first SoC in the UltraRISC series is UR-DP1000, containing octa
> > > > UltraRISC C100 cores.
> > >
> > > Not gonna lie, I find it odd that pcie is where this platform starts
> > > off, but sure. What's the plan for adding the rest of the platform?
> > >
> >
> > Hi Conor,
> >
> > Thanks for the question.
> >
> > Our next step is to upstream the pinctrl driver together with the related
> > DTS updates. The pinctrl series only affects the SoC’s low-speed peripheral
> > interfaces. For GMAC, SPI, I2C, and GPIO, we plan to use the existing
> > kernel drivers, so no new controller drivers are needed
>
> And clocks? pinctrl and clocks would be the bare minimum level of
> support required before a platform should be merged. Obviously, you can
> get device drivers for PCI etc etc merged without clock drivers, but the
> initial dts should contain the clocks too.
>
On our platform, all functional clocks are fully configured and enabled by
the firmware before Linux boots. The kernel is not expected to adjust clock
rates or gate/ungate clocks at runtime.
Therefore, in the initial device tree we only describe the fixed clocks
required by the standard subsystem drivers, using `fixed-clock` where needed.
Since there is no clock controller accessible to the OS, we do not plan to
add a clock driver at this stage. If future hardware versions expose a
programmable clock controller to Linux, we will upstream the corresponding
driver and update the DT accordingly.
> > > >
> > > > Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> > > > ---
> > > > arch/riscv/Kconfig.socs | 9 +++++++++
> > > > 1 file changed, 9 insertions(+)
> > > >
> > > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > > > index d621b85dd63b..98708569ec6a 100644
> > > > --- a/arch/riscv/Kconfig.socs
> > > > +++ b/arch/riscv/Kconfig.socs
> > > > @@ -84,6 +84,15 @@ config ARCH_THEAD
> > > > help
> > > > This enables support for the RISC-V based T-HEAD SoCs.
> > > >
> > > > +config ARCH_ULTRARISC
> > > > + bool "UltraRISC RISC-V SoCs"
> > > > + help
> > > > + This enables support for UltraRISC SoC platform hardware,
> > > > + including boards based on the UR-DP1000.
> > >
> > > > + UR-DP1000 is an 8-core 64-bit RISC-V SoC that supports
> > > > + the RV64GCBHX ISA. It supports Hardware Virtualization
> > > > + and RISC-V RV64 ISA H(v1.0) Extension.
> > >
> > > Delete this section IMO, doesn't provide any real value. Don't need nor
> > > want the marketing brochure in the help text. The first sentence is
> > > sufficient.
> > >
> >
> > I’ll drop the SoC description part from the Kconfig help text as you
> > suggested.
> >
> > > > +
> > > > config ARCH_VIRT
> > > > bool "QEMU Virt Machine"
> > > > select POWER_RESET
> > > >
> > > > --
> > > > 2.34.1
> > > >
> >
> > Best regards,
> > Jia Wang
> >
^ permalink raw reply
* Re: [PATCH v7 0/2] arm64: dts/defconfig: enable BST C1200 eMMC
From: Albert Yang @ 2026-04-14 3:10 UTC (permalink / raw)
To: Gordon Ge
Cc: Albert Yang, krzk, arnd, krzk+dt, robh, conor+dt, bst-upstream,
linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20260310091211.4171307-1-yangzh0906@thundersoft.com>
Hi Gordon,
Could you please help with:
1) Reviewing the remaining 2 patches in this series.
If acceptable, please reply with an Acked-by on each patch below:
- [PATCH v7 1/2] arm64: dts: bst: enable eMMC controller in C1200 CDCU1.0 board
- [PATCH v7 2/2] arm64: defconfig: enable BST SDHCI controller
I will carry your tags in the next revision.
Thanks,
Albert
^ permalink raw reply
* Re: Re: [PATCH v3 1/2] dt-bindings: pwm: dwc: add reset optional
From: Xuyang Dong @ 2026-04-14 2:52 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: ukleinek, robh, krzk+dt, conor+dt, ben-linux, ben.dooks, p.zabel,
linux-pwm, devicetree, linux-kernel, ningyu, linmin, xuxiang,
wangguosheng, pinkesh.vaghela
In-Reply-To: <20260403-glossy-industrious-pug-4f2b2c@quoll>
> >
> > The DesignWare PWM controller provides separate reset signals for each
>
> So one controller has signals. Plural, right? Then why do you define
> only one reset signal?
>
Hi Krzysztof,
There are two reset signals matching the two clocks, so maxItems is set to 2.
> > clock domain, as specified in the hardware documentation. Without
> > asserting and deasserting these resets during probe, PWM outputs may
> > remain in an undefined state after system reboot.
> >
> > To address this, the driver now supports an optional 'resets' property.
>
> This is binding change, not driver.
>
> > A full reset is performed only when no PWM channel is enabled, as
> > determined by reading the enable bit in each channel's control register.
>
> Do you describe hardware or driver behavior? This is not a change about
> driver. Describe the hardware here - what is expected with that reset.
>
> > This allows safe coexistence with bootloaders that have already
> > configured active PWM channels.
>
The improvement commit message for the next version will be revised
as follows:
The DesignWare PWM includes separate reset signals dedicated to each clock
domain:
The presetn signal resets logic in pclk domain.
The timer_N_resetn signal resets logic in the timer_N_clk domain.
The resets are active-low.
In the next version, we will address the changes as described above.
Best regards,
Xuyang Dong
^ permalink raw reply
* Re: [PATCH v2 2/2] usb: dwc3: starfive: Add JHB100 USB 2.0 DRD controller
From: Thinh Nguyen @ 2026-04-14 0:59 UTC (permalink / raw)
To: Minda Chen
Cc: Greg Kroah-Hartman, Thinh Nguyen, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-usb@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
In-Reply-To: <20260410112500.90432-3-minda.chen@starfivetech.com>
On Fri, Apr 10, 2026, Minda Chen wrote:
> JHB100 contains 2 dwc3 USB controllers and PHYs and working
> as USB 2.0 speed. It can working in generic platform and
> setting default properties.
>
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> ---
> drivers/usb/dwc3/dwc3-generic-plat.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c
> index e846844e0023..e9e29b63aaa4 100644
> --- a/drivers/usb/dwc3/dwc3-generic-plat.c
> +++ b/drivers/usb/dwc3/dwc3-generic-plat.c
> @@ -214,6 +214,7 @@ static const struct of_device_id dwc3_generic_of_match[] = {
> { .compatible = "spacemit,k1-dwc3", },
> { .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3},
> { .compatible = "eswin,eic7700-dwc3", &eic7700_dwc3},
> + { .compatible = "starfive,jhb100-dwc3", },
> { /* sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, dwc3_generic_of_match);
> --
> 2.17.1
>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
BR,
Thinh
^ permalink raw reply
* Re: Re: [PATCH 2/3] clk: eswin: Add eic7700 HSP clock driver
From: Xuyang Dong @ 2026-04-14 2:36 UTC (permalink / raw)
To: Brian Masney
Cc: mturquette, sboyd, robh, krzk+dt, conor+dt, linux-clk, devicetree,
linux-kernel, p.zabel, huangyifeng, ningyu, linmin,
pinkesh.vaghela
In-Reply-To: <ac_H7kSCgzz5HRxV@redhat.com>
> > +
> > +static struct clk_parent_data hsp_usb_sata[] = {
> > + { .fw_name = "hsp_sata" }
> > +};
> > +
> > +static struct eswin_fixed_factor_clock eic7700_hsp_factor_clks[] = {
>
> More places for static const? I'll leave out the others.
>
Hi Brian,
When registering a clock, the 'hw' field in the structure will be assigned,
so these clock structures cannot be declared const.
Other comments will be fixed in the next version.
Best regards,
Xuyang Dong
> > + ESWIN_FACTOR(EIC7700_HSP_CLK_FAC_CFG_DIV2, "factor_hsp_cfg_div2",
> > + hsp_cfg, 1, 2, 0),
> > + ESWIN_FACTOR(EIC7700_HSP_CLK_FAC_CFG_DIV4, "factor_hsp_cfg_div4",
> > + hsp_cfg, 1, 4, 0),
> > + ESWIN_FACTOR(EIC7700_HSP_CLK_FAC_MMC_DIV10, "factor_hsp_mmc_div10",
> > + hsp_mmc, 1, 10, 0),
> > +};
> > +
> > +static struct eswin_gate_clock eic7700_hsp_gate_clks[] = {
> > + ESWIN_GATE(EIC7700_HSP_CLK_GATE_SATA, "gate_clk_hsp_sata", hsp_usb_sata,
> > + CLK_SET_RATE_PARENT, EIC7700_HSP_SATA_REG, 28, 0),
> > + ESWIN_GATE(EIC7700_HSP_CLK_GATE_MSHC0_TMR, "gate_clk_hsp_mshc0_tmr",
> > + hsp_mmc, CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC0_REG, 8, 0),
> > + ESWIN_GATE(EIC7700_HSP_CLK_GATE_MSHC1_TMR, "gate_clk_hsp_mshc1_tmr",
> > + hsp_mmc, CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC1_REG, 8, 0),
> > + ESWIN_GATE(EIC7700_HSP_CLK_GATE_MSHC2_TMR, "gate_clk_hsp_mshc2_tmr",
> > + hsp_mmc, CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC2_REG, 8, 0),
> > +};
> > +
> > +static struct eic7700_hsp_clk_gate eic7700_hsp_spec_gate_clks[] = {
> > + EIC7700_HSP_GATE(EIC7700_HSP_CLK_GATE_USB0, "gate_clk_hsp_usb0",
> > + hsp_usb_sata, CLK_SET_RATE_PARENT,
> > + EIC7700_HSP_USB0_REG, 28, EIC7700_HSP_USB0_REF_REG),
> > + EIC7700_HSP_GATE(EIC7700_HSP_CLK_GATE_USB1, "gate_clk_hsp_usb1",
> > + hsp_usb_sata, CLK_SET_RATE_PARENT,
> > + EIC7700_HSP_USB1_REG, 28, EIC7700_HSP_USB1_REF_REG),
> > +};
> > +
> > +static const struct clk_parent_data mux_mmc_3mux1_p[] = {
> > + { .fw_name = "hsp_cfg" },
> > + { .hw = &eic7700_hsp_factor_clks[0].hw },
> > + { .hw = &eic7700_hsp_factor_clks[1].hw },
> > +};
> > +
> > +static const struct clk_parent_data mux_mmc_2mux1_p[] = {
> > + { .fw_name = "hsp_mmc" },
> > + { .hw = &eic7700_hsp_factor_clks[2].hw },
> > +};
> > +
> > +static u32 mux_mmc_3mux1_tbl[] = { 0x0, 0x1, 0x3 };
> > +
> > +static struct eswin_mux_clock eic7700_hsp_mux_clks[] = {
> > + ESWIN_MUX_TBL(EIC7700_HSP_CLK_MUX_EMMC_3MUX1, "mux_hsp_emmc_3mux1",
> > + mux_mmc_3mux1_p, ARRAY_SIZE(mux_mmc_3mux1_p),
> > + CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC0_REG, 16, 2, 0,
> > + mux_mmc_3mux1_tbl),
> > + ESWIN_MUX_TBL(EIC7700_HSP_CLK_MUX_SD0_3MUX1, "mux_hsp_sd0_3mux1",
> > + mux_mmc_3mux1_p, ARRAY_SIZE(mux_mmc_3mux1_p),
> > + CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC1_REG, 16, 2, 0,
> > + mux_mmc_3mux1_tbl),
> > + ESWIN_MUX_TBL(EIC7700_HSP_CLK_MUX_SD1_3MUX1, "mux_hsp_sd1_3mux1",
> > + mux_mmc_3mux1_p, ARRAY_SIZE(mux_mmc_3mux1_p),
> > + CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC2_REG, 16, 2, 0,
> > + mux_mmc_3mux1_tbl),
> > + ESWIN_MUX(EIC7700_HSP_CLK_MUX_EMMC_CQE_2MUX1, "mux_hsp_emmc_cqe_2mux1",
> > + mux_mmc_2mux1_p, ARRAY_SIZE(mux_mmc_2mux1_p),
> > + CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC0_REG, 0, 1, 0),
> > + ESWIN_MUX(EIC7700_HSP_CLK_MUX_SD0_CQE_2MUX1, "mux_hsp_sd0_cqe_2mux1",
> > + mux_mmc_2mux1_p, ARRAY_SIZE(mux_mmc_2mux1_p),
> > + CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC1_REG, 0, 1, 0),
> > + ESWIN_MUX(EIC7700_HSP_CLK_MUX_SD1_CQE_2MUX1, "mux_hsp_sd1_cqe_2mux1",
> > + mux_mmc_2mux1_p, ARRAY_SIZE(mux_mmc_2mux1_p),
> > + CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC2_REG, 0, 1, 0),
> > +};
> > +
> > +static struct eswin_clk_info eic7700_hsp_clks[] = {
> > + ESWIN_GATE_TYPE(EIC7700_HSP_CLK_GATE_EMMC, "gate_clk_hsp_emmc",
> > + EIC7700_HSP_CLK_MUX_EMMC_3MUX1,
> > + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + EIC7700_HSP_MSHC0_REG, 24, 0),
> > + ESWIN_GATE_TYPE(EIC7700_HSP_CLK_GATE_SD0, "gate_clk_hsp_sd0",
> > + EIC7700_HSP_CLK_MUX_SD0_3MUX1,
> > + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + EIC7700_HSP_MSHC1_REG, 24, 0),
> > + ESWIN_GATE_TYPE(EIC7700_HSP_CLK_GATE_SD1, "gate_clk_hsp_sd1",
> > + EIC7700_HSP_CLK_MUX_SD1_3MUX1,
> > + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + EIC7700_HSP_MSHC2_REG, 24, 0),
> > +};
> > +
> > +static int eic7700_hsp_clk_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct auxiliary_device *adev;
> > + struct eswin_clock_data *data;
> > + struct clk_hw *hw;
> > + int i, ret;
> > +
> > + data = eswin_clk_init(pdev, EIC7700_HSP_NR_CLKS);
> > + if (IS_ERR(data))
> > + return dev_err_probe(dev, PTR_ERR(data),
> > + "failed to get clk data!\n");
> > +
> > + ret = eswin_clk_register_fixed_factor
> > + (dev, eic7700_hsp_factor_clks,
> > + ARRAY_SIZE(eic7700_hsp_factor_clks), data);
>
> The first two lines can be combined together to improve the formatting:
>
> ret = eswin_clk_register_fixed_factor(dev, eic7700_hsp_factor_clks,
>
> > + if (ret)
> > + return dev_err_probe(dev, ret,
> > + "failed to register fixed factor clock\n");
> > +
> > + ret = eswin_clk_register_gate(dev, eic7700_hsp_gate_clks,
> > + ARRAY_SIZE(eic7700_hsp_gate_clks), data);
> > + if (ret)
> > + return dev_err_probe(dev, ret,
> > + "failed to register gate clock\n");
> > +
> > + ret = eswin_clk_register_mux(dev, eic7700_hsp_mux_clks,
> > + ARRAY_SIZE(eic7700_hsp_mux_clks),
> > + data);
> > + if (ret)
> > + return dev_err_probe(dev, ret,
> > + "failed to register mux clock\n");
> > +
> > + ret = eswin_clk_register_clks(dev, eic7700_hsp_clks,
> > + ARRAY_SIZE(eic7700_hsp_clks), data);
> > + if (ret)
> > + return dev_err_probe(dev, ret,
> > + "failed to register clock\n");
> > +
> > + for (i = 0; i < ARRAY_SIZE(eic7700_hsp_spec_gate_clks); i++) {
> > + struct eic7700_hsp_clk_gate *gate;
> > +
> > + gate = &eic7700_hsp_spec_gate_clks[i];
> > + hw = hsp_clk_register_gate(dev, gate->id, gate->name,
> > + gate->parent_data, gate->flags,
> > + data->base + gate->offset,
> > + data->base + gate->ref_offset,
> > + gate->bit_idx, 0, &data->lock);
> > + if (IS_ERR(hw))
> > + return dev_err_probe(dev, PTR_ERR(hw),
> > + "failed to register gate clock\n");
> > +
> > + data->clk_data.hws[gate->id] = hw;
> > + }
> > +
> > + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
> > + &data->clk_data);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "add clk provider failed\n");
> > +
> > + adev = devm_auxiliary_device_create(dev, "hsp-reset",
> > + (__force void *)data->base);
>
> So this driver is sharing the same register space with the reset driver,
> and the reset driver calls devm_regmap_init_mmio(). What do you think
> about having a shared regmap between the two drivers so that the __force
> is not needed?
>
> Brian
>
>
> > + if (!adev)
> > + return dev_err_probe(dev, -ENODEV,
> > + "register hsp-reset device failed\n");
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id eic7700_hsp_clock_dt_ids[] = {
> > + { .compatible = "eswin,eic7700-hspcrg", },
> > + { /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, eic7700_hsp_clock_dt_ids);
> > +
> > +static struct platform_driver eic7700_hsp_clock_driver = {
> > + .probe = eic7700_hsp_clk_probe,
> > + .driver = {
> > + .name = "eic7700-hsp-clock",
> > + .of_match_table = eic7700_hsp_clock_dt_ids,
> > + },
> > +};
> > +
> > +module_platform_driver(eic7700_hsp_clock_driver);
> > +
> > +MODULE_LICENSE("GPL");
> > +MODULE_AUTHOR("Xuyang Dong <dongxuyang@eswincomputing.com>");
> > +MODULE_DESCRIPTION("ESWIN EIC7700 HSP clock controller driver");
> > --
> > 2.34.1
> >
^ permalink raw reply
* Re: [PATCH v2] dt-bindings: arm: marvell: Convert armada-380-mpcore-soc-ctrl to DT Schema
From: Padmashree S S @ 2026-04-14 2:13 UTC (permalink / raw)
To: Rob Herring
Cc: andrew, gregory.clement, sebastian.hesselbarth, krzk+dt, conor+dt,
linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20260407184455.GA3369046-robh@kernel.org>
On Wed, Apr 8, 2026 at 12:14 AM Rob Herring <robh@kernel.org> wrote:
>
> On Fri, Mar 27, 2026 at 05:16:53PM +0530, Padmashree S S wrote:
> > Convert armada-380-mpcore-soc-ctrl to DT schema
> >
> > Signed-off-by: Padmashree S S <padmashreess2006@gmail.com>
> > ---
> > .../marvell/armada-380-mpcore-soc-ctrl.txt | 14 --------
> > .../marvell/armada-380-mpcore-soc-ctrl.yaml | 32 +++++++++++++++++++
> > 2 files changed, 32 insertions(+), 14 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.txt
> > create mode 100644 Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.yaml
>
> Please move this to
> bindings/soc/marvell/marvell,armada-380-mpcore-soc-ctrl.yaml
>
> Don't forget to update the '$id' value.
>
> Rob
Thank you for the review, I'll move the binding and change the $id in
the next version of this patch.
^ permalink raw reply
* [PATCH v2 2/2] ASoC: tas2781: Add tas5832 support
From: Baojun Xu @ 2026-04-14 1:54 UTC (permalink / raw)
To: broonie, tiwai
Cc: andriy.shevchenko, 13916275206, shenghao-ding, baojun.xu,
linux-sound, linux-kernel, lgirdwood, robh, krzk+dt, conor+dt,
devicetree, k-yi, henry.lo, robinchen, will-wang, jim.shil,
toastcheng, chinkaiting
In-Reply-To: <20260414015441.2439-1-baojun.xu@ti.com>
TAS5832 is in same family with TAS5827/28/30.
Signed-off-by: Baojun Xu <baojun.xu@ti.com>
---
v2:
- Follow the updated association protocol based on device name and id.
---
include/sound/tas2781.h | 1 +
sound/soc/codecs/tas2781-i2c.c | 5 +++++
2 files changed, 6 insertions(+)
diff --git a/include/sound/tas2781.h b/include/sound/tas2781.h
index e847cf51878c..95296bb4a33a 100644
--- a/include/sound/tas2781.h
+++ b/include/sound/tas2781.h
@@ -131,6 +131,7 @@ enum audio_device {
TAS5827,
TAS5828,
TAS5830,
+ TAS5832,
TAS_OTHERS,
};
diff --git a/sound/soc/codecs/tas2781-i2c.c b/sound/soc/codecs/tas2781-i2c.c
index c593f9da0c5b..86b591c489c2 100644
--- a/sound/soc/codecs/tas2781-i2c.c
+++ b/sound/soc/codecs/tas2781-i2c.c
@@ -119,6 +119,7 @@ static const struct i2c_device_id tasdevice_id[] = {
{ "tas5827", TAS5827 },
{ "tas5828", TAS5828 },
{ "tas5830", TAS5830 },
+ { "tas5832", TAS5832 },
{}
};
@@ -143,6 +144,7 @@ static const struct of_device_id tasdevice_of_match[] = {
{ .compatible = "ti,tas5827", .data = &tasdevice_id[TAS5827] },
{ .compatible = "ti,tas5828", .data = &tasdevice_id[TAS5828] },
{ .compatible = "ti,tas5830", .data = &tasdevice_id[TAS5830] },
+ { .compatible = "ti,tas5832", .data = &tasdevice_id[TAS5832] },
{},
};
MODULE_DEVICE_TABLE(of, tasdevice_of_match);
@@ -1746,6 +1748,7 @@ static void tasdevice_fw_ready(const struct firmware *fmw,
case TAS5827:
case TAS5828:
case TAS5830:
+ case TAS5832:
/* If DSP FW fail, DSP kcontrol won't be created. */
tasdevice_dsp_remove(tas_priv);
}
@@ -1917,6 +1920,7 @@ static int tasdevice_codec_probe(struct snd_soc_component *codec)
case TAS5827:
case TAS5828:
case TAS5830:
+ case TAS5832:
p = (struct snd_kcontrol_new *)tas5825_snd_controls;
size = ARRAY_SIZE(tas5825_snd_controls);
break;
@@ -2104,6 +2108,7 @@ static const struct acpi_device_id tasdevice_acpi_match[] = {
{ "TXNW5827", (kernel_ulong_t)&tasdevice_id[TAS5827] },
{ "TXNW5828", (kernel_ulong_t)&tasdevice_id[TAS5828] },
{ "TXNW5830", (kernel_ulong_t)&tasdevice_id[TAS5830] },
+ { "TXNW5832", (kernel_ulong_t)&tasdevice_id[TAS5832] },
{},
};
--
2.25.1
^ permalink raw reply related
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