* Re: [PATCH v12 10/22] dt-bindings: media: i2c: max96712: add control-channel-port property
From: sashiko-bot @ 2026-05-21 13:02 UTC (permalink / raw)
To: Dumitru Ceclan via B4 Relay; +Cc: conor+dt, robh, devicetree
In-Reply-To: <20260521-gmsl2-3_serdes-v12-10-b26d92931196@analog.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Missing formal `default` keyword for the `maxim,control-channel-port` property.
--
commit b55632a6d213d38d8586238541441292d954e479
Author: Dumitru Ceclan <dumitru.ceclan@analog.com>
dt-bindings: media: i2c: max96712: add control-channel-port property
This commit adds the maxim,control-channel-port property to the binding,
allowing platforms to choose which control-channel port is connected to the
upstream I2C host.
> diff --git a/Documentation/devicetree/bindings/media/i2c/maxim,max96712.yaml b/Documentation/devicetree/bindings/media/i2c/maxim,max96712.yaml
> index 161d40acdd28f..538b639d4f542 100644
> --- a/Documentation/devicetree/bindings/media/i2c/maxim,max96712.yaml
> +++ b/Documentation/devicetree/bindings/media/i2c/maxim,max96712.yaml
> @@ -41,6 +41,14 @@ properties:
>
> enable-gpios: true
>
> + maxim,control-channel-port:
> + description:
> + Selects which deserializer control-channel port is connected to the
> + upstream I2C segment when the device resets. 0 selects port 0, 1 selects
> + port 1. Defaults to 0 when omitted.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1]
[Severity: Low]
The description states this defaults to 0 when omitted, but the schema does
not include the corresponding default keyword. Should a formal "default: 0"
declaration be added here?
> +
> i2c-alias-pool:
> maxItems: 4
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260521-gmsl2-3_serdes-v12-0-b26d92931196@analog.com?part=10
^ permalink raw reply
* Re: [PATCH v7 09/28] media: rockchip: rga: remove redundant rga_frame variables
From: Michael Tretter @ 2026-05-21 13:03 UTC (permalink / raw)
To: Sven Püschel
Cc: Jacob Chen, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Hans Verkuil, linux-media, linux-rockchip, linux-arm-kernel,
linux-kernel, devicetree, kernel, nicolas, sebastian.reichel,
p.zabel, Nicolas Dufresne
In-Reply-To: <20260521-spu-rga3-v7-9-3f33e8c7145f@pengutronix.de>
On Thu, 21 May 2026 00:44:14 +0200, Sven Püschel wrote:
> Remove the redundant rga_frame variables width, height and color space.
> The value of these variables is already contained in the pix member
> of rga_frame. The code also keeps these values in sync. Therefore drop
> them in favor of the existing pix member.
>
> Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
> Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
Reviewed-by: Michael Tretter <m.tretter@pengutronix.de>
> ---
> drivers/media/platform/rockchip/rga/rga-buf.c | 6 ++---
> drivers/media/platform/rockchip/rga/rga-hw.c | 6 ++---
> drivers/media/platform/rockchip/rga/rga.c | 32 ++++++++++-----------------
> drivers/media/platform/rockchip/rga/rga.h | 5 -----
> 4 files changed, 18 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/media/platform/rockchip/rga/rga-buf.c b/drivers/media/platform/rockchip/rga/rga-buf.c
> index 65fc0d5b4aa10..ffc6162b2e681 100644
> --- a/drivers/media/platform/rockchip/rga/rga-buf.c
> +++ b/drivers/media/platform/rockchip/rga/rga-buf.c
> @@ -103,10 +103,10 @@ static int get_plane_offset(struct rga_frame *f,
> if (plane == 0)
> return 0;
> if (plane == 1)
> - return stride * f->height;
> + return stride * f->pix.height;
> if (plane == 2)
> - return stride * f->height +
> - (stride * f->height / info->hdiv / info->vdiv);
> + return stride * f->pix.height +
> + (stride * f->pix.height / info->hdiv / info->vdiv);
>
> return -EINVAL;
> }
> diff --git a/drivers/media/platform/rockchip/rga/rga-hw.c b/drivers/media/platform/rockchip/rga/rga-hw.c
> index d1618bb247501..ec6c17504ca15 100644
> --- a/drivers/media/platform/rockchip/rga/rga-hw.c
> +++ b/drivers/media/platform/rockchip/rga/rga-hw.c
> @@ -53,7 +53,7 @@ rga_get_addr_offset(struct rga_frame *frm, struct rga_addr_offset *offset,
> x_div = frm->fmt->x_div;
> y_div = frm->fmt->y_div;
> uv_stride = frm->stride / x_div;
> - pixel_width = frm->stride / frm->width;
> + pixel_width = frm->stride / frm->pix.width;
>
> lt->y_off = offset->y_off + y * frm->stride + x * pixel_width;
> lt->u_off = offset->u_off + (y / y_div) * uv_stride + x / x_div;
> @@ -191,7 +191,7 @@ static void rga_cmd_set_trans_info(struct rga_ctx *ctx)
>
> if (RGA_COLOR_FMT_IS_YUV(ctx->in.fmt->hw_format) &&
> RGA_COLOR_FMT_IS_RGB(ctx->out.fmt->hw_format)) {
> - switch (ctx->in.colorspace) {
> + switch (ctx->in.pix.colorspace) {
> case V4L2_COLORSPACE_REC709:
> src_info.data.csc_mode = RGA_SRC_CSC_MODE_BT709_R0;
> break;
> @@ -203,7 +203,7 @@ static void rga_cmd_set_trans_info(struct rga_ctx *ctx)
>
> if (RGA_COLOR_FMT_IS_RGB(ctx->in.fmt->hw_format) &&
> RGA_COLOR_FMT_IS_YUV(ctx->out.fmt->hw_format)) {
> - switch (ctx->out.colorspace) {
> + switch (ctx->out.pix.colorspace) {
> case V4L2_COLORSPACE_REC709:
> dst_info.data.csc_mode = RGA_SRC_CSC_MODE_BT709_R0;
> break;
> diff --git a/drivers/media/platform/rockchip/rga/rga.c b/drivers/media/platform/rockchip/rga/rga.c
> index c07207edffdb6..ca8d8a53dc251 100644
> --- a/drivers/media/platform/rockchip/rga/rga.c
> +++ b/drivers/media/platform/rockchip/rga/rga.c
> @@ -329,9 +329,6 @@ static struct rga_fmt *rga_fmt_find(u32 pixelformat)
> }
>
> static struct rga_frame def_frame = {
> - .width = DEFAULT_WIDTH,
> - .height = DEFAULT_HEIGHT,
> - .colorspace = V4L2_COLORSPACE_DEFAULT,
> .crop.left = 0,
> .crop.top = 0,
> .crop.width = DEFAULT_WIDTH,
> @@ -363,9 +360,9 @@ static int rga_open(struct file *file)
> ctx->out = def_frame;
>
> v4l2_fill_pixfmt_mp(&ctx->in.pix,
> - ctx->in.fmt->fourcc, ctx->out.width, ctx->out.height);
> + ctx->in.fmt->fourcc, DEFAULT_WIDTH, DEFAULT_HEIGHT);
> v4l2_fill_pixfmt_mp(&ctx->out.pix,
> - ctx->out.fmt->fourcc, ctx->out.width, ctx->out.height);
> + ctx->out.fmt->fourcc, DEFAULT_WIDTH, DEFAULT_HEIGHT);
>
> if (mutex_lock_interruptible(&rga->mutex)) {
> kfree(ctx);
> @@ -453,10 +450,8 @@ static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
> if (IS_ERR(frm))
> return PTR_ERR(frm);
>
> - v4l2_fill_pixfmt_mp(pix_fmt, frm->fmt->fourcc, frm->width, frm->height);
> -
> + *pix_fmt = frm->pix;
> pix_fmt->field = V4L2_FIELD_NONE;
> - pix_fmt->colorspace = frm->colorspace;
>
> return 0;
> }
> @@ -505,27 +500,24 @@ static int vidioc_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
> frm = rga_get_frame(ctx, f->type);
> if (IS_ERR(frm))
> return PTR_ERR(frm);
> - frm->width = pix_fmt->width;
> - frm->height = pix_fmt->height;
> frm->size = 0;
> for (i = 0; i < pix_fmt->num_planes; i++)
> frm->size += pix_fmt->plane_fmt[i].sizeimage;
> frm->fmt = rga_fmt_find(pix_fmt->pixelformat);
> frm->stride = pix_fmt->plane_fmt[0].bytesperline;
> - frm->colorspace = pix_fmt->colorspace;
>
> /* Reset crop settings */
> frm->crop.left = 0;
> frm->crop.top = 0;
> - frm->crop.width = frm->width;
> - frm->crop.height = frm->height;
> + frm->crop.width = pix_fmt->width;
> + frm->crop.height = pix_fmt->height;
>
> frm->pix = *pix_fmt;
>
> v4l2_dbg(debug, 1, &rga->v4l2_dev,
> "[%s] fmt - %p4cc %dx%d (stride %d, sizeimage %d)\n",
> V4L2_TYPE_IS_OUTPUT(f->type) ? "OUTPUT" : "CAPTURE",
> - &frm->fmt->fourcc, frm->width, frm->height,
> + &frm->fmt->fourcc, pix_fmt->width, pix_fmt->height,
> frm->stride, frm->size);
>
> for (i = 0; i < pix_fmt->num_planes; i++) {
> @@ -579,8 +571,8 @@ static int vidioc_g_selection(struct file *file, void *priv,
> } else {
> s->r.left = 0;
> s->r.top = 0;
> - s->r.width = f->width;
> - s->r.height = f->height;
> + s->r.width = f->pix.width;
> + s->r.height = f->pix.height;
> }
>
> return 0;
> @@ -629,8 +621,8 @@ static int vidioc_s_selection(struct file *file, void *priv,
> return -EINVAL;
> }
>
> - if (s->r.left + s->r.width > f->width ||
> - s->r.top + s->r.height > f->height ||
> + if (s->r.left + s->r.width > f->pix.width ||
> + s->r.top + s->r.height > f->pix.height ||
> s->r.width < MIN_WIDTH || s->r.height < MIN_HEIGHT) {
> v4l2_dbg(debug, 1, &rga->v4l2_dev, "unsupported crop value.\n");
> return -EINVAL;
> @@ -821,8 +813,8 @@ static int rga_probe(struct platform_device *pdev)
> goto rel_m2m;
> }
>
> - def_frame.stride = (def_frame.width * def_frame.fmt->depth) >> 3;
> - def_frame.size = def_frame.stride * def_frame.height;
> + def_frame.stride = (DEFAULT_WIDTH * def_frame.fmt->depth) >> 3;
> + def_frame.size = def_frame.stride * DEFAULT_HEIGHT;
>
> ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1);
> if (ret) {
> diff --git a/drivers/media/platform/rockchip/rga/rga.h b/drivers/media/platform/rockchip/rga/rga.h
> index 477cf5b62bbb2..c4a3905a48f0d 100644
> --- a/drivers/media/platform/rockchip/rga/rga.h
> +++ b/drivers/media/platform/rockchip/rga/rga.h
> @@ -24,11 +24,6 @@ struct rga_fmt {
> };
>
> struct rga_frame {
> - /* Original dimensions */
> - u32 width;
> - u32 height;
> - u32 colorspace;
> -
> /* Crop */
> struct v4l2_rect crop;
>
>
> --
> 2.54.0
>
>
--
Pengutronix e.K. | Michael Tretter |
Steuerwalder Str. 21 | https://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* Re: (subset) [PATCH v2 03/10] mfd: qcom_rpm: add msm8960 QDSS clock resource
From: Lee Jones @ 2026-05-21 13:04 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Lee Jones, Konrad Dybcio,
Antony Kurniawan Soemardi
Cc: Krzysztof Kozlowski, linux-arm-msm, linux-clk, devicetree,
linux-kernel, phone-devel, Rudraksha Gupta
In-Reply-To: <20260514-msm8960-wifi-v2-3-7cbae45dab5e@smankusors.com>
On Thu, 14 May 2026 21:08:32 +0700, Antony Kurniawan Soemardi wrote:
> The msm8960 RPM resource table is missing the QDSS clock entry (resource
> ID 209) that is present in the android-msm-mako-3.4 downstream kernel.
> Add it so that RPM clock initialization succeeds.
Applied, thanks!
[03/10] mfd: qcom_rpm: add msm8960 QDSS clock resource
commit: 72c793196d12cb27e192dee77c3ea64c755b7687
--
Lee Jones [李琼斯]
^ permalink raw reply
* Re: [PATCH v5 2/2] drm: panel: add support for the Renesas R63419 based dual-DSI video mode Display Panels
From: Neil Armstrong @ 2026-05-21 13:05 UTC (permalink / raw)
To: sashiko-reviews; +Cc: wsa+renesas, devicetree, robh, conor+dt
In-Reply-To: <20260521083821.998661F000E9@smtp.kernel.org>
On 5/21/26 10:38, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
> - [High] Uninitialized stack variable `dsi_ctx` causes undefined behavior in DSI initialization
> - [High] Incorrect MIPI DCS initialization sequence (Set Display On before Exit Sleep Mode)
> - [High] Race condition due to panel registration before DSI hardware is attached
> --
>
> commit 1aa27fde3d1fe4c1d08cfa9a63d3e7e28912831f
> Author: KancyJoe <kancy2333@outlook.com>
>
> drm: panel: add support for the Renesas R63419 based dual-DSI video mode Display Panels
>
> Implement support for the Renesas 63419 based dual-DSI video mode
> Display Panels found in the Ayaneo gaming handled devices.
>
>> diff --git a/drivers/gpu/drm/panel/panel-renesas-r63419.c b/drivers/gpu/drm/panel/panel-renesas-r63419.c
>> new file mode 100644
>> --- /dev/null
>> +++ b/drivers/gpu/drm/panel/panel-renesas-r63419.c
>
> [ ... ]
>
>> +static int renesas_r63419_on(struct renesas_r63419_panel *ctx)
>> +{
>> + struct mipi_dsi_multi_context dsi_ctx;
>
> [Severity: High]
> Does leaving dsi_ctx uninitialized here leave dsi_ctx.accum_err with
> random stack garbage?
>
> The helper dsi_link_switch() only assigns the dsi pointer, so subsequent
> multi-context calls like mipi_dsi_dcs_set_display_on_multi() might immediately
> return if accum_err is non-zero, silently skipping the initialization.
Good point
>
>> +
>> + dsi_link_switch(ctx, &dsi_ctx, 0);
>> + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
>> + dsi_link_switch(ctx, &dsi_ctx, 1);
>> + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
>> + mipi_dsi_msleep(&dsi_ctx, 150);
>> +
>> + dsi_link_switch(ctx, &dsi_ctx, 0);
>> + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
>> + dsi_link_switch(ctx, &dsi_ctx, 1);
>> + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
>> + mipi_dsi_msleep(&dsi_ctx, 50);
>
> [Severity: High]
> Is it intentional to send the Set Display On command before Exit Sleep Mode?
>
> According to the MIPI DCS specification, the display must exit sleep mode and
> stabilize before it can process the Set Display On command. Sending these
> commands in this order will likely result in the panel ignoring Set Display On,
> causing it to remain blank.
It's required by the panel spec
>> +
>> + return dsi_ctx.accum_err;
>> +}
>> +
>> +static int renesas_r63419_disable(struct drm_panel *panel)
>> +{
>> + struct renesas_r63419_panel *ctx = to_renesas_r63419_panel(panel);
>> + struct mipi_dsi_multi_context dsi_ctx;
>
> [Severity: High]
> Like in renesas_r63419_on(), can this uninitialized struct leave
> dsi_ctx.accum_err with stack garbage? This might cause the panel disable
> commands to be silently skipped.
Good point
>
>> +
>> + dsi_link_switch(ctx, &dsi_ctx, 0);
>> + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
>
> [ ... ]
>
>> +static int renesas_r63419_probe(struct mipi_dsi_device *dsi)
>> +{
>
> [ ... ]
>
>> + ret = devm_drm_panel_add(dev, &ctx->panel);
>> + if (ret)
>> + return dev_err_probe(dev, ret, "Failed to add panel\n");
>> +
>> + /* Configure and attach both DSI devices */
>> + for (i = 0; i < ARRAY_SIZE(ctx->dsi); i++) {
>> + ctx->dsi[i]->lanes = ctx->desc->lanes;
>> + ctx->dsi[i]->format = ctx->desc->format;
>> + ctx->dsi[i]->mode_flags = ctx->desc->mode_flags;
>> +
>> + ret = devm_mipi_dsi_attach(dev, ctx->dsi[i]);
>
> [Severity: High]
> Could registering the panel before the DSI hardware is attached cause a race
> condition?
>
> If a bridge driver concurrently finds the panel and triggers a display enable
> sequence, it might invoke the panel's callbacks before the DSI endpoints are
> actually attached, leading to DCS command timeouts or crashes.
>
> Additionally, because devm actions are executed in reverse order on cleanup,
> the DSI devices would be detached before the panel is unregistered, exposing
> an unattached panel during driver unload. Should devm_drm_panel_add() be
> called only after all hardware setup and DSI attachments are complete?
No
>
>> + if (ret < 0)
>> + return dev_err_probe(dev, ret,
>> + "Failed to attach DSI device %d\n", i);
>> + }
>> +
>> + return 0;
>> +}
>
^ permalink raw reply
* Re: (subset) [PATCH] dt-bindings: mfd: qcom,tcsr: Document the IPQ5210 TCSR block
From: Lee Jones @ 2026-05-21 13:06 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Kathiravan Thirumoorthy
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260511-ipq5210_tcsr_binding-v1-1-c8d20fed014f@oss.qualcomm.com>
On Mon, 11 May 2026 16:28:21 +0530, Kathiravan Thirumoorthy wrote:
> Document the TCSR block found on the Qualcomm's IPQ5210 SoC.
Applied, thanks!
[1/1] dt-bindings: mfd: qcom,tcsr: Document the IPQ5210 TCSR block
commit: 13e12359de48e3c9826cb97c2f85013596fb9f0c
--
Lee Jones [李琼斯]
^ permalink raw reply
* [PATCH 00/18] arm64: dts: qcom: Fix PCIe wake GPIO polarity
From: Krishna Chaitanya Chundru @ 2026-05-21 13:06 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio, Manivannan Sadhasivam
PCIe wake is active low signal as per the PCIe base spec, Several Qualcomm
platform devicetrees incorrectly describe wake-gpios as GPIO_ACTIVE_HIGH.
No Fixes tag is added as no functional issue has been observed.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
---
Krishna Chaitanya Chundru (18):
ARM: dts: qcom: sdx55: Fix PCIe wake GPIO polarity
arm64: dts: qcom: msm8996: Fix PCIe wake GPIO polarity
arm64: dts: qcom: sdm845: Fix PCIe wake GPIO polarity
arm64: dts: qcom: sc8180x: Fix PCIe wake GPIO polarity
arm64: dts: qcom: sm8150: Fix PCIe wake GPIO polarity
arm64: dts: qcom: sm8250: Fix PCIe wake GPIO polarity
arm64: dts: qcom: sm8350: Fix PCIe wake GPIO polarity
arm64: dts: qcom: sm8450: Fix PCIe wake GPIO polarity
arm64: dts: qcom: sm8550: Fix PCIe wake GPIO polarity
arm64: dts: qcom: sm8650: Fix PCIe wake GPIO polarity
arm64: dts: qcom: sm8750: Fix PCIe wake GPIO polarity
arm64: dts: qcom: kaanapali: Fix PCIe wake GPIO polarity
arm64: dts: qcom: sar2130p: Fix PCIe wake GPIO polarity
arm64: dts: qcom: monaco: Fix PCIe wake GPIO polarity
arm64: dts: qcom: lemans: Fix PCIe wake GPIO polarity
arm64: dts: qcom: sa8540p-ride: Fix PCIe wake GPIO polarity
arm64: dts: qcom: kodiak: Fix PCIe wake GPIO polarity
arm64: dts: qcom: talos: Fix PCIe wake GPIO polarity
arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts | 2 +-
arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 2 +-
arch/arm64/boot/dts/qcom/lemans-evk.dts | 4 ++--
arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/monaco-evk.dts | 4 ++--
arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi | 2 +-
arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 2 +-
arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts | 2 +-
arch/arm64/boot/dts/qcom/qcs615-ride.dts | 2 +-
arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 4 ++--
arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts | 4 ++--
arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts | 2 +-
arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 4 ++--
arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 4 ++--
arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts | 2 +-
arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 2 +-
arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 2 +-
arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 2 +-
arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 +++---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 4 ++--
arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ++--
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ++--
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 2 +-
arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 2 +-
arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 2 +-
arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts | 4 ++--
arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 4 ++--
arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ++--
arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 2 +-
arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 2 +-
arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 2 +-
34 files changed, 51 insertions(+), 51 deletions(-)
---
base-commit: e1914add2799225a87502051415fc5c32aeb02ae
change-id: 20260514-wake-1dfbdedcd173
Best regards,
--
Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
^ permalink raw reply
* [PATCH 01/18] ARM: dts: qcom: sdx55: Fix PCIe wake GPIO polarity
From: Krishna Chaitanya Chundru @ 2026-05-21 13:06 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio, Manivannan Sadhasivam
In-Reply-To: <20260521-wake-v1-0-d822567be258@oss.qualcomm.com>
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
---
arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts
index 082f7ed1a01f..302c88c47960 100644
--- a/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts
+++ b/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts
@@ -251,7 +251,7 @@ &pcie_phy {
&pcie_rc {
perst-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie_default>;
pinctrl-names = "default";
--
2.34.1
^ permalink raw reply related
* [PATCH 02/18] arm64: dts: qcom: msm8996: Fix PCIe wake GPIO polarity
From: Krishna Chaitanya Chundru @ 2026-05-21 13:06 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio, Manivannan Sadhasivam
In-Reply-To: <20260521-wake-v1-0-d822567be258@oss.qualcomm.com>
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
---
arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi | 2 +-
arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
index d55e4075040f..5b42c266557a 100644
--- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
@@ -192,7 +192,7 @@ &mmcc {
&pcie0 {
perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&wlan_en>;
vdda-supply = <&pm8994_l28>;
status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
index 77ad613590a3..2abcc733dad8 100644
--- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
@@ -280,7 +280,7 @@ &pcie0 {
vdda-supply = <&vreg_l28a_0p925>;
perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
};
&pcie_phy {
--
2.34.1
^ permalink raw reply related
* [PATCH 03/18] arm64: dts: qcom: sdm845: Fix PCIe wake GPIO polarity
From: Krishna Chaitanya Chundru @ 2026-05-21 13:06 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio, Manivannan Sadhasivam
In-Reply-To: <20260521-wake-v1-0-d822567be258@oss.qualcomm.com>
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
---
arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
index 02416812b6a7..24c0e97bb122 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
@@ -619,7 +619,7 @@ &mss_pil {
&pcie0 {
status = "okay";
perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 134 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 134 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&pcie0_3p3v_dual>;
--
2.34.1
^ permalink raw reply related
* [PATCH 04/18] arm64: dts: qcom: sc8180x: Fix PCIe wake GPIO polarity
From: Krishna Chaitanya Chundru @ 2026-05-21 13:06 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio, Manivannan Sadhasivam
In-Reply-To: <20260521-wake-v1-0-d822567be258@oss.qualcomm.com>
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
---
arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 2 +-
arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
index d86a31ddede2..44bf3db01d3a 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
+++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
@@ -458,7 +458,7 @@ &mdss_edp_out {
&pcie3 {
perst-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 180 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 180 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie3_default_state>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts
index aff398390eba..a4644ecca536 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts
+++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts
@@ -559,7 +559,7 @@ &mdss_edp_out {
&pcie1 {
perst-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 177 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 177 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie2_default_state>;
--
2.34.1
^ permalink raw reply related
* [PATCH 05/18] arm64: dts: qcom: sm8150: Fix PCIe wake GPIO polarity
From: Krishna Chaitanya Chundru @ 2026-05-21 13:06 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio, Manivannan Sadhasivam
In-Reply-To: <20260521-wake-v1-0-d822567be258@oss.qualcomm.com>
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 0e101096209a..8da494de4308 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -1905,7 +1905,7 @@ pcie0: pcie@1c00000 {
phy-names = "pciephy";
perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
- wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
--
2.34.1
^ permalink raw reply related
* [PATCH 06/18] arm64: dts: qcom: sm8250: Fix PCIe wake GPIO polarity
From: Krishna Chaitanya Chundru @ 2026-05-21 13:06 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio, Manivannan Sadhasivam
In-Reply-To: <20260521-wake-v1-0-d822567be258@oss.qualcomm.com>
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 7076720413ab..eca66d1c1c5b 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2202,7 +2202,7 @@ pcie0: pcie@1c00000 {
phy-names = "pciephy";
perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 81 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
@@ -2329,7 +2329,7 @@ pcie1: pcie@1c08000 {
phy-names = "pciephy";
perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 84 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
@@ -2456,7 +2456,7 @@ pcie2: pcie@1c10000 {
phy-names = "pciephy";
perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie2_default_state>;
--
2.34.1
^ permalink raw reply related
* [PATCH 07/18] arm64: dts: qcom: sm8350: Fix PCIe wake GPIO polarity
From: Krishna Chaitanya Chundru @ 2026-05-21 13:06 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio, Manivannan Sadhasivam
In-Reply-To: <20260521-wake-v1-0-d822567be258@oss.qualcomm.com>
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index 5f975d009465..0897ed1bbc6f 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -494,7 +494,7 @@ &pcie0 {
pinctrl-0 = <&pcie0_default_state>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
status = "okay";
};
@@ -508,7 +508,7 @@ &pcie0_phy {
&pcie1 {
perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
--
2.34.1
^ permalink raw reply related
* [PATCH 08/18] arm64: dts: qcom: sm8450: Fix PCIe wake GPIO polarity
From: Krishna Chaitanya Chundru @ 2026-05-21 13:06 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio, Manivannan Sadhasivam
In-Reply-To: <20260521-wake-v1-0-d822567be258@oss.qualcomm.com>
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 03bf30b53f28..acb36aaaf20b 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -2035,7 +2035,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
phy-names = "pciephy";
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
@@ -2200,7 +2200,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
phy-names = "pciephy";
perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
--
2.34.1
^ permalink raw reply related
* [PATCH 09/18] arm64: dts: qcom: sm8550: Fix PCIe wake GPIO polarity
From: Krishna Chaitanya Chundru @ 2026-05-21 13:06 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio, Manivannan Sadhasivam
In-Reply-To: <20260521-wake-v1-0-d822567be258@oss.qualcomm.com>
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
---
arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ++--
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ++--
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 2 +-
arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 2 +-
arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 2 +-
6 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
index e6ebb643203b..5eb4626c6129 100644
--- a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
@@ -336,7 +336,7 @@ &mdss_dsi0_phy {
&pcie0 {
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
@@ -349,7 +349,7 @@ &pcie0_phy {
&pcie1 {
perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_default_state>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
index ee13e6136a82..4709eb34521d 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
@@ -1003,7 +1003,7 @@ &mdss_dp0 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_default_state>;
@@ -1037,7 +1037,7 @@ &pcie0_phy {
};
&pcie1 {
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_default_state>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
index 5769be83cfbd..7703ebfc1b67 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
@@ -739,7 +739,7 @@ &mdss_dp0 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
@@ -756,7 +756,7 @@ &pcie0_phy {
};
&pcie1 {
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
index 2fb2e0be5e4c..5ce81ac3ab4c 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
@@ -903,7 +903,7 @@ &mdss_dp0 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_default_state>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts
index 81c02ee27fe9..cf4e4e9d9e26 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts
@@ -510,7 +510,7 @@ &i2c_master_hub_0 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
index 0e6ed6fce614..d23fe714bd27 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
@@ -584,7 +584,7 @@ cirrus,gpio-ctrl2 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_default_state>;
--
2.34.1
^ permalink raw reply related
* [PATCH 10/18] arm64: dts: qcom: sm8650: Fix PCIe wake GPIO polarity
From: Krishna Chaitanya Chundru @ 2026-05-21 13:06 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio, Manivannan Sadhasivam
In-Reply-To: <20260521-wake-v1-0-d822567be258@oss.qualcomm.com>
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
---
arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts | 4 ++--
arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 4 ++--
arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ++--
arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 2 +-
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts
index 0dc994f4e48d..2123312d88f6 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts
@@ -1074,7 +1074,7 @@ &mdss_dp0_out {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_default_state>;
@@ -1108,7 +1108,7 @@ &pcie0_phy {
};
&pcie1 {
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_default_state>;
diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
index eabc828c05b4..775ce9f2dba0 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
@@ -942,7 +942,7 @@ &mdss_dp0 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_default_state>;
@@ -976,7 +976,7 @@ &pcie0_phy {
};
&pcie1 {
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_default_state>;
diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
index dd6e33d2dc5d..8cc0d2cb3515 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
@@ -642,7 +642,7 @@ &mdss_dsi0_phy {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_default_state>;
@@ -659,7 +659,7 @@ &pcie0_phy {
};
&pcie1 {
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_default_state>;
diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
index a3982ae22929..c302996a7857 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
@@ -936,7 +936,7 @@ &mdss_dp0 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_default_state>;
--
2.34.1
^ permalink raw reply related
* [PATCH 11/18] arm64: dts: qcom: sm8750: Fix PCIe wake GPIO polarity
From: Krishna Chaitanya Chundru @ 2026-05-21 13:06 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio, Manivannan Sadhasivam
In-Reply-To: <20260521-wake-v1-0-d822567be258@oss.qualcomm.com>
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
---
arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
index 3837f6785320..2c2753683c69 100644
--- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
@@ -1119,7 +1119,7 @@ &pcie0_phy {
};
&pcieport0 {
- wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 104 GPIO_ACTIVE_LOW>;
reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
wifi@0 {
--
2.34.1
^ permalink raw reply related
* [PATCH 12/18] arm64: dts: qcom: kaanapali: Fix PCIe wake GPIO polarity
From: Krishna Chaitanya Chundru @ 2026-05-21 13:06 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio, Manivannan Sadhasivam
In-Reply-To: <20260521-wake-v1-0-d822567be258@oss.qualcomm.com>
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
---
arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
index 07247dc98b70..dc773da863c0 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
@@ -933,7 +933,7 @@ &pcie0_phy {
};
&pcie_port0 {
- wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 104 GPIO_ACTIVE_LOW>;
reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
wifi@0 {
--
2.34.1
^ permalink raw reply related
* [PATCH 13/18] arm64: dts: qcom: sar2130p: Fix PCIe wake GPIO polarity
From: Krishna Chaitanya Chundru @ 2026-05-21 13:06 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio, Manivannan Sadhasivam
In-Reply-To: <20260521-wake-v1-0-d822567be258@oss.qualcomm.com>
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
---
arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts b/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts
index 74778a5b19ba..71a09e76b359 100644
--- a/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts
+++ b/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts
@@ -358,7 +358,7 @@ &i2c10 {
&pcie0 {
perst-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
--
2.34.1
^ permalink raw reply related
* [PATCH 14/18] arm64: dts: qcom: monaco: Fix PCIe wake GPIO polarity
From: Krishna Chaitanya Chundru @ 2026-05-21 13:06 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio, Manivannan Sadhasivam
In-Reply-To: <20260521-wake-v1-0-d822567be258@oss.qualcomm.com>
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
---
arch/arm64/boot/dts/qcom/monaco-evk.dts | 4 ++--
arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts
index 9d17ef7d2caf..b30fc7ecdf32 100644
--- a/arch/arm64/boot/dts/qcom/monaco-evk.dts
+++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts
@@ -643,12 +643,12 @@ &pcie1_phy {
&pcieport0 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
};
&pcieport1 {
reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 21 GPIO_ACTIVE_LOW>;
};
&pmm8620au_0_gpios {
diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
index e9a8553a8d82..f9891fbcca90 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
@@ -615,7 +615,7 @@ &pcie0 {
&pcieport0 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
wifi@0 {
compatible = "pci17cb,1103";
@@ -651,7 +651,7 @@ &pcie1 {
&pcieport1 {
reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 21 GPIO_ACTIVE_LOW>;
};
&pcie1_phy {
--
2.34.1
^ permalink raw reply related
* [PATCH 15/18] arm64: dts: qcom: lemans: Fix PCIe wake GPIO polarity
From: Krishna Chaitanya Chundru @ 2026-05-21 13:06 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio, Manivannan Sadhasivam
In-Reply-To: <20260521-wake-v1-0-d822567be258@oss.qualcomm.com>
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
---
arch/arm64/boot/dts/qcom/lemans-evk.dts | 4 ++--
arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts
index c665db6a4595..fe9a2cd325d4 100644
--- a/arch/arm64/boot/dts/qcom/lemans-evk.dts
+++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts
@@ -703,7 +703,7 @@ &mdss0_dp1_phy {
&pcie0 {
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
@@ -720,7 +720,7 @@ &pcie0_phy {
&pcie1 {
perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_default_state>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi
index 31bd00546d55..3a6d73b485a9 100644
--- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi
@@ -854,7 +854,7 @@ wake-pins {
&pcie0 {
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
@@ -864,7 +864,7 @@ &pcie0 {
&pcie1 {
perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
--
2.34.1
^ permalink raw reply related
* [PATCH 16/18] arm64: dts: qcom: sa8540p-ride: Fix PCIe wake GPIO polarity
From: Krishna Chaitanya Chundru @ 2026-05-21 13:06 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio, Manivannan Sadhasivam
In-Reply-To: <20260521-wake-v1-0-d822567be258@oss.qualcomm.com>
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
---
arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
index 44177e9b64b5..702ae4cd3d0c 100644
--- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
@@ -367,7 +367,7 @@ &pcie2a {
<0x03000000 0x5 0x00000000 0x5 0x00000000 0x1 0x00000000>;
perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie2a_default>;
@@ -388,7 +388,7 @@ &pcie3a {
<0x03000000 0x6 0x00000000 0x6 0x00000000 0x2 0x00000000>;
perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie3a_default>;
--
2.34.1
^ permalink raw reply related
* [PATCH 17/18] arm64: dts: qcom: kodiak: Fix PCIe wake GPIO polarity
From: Krishna Chaitanya Chundru @ 2026-05-21 13:06 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio, Manivannan Sadhasivam
In-Reply-To: <20260521-wake-v1-0-d822567be258@oss.qualcomm.com>
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
---
arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts | 2 +-
arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 4 ++--
arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts | 4 ++--
arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts | 2 +-
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
index bf18c4852081..b1ad1d7c346a 100644
--- a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
+++ b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
@@ -546,7 +546,7 @@ &mdss_dp_out {
&pcie0 {
perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index bb5a42b038f1..3a9fbef89aff 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -523,7 +523,7 @@ &lpass_va_macro {
&pcie0 {
perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>;
pinctrl-names = "default";
@@ -540,7 +540,7 @@ &pcie0_phy {
&pcie1 {
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
index a5ad796cb65d..e0275430ef82 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
@@ -685,7 +685,7 @@ &mdss_dsi_phy {
&pcie0 {
perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_clkreq_n>,
<&pcie0_reset_n>,
@@ -704,7 +704,7 @@ &pcie0_phy {
&pcie1 {
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_clkreq_n>,
<&pcie1_reset_n>,
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts
index f47efca42d48..681a9ff5ef77 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts
@@ -813,7 +813,7 @@ &mdss_dsi_phy {
&pcie0 {
perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_clkreq_n>,
<&pcie0_reset_n>,
--
2.34.1
^ permalink raw reply related
* [PATCH 18/18] arm64: dts: qcom: talos: Fix PCIe wake GPIO polarity
From: Krishna Chaitanya Chundru @ 2026-05-21 13:06 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio, Manivannan Sadhasivam
In-Reply-To: <20260521-wake-v1-0-d822567be258@oss.qualcomm.com>
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
---
arch/arm64/boot/dts/qcom/qcs615-ride.dts | 2 +-
arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
index 7e05f873194a..d89548a2a3f1 100644
--- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
@@ -445,7 +445,7 @@ &mdss_dsi0_phy {
&pcie {
perst-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie_default_state>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi
index 294354c034c3..6eca3791e2b9 100644
--- a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi
@@ -359,7 +359,7 @@ &mdss_dsi0_phy {
&pcie {
perst-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie_default_state>;
pinctrl-names = "default";
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v15 2/3] of: Factor arguments passed to of_map_id() into a struct
From: Vijayanand Jitta @ 2026-05-21 13:10 UTC (permalink / raw)
To: sashiko-reviews; +Cc: Frank.Li, devicetree, imx, linux-pci, robh, conor+dt
In-Reply-To: <20260520085613.9052F1F000E9@smtp.kernel.org>
On 5/20/2026 2:26 PM, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
>
> Pre-existing issues:
> - [High] Unconditional dereference of `msi_node` in `of_check_msi_parent` when it can be NULL.
> --
>
> commit d17879206927f3ee695759bc3559fd04a6a551ab
> Author: Charan Teja Kalla <charan.kalla@oss.qualcomm.com>
> Subject: of: Factor arguments passed to of_map_id() into a struct
>
> This patch updates of_map_id() to take a struct of_phandle_args instead of
> passing the target device node and translated IDs separately. It explicitly
> separates the input filter node from the output arguments and transfers
> ownership of the matched node reference to the caller.
>
>> diff --git a/drivers/of/irq.c b/drivers/of/irq.c
>> index e37c1b3f87362..e63a43be6c4a3 100644
>> --- a/drivers/of/irq.c
>> +++ b/drivers/of/irq.c
>> @@ -796,14 +796,15 @@ static int of_check_msi_parent(struct device_node *dev_node, struct device_node
>> /**
>> * of_msi_xlate - map a MSI ID and find relevant MSI controller node
>> * @dev: device for which the mapping is to be done.
>> - * @msi_np: Pointer to target MSI controller node
>> + * @msi_np: Pointer to target MSI controller node, or NULL if the caller
>> + * only needs the translated ID without receiving the controller node.
>> + * If non-NULL and pointing to a non-NULL node, only entries targeting
>> + * that node will be matched. If non-NULL and pointing to NULL, it will
>> + * receive the first matching target node with a reference held.
>> * @id_in: Device ID.
>> *
>> * Walk up the device hierarchy looking for devices with a "msi-map"
>> * or "msi-parent" property. If found, apply the mapping to @id_in.
>> - * If @msi_np points to a non-NULL device node pointer, only entries targeting
>> - * that node will be matched; if it points to a NULL value, it will receive the
>> - * device node of the first matching target phandle, with a reference held.
>> *
>> * Returns: The mapped MSI id.
>> */
>> @@ -817,8 +818,21 @@ u32 of_msi_xlate(struct device *dev, struct device_node **msi_np, u32 id_in)
>> * "msi-map" or an "msi-parent" property.
>> */
>> for (parent_dev = dev; parent_dev; parent_dev = parent_dev->parent) {
>> - if (!of_map_msi_id(parent_dev->of_node, id_in, msi_np, &id_out))
>> + struct of_phandle_args msi_spec = {};
>> +
>> + if (!of_map_msi_id(parent_dev->of_node, id_in, msi_np, &msi_spec)) {
>> + if (msi_spec.np) {
>> + /* msi-map matched: use the translated ID and target node */
>> + if (msi_spec.args_count > 0)
>> + id_out = msi_spec.args[0];
>> + if (msi_np && !*msi_np)
>> + *msi_np = of_node_get(msi_spec.np);
>> + of_node_put(msi_spec.np);
>> + }
>> + /* msi-map present but no match → stop walking */
>> break;
>> + }
>> + /* -ENODEV: msi-map absent → check for msi-parent */
>> if (!of_check_msi_parent(parent_dev->of_node, msi_np))
>
> [Severity: High]
> This is a pre-existing issue, but does of_check_msi_parent() handle a NULL
> msi_np pointer correctly here?
>
> The documentation added above explicitly states that msi_np can be NULL if
> the caller only needs the translated ID without receiving the controller node.
> However, if msi-map is absent, execution falls through to
> of_check_msi_parent() with that potentially NULL pointer.
>
> Looking at drivers/of/irq.c:of_check_msi_parent(), if the msi-parent
> property is found, it evaluates:
>
> if ((*msi_node && *msi_node != msi_spec.np) || msi_spec.args_count != 0)
> ret = -EINVAL;
>
> if (!ret) {
> /* Return with a node reference held */
> *msi_node = msi_spec.np;
> return 0;
> }
>
> If msi_np is NULL, wouldn't dereferencing it via *msi_node trigger a NULL
> pointer dereference? Should this be fixed to safely handle a NULL pointer?
>
I see this is indeed a pre-existing latent bug .
fsl_mc_get_msi_id() in drivers/bus/fsl-mc/fsl-mc-msi.c already passes NULL for msi_np:
return (root_dprc_dev->parent->of_node ?
of_msi_xlate(dev, NULL, mc_dev->icid) :
iort_msi_map_id(dev, mc_dev->icid));
In practice it never triggered because FSL MC devices use msi-map, so of_map_msi_id()
succeeds and of_check_msi_parent() is never reached.
I'll will fix this in v16 by checking for msi_np aswell before calling
of_check_msi_parent() in of_msi_xlate().
if (msi_np && !of_check_msi_parent(parent_dev->of_node, msi_np))
break;
Thanks,
Vijay
>> break;
>> }
>
^ permalink raw reply
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