* Re: [PATCH v4 5/5] drm/panel: Add driver for Synaptics R63455 DSI panel
From: Neil Armstrong @ 2026-05-22 12:40 UTC (permalink / raw)
To: sashiko-reviews, Jun Nie; +Cc: robh, conor+dt, devicetree
In-Reply-To: <20260521163039.30D3A1F000E9@smtp.kernel.org>
On 5/21/26 18:30, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 10 potential issue(s) to consider:
> - [High] Incorrect order of error unwinding labels in `r63455_prepare` causes resource leaks and unbalanced regulator operations.
> - [High] The secondary DSI device registered during probe is never unregistered, causing a memory and device leak.
> - [High] Endianness extraction macros misuse host-endian functions, resulting in reversed byte order on Big Endian architectures.
> - [High] Unconditional access to `ctx->reset_gpios->desc[1]` leads to an out-of-bounds array read if only one reset GPIO is provided.
> - [High] Failure of `drm_dsc_setup_rc_params` is logged but ignored, leading to division by zero and uninitialized data usage.
> - [High] Backlight updates send DSI commands after the panel has entered sleep mode, risking hardware timeouts.
> - [High] Premature publication of backlight and panel interfaces leads to use-before-initialization races.
> - [High] Unprotected concurrent read-modify-write on `mode_flags` causes data races.
> - [High] Unaligned pointer cast causes unaligned memory access when packing DSC PPS payload.
> - [Low] Missing Kconfig dependencies for DRM DSC helpers causes build failures.
> --
>
> commit b5b6e09241eeff17cb03a31aac27b70f4e5ca911
> Author: Jun Nie <jun.nie@linaro.org>
> Subject: drm/panel: Add driver for Synaptics R63455 DSI panel
>
> This commit adds support for the DSI panels used in the virtual reality
> device. The device features two physical panels, each providing a MIPI DSI
> interface and a built-in LED backlight, and exposes a single logical panel
> to the DRM framework.
>
>> diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
>> --- a/drivers/gpu/drm/panel/Kconfig
>> +++ b/drivers/gpu/drm/panel/Kconfig
> [ ... ]
>> @@ -1185,6 +1185,15 @@ config DRM_PANEL_SYNAPTICS_TDDI
>> namesake, with varying resolutions and data lanes. They also have a
>> built-in LED backlight and a touch controller.
>>
>> +config DRM_PANEL_SYNAPTICS_R63455
>> + tristate "Synaptics R63455-based panels"
>> + depends on OF
>> + depends on DRM_MIPI_DSI
>> + depends on BACKLIGHT_CLASS_DEVICE
>> + help
>> + Say Y if you want to enable support for panels based on the
>> + Synaptics R63455 controller.
>
> [Severity: Low]
> Does this need to select DRM_DISPLAY_DSC_HELPER or DRM_DISPLAY_HELPER?
> The driver calls drm_dsc_set_const_params and other DSC helpers, which
> might cause link-time failures if the helper infrastructure is not built.
Yes
>
> [ ... ]
>> diff --git a/drivers/gpu/drm/panel/panel-synaptics-r63455.c b/drivers/gpu/drm/panel/panel-synaptics-r63455.c
>> --- /dev/null
>> +++ b/drivers/gpu/drm/panel/panel-synaptics-r63455.c
> [ ... ]
>> +#define r63455_dsi_write_buffer(ctx, dsi_ctx, d) \
>> + do { \
>> + dsi_ctx.dsi = ctx->dsi[0]; \
>> + mipi_dsi_dcs_write_buffer_multi(&dsi_ctx, d, ARRAY_SIZE(d)); \
>> + dsi_ctx.dsi = ctx->dsi[1]; \
>> + mipi_dsi_dcs_write_buffer_multi(&dsi_ctx, d, ARRAY_SIZE(d)); \
>> + } while (0)
>> +
>> +#define LE16_BYTE0(val) (le16_to_cpu(val) & 0xff)
>> +#define LE16_BYTE1(val) ((le16_to_cpu(val) >> 8) & 0xff)
>
> [Severity: High]
> Are these macros extracting the correct bytes on big endian architectures?
> Using le16_to_cpu() on a native integer constant swaps the bytes on big
> endian systems. Applying the bitwise operations afterward will extract the
> most significant byte instead of the least significant byte. Would standard
> bitwise shifts be safer here?
No we extract the low byte and high byte of the 16bit number converted to the cpu endianness,
so it's the right code here.
>
> [ ... ]
>> +static int r63455_dsi_populate_dsc_params(struct r63455_ctx *ctx)
>> +{
>> + int ret;
>> + struct drm_dsc_config *dsc = &ctx->dsc_cfg;
> [ ... ]
>> + /* handle only bpp = bpc = 8, pre-SCR panels */
>> + ret = drm_dsc_setup_rc_params(dsc, DRM_DSC_1_1_PRE_SCR);
>> + if (ret < 0)
>> + DRM_DEV_ERROR(ctx->dev, "failed to setup dsc params\n");
>> +
>> + dsc->initial_scale_value = drm_dsc_initial_scale_value(dsc);
>
> [Severity: High]
> Should this return early if drm_dsc_setup_rc_params() fails? If execution
> continues, the driver will use uninitialized DSC configuration parameters.
> Because values like initial_xmit_delay might remain zero, it can result in
> a division by zero when calculating final_scale inside
> drm_dsc_compute_rc_parameters().
Good catch
>
>> + dsc->line_buf_depth = dsc->bits_per_component + 1;
>> +
>> + return drm_dsc_compute_rc_parameters(dsc);
>> +}
> [ ... ]
>> +static int r63455_panel_on_sharp_ls026b3sa06(struct drm_panel *panel)
>> +{
>> + struct r63455_ctx *ctx = panel_to_ctx(panel);
>> + struct mipi_dsi_multi_context dsi_ctx = { 0 };
>> +
>> + u8 pps_cmd[1 + sizeof(struct drm_dsc_picture_parameter_set)];
>> +
>> + drm_dsc_pps_payload_pack((void *)&pps_cmd[1], &ctx->dsc_cfg);
>
> [Severity: High]
> Can this unaligned pointer cause alignment faults? Passing &pps_cmd[1] forces
> the base address to be odd. Since drm_dsc_pps_payload_pack() treats the
> pointer as a struct and performs 16-bit stores to its fields, this might
> trigger alignment panics on architectures that strictly enforce memory
> alignment.
Yep, best would be to work on a struct drm_dsc_picture_parameter_set on the stack
and copy it to pps_cmd[1].
>
> [ ... ]
>> +static int r63455_set_brightness(struct r63455_ctx *ctx, u16 brightness,
>> + u16 pulse_offset_rows)
>> +{
>> + struct mipi_dsi_multi_context dsi_ctx = { 0 };
>> + u16 gpo1_tew1;
>> +
>> + gpo1_tew1 = brightness > BRIGHTNESS_MAX_120 ?
>> + BRIGHTNESS_MAX_120 : brightness;
>> +
>> + ctx->dsi[0]->mode_flags &= ~MIPI_DSI_MODE_LPM;
>
> [Severity: High]
> Can this read-modify-write of mode_flags race with the similar modifications
> in r63455_enable() and r63455_disable()? Because set_brightness() is called
> from sysfs context and enable/disable from DRM commit context, concurrent
> access might corrupt mode_flags and drop critical settings like
> MIPI_DSI_MODE_VIDEO.
It's very improbable this happens, panel cmds and backlight are called at very different times.
>
>> + ctx->dsi[1]->mode_flags &= ~MIPI_DSI_MODE_LPM;
> [ ... ]
>> +static int r63455_disable(struct drm_panel *panel)
>> +{
>> + struct r63455_ctx *ctx = panel_to_ctx(panel);
>> + struct mipi_dsi_multi_context dsi_ctx = { 0 };
>> +
>> + ctx->dsi[0]->mode_flags &= ~MIPI_DSI_MODE_LPM;
>> + ctx->dsi[1]->mode_flags &= ~MIPI_DSI_MODE_LPM;
>> +
>> + r63455_dsi_write_seq(ctx, dsi_ctx, MIPI_DCS_SET_DISPLAY_OFF);
>> + r63455_dsi_write_seq(ctx, dsi_ctx, MIPI_DCS_SET_TEAR_OFF);
>> + r63455_dsi_write_seq(ctx, dsi_ctx, MIPI_DCS_ENTER_SLEEP_MODE);
>> +
>> + mipi_dsi_msleep(&dsi_ctx, 200);
>> +
>> + if (dsi_ctx.accum_err)
>> + return dsi_ctx.accum_err;
>> +
>> + return backlight_disable(ctx->backlight);
>
> [Severity: High]
> Is it safe to disable the backlight here? The backlight_disable() function
> calls r63455_set_brightness(), which will send DSI configuration commands to
> the panel. Doing so after sending MIPI_DCS_ENTER_SLEEP_MODE violates the DSI
> hardware contracts and might cause bus timeouts or hardware crashes.
It's required by the hw spec.
>
>> +}
>> +
>> +static int r63455_unprepare(struct drm_panel *panel)
>> +{
>> + struct r63455_ctx *ctx = panel_to_ctx(panel);
>> + int ret;
>> +
>> + gpiod_set_value(ctx->reset_gpios->desc[0], 0);
>> + gpiod_set_value(ctx->reset_gpios->desc[1], 0);
>
> [Severity: High]
> What happens if the device tree only provides a single reset GPIO? If ndescs
> is 1, accessing desc[1] will read past the end of the flexible array,
> resulting in a garbage pointer dereference.
Won't happen, both are mandatory
>
> [ ... ]
>> +static int r63455_prepare(struct drm_panel *panel)
>> +{
>> + struct r63455_ctx *ctx = panel_to_ctx(panel);
>> + int ret;
> [ ... ]
>> + msleep(20);
>> + gpiod_set_value(ctx->reset_gpios->desc[0], 1);
>> + gpiod_set_value(ctx->reset_gpios->desc[1], 1);
>> +
>> + return 0;
>> +
>> +bl_off:
>> + regulator_bulk_disable(ARRAY_SIZE(ctx->reg_bl), ctx->reg_bl);
>> +vdda_off:
>> + regulator_bulk_disable(ARRAY_SIZE(ctx->reg_vdda), ctx->reg_vdda);
>> +bias_off:
>> + regulator_bulk_disable(ARRAY_SIZE(ctx->reg_lcd_bias_pos),
>> + ctx->reg_lcd_bias_pos);
>> + return ret;
>
> [Severity: High]
> Are these error labels in the correct order? They appear to fall through
> sequentially rather than unwinding in reverse. If reg_vdda fails to enable,
> the jump to bl_off will disable the backlight, but then incorrectly fall
> through to vdda_off and bias_off. This causes regulators that were never
> enabled to be disabled, and completely skips disabling regulators that were
> actually enabled.
Jun, please check the order
>
>> +}
> [ ... ]
>> +static int r63455_probe(struct mipi_dsi_device *dsi)
>> +{
>> + struct device *dev = &dsi->dev;
>> + struct r63455_ctx *ctx;
>> + struct mipi_dsi_device *dsi1_device;
> [ ... ]
>> + dsi1_host = of_find_mipi_dsi_host_by_node(dsi1);
>> + of_node_put(dsi1);
>> + if (!dsi1_host) {
>> + DRM_DEV_ERROR(dev, "failed to find secondary dsi host\n");
>> + return -EPROBE_DEFER;
>> + }
>> +
>> + dsi1_device = mipi_dsi_device_register_full(dsi1_host, &info);
>
> [Severity: High]
> Does this dynamically allocated dsi1_device need to be unregistered? There
> is no call to mipi_dsi_device_unregister() in the error paths below or in a
> remove callback for the driver, which could cause a permanent device and
> memory leak when the module is unloaded or fails to probe.
Good catchm, should be devm_mipi_dsi_device_register_full()
>
>> + if (IS_ERR(dsi1_device)) {
>> + DRM_DEV_ERROR(dev, "failed to create dsi device\n");
>> + return PTR_ERR(dsi1_device);
>> + }
> [ ... ]
>> + ret = r63455_panel_add(ctx);
>> + if (ret) {
>> + DRM_DEV_ERROR(dev, "failed to add panel %d\n", ret);
>> + return ret;
>> + }
>> +
>> + for (i = 0; i < 2; i++) {
>> + dsi_dev = ctx->dsi[i];
>> + dsi_dev->lanes = 3;
>> + dsi_dev->format = MIPI_DSI_FMT_RGB888;
>> + dsi_dev->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM |
>> + MIPI_DSI_CLOCK_NON_CONTINUOUS;
>> + ret = devm_mipi_dsi_attach(dev, dsi_dev);
>
> [Severity: High]
> Does calling r63455_panel_add() before devm_mipi_dsi_attach() expose the
> backlight sysfs interface too early? If userspace writes to the brightness
> node before the DSI lanes and formats are configured and attached, it could
> trigger a DSI transfer on an unattached device and crash the system.
No
>
>> + if (ret < 0) {
>> + DRM_DEV_ERROR(dev, "dsi attach failed i = %d\n", i);
>> + return ret;
>> + }
>> + }
>> +
>> + return 0;
>> +}
>
^ permalink raw reply
* Re: [PATCH 2/2] iio: adc: ad4080: add support for AD4884
From: Jonathan Cameron @ 2026-05-22 12:33 UTC (permalink / raw)
To: Antoniu Miclaus
Cc: Nuno Sá, Michael Hennerich, David Lechner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux, linux-iio, devicetree,
linux-kernel
In-Reply-To: <20260522115337.18188-3-antoniu.miclaus@analog.com>
On Fri, 22 May 2026 14:53:37 +0300
Antoniu Miclaus <antoniu.miclaus@analog.com> wrote:
> Add support for the AD4884, a dual-channel, 16-bit, 40 MSPS SAR ADC.
>
> The AD4884 is the dual-channel variant of the AD4084, sharing the same
> register map and SPI interface as the rest of the AD4080 family. Like
> the AD4880, it uses two independent ADC channels, each with its own SPI
> configuration interface.
>
> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
LGTM.
^ permalink raw reply
* Re: [PATCH 4/5] arm64: dts: freescale: imx95-15x15-frdm: remove common rmem regions
From: sashiko-bot @ 2026-05-22 12:32 UTC (permalink / raw)
To: Laurentiu Mihalcea; +Cc: devicetree, conor+dt, Frank.Li, robh, imx
In-Reply-To: <20260522111849.783-5-laurentiumihalcea111@gmail.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Incomplete cleanup leaving orphaned remoteproc memory regions (`vdev1vring0` and `vdev1vring1`), causing a code and commit message mismatch.
--
commit c3d174a8ecea96cc404dfedae6ae093499f849dd
Author: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
arm64: dts: freescale: imx95-15x15-frdm: remove common rmem regions
This commit removes reserved memory regions used for remoteproc on the
MX95-15x15-FRDM platform, noting they are unused and can be included in an
RPMSG-specific DTS instead.
> diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
> index 0f43e3be70589..f9b0e266754d6 100644
> --- a/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
> +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
> @@ -188,16 +188,6 @@ linux_cma: linux,cma {
> linux,cma-default;
> };
>
> - vdev0vring0: memory@88000000 {
> - reg = <0 0x88000000 0 0x8000>;
> - no-map;
> - };
> -
> - vdev0vring1: memory@88008000 {
> - reg = <0 0x88008000 0 0x8000>;
> - no-map;
> - };
> -
> vdev1vring0: memory@88010000 {
> reg = <0 0x88010000 0 0x8000>;
> no-map;
> @@ -208,17 +198,6 @@ vdev1vring1: memory@88018000 {
> no-map;
> };
[Severity: Medium]
The commit message mentions removing the reserved memory regions used for
remoteproc. Should vdev1vring0 and vdev1vring1 also be removed here?
Since they retain the no-map property, do these remaining nodes unnecessarily
carve out memory without being referenced anymore?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260522111849.783-1-laurentiumihalcea111@gmail.com?part=4
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: iio: adc: ad4080: add AD4884 support
From: Jonathan Cameron @ 2026-05-22 12:32 UTC (permalink / raw)
To: Antoniu Miclaus
Cc: Nuno Sá, Michael Hennerich, David Lechner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux, linux-iio, devicetree,
linux-kernel
In-Reply-To: <20260522115337.18188-2-antoniu.miclaus@analog.com>
On Fri, 22 May 2026 14:53:36 +0300
Antoniu Miclaus <antoniu.miclaus@analog.com> wrote:
> Add AD4884 compatible string to the AD4080 devicetree binding.
>
> The AD4884 is a dual-channel, 16-bit, 40 MSPS SAR ADC, sharing the same
> register map and interface as the AD4080 family. Like the AD4880, it
> requires two SPI chip selects and two io-backends for its independent
> ADC channels.
I don't see anything in here to say how it is different in a fashion
that doesn't allow a fall back compatible to the ad4880. Probably just
needs a statement about the resolution being different.
>
> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
> ---
> Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml
> index 9c6a56c7c8ef..4a3f7d3e05c3 100644
> --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml
> +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml
> @@ -39,6 +39,7 @@ properties:
> - adi,ad4087
> - adi,ad4088
> - adi,ad4880
> + - adi,ad4884
>
> reg:
> minItems: 1
> @@ -99,7 +100,9 @@ allOf:
> properties:
> compatible:
> contains:
> - const: adi,ad4880
> + enum:
> + - adi,ad4880
> + - adi,ad4884
> then:
> properties:
> reg:
^ permalink raw reply
* [PATCH v7 9/9] clk: eyeq: Add EyeQ7H compatibles
From: Benoît Monin @ 2026-05-22 12:31 UTC (permalink / raw)
To: Vladimir Kondratiev, Gregory CLEMENT, Théo Lebrun,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd, Brian Masney, Philipp Zabel
Cc: Benoît Monin, Thomas Petazzoni, linux-mips, devicetree,
linux-kernel, linux-clk
In-Reply-To: <20260522-clk-eyeq7-v7-0-14ad6c2c5213@bootlin.com>
Add the entries for the 14 Other Logic Blocks found in the EyeQ7H SoC. The
clock tree is more complex than the previous generation of SoC, as some
OLB depend on the clock output of other OLB instead of all referring to
the main oscillator.
The OLB south, east and west generate those reference clocks used by other
blocks. They also use the reference clock internally. The reference clock
provided by OLB south is named "ref_100p0", "ref_106p6_e" by OLB east and
"ref_106p6_w" by OLB west.
For the OLB with a single parent clock, We use the same logic as the
blocks found in previous SoC and refer to it with the name "ref".
The OLB with two parent clocks use the reference clock provided by the
OLB south, east and west as "ref_100p0" and "ref_106p6" and the main
oscillator as "ref".
The three dividers found in the DDR OLBs are configured by the same
register and are declared read-only.
The reset controllers found is 11 of the OLB are declared as auxiliary
device attached to the clock device.
Also add the functions to parse the registers of the two types of PLL
in the EyeQ7H OLB.
The JFRACR PLL have similar properties as the FRACG PLL, but its
configuration is spread on three registers instead of two. It also have
a wider fractional part for the multiplier on 24 bits instead of 20.
The AINTP PLL does not support spread spectrum and uses a single
register. It is registered as a fixed factor without the flag
CLK_FIXED_FACTOR_FIXED_ACCURACY and thus inherit the accuracy of its
parent clock.
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
drivers/clk/clk-eyeq.c | 513 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 512 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index 5200d5f0ff06..d55be678c597 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * PLL clock driver for the Mobileye EyeQ5, EyeQ6L and EyeQ6H platforms.
+ * PLL clock driver for the Mobileye EyeQ platforms.
*
* This controller handles:
* - Read-only PLLs, all derived from the same main crystal clock.
@@ -46,6 +46,7 @@
#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
#include <dt-bindings/clock/mobileye,eyeq6lplus-clk.h>
+#include <dt-bindings/clock/mobileye,eyeq7h-clk.h>
/* In frac mode, it enables fractional noise canceling DAC. Else, no function. */
#define FRACG_PCSR0_DAC_EN BIT(0)
@@ -71,6 +72,41 @@
#define FRACG_PCSR1_DOWN_SPREAD BIT(11)
#define FRACG_PCSR1_FRAC_IN GENMASK(31, 12)
+#define JFRACR_PCSR0_BYPASS BIT(0)
+#define JFRACR_PCSR0_PLL_EN BIT(1)
+#define JFRACR_PCSR0_FOUTVCO_EN BIT(2)
+#define JFRACR_PCSR0_FOUTPOSTDIV_EN BIT(3)
+#define JFRACR_PCSR0_POST_DIV1 GENMASK(6, 4)
+#define JFRACR_PCSR0_POST_DIV2 GENMASK(9, 7)
+#define JFRACR_PCSR0_REF_DIV GENMASK(15, 10)
+#define JFRACR_PCSR0_FB_DIV GENMASK(27, 16)
+#define JFRACR_PCSR0_VCO_SEL GENMASK(29, 28)
+#define JFRACR_PCSR0_PLL_LOCKED GENMASK(31, 30)
+
+#define JFRACR_PCSR1_FRAC_IN GENMASK(23, 0)
+#define JFRACR_PCSR1_FOUT4PHASE_EN BIT(24)
+#define JFRACR_PCSR1_DAC_EN BIT(25)
+#define JFRACR_PCSR1_DSM_EN BIT(26)
+/* Bits 31..27 are reserved */
+#define JFRACR_PCSR2_RESET BIT(0)
+#define JFRACR_PCSR2_DIS_SSCG BIT(1)
+#define JFRACR_PCSR2_DOWN_SPREAD BIT(2)
+#define JFRACR_PCSR2_SSGC_DIV GENMASK(7, 4)
+#define JFRACR_PCSR2_SPREAD GENMASK(12, 8)
+/* Bits 31..13 are reserved */
+
+#define AINTP_PCSR_BYPASS BIT(0)
+#define AINTP_PCSR_PLL_EN BIT(1)
+#define AINTP_PCSR_FOUTVCO_EN BIT(2)
+#define AINTP_PCSR_FOUTPOSTDIV_EN BIT(3)
+#define AINTP_PCSR_POST_DIV1 GENMASK(6, 4)
+#define AINTP_PCSR_POST_DIV2 GENMASK(9, 7)
+#define AINTP_PCSR_REF_DIV GENMASK(15, 10)
+#define AINTP_PCSR_FB_DIV GENMASK(27, 16)
+#define AINTP_PCSR_VCO_SEL GENMASK(29, 28)
+/* bit 30 is reserved */
+#define AINTP_PCSR_PLL_LOCKED BIT(31)
+
/*
* Special index values to lookup a parent clock by its name
* from the device tree or by its globally unique name.
@@ -160,6 +196,29 @@ static void eqc_pll_downshift_factors(unsigned long *mult, unsigned long *div)
*div >>= shift;
}
+static int eqc_pll_parse_aintp(void __iomem *base, unsigned long *mult, unsigned long *div)
+{
+ u32 r0;
+
+ r0 = readl(base);
+ if (r0 & AINTP_PCSR_BYPASS) {
+ *mult = 1;
+ *div = 1;
+ return 0;
+ }
+
+ if (!(r0 & AINTP_PCSR_PLL_LOCKED))
+ return -EINVAL;
+
+ *mult = FIELD_GET(AINTP_PCSR_FB_DIV, r0);
+ *div = FIELD_GET(AINTP_PCSR_REF_DIV, r0);
+
+ if (!*mult || !*div)
+ return -EINVAL;
+
+ return 0;
+}
+
static int eqc_pll_parse_fracg(void __iomem *base, unsigned long *mult,
unsigned long *div, unsigned long *acc)
{
@@ -229,6 +288,60 @@ static int eqc_pll_parse_fracg(void __iomem *base, unsigned long *mult,
return 0;
}
+static int eqc_pll_parse_jfracr(void __iomem *base, unsigned long *mult,
+ unsigned long *div, unsigned long *acc)
+{
+ unsigned long spread;
+ u32 r0, r1, r2;
+ u64 val;
+
+ val = readq(base);
+ r0 = val;
+ r1 = val >> 32;
+ r2 = readl(base + 8);
+
+ if (r0 & JFRACR_PCSR0_BYPASS) {
+ *mult = 1;
+ *div = 1;
+ *acc = 0;
+ return 0;
+ }
+
+ /* Consider the PLL locked if either the phase or the frequency is locked */
+ if (!(r0 & JFRACR_PCSR0_PLL_LOCKED))
+ return -EINVAL;
+
+ *mult = FIELD_GET(JFRACR_PCSR0_FB_DIV, r0);
+ *div = FIELD_GET(JFRACR_PCSR0_REF_DIV, r0);
+
+ /* fractional part on 24 bits */
+ if (r1 & JFRACR_PCSR1_DSM_EN) {
+ *div *= (1ULL << 24);
+ *mult = *mult * (1ULL << 24) + FIELD_GET(JFRACR_PCSR1_FRAC_IN, r1);
+ }
+
+ if (!*mult || !*div)
+ return -EINVAL;
+
+ if (r2 & (JFRACR_PCSR2_RESET | JFRACR_PCSR2_DIS_SSCG)) {
+ *acc = 0;
+ } else {
+ /* spread spectrum is identical to FRACG PLL */
+ spread = FIELD_GET(JFRACR_PCSR2_SPREAD, r2);
+ *acc = DIV_ROUND_CLOSEST(spread * 1000000000, 1024 * 2);
+
+ if (r2 & JFRACR_PCSR2_DOWN_SPREAD) {
+ *mult *= 2048 - spread;
+ *div *= 2048;
+ }
+ }
+
+ /* make sure mult and div fit in 32 bits */
+ eqc_pll_downshift_factors(mult, div);
+
+ return 0;
+}
+
static void eqc_auxdev_create_optional(struct device *dev, void __iomem *base,
const char *name)
{
@@ -313,6 +426,33 @@ static int eqc_probe_fixed_factor(struct device *dev, struct device_node *np,
return 0;
}
+static int eqc_probe_pll_aintp(struct device *dev, struct device_node *np,
+ const struct eqc_clock *clk, void __iomem *base,
+ struct clk_hw_onecell_data *cells)
+{
+ struct clk_parent_data parent_data = { };
+ unsigned long mult, div;
+ struct clk_hw *hw;
+ int ret;
+
+ ret = eqc_pll_parse_aintp(base + clk->pll.reg, &mult, &div);
+ if (ret)
+ return ret;
+
+ ret = eqc_fill_parent_data(clk, cells, &parent_data);
+ if (ret)
+ return ret;
+
+ hw = clk_hw_register_fixed_factor_pdata(dev, np, clk->name, &parent_data,
+ 0, mult, div, 0, 0);
+
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
+ cells->hws[clk->index] = hw;
+ return 0;
+}
+
static int eqc_probe_pll_fracg(struct device *dev, struct device_node *np,
const struct eqc_clock *clk, void __iomem *base,
struct clk_hw_onecell_data *cells)
@@ -339,6 +479,32 @@ static int eqc_probe_pll_fracg(struct device *dev, struct device_node *np,
return 0;
}
+static int eqc_probe_pll_jfracr(struct device *dev, struct device_node *np,
+ const struct eqc_clock *clk, void __iomem *base,
+ struct clk_hw_onecell_data *cells)
+{
+ struct clk_parent_data parent_data = { };
+ unsigned long mult, div, acc;
+ struct clk_hw *hw;
+ int ret;
+
+ ret = eqc_pll_parse_jfracr(base + clk->pll.reg, &mult, &div, &acc);
+ if (ret)
+ return ret;
+
+ ret = eqc_fill_parent_data(clk, cells, &parent_data);
+ if (ret)
+ return ret;
+
+ hw = clk_hw_register_fixed_factor_pdata(dev, np, clk->name, &parent_data, 0, mult,
+ div, acc, CLK_FIXED_FACTOR_FIXED_ACCURACY);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
+ cells->hws[clk->index] = hw;
+ return 0;
+}
+
static int eqc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -411,6 +577,22 @@ static int eqc_probe(struct platform_device *pdev)
.div.table = NULL, \
}
+#define DIV_TABLE_RO(_index, _parent_idx, _name, _parent_name, \
+ _reg, _shift, _width, _table) \
+ { \
+ .index = _index, \
+ .parent_idx = _parent_idx, \
+ .name = _name, \
+ .parent_name = _parent_name, \
+ .probe = eqc_probe_divider, \
+ .unregister = clk_hw_unregister_divider, \
+ .div.reg = _reg, \
+ .div.shift = _shift, \
+ .div.width = _width, \
+ .div.flags = CLK_DIVIDER_READ_ONLY, \
+ .div.table = _table, \
+ }
+
#define FF(_index, _parent_idx, _name, _parent_name, _mult, _div) \
{ \
.index = _index, \
@@ -423,6 +605,17 @@ static int eqc_probe(struct platform_device *pdev)
.ff.div = _div, \
}
+#define PLL_AINTP(_index, _parent_idx, _name, _parent_name, _reg) \
+ { \
+ .index = _index, \
+ .parent_idx = _parent_idx, \
+ .name = _name, \
+ .parent_name = _parent_name, \
+ .probe = eqc_probe_pll_aintp, \
+ .unregister = clk_hw_unregister_fixed_factor, \
+ .pll.reg = _reg, \
+ }
+
#define PLL_FRACG(_index, _parent_idx, _name, _parent_name, _reg) \
{ \
.index = _index, \
@@ -434,6 +627,17 @@ static int eqc_probe(struct platform_device *pdev)
.pll.reg = _reg, \
}
+#define PLL_JFRACR(_index, _parent_idx, _name, _parent_name, _reg) \
+ { \
+ .index = _index, \
+ .parent_idx = _parent_idx, \
+ .name = _name, \
+ .parent_name = _parent_name, \
+ .probe = eqc_probe_pll_jfracr, \
+ .unregister = clk_hw_unregister_fixed_factor, \
+ .pll.reg = _reg, \
+ }
+
enum {
/*
* EQ5C_PLL_CPU children.
@@ -675,6 +879,297 @@ static const struct eqc_match_data eqc_eyeq6h_acc_match_data = {
.reset_auxdev_name = "reset_acc",
};
+static const struct eqc_clock eqc_eyeq7h_acc0_clks[] = {
+ PLL_AINTP(EQ7HC_ACC_PLL_VMP, PARENT_BY_FWNAME, "pll-acc0-vmp", "ref_100p0", 0x400),
+ PLL_AINTP(EQ7HC_ACC_PLL_MPC, PARENT_BY_FWNAME, "pll-acc0-mpc", "ref_100p0", 0x404),
+ PLL_AINTP(EQ7HC_ACC_PLL_PMA, PARENT_BY_FWNAME, "pll-acc0-pma", "ref_100p0", 0x408),
+ PLL_AINTP(EQ7HC_ACC_PLL_NOC, PARENT_BY_FWNAME, "pll-acc0-noc-acc", "ref_106p6", 0x40c),
+
+ FF(EQ7HC_ACC_DIV_PMA, EQ7HC_ACC_PLL_PMA, "acc0_pma", NULL, 1, 2),
+ FF(EQ7HC_ACC_DIV_NCORE, EQ7HC_ACC_PLL_NOC, "acc0_ncore", NULL, 1, 2),
+ FF(EQ7HC_ACC_DIV_CFG, EQ7HC_ACC_PLL_NOC, "acc0_cfg", NULL, 1, 8),
+};
+
+static const struct eqc_match_data eqc_eyeq7h_acc0_match_data = {
+ .clk_count = ARRAY_SIZE(eqc_eyeq7h_acc0_clks),
+ .clks = eqc_eyeq7h_acc0_clks,
+
+ .reset_auxdev_name = "reset_acc0",
+};
+
+static const struct eqc_clock eqc_eyeq7h_acc1_clks[] = {
+ PLL_AINTP(EQ7HC_ACC_PLL_VMP, PARENT_BY_FWNAME, "pll-acc1-vmp", "ref_100p0", 0x400),
+ PLL_AINTP(EQ7HC_ACC_PLL_MPC, PARENT_BY_FWNAME, "pll-acc1-mpc", "ref_100p0", 0x404),
+ PLL_AINTP(EQ7HC_ACC_PLL_PMA, PARENT_BY_FWNAME, "pll-acc1-pma", "ref_100p0", 0x408),
+ PLL_AINTP(EQ7HC_ACC_PLL_NOC, PARENT_BY_FWNAME, "pll-acc1-noc-acc", "ref_106p6", 0x40c),
+};
+
+static const struct eqc_match_data eqc_eyeq7h_acc1_match_data = {
+ .clk_count = ARRAY_SIZE(eqc_eyeq7h_acc1_clks),
+ .clks = eqc_eyeq7h_acc1_clks,
+
+ .reset_auxdev_name = "reset_acc1",
+};
+
+static const struct clk_div_table eqc_eyeq7h_ddr_apb_div_table[] = {
+ { .val = 0, .div = 8 },
+ { .val = 1, .div = 128 },
+ { .val = 0, .div = 0 },
+};
+
+static const struct clk_div_table eqc_eyeq7h_ddr_ref_div_table[] = {
+ { .val = 0, .div = 2 },
+ { .val = 1, .div = 8 },
+ { .val = 0, .div = 0 },
+};
+
+static const struct clk_div_table eqc_eyeq7h_ddr_dfi_div_table[] = {
+ { .val = 0, .div = 2 },
+ { .val = 1, .div = 32 },
+ { .val = 0, .div = 0 },
+};
+
+static const struct eqc_clock eqc_eyeq7h_ddr0_clks[] = {
+ PLL_AINTP(EQ7HC_DDR_PLL, PARENT_BY_FWNAME, "pll-ddr0", "ref", 0x0),
+
+ /* A single bit configures the 3 dividers below */
+ DIV_TABLE_RO(EQ7HC_DDR_DIV_APB, EQ7HC_DDR_PLL, "div-ddr0_apb", NULL,
+ 0x08, 10, 1, eqc_eyeq7h_ddr_apb_div_table),
+ DIV_TABLE_RO(EQ7HC_DDR_DIV_PLLREF, EQ7HC_DDR_PLL, "div-ddr0_pllref", NULL,
+ 0x08, 10, 1, eqc_eyeq7h_ddr_ref_div_table),
+ DIV_TABLE_RO(EQ7HC_DDR_DIV_DFI, EQ7HC_DDR_PLL, "div-ddr0-dfi", NULL,
+ 0x08, 10, 1, eqc_eyeq7h_ddr_dfi_div_table),
+};
+
+static const struct eqc_match_data eqc_eyeq7h_ddr0_match_data = {
+ .clk_count = ARRAY_SIZE(eqc_eyeq7h_ddr0_clks),
+ .clks = eqc_eyeq7h_ddr0_clks,
+
+ .reset_auxdev_name = "reset_ddr0",
+};
+
+static const struct eqc_clock eqc_eyeq7h_ddr1_clks[] = {
+ PLL_AINTP(EQ7HC_DDR_PLL, PARENT_BY_FWNAME, "pll-ddr1", "ref", 0x0),
+
+ /* A single bit configures the 3 dividers below */
+ DIV_TABLE_RO(EQ7HC_DDR_DIV_APB, EQ7HC_DDR_PLL, "div-ddr1_apb", NULL,
+ 0x08, 10, 1, eqc_eyeq7h_ddr_apb_div_table),
+ DIV_TABLE_RO(EQ7HC_DDR_DIV_PLLREF, EQ7HC_DDR_PLL, "div-ddr1_pllref", NULL,
+ 0x08, 10, 1, eqc_eyeq7h_ddr_ref_div_table),
+ DIV_TABLE_RO(EQ7HC_DDR_DIV_DFI, EQ7HC_DDR_PLL, "div-ddr1-dfi", NULL,
+ 0x08, 10, 1, eqc_eyeq7h_ddr_dfi_div_table),
+};
+
+static const struct eqc_match_data eqc_eyeq7h_ddr1_match_data = {
+ .clk_count = ARRAY_SIZE(eqc_eyeq7h_ddr1_clks),
+ .clks = eqc_eyeq7h_ddr1_clks,
+
+ .reset_auxdev_name = "reset_ddr1",
+};
+
+static const struct eqc_clock eqc_eyeq7h_east_clocks[] = {
+ PLL_JFRACR(EQ7HC_EAST_PLL_106P6, PARENT_BY_FWNAME, "pll-106p6-e", "ref", 0x00),
+
+ FF(EQ7HC_EAST_DIV_REF_106P6, EQ7HC_EAST_PLL_106P6, "ref_106p6_e", NULL, 1, 40),
+
+ PLL_AINTP(EQ7HC_EAST_PLL_NOC, EQ7HC_EAST_DIV_REF_106P6, "pll-noc-e", NULL, 0x30),
+ PLL_AINTP(EQ7HC_EAST_PLL_ISP, PARENT_BY_FWNAME, "pll-isp", "ref_100p0", 0x38),
+ PLL_AINTP(EQ7HC_EAST_PLL_VEU, PARENT_BY_FWNAME, "pll-veu", "ref_100p0", 0x40),
+
+ FF(EQ7HC_EAST_DIV_REF_DDR_PHY, EQ7HC_EAST_PLL_106P6, "ref_ddr_phy_e", NULL, 1, 2),
+
+ FF(EQ7HC_EAST_DIV_CORE, EQ7HC_EAST_PLL_NOC, "core_e", NULL, 1, 2),
+ FF(EQ7HC_EAST_DIV_CORE_MBIST, EQ7HC_EAST_PLL_NOC, "core_mbist_e", NULL, 1, 2),
+ FF(EQ7HC_EAST_DIV_ISRAM_MBIST, EQ7HC_EAST_PLL_NOC, "isram_mbist_e", NULL, 1, 2),
+ FF(EQ7HC_EAST_DIV_CFG, EQ7HC_EAST_PLL_NOC, "cfg_e", NULL, 1, 4),
+
+ FF(EQ7HC_EAST_DIV_VEU_CORE, EQ7HC_EAST_PLL_VEU, "veu_core", NULL, 1, 4),
+ FF(EQ7HC_EAST_DIV_VEU_MBIST, EQ7HC_EAST_PLL_VEU, "veu_mbist", NULL, 1, 4),
+ FF(EQ7HC_EAST_DIV_VEU_OCP, EQ7HC_EAST_PLL_VEU, "veu_ocp", NULL, 1, 16),
+
+ FF(EQ7HC_EAST_DIV_LBITS, EQ7HC_EAST_PLL_ISP, "lbits_e", NULL, 1, 48),
+ FF(EQ7HC_EAST_DIV_ISP0_CORE, EQ7HC_EAST_PLL_ISP, "isp0_core", NULL, 1, 2),
+};
+
+static const struct eqc_match_data eqc_eyeq7h_east_match_data = {
+ .clk_count = ARRAY_SIZE(eqc_eyeq7h_east_clocks),
+ .clks = eqc_eyeq7h_east_clocks,
+
+ .reset_auxdev_name = "reset_east",
+};
+
+static const struct eqc_clock eqc_eyeq7h_mips0_clks[] = {
+ PLL_AINTP(EQ7HC_MIPS_PLL_CPU, PARENT_BY_FWNAME, "pll-cpu0", "ref", 0x0),
+
+ FF(EQ7HC_MIPS_DIV_CM, EQ7HC_MIPS_PLL_CPU, "mips0_cm", NULL, 1, 2),
+};
+
+static const struct eqc_match_data eqc_eyeq7h_mips0_match_data = {
+ .clk_count = ARRAY_SIZE(eqc_eyeq7h_mips0_clks),
+ .clks = eqc_eyeq7h_mips0_clks,
+};
+
+static const struct eqc_clock eqc_eyeq7h_mips1_clks[] = {
+ PLL_AINTP(EQ7HC_MIPS_PLL_CPU, PARENT_BY_FWNAME, "pll-cpu1", "ref", 0x0),
+
+ FF(EQ7HC_MIPS_DIV_CM, EQ7HC_MIPS_PLL_CPU, "mips1_cm", NULL, 1, 2),
+};
+
+static const struct eqc_match_data eqc_eyeq7h_mips1_match_data = {
+ .clk_count = ARRAY_SIZE(eqc_eyeq7h_mips1_clks),
+ .clks = eqc_eyeq7h_mips1_clks,
+};
+
+static const struct eqc_clock eqc_eyeq7h_mips2_clks[] = {
+ PLL_AINTP(EQ7HC_MIPS_PLL_CPU, PARENT_BY_FWNAME, "pll-cpu2", "ref", 0x0),
+
+ FF(EQ7HC_MIPS_DIV_CM, EQ7HC_MIPS_PLL_CPU, "mips2_cm", NULL, 1, 2),
+};
+
+static const struct eqc_match_data eqc_eyeq7h_mips2_match_data = {
+ .clk_count = ARRAY_SIZE(eqc_eyeq7h_mips2_clks),
+ .clks = eqc_eyeq7h_mips2_clks,
+};
+
+static const struct eqc_clock eqc_eyeq7h_periph_east_clks[] = {
+ PLL_AINTP(EQ7HC_PERIPH_EAST_PLL_PER, PARENT_BY_FWNAME, "pll-periph_east_per", "ref", 0x0),
+
+ FF(EQ7HC_PERIPH_EAST_DIV_PER, EQ7HC_PERIPH_EAST_PLL_PER, "periph_e", NULL, 1, 10),
+};
+
+static const struct eqc_match_data eqc_eyeq7h_periph_east_match_data = {
+ .clk_count = ARRAY_SIZE(eqc_eyeq7h_periph_east_clks),
+ .clks = eqc_eyeq7h_periph_east_clks,
+
+ .reset_auxdev_name = "reset_periph_east",
+};
+
+static const struct eqc_clock eqc_eyeq7h_periph_west_clks[] = {
+ PLL_AINTP(EQ7HC_PERIPH_WEST_PLL_PER, PARENT_BY_FWNAME,
+ "pll-periph_west_per", "ref_100p0", 0x0),
+ PLL_AINTP(EQ7HC_PERIPH_WEST_PLL_I2S, PARENT_BY_FWNAME,
+ "pll-periph_west_i2s", "ref_106p6", 0x4),
+
+ FF(EQ7HC_PERIPH_WEST_DIV_PER, EQ7HC_PERIPH_WEST_PLL_PER, "periph_w", NULL, 1, 10),
+ FF(EQ7HC_PERIPH_WEST_DIV_I2S, EQ7HC_PERIPH_WEST_PLL_I2S, "periph_i2s_ser_w", NULL, 1, 100),
+};
+
+static const struct eqc_match_data eqc_eyeq7h_periph_west_match_data = {
+ .clk_count = ARRAY_SIZE(eqc_eyeq7h_periph_west_clks),
+ .clks = eqc_eyeq7h_periph_west_clks,
+
+ .reset_auxdev_name = "reset_periph_west",
+};
+
+static const struct eqc_clock eqc_eyeq7h_south_clks[] = {
+ PLL_JFRACR(EQ7HC_SOUTH_PLL_100P0, PARENT_BY_FWNAME, "pll-100p0", "ref", 0x40),
+
+ FF(EQ7HC_SOUTH_DIV_REF_100P0, EQ7HC_SOUTH_PLL_100P0, "ref_100p0", NULL, 1, 48),
+
+ PLL_AINTP(EQ7HC_SOUTH_PLL_XSPI, EQ7HC_SOUTH_DIV_REF_100P0, "pll-xspi", NULL, 0x10),
+ PLL_AINTP(EQ7HC_SOUTH_PLL_VDIO, EQ7HC_SOUTH_DIV_REF_100P0, "pll-vdio", NULL, 0x18),
+ PLL_AINTP(EQ7HC_SOUTH_PLL_PER, EQ7HC_SOUTH_DIV_REF_100P0, "pll-per-s", NULL, 0x20),
+
+ FF(EQ7HC_SOUTH_DIV_VDO_DSI_SYS, EQ7HC_SOUTH_PLL_100P0, "vdo_dsi_sys", NULL, 1, 9),
+ FF(EQ7HC_SOUTH_DIV_PMA_CMN_REF, EQ7HC_SOUTH_PLL_100P0, "pma_cmn_ref", NULL, 1, 48),
+ FF(EQ7HC_SOUTH_DIV_REF_UFS, EQ7HC_SOUTH_PLL_100P0, "ref_ufs", NULL, 1, 250),
+ FF(EQ7HC_SOUTH_DIV_XSPI_SYS, EQ7HC_SOUTH_PLL_XSPI, "xspi_sys", NULL, 1, 8),
+ FF(EQ7HC_SOUTH_DIV_XSPI_MBIST, EQ7HC_SOUTH_PLL_XSPI, "xspi_mbist", NULL, 1, 8),
+ FF(EQ7HC_SOUTH_DIV_NOC_S, EQ7HC_SOUTH_PLL_PER, "noc_s", NULL, 1, 2),
+ FF(EQ7HC_SOUTH_DIV_PCIE_SYS, EQ7HC_SOUTH_PLL_PER, "pcie_sys", NULL, 1, 4),
+ FF(EQ7HC_SOUTH_DIV_PCIE_SYS_MBIST, EQ7HC_SOUTH_PLL_PER, "pcie_sys_mbist", NULL, 1, 4),
+ FF(EQ7HC_SOUTH_DIV_PCIE_GBE_PHY, EQ7HC_SOUTH_PLL_PER, "pcie_gbe_phy_apb", NULL, 1, 16),
+ FF(EQ7HC_SOUTH_DIV_UFS_CORE, EQ7HC_SOUTH_PLL_PER, "ufs_core", NULL, 1, 8),
+ FF(EQ7HC_SOUTH_DIV_UFS_SMS, EQ7HC_SOUTH_PLL_PER, "ufs_sms", NULL, 1, 5),
+ FF(EQ7HC_SOUTH_DIV_UFS_ROM_SMS, EQ7HC_SOUTH_PLL_PER, "ufs_rom_sms", NULL, 1, 5),
+ FF(EQ7HC_SOUTH_DIV_ETH_SYS, EQ7HC_SOUTH_PLL_PER, "eth_sys", NULL, 1, 8),
+ FF(EQ7HC_SOUTH_DIV_ETH_MBIST, EQ7HC_SOUTH_PLL_PER, "eth_mbist", NULL, 1, 8),
+ FF(EQ7HC_SOUTH_DIV_CFG_S, EQ7HC_SOUTH_PLL_PER, "cfg_s", NULL, 1, 8),
+ FF(EQ7HC_SOUTH_DIV_TSU, EQ7HC_SOUTH_PLL_PER, "tsu", NULL, 1, 64),
+ FF(EQ7HC_SOUTH_DIV_VDIO, EQ7HC_SOUTH_PLL_VDIO, "vdio", NULL, 1, 4),
+ FF(EQ7HC_SOUTH_DIV_VDIO_CORE, EQ7HC_SOUTH_PLL_VDIO, "vdio_core", NULL, 1, 4),
+ FF(EQ7HC_SOUTH_DIV_VDIO_CORE_MBIST, EQ7HC_SOUTH_PLL_VDIO, "vdio_core_mbist", NULL, 1, 4),
+ FF(EQ7HC_SOUTH_DIV_VDO_CORE_MBIST, EQ7HC_SOUTH_PLL_VDIO, "vdo_core_mbist", NULL, 1, 4),
+ FF(EQ7HC_SOUTH_DIV_VDO_P, EQ7HC_SOUTH_PLL_VDIO, "vdo_p", NULL, 1, 40),
+ FF(EQ7HC_SOUTH_DIV_VDIO_CFG, EQ7HC_SOUTH_PLL_VDIO, "vdio_cfg", NULL, 1, 150),
+ FF(EQ7HC_SOUTH_DIV_VDIO_TXCLKESC, EQ7HC_SOUTH_PLL_VDIO, "vdio_txclkesc", NULL, 1, 8),
+};
+
+static const struct eqc_match_data eqc_eyeq7h_south_match_data = {
+ .clk_count = ARRAY_SIZE(eqc_eyeq7h_south_clks),
+ .clks = eqc_eyeq7h_south_clks,
+
+ .reset_auxdev_name = "reset_south",
+};
+
+static const struct eqc_clock eqc_eyeq7h_west_clks[] = {
+ PLL_JFRACR(EQ7HC_WEST_PLL_106P6, PARENT_BY_FWNAME, "pll-106p6-w", "ref", 0x0),
+
+ FF(EQ7HC_WEST_DIV_REF_106P6, EQ7HC_WEST_PLL_106P6, "ref_106p6_w", NULL, 1, 40),
+
+ PLL_AINTP(EQ7HC_WEST_PLL_NOC, EQ7HC_WEST_DIV_REF_106P6, "pll-noc-w", NULL, 0x30),
+ PLL_AINTP(EQ7HC_WEST_PLL_GPU, PARENT_BY_FWNAME, "pll-gpu", "ref_100p0", 0x38),
+ PLL_AINTP(EQ7HC_WEST_PLL_SSI, PARENT_BY_FWNAME, "pll-ssi", "ref_100p0", 0x40),
+
+ FF(EQ7HC_WEST_DIV_GPU, EQ7HC_WEST_PLL_GPU, "gpu", NULL, 1, 2),
+ FF(EQ7HC_WEST_DIV_GPU_MBIST, EQ7HC_WEST_PLL_GPU, "gpu_mbist", NULL, 1, 2),
+ FF(EQ7HC_WEST_DIV_LBITS, EQ7HC_WEST_PLL_GPU, "lbits_w", NULL, 1, 40),
+ FF(EQ7HC_WEST_DIV_MIPS_TIMER, EQ7HC_WEST_PLL_SSI, "mips_timer", NULL, 1, 24),
+ FF(EQ7HC_WEST_DIV_SSI_CORE, EQ7HC_WEST_PLL_SSI, "ssi_core", NULL, 1, 2),
+ FF(EQ7HC_WEST_DIV_SSI_CORE_MBIST, EQ7HC_WEST_PLL_SSI, "ssi_core_mbist", NULL, 1, 2),
+ FF(EQ7HC_WEST_DIV_SSI_ROM, EQ7HC_WEST_PLL_SSI, "ssi_rom", NULL, 1, 8),
+ FF(EQ7HC_WEST_DIV_SSI_ROM_MBIST, EQ7HC_WEST_PLL_SSI, "ssi_rom_mbist", NULL, 1, 8),
+ FF(EQ7HC_WEST_DIV_REF_DDR_PHY, EQ7HC_WEST_PLL_106P6, "ref_ddr_phy_w", NULL, 1, 2),
+ FF(EQ7HC_WEST_DIV_CORE, EQ7HC_WEST_PLL_NOC, "core_w", NULL, 1, 2),
+ FF(EQ7HC_WEST_DIV_CORE_MBIST, EQ7HC_WEST_PLL_NOC, "core_mbist_w", NULL, 1, 2),
+ FF(EQ7HC_WEST_DIV_CFG, EQ7HC_WEST_PLL_NOC, "cfg_w", NULL, 1, 4),
+ FF(EQ7HC_WEST_DIV_CAU, EQ7HC_WEST_PLL_NOC, "cau_w", NULL, 1, 8),
+ FF(EQ7HC_WEST_DIV_CAU_MBIST, EQ7HC_WEST_PLL_NOC, "cau_mbist_w", NULL, 1, 8),
+};
+
+static const struct eqc_match_data eqc_eyeq7h_west_match_data = {
+ .clk_count = ARRAY_SIZE(eqc_eyeq7h_west_clks),
+ .clks = eqc_eyeq7h_west_clks,
+
+ .reset_auxdev_name = "reset_west",
+};
+
+static const struct eqc_clock eqc_eyeq7h_xnn0_clks[] = {
+ PLL_AINTP(EQ7HC_XNN_PLL_XNN0, PARENT_BY_FWNAME, "pll-xnn0-0", "ref_100p0", 0x400),
+ PLL_AINTP(EQ7HC_XNN_PLL_XNN1, PARENT_BY_FWNAME, "pll-xnn0-1", "ref_100p0", 0x404),
+ PLL_AINTP(EQ7HC_XNN_PLL_XNN2, PARENT_BY_FWNAME, "pll-xnn0-2", "ref_100p0", 0x408),
+ PLL_AINTP(EQ7HC_XNN_PLL_CLSTR, PARENT_BY_FWNAME, "pll-xnn0-clstr", "ref_106p6", 0x410),
+
+ FF(EQ7HC_XNN_DIV_XNN0, EQ7HC_XNN_PLL_XNN0, "xnn0", NULL, 1, 2),
+ FF(EQ7HC_XNN_DIV_XNN1, EQ7HC_XNN_PLL_XNN1, "xnn1", NULL, 1, 2),
+ FF(EQ7HC_XNN_DIV_XNN2, EQ7HC_XNN_PLL_XNN2, "xnn2", NULL, 1, 2),
+ FF(EQ7HC_XNN_DIV_CLSTR, EQ7HC_XNN_PLL_CLSTR, "xnn0_clstr", NULL, 1, 2),
+ FF(EQ7HC_XNN_DIV_I2, EQ7HC_XNN_PLL_CLSTR, "xnn0_i2", NULL, 1, 4),
+ FF(EQ7HC_XNN_DIV_I2_SMS, EQ7HC_XNN_PLL_CLSTR, "xnn0_i2_sms", NULL, 1, 4),
+ FF(EQ7HC_XNN_DIV_CFG, EQ7HC_XNN_PLL_CLSTR, "xnn0_cfg", NULL, 1, 8),
+};
+
+static const struct eqc_match_data eqc_eyeq7h_xnn0_match_data = {
+ .clk_count = ARRAY_SIZE(eqc_eyeq7h_xnn0_clks),
+ .clks = eqc_eyeq7h_xnn0_clks,
+
+ .reset_auxdev_name = "reset_xnn0",
+};
+
+static const struct eqc_clock eqc_eyeq7h_xnn1_clks[] = {
+ PLL_AINTP(EQ7HC_XNN_PLL_XNN0, PARENT_BY_FWNAME, "pll-xnn1-0", "ref_100p0", 0x400),
+ PLL_AINTP(EQ7HC_XNN_PLL_XNN1, PARENT_BY_FWNAME, "pll-xnn1-1", "ref_100p0", 0x404),
+ PLL_AINTP(EQ7HC_XNN_PLL_XNN2, PARENT_BY_FWNAME, "pll-xnn1-2", "ref_100p0", 0x408),
+ PLL_AINTP(EQ7HC_XNN_PLL_CLSTR, PARENT_BY_FWNAME, "pll-xnn1-clstr", "ref_106p6", 0x410),
+};
+
+static const struct eqc_match_data eqc_eyeq7h_xnn1_match_data = {
+ .clk_count = ARRAY_SIZE(eqc_eyeq7h_xnn1_clks),
+ .clks = eqc_eyeq7h_xnn1_clks,
+
+ .reset_auxdev_name = "reset_xnn1",
+};
+
static const struct of_device_id eqc_match_table[] = {
{ .compatible = "mobileye,eyeq5-olb", .data = &eqc_eyeq5_match_data },
{ .compatible = "mobileye,eyeq6l-olb", .data = &eqc_eyeq6l_match_data },
@@ -685,6 +1180,22 @@ static const struct of_device_id eqc_match_table[] = {
{ .compatible = "mobileye,eyeq6h-ddr0-olb", .data = &eqc_eyeq6h_ddr0_match_data },
{ .compatible = "mobileye,eyeq6h-ddr1-olb", .data = &eqc_eyeq6h_ddr1_match_data },
{ .compatible = "mobileye,eyeq6h-acc-olb", .data = &eqc_eyeq6h_acc_match_data },
+ { .compatible = "mobileye,eyeq7h-acc0-olb", .data = &eqc_eyeq7h_acc0_match_data },
+ { .compatible = "mobileye,eyeq7h-acc1-olb", .data = &eqc_eyeq7h_acc1_match_data },
+ { .compatible = "mobileye,eyeq7h-ddr0-olb", .data = &eqc_eyeq7h_ddr0_match_data },
+ { .compatible = "mobileye,eyeq7h-ddr1-olb", .data = &eqc_eyeq7h_ddr1_match_data },
+ { .compatible = "mobileye,eyeq7h-east-olb", .data = &eqc_eyeq7h_east_match_data },
+ { .compatible = "mobileye,eyeq7h-mips0-olb", .data = &eqc_eyeq7h_mips0_match_data },
+ { .compatible = "mobileye,eyeq7h-mips1-olb", .data = &eqc_eyeq7h_mips1_match_data },
+ { .compatible = "mobileye,eyeq7h-mips2-olb", .data = &eqc_eyeq7h_mips2_match_data },
+ { .compatible = "mobileye,eyeq7h-periph-east-olb",
+ .data = &eqc_eyeq7h_periph_east_match_data },
+ { .compatible = "mobileye,eyeq7h-periph-west-olb",
+ .data = &eqc_eyeq7h_periph_west_match_data },
+ { .compatible = "mobileye,eyeq7h-south-olb", .data = &eqc_eyeq7h_south_match_data },
+ { .compatible = "mobileye,eyeq7h-west-olb", .data = &eqc_eyeq7h_west_match_data },
+ { .compatible = "mobileye,eyeq7h-xnn0-olb", .data = &eqc_eyeq7h_xnn0_match_data },
+ { .compatible = "mobileye,eyeq7h-xnn1-olb", .data = &eqc_eyeq7h_xnn1_match_data },
{}
};
--
2.54.0
^ permalink raw reply related
* [PATCH v7 8/9] clk: eyeq: Drop PLL, dividers, and fixed factors structs
From: Benoît Monin @ 2026-05-22 12:31 UTC (permalink / raw)
To: Vladimir Kondratiev, Gregory CLEMENT, Théo Lebrun,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd, Brian Masney, Philipp Zabel
Cc: Benoît Monin, Thomas Petazzoni, linux-mips, devicetree,
linux-kernel, linux-clk
In-Reply-To: <20260522-clk-eyeq7-v7-0-14ad6c2c5213@bootlin.com>
Now that there are no users of the eqc_pll, eqc_div, and eqc_fixed_factor
structures since they have been converted to eqc_clock, remove these
structs and the code related to their parsing in probe and early
initialization.
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
drivers/clk/clk-eyeq.c | 192 +------------------------------------------------
1 file changed, 3 insertions(+), 189 deletions(-)
diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index 8a38ad9afb5e..5200d5f0ff06 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -78,33 +78,6 @@
#define PARENT_BY_FWNAME (-1)
#define PARENT_BY_NAME (-2)
-struct eqc_pll {
- unsigned int index;
- const char *name;
- unsigned int reg64;
-};
-
-/*
- * Divider clock. Divider is 2*(v+1), with v the register value.
- * Min divider is 2, max is 2*(2^width).
- */
-struct eqc_div {
- unsigned int index;
- const char *name;
- unsigned int parent;
- unsigned int reg;
- u8 shift;
- u8 width;
-};
-
-struct eqc_fixed_factor {
- unsigned int index;
- const char *name;
- unsigned int mult;
- unsigned int div;
- unsigned int parent;
-};
-
struct eqc_clock {
int index;
int parent_idx;
@@ -133,15 +106,6 @@ struct eqc_clock {
};
struct eqc_match_data {
- unsigned int pll_count;
- const struct eqc_pll *plls;
-
- unsigned int div_count;
- const struct eqc_div *divs;
-
- unsigned int fixed_factor_count;
- const struct eqc_fixed_factor *fixed_factors;
-
unsigned int clk_count;
const struct eqc_clock *clks;
@@ -153,12 +117,6 @@ struct eqc_match_data {
};
struct eqc_early_match_data {
- unsigned int early_pll_count;
- const struct eqc_pll *early_plls;
-
- unsigned int early_fixed_factor_count;
- const struct eqc_fixed_factor *early_fixed_factors;
-
unsigned int early_clk_count;
const struct eqc_clock *early_clks;
@@ -271,97 +229,6 @@ static int eqc_pll_parse_fracg(void __iomem *base, unsigned long *mult,
return 0;
}
-static void eqc_probe_init_plls(struct device *dev, const struct eqc_match_data *data,
- void __iomem *base, struct clk_hw_onecell_data *cells)
-{
- unsigned long mult, div, acc;
- const struct eqc_pll *pll;
- struct clk_hw *hw;
- unsigned int i;
- int ret;
-
- for (i = 0; i < data->pll_count; i++) {
- pll = &data->plls[i];
-
- ret = eqc_pll_parse_fracg(base + pll->reg64, &mult, &div, &acc);
- if (ret) {
- dev_warn(dev, "failed parsing state of %s\n", pll->name);
- cells->hws[pll->index] = ERR_PTR(ret);
- continue;
- }
-
- hw = clk_hw_register_fixed_factor_with_accuracy_fwname(dev,
- dev->of_node, pll->name, "ref", 0, mult, div, acc);
- cells->hws[pll->index] = hw;
- if (IS_ERR(hw))
- dev_warn(dev, "failed registering %s: %pe\n", pll->name, hw);
- }
-}
-
-static void eqc_probe_init_divs(struct device *dev, const struct eqc_match_data *data,
- void __iomem *base, struct clk_hw_onecell_data *cells)
-{
- struct clk_parent_data parent_data = { };
- const struct eqc_div *div;
- struct clk_hw *parent;
- void __iomem *reg;
- struct clk_hw *hw;
- unsigned int i;
-
- for (i = 0; i < data->div_count; i++) {
- div = &data->divs[i];
- reg = base + div->reg;
- parent = cells->hws[div->parent];
-
- if (IS_ERR(parent)) {
- /* Parent is in early clk provider. */
- parent_data.index = div->parent;
- parent_data.hw = NULL;
- } else {
- /* Avoid clock lookup when we already have the hw reference. */
- parent_data.index = 0;
- parent_data.hw = parent;
- }
-
- hw = clk_hw_register_divider_table_parent_data(dev, div->name,
- &parent_data, 0, reg, div->shift, div->width,
- CLK_DIVIDER_EVEN_INTEGERS, NULL, NULL);
- cells->hws[div->index] = hw;
- if (IS_ERR(hw))
- dev_warn(dev, "failed registering %s: %pe\n",
- div->name, hw);
- }
-}
-
-static void eqc_probe_init_fixed_factors(struct device *dev,
- const struct eqc_match_data *data,
- struct clk_hw_onecell_data *cells)
-{
- const struct eqc_fixed_factor *ff;
- struct clk_hw *hw, *parent_hw;
- unsigned int i;
-
- for (i = 0; i < data->fixed_factor_count; i++) {
- ff = &data->fixed_factors[i];
- parent_hw = cells->hws[ff->parent];
-
- if (IS_ERR(parent_hw)) {
- /* Parent is in early clk provider. */
- hw = clk_hw_register_fixed_factor_index(dev, ff->name,
- ff->parent, 0, ff->mult, ff->div);
- } else {
- /* Avoid clock lookup when we already have the hw reference. */
- hw = clk_hw_register_fixed_factor_parent_hw(dev, ff->name,
- parent_hw, 0, ff->mult, ff->div);
- }
-
- cells->hws[ff->index] = hw;
- if (IS_ERR(hw))
- dev_warn(dev, "failed registering %s: %pe\n",
- ff->name, hw);
- }
-}
-
static void eqc_auxdev_create_optional(struct device *dev, void __iomem *base,
const char *name)
{
@@ -500,12 +367,10 @@ static int eqc_probe(struct platform_device *pdev)
eqc_auxdev_create_optional(dev, base, data->pinctrl_auxdev_name);
eqc_auxdev_create_optional(dev, base, data->eth_phy_auxdev_name);
- if (data->pll_count + data->div_count + data->fixed_factor_count + data->clk_count == 0)
+ if (data->clk_count == 0)
return 0; /* Zero clocks, we are done. */
- clk_count = data->pll_count + data->div_count +
- data->fixed_factor_count + data->clk_count +
- data->early_clk_count;
+ clk_count = data->clk_count + data->early_clk_count;
cells = kzalloc_flex(*cells, hws, clk_count);
if (!cells)
return -ENOMEM;
@@ -516,12 +381,6 @@ static int eqc_probe(struct platform_device *pdev)
for (i = 0; i < clk_count; i++)
cells->hws[i] = ERR_PTR(-EINVAL);
- eqc_probe_init_plls(dev, data, base, cells);
-
- eqc_probe_init_divs(dev, data, base, cells);
-
- eqc_probe_init_fixed_factors(dev, data, cells);
-
for (i = 0; i < data->clk_count; i++) {
const struct eqc_clock *clk = &data->clks[i];
@@ -872,8 +731,7 @@ static void __init eqc_early_init(struct device_node *np,
void __iomem *base;
int ret;
- clk_count = early_data->early_pll_count + early_data->early_fixed_factor_count +
- early_data->early_clk_count + early_data->late_clk_count;
+ clk_count = early_data->early_clk_count + early_data->late_clk_count;
cells = kzalloc_flex(*cells, hws, clk_count);
if (!cells) {
ret = -ENOMEM;
@@ -899,42 +757,6 @@ static void __init eqc_early_init(struct device_node *np,
goto err;
}
- for (i = 0; i < early_data->early_pll_count; i++) {
- const struct eqc_pll *pll = &early_data->early_plls[i];
- unsigned long mult, div, acc;
- struct clk_hw *hw;
-
- ret = eqc_pll_parse_fracg(base + pll->reg64, &mult, &div, &acc);
- if (ret) {
- pr_err("failed parsing state of %s\n", pll->name);
- goto err;
- }
-
- hw = clk_hw_register_fixed_factor_with_accuracy_fwname(NULL,
- np, pll->name, "ref", 0, mult, div, acc);
- cells->hws[pll->index] = hw;
- if (IS_ERR(hw)) {
- pr_err("failed registering %s: %pe\n", pll->name, hw);
- ret = PTR_ERR(hw);
- goto err;
- }
- }
-
- for (i = 0; i < early_data->early_fixed_factor_count; i++) {
- const struct eqc_fixed_factor *ff = &early_data->early_fixed_factors[i];
- struct clk_hw *parent_hw = cells->hws[ff->parent];
- struct clk_hw *hw;
-
- hw = clk_hw_register_fixed_factor_parent_hw(NULL, ff->name,
- parent_hw, 0, ff->mult, ff->div);
- cells->hws[ff->index] = hw;
- if (IS_ERR(hw)) {
- pr_err("failed registering %s: %pe\n", ff->name, hw);
- ret = PTR_ERR(hw);
- goto err;
- }
- }
-
for (i = 0; i < early_data->early_clk_count; i++) {
const struct eqc_clock *clk = &early_data->early_clks[i];
@@ -969,14 +791,6 @@ static void __init eqc_early_init(struct device_node *np,
if (cells) {
of_clk_del_provider(np);
- for (i = 0; i < early_data->early_pll_count; i++) {
- const struct eqc_pll *pll = &early_data->early_plls[i];
- struct clk_hw *hw = cells->hws[pll->index];
-
- if (!IS_ERR_OR_NULL(hw))
- clk_hw_unregister_fixed_factor(hw);
- }
-
for (i = 0; i < early_data->early_clk_count; i++) {
const struct eqc_clock *clk = &early_data->early_clks[i];
struct clk_hw *hw = cells->hws[clk->index];
--
2.54.0
^ permalink raw reply related
* [PATCH v7 7/9] clk: eyeq: Convert clocks declaration to eqc_clock
From: Benoît Monin @ 2026-05-22 12:31 UTC (permalink / raw)
To: Vladimir Kondratiev, Gregory CLEMENT, Théo Lebrun,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd, Brian Masney, Philipp Zabel
Cc: Benoît Monin, Thomas Petazzoni, linux-mips, devicetree,
linux-kernel, linux-clk
In-Reply-To: <20260522-clk-eyeq7-v7-0-14ad6c2c5213@bootlin.com>
Convert all declarations of PLLs, dividers, and fixed factors to struct
eqc_clock for the EyeQ5, EyeQ6H, EyeQ6L, and EyeQ6Lplus, both for the
match data used during probe and the early match data used in early
initialization.
Tested on the EyeQ5, EyeQ6H and EyeQ6Lplus evaluation boards. For the
EyeQ6Lplus and EyeQ6H, the clock tree is unchanged. For the EyeQ5,
this change allows us to set the parent of some probed dividers and
fixed factors by name as they refer to clocks registered in early
init. While these clocks were previously orphaned, they were not yet
used by a peripheral.
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
drivers/clk/clk-eyeq.c | 354 +++++++++++++++++++------------------------------
1 file changed, 135 insertions(+), 219 deletions(-)
diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index 7b8de08388d3..8a38ad9afb5e 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -575,23 +575,6 @@ static int eqc_probe(struct platform_device *pdev)
.pll.reg = _reg, \
}
-/* Required early for GIC timer (pll-cpu) and UARTs (pll-per). */
-static const struct eqc_pll eqc_eyeq5_early_plls[] = {
- { .index = EQ5C_PLL_CPU, .name = "pll-cpu", .reg64 = 0x02C },
- { .index = EQ5C_PLL_PER, .name = "pll-per", .reg64 = 0x05C },
-};
-
-static const struct eqc_pll eqc_eyeq5_plls[] = {
- { .index = EQ5C_PLL_VMP, .name = "pll-vmp", .reg64 = 0x034 },
- { .index = EQ5C_PLL_PMA, .name = "pll-pma", .reg64 = 0x03C },
- { .index = EQ5C_PLL_VDI, .name = "pll-vdi", .reg64 = 0x044 },
- { .index = EQ5C_PLL_DDR0, .name = "pll-ddr0", .reg64 = 0x04C },
- { .index = EQ5C_PLL_PCI, .name = "pll-pci", .reg64 = 0x054 },
- { .index = EQ5C_PLL_PMAC, .name = "pll-pmac", .reg64 = 0x064 },
- { .index = EQ5C_PLL_MPC, .name = "pll-mpc", .reg64 = 0x06C },
- { .index = EQ5C_PLL_DDR1, .name = "pll-ddr1", .reg64 = 0x074 },
-};
-
enum {
/*
* EQ5C_PLL_CPU children.
@@ -629,263 +612,206 @@ enum {
EQ5C_PER_FCMU_A,
};
-static const struct eqc_fixed_factor eqc_eyeq5_early_fixed_factors[] = {
- /* EQ5C_PLL_CPU children */
- { EQ5C_CPU_OCC, "occ-cpu", 1, 1, EQ5C_PLL_CPU },
- { EQ5C_CPU_SI_CSS0, "si-css0", 1, 1, EQ5C_CPU_OCC },
- { EQ5C_CPU_CORE0, "core0", 1, 1, EQ5C_CPU_SI_CSS0 },
- { EQ5C_CPU_CORE1, "core1", 1, 1, EQ5C_CPU_SI_CSS0 },
- { EQ5C_CPU_CORE2, "core2", 1, 1, EQ5C_CPU_SI_CSS0 },
- { EQ5C_CPU_CORE3, "core3", 1, 1, EQ5C_CPU_SI_CSS0 },
+/* Required early for GIC timer (pll-cpu) and UARTs (pll-per). */
+static const struct eqc_clock eqc_eyeq5_early_clks[] = {
+ PLL_FRACG(EQ5C_PLL_CPU, PARENT_BY_FWNAME, "pll-cpu", "ref", 0x02C),
+ PLL_FRACG(EQ5C_PLL_PER, PARENT_BY_FWNAME, "pll-per", "ref", 0x05C),
- /* EQ5C_PLL_PER children */
- { EQ5C_PER_OCC, "occ-periph", 1, 16, EQ5C_PLL_PER },
- { EQ5C_PER_UART, "uart", 1, 1, EQ5C_PER_OCC },
+ FF(EQ5C_CPU_OCC, EQ5C_PLL_CPU, "occ-cpu", NULL, 1, 1),
+ FF(EQ5C_CPU_SI_CSS0, EQ5C_CPU_OCC, "si-css0", NULL, 1, 1),
+ FF(EQ5C_CPU_CORE0, EQ5C_CPU_SI_CSS0, "core0", NULL, 1, 1),
+ FF(EQ5C_CPU_CORE1, EQ5C_CPU_SI_CSS0, "core1", NULL, 1, 1),
+ FF(EQ5C_CPU_CORE2, EQ5C_CPU_SI_CSS0, "core2", NULL, 1, 1),
+ FF(EQ5C_CPU_CORE3, EQ5C_CPU_SI_CSS0, "core3", NULL, 1, 1),
+
+ FF(EQ5C_PER_OCC, EQ5C_PLL_PER, "occ-periph", NULL, 1, 16),
+ FF(EQ5C_PER_UART, EQ5C_PER_OCC, "uart", NULL, 1, 1),
};
-static const struct eqc_fixed_factor eqc_eyeq5_fixed_factors[] = {
- /* EQ5C_PLL_CPU children */
- { EQ5C_CPU_CPC, "cpc", 1, 1, EQ5C_CPU_SI_CSS0 },
- { EQ5C_CPU_CM, "cm", 1, 1, EQ5C_CPU_SI_CSS0 },
- { EQ5C_CPU_MEM, "mem", 1, 1, EQ5C_CPU_SI_CSS0 },
- { EQ5C_CPU_OCC_ISRAM, "occ-isram", 1, 2, EQ5C_PLL_CPU },
- { EQ5C_CPU_ISRAM, "isram", 1, 1, EQ5C_CPU_OCC_ISRAM },
- { EQ5C_CPU_OCC_DBU, "occ-dbu", 1, 10, EQ5C_PLL_CPU },
- { EQ5C_CPU_SI_DBU_TP, "si-dbu-tp", 1, 1, EQ5C_CPU_OCC_DBU },
+static const struct eqc_clock eqc_eyeq5_clks[] = {
+ PLL_FRACG(EQ5C_PLL_VMP, PARENT_BY_FWNAME, "pll-vmp", "ref", 0x034),
+ PLL_FRACG(EQ5C_PLL_PMA, PARENT_BY_FWNAME, "pll-pma", "ref", 0x03C),
+ PLL_FRACG(EQ5C_PLL_VDI, PARENT_BY_FWNAME, "pll-vdi", "ref", 0x044),
+ PLL_FRACG(EQ5C_PLL_DDR0, PARENT_BY_FWNAME, "pll-ddr0", "ref", 0x04C),
+ PLL_FRACG(EQ5C_PLL_PCI, PARENT_BY_FWNAME, "pll-pci", "ref", 0x054),
+ PLL_FRACG(EQ5C_PLL_PMAC, PARENT_BY_FWNAME, "pll-pmac", "ref", 0x064),
+ PLL_FRACG(EQ5C_PLL_MPC, PARENT_BY_FWNAME, "pll-mpc", "ref", 0x06C),
+ PLL_FRACG(EQ5C_PLL_DDR1, PARENT_BY_FWNAME, "pll-ddr1", "ref", 0x074),
- /* EQ5C_PLL_VDI children */
- { EQ5C_VDI_OCC_VDI, "occ-vdi", 1, 2, EQ5C_PLL_VDI },
- { EQ5C_VDI_VDI, "vdi", 1, 1, EQ5C_VDI_OCC_VDI },
- { EQ5C_VDI_OCC_CAN_SER, "occ-can-ser", 1, 16, EQ5C_PLL_VDI },
- { EQ5C_VDI_CAN_SER, "can-ser", 1, 1, EQ5C_VDI_OCC_CAN_SER },
- { EQ5C_VDI_I2C_SER, "i2c-ser", 1, 20, EQ5C_PLL_VDI },
+ DIV(EQ5C_DIV_OSPI, PARENT_BY_NAME, "div-ospi", "pll-per", 0x11C, 0, 4),
- /* EQ5C_PLL_PER children */
- { EQ5C_PER_PERIPH, "periph", 1, 1, EQ5C_PER_OCC },
- { EQ5C_PER_CAN, "can", 1, 1, EQ5C_PER_OCC },
- { EQ5C_PER_SPI, "spi", 1, 1, EQ5C_PER_OCC },
- { EQ5C_PER_I2C, "i2c", 1, 1, EQ5C_PER_OCC },
- { EQ5C_PER_TIMER, "timer", 1, 1, EQ5C_PER_OCC },
- { EQ5C_PER_GPIO, "gpio", 1, 1, EQ5C_PER_OCC },
- { EQ5C_PER_EMMC, "emmc-sys", 1, 10, EQ5C_PLL_PER },
- { EQ5C_PER_CCF, "ccf-ctrl", 1, 4, EQ5C_PLL_PER },
- { EQ5C_PER_OCC_MJPEG, "occ-mjpeg", 1, 2, EQ5C_PLL_PER },
- { EQ5C_PER_HSM, "hsm", 1, 1, EQ5C_PER_OCC_MJPEG },
- { EQ5C_PER_MJPEG, "mjpeg", 1, 1, EQ5C_PER_OCC_MJPEG },
- { EQ5C_PER_FCMU_A, "fcmu-a", 1, 20, EQ5C_PLL_PER },
- { EQ5C_PER_OCC_PCI, "occ-pci-sys", 1, 8, EQ5C_PLL_PER },
-};
+ FF(EQ5C_CPU_CPC, PARENT_BY_NAME, "cpc", "si-css0", 1, 1),
+ FF(EQ5C_CPU_CM, PARENT_BY_NAME, "cm", "si-css0", 1, 1),
+ FF(EQ5C_CPU_MEM, PARENT_BY_NAME, "mem", "si-css0", 1, 1),
+ FF(EQ5C_CPU_OCC_ISRAM, PARENT_BY_NAME, "occ-isram", "pll-cpu", 1, 2),
+ FF(EQ5C_CPU_ISRAM, EQ5C_CPU_OCC_ISRAM, "isram", NULL, 1, 1),
+ FF(EQ5C_CPU_OCC_DBU, PARENT_BY_NAME, "occ-dbu", "pll-cpu", 1, 10),
+ FF(EQ5C_CPU_SI_DBU_TP, EQ5C_CPU_OCC_DBU, "si-dbu-tp", NULL, 1, 1),
-static const struct eqc_div eqc_eyeq5_divs[] = {
- {
- .index = EQ5C_DIV_OSPI,
- .name = "div-ospi",
- .parent = EQ5C_PLL_PER,
- .reg = 0x11C,
- .shift = 0,
- .width = 4,
- },
+ FF(EQ5C_VDI_OCC_VDI, PARENT_BY_NAME, "occ-vdi", "pll-vdi", 1, 2),
+ FF(EQ5C_VDI_VDI, EQ5C_VDI_OCC_VDI, "vdi", NULL, 1, 1),
+ FF(EQ5C_VDI_OCC_CAN_SER, PARENT_BY_NAME, "occ-can-ser", "pll-vdi", 1, 16),
+ FF(EQ5C_VDI_CAN_SER, EQ5C_VDI_OCC_CAN_SER, "can-ser", NULL, 1, 1),
+ FF(EQ5C_VDI_I2C_SER, PARENT_BY_NAME, "i2c-ser", "pll-vdi", 1, 20),
+
+ FF(EQ5C_PER_PERIPH, PARENT_BY_NAME, "periph", "occ-periph", 1, 1),
+ FF(EQ5C_PER_CAN, PARENT_BY_NAME, "can", "occ-periph", 1, 1),
+ FF(EQ5C_PER_SPI, PARENT_BY_NAME, "spi", "occ-periph", 1, 1),
+ FF(EQ5C_PER_I2C, PARENT_BY_NAME, "i2c", "occ-periph", 1, 1),
+ FF(EQ5C_PER_TIMER, PARENT_BY_NAME, "timer", "occ-periph", 1, 1),
+ FF(EQ5C_PER_GPIO, PARENT_BY_NAME, "gpio", "occ-periph", 1, 1),
+ FF(EQ5C_PER_EMMC, PARENT_BY_NAME, "emmc-sys", "pll-per", 1, 10),
+ FF(EQ5C_PER_CCF, PARENT_BY_NAME, "ccf-ctrl", "pll-per", 1, 4),
+ FF(EQ5C_PER_OCC_MJPEG, PARENT_BY_NAME, "occ-mjpeg", "pll-per", 1, 2),
+ FF(EQ5C_PER_HSM, EQ5C_PER_OCC_MJPEG, "hsm", NULL, 1, 1),
+ FF(EQ5C_PER_MJPEG, EQ5C_PER_OCC_MJPEG, "mjpeg", NULL, 1, 1),
+ FF(EQ5C_PER_FCMU_A, PARENT_BY_NAME, "fcmu-a", "pll-per", 1, 20),
+ FF(EQ5C_PER_OCC_PCI, PARENT_BY_NAME, "occ-pci-sys", "pll-per", 1, 8),
};
static const struct eqc_early_match_data eqc_eyeq5_early_match_data __initconst = {
- .early_pll_count = ARRAY_SIZE(eqc_eyeq5_early_plls),
- .early_plls = eqc_eyeq5_early_plls,
+ .early_clk_count = ARRAY_SIZE(eqc_eyeq5_early_clks),
+ .early_clks = eqc_eyeq5_early_clks,
- .early_fixed_factor_count = ARRAY_SIZE(eqc_eyeq5_early_fixed_factors),
- .early_fixed_factors = eqc_eyeq5_early_fixed_factors,
-
- .late_clk_count = ARRAY_SIZE(eqc_eyeq5_plls) + ARRAY_SIZE(eqc_eyeq5_divs) +
- ARRAY_SIZE(eqc_eyeq5_fixed_factors),
+ .late_clk_count = ARRAY_SIZE(eqc_eyeq5_clks),
};
static const struct eqc_match_data eqc_eyeq5_match_data = {
- .pll_count = ARRAY_SIZE(eqc_eyeq5_plls),
- .plls = eqc_eyeq5_plls,
-
- .div_count = ARRAY_SIZE(eqc_eyeq5_divs),
- .divs = eqc_eyeq5_divs,
-
- .fixed_factor_count = ARRAY_SIZE(eqc_eyeq5_fixed_factors),
- .fixed_factors = eqc_eyeq5_fixed_factors,
+ .clk_count = ARRAY_SIZE(eqc_eyeq5_clks),
+ .clks = eqc_eyeq5_clks,
.reset_auxdev_name = "reset",
.pinctrl_auxdev_name = "pinctrl",
.eth_phy_auxdev_name = "phy",
- .early_clk_count = ARRAY_SIZE(eqc_eyeq5_early_plls) +
- ARRAY_SIZE(eqc_eyeq5_early_fixed_factors),
+ .early_clk_count = ARRAY_SIZE(eqc_eyeq5_early_clks),
};
-static const struct eqc_pll eqc_eyeq6l_plls[] = {
- { .index = EQ6LC_PLL_DDR, .name = "pll-ddr", .reg64 = 0x02C },
- { .index = EQ6LC_PLL_CPU, .name = "pll-cpu", .reg64 = 0x034 }, /* also acc */
- { .index = EQ6LC_PLL_PER, .name = "pll-per", .reg64 = 0x03C },
- { .index = EQ6LC_PLL_VDI, .name = "pll-vdi", .reg64 = 0x044 },
+static const struct eqc_clock eqc_eyeq6l_clks[] = {
+ PLL_FRACG(EQ6LC_PLL_DDR, PARENT_BY_FWNAME, "pll-ddr", "ref", 0x02C),
+ PLL_FRACG(EQ6LC_PLL_CPU, PARENT_BY_FWNAME, "pll-cpu", "ref", 0x034),
+ PLL_FRACG(EQ6LC_PLL_PER, PARENT_BY_FWNAME, "pll-per", "ref", 0x03C),
+ PLL_FRACG(EQ6LC_PLL_VDI, PARENT_BY_FWNAME, "pll-vdi", "ref", 0x044),
};
static const struct eqc_match_data eqc_eyeq6l_match_data = {
- .pll_count = ARRAY_SIZE(eqc_eyeq6l_plls),
- .plls = eqc_eyeq6l_plls,
+ .clk_count = ARRAY_SIZE(eqc_eyeq6l_clks),
+ .clks = eqc_eyeq6l_clks,
.reset_auxdev_name = "reset",
};
-static const struct eqc_pll eqc_eyeq6lplus_early_plls[] = {
- { .index = EQ6LPC_PLL_CPU, .name = "pll-cpu", .reg64 = 0x058 },
+static const struct eqc_clock eqc_eyeq6lplus_early_clks[] = {
+ PLL_FRACG(EQ6LPC_PLL_CPU, PARENT_BY_FWNAME, "pll-cpu", "ref", 0x058),
+
+ FF(EQ6LPC_CPU_OCC, EQ6LPC_PLL_CPU, "occ-cpu", NULL, 1, 1),
};
-static const struct eqc_pll eqc_eyeq6lplus_plls[] = {
- { .index = EQ6LPC_PLL_DDR, .name = "pll-ddr", .reg64 = 0x02C },
- { .index = EQ6LPC_PLL_ACC, .name = "pll-acc", .reg64 = 0x034 },
- { .index = EQ6LPC_PLL_PER, .name = "pll-per", .reg64 = 0x03C },
- { .index = EQ6LPC_PLL_VDI, .name = "pll-vdi", .reg64 = 0x044 },
-};
+static const struct eqc_clock eqc_eyeq6lplus_clks[] = {
+ PLL_FRACG(EQ6LPC_PLL_DDR, PARENT_BY_FWNAME, "pll-ddr", "ref", 0x02C),
+ PLL_FRACG(EQ6LPC_PLL_ACC, PARENT_BY_FWNAME, "pll-acc", "ref", 0x034),
+ PLL_FRACG(EQ6LPC_PLL_PER, PARENT_BY_FWNAME, "pll-per", "ref", 0x03C),
+ PLL_FRACG(EQ6LPC_PLL_VDI, PARENT_BY_FWNAME, "pll-vdi", "ref", 0x044),
-static const struct eqc_fixed_factor eqc_eyeq6lplus_early_fixed_factors[] = {
- { EQ6LPC_CPU_OCC, "occ-cpu", 1, 1, EQ6LPC_PLL_CPU },
-};
+ FF(EQ6LPC_DDR_OCC, EQ6LPC_PLL_DDR, "occ-ddr", NULL, 1, 1),
-static const struct eqc_fixed_factor eqc_eyeq6lplus_fixed_factors[] = {
- { EQ6LPC_DDR_OCC, "occ-ddr", 1, 1, EQ6LPC_PLL_DDR },
+ FF(EQ6LPC_ACC_VDI, EQ6LPC_PLL_ACC, "vdi-div", NULL, 1, 10),
+ FF(EQ6LPC_ACC_OCC, EQ6LPC_PLL_ACC, "occ-acc", NULL, 1, 1),
+ FF(EQ6LPC_ACC_FCMU, EQ6LPC_ACC_OCC, "fcmu-a-clk", NULL, 1, 10),
- { EQ6LPC_ACC_VDI, "vdi-div", 1, 10, EQ6LPC_PLL_ACC },
- { EQ6LPC_ACC_OCC, "occ-acc", 1, 1, EQ6LPC_PLL_ACC },
- { EQ6LPC_ACC_FCMU, "fcmu-a-clk", 1, 10, EQ6LPC_ACC_OCC },
+ FF(EQ6LPC_PER_OCC, EQ6LPC_PLL_PER, "occ-per", NULL, 1, 1),
+ FF(EQ6LPC_PER_I2C_SER, EQ6LPC_PER_OCC, "i2c-ser-clk", NULL, 1, 10),
+ FF(EQ6LPC_PER_PCLK, EQ6LPC_PER_OCC, "pclk", NULL, 1, 4),
+ FF(EQ6LPC_PER_TSU, EQ6LPC_PER_OCC, "tsu-clk", NULL, 1, 8),
+ FF(EQ6LPC_PER_OSPI, EQ6LPC_PER_OCC, "ospi-ref-clk", NULL, 1, 10),
+ FF(EQ6LPC_PER_GPIO, EQ6LPC_PER_OCC, "gpio-clk", NULL, 1, 4),
+ FF(EQ6LPC_PER_TIMER, EQ6LPC_PER_OCC, "timer-clk", NULL, 1, 4),
+ FF(EQ6LPC_PER_I2C, EQ6LPC_PER_OCC, "i2c-clk", NULL, 1, 4),
+ FF(EQ6LPC_PER_UART, EQ6LPC_PER_OCC, "uart-clk", NULL, 1, 4),
+ FF(EQ6LPC_PER_SPI, EQ6LPC_PER_OCC, "spi-clk", NULL, 1, 4),
+ FF(EQ6LPC_PER_PERIPH, EQ6LPC_PER_OCC, "periph-clk", NULL, 1, 1),
- { EQ6LPC_PER_OCC, "occ-per", 1, 1, EQ6LPC_PLL_PER },
- { EQ6LPC_PER_I2C_SER, "i2c-ser-clk", 1, 10, EQ6LPC_PER_OCC },
- { EQ6LPC_PER_PCLK, "pclk", 1, 4, EQ6LPC_PER_OCC },
- { EQ6LPC_PER_TSU, "tsu-clk", 1, 8, EQ6LPC_PER_OCC },
- { EQ6LPC_PER_OSPI, "ospi-ref-clk", 1, 10, EQ6LPC_PER_OCC },
- { EQ6LPC_PER_GPIO, "gpio-clk", 1, 4, EQ6LPC_PER_OCC },
- { EQ6LPC_PER_TIMER, "timer-clk", 1, 4, EQ6LPC_PER_OCC },
- { EQ6LPC_PER_I2C, "i2c-clk", 1, 4, EQ6LPC_PER_OCC },
- { EQ6LPC_PER_UART, "uart-clk", 1, 4, EQ6LPC_PER_OCC },
- { EQ6LPC_PER_SPI, "spi-clk", 1, 4, EQ6LPC_PER_OCC },
- { EQ6LPC_PER_PERIPH, "periph-clk", 1, 1, EQ6LPC_PER_OCC },
-
- { EQ6LPC_VDI_OCC, "occ-vdi", 1, 1, EQ6LPC_PLL_VDI },
+ FF(EQ6LPC_VDI_OCC, EQ6LPC_PLL_VDI, "occ-vdi", NULL, 1, 1),
};
static const struct eqc_early_match_data eqc_eyeq6lplus_early_match_data __initconst = {
- .early_pll_count = ARRAY_SIZE(eqc_eyeq6lplus_early_plls),
- .early_plls = eqc_eyeq6lplus_early_plls,
+ .early_clk_count = ARRAY_SIZE(eqc_eyeq6lplus_early_clks),
+ .early_clks = eqc_eyeq6lplus_early_clks,
- .early_fixed_factor_count = ARRAY_SIZE(eqc_eyeq6lplus_early_fixed_factors),
- .early_fixed_factors = eqc_eyeq6lplus_early_fixed_factors,
-
- .late_clk_count = ARRAY_SIZE(eqc_eyeq6lplus_plls) +
- ARRAY_SIZE(eqc_eyeq6lplus_fixed_factors),
+ .late_clk_count = ARRAY_SIZE(eqc_eyeq6lplus_clks),
};
static const struct eqc_match_data eqc_eyeq6lplus_match_data = {
- .pll_count = ARRAY_SIZE(eqc_eyeq6lplus_plls),
- .plls = eqc_eyeq6lplus_plls,
-
- .fixed_factor_count = ARRAY_SIZE(eqc_eyeq6lplus_fixed_factors),
- .fixed_factors = eqc_eyeq6lplus_fixed_factors,
+ .clk_count = ARRAY_SIZE(eqc_eyeq6lplus_clks),
+ .clks = eqc_eyeq6lplus_clks,
.reset_auxdev_name = "reset",
.pinctrl_auxdev_name = "pinctrl",
- .early_clk_count = ARRAY_SIZE(eqc_eyeq6lplus_early_plls) +
- ARRAY_SIZE(eqc_eyeq6lplus_early_fixed_factors),
+ .early_clk_count = ARRAY_SIZE(eqc_eyeq6lplus_early_clks),
};
static const struct eqc_match_data eqc_eyeq6h_west_match_data = {
.reset_auxdev_name = "reset_west",
};
-static const struct eqc_pll eqc_eyeq6h_east_plls[] = {
- { .index = 0, .name = "pll-east", .reg64 = 0x074 },
+static const struct eqc_clock eqc_eyeq6h_east_clks[] = {
+ PLL_FRACG(0, PARENT_BY_FWNAME, "pll-east", "ref", 0x074),
};
static const struct eqc_match_data eqc_eyeq6h_east_match_data = {
- .pll_count = ARRAY_SIZE(eqc_eyeq6h_east_plls),
- .plls = eqc_eyeq6h_east_plls,
+ .clk_count = ARRAY_SIZE(eqc_eyeq6h_east_clks),
+ .clks = eqc_eyeq6h_east_clks,
.reset_auxdev_name = "reset_east",
};
-static const struct eqc_pll eqc_eyeq6h_south_plls[] = {
- { .index = EQ6HC_SOUTH_PLL_VDI, .name = "pll-vdi", .reg64 = 0x000 },
- { .index = EQ6HC_SOUTH_PLL_PCIE, .name = "pll-pcie", .reg64 = 0x008 },
- { .index = EQ6HC_SOUTH_PLL_PER, .name = "pll-per", .reg64 = 0x010 },
- { .index = EQ6HC_SOUTH_PLL_ISP, .name = "pll-isp", .reg64 = 0x018 },
-};
+static const struct eqc_clock eqc_eyeq6h_south_clks[] = {
+ PLL_FRACG(EQ6HC_SOUTH_PLL_VDI, PARENT_BY_FWNAME, "pll-vdi", "ref", 0x000),
+ PLL_FRACG(EQ6HC_SOUTH_PLL_PCIE, PARENT_BY_FWNAME, "pll-pcie", "ref", 0x008),
+ PLL_FRACG(EQ6HC_SOUTH_PLL_PER, PARENT_BY_FWNAME, "pll-per", "ref", 0x010),
+ PLL_FRACG(EQ6HC_SOUTH_PLL_ISP, PARENT_BY_FWNAME, "pll-isp", "ref", 0x018),
-static const struct eqc_div eqc_eyeq6h_south_divs[] = {
- {
- .index = EQ6HC_SOUTH_DIV_EMMC,
- .name = "div-emmc",
- .parent = EQ6HC_SOUTH_PLL_PER,
- .reg = 0x070,
- .shift = 4,
- .width = 4,
- },
- {
- .index = EQ6HC_SOUTH_DIV_OSPI_REF,
- .name = "div-ospi-ref",
- .parent = EQ6HC_SOUTH_PLL_PER,
- .reg = 0x090,
- .shift = 4,
- .width = 4,
- },
- {
- .index = EQ6HC_SOUTH_DIV_OSPI_SYS,
- .name = "div-ospi-sys",
- .parent = EQ6HC_SOUTH_PLL_PER,
- .reg = 0x090,
- .shift = 8,
- .width = 1,
- },
- {
- .index = EQ6HC_SOUTH_DIV_TSU,
- .name = "div-tsu",
- .parent = EQ6HC_SOUTH_PLL_PCIE,
- .reg = 0x098,
- .shift = 4,
- .width = 8,
- },
+ DIV(EQ6HC_SOUTH_DIV_EMMC, EQ6HC_SOUTH_PLL_PER, "div-emmc", NULL, 0x070, 4, 4),
+ DIV(EQ6HC_SOUTH_DIV_OSPI_REF, EQ6HC_SOUTH_PLL_PER, "div-ospi-ref", NULL, 0x090, 4, 4),
+ DIV(EQ6HC_SOUTH_DIV_OSPI_SYS, EQ6HC_SOUTH_PLL_PER, "div-ospi-sys", NULL, 0x090, 8, 1),
+ DIV(EQ6HC_SOUTH_DIV_TSU, EQ6HC_SOUTH_PLL_PCIE, "div-tsu", NULL, 0x098, 4, 8),
};
static const struct eqc_match_data eqc_eyeq6h_south_match_data = {
- .pll_count = ARRAY_SIZE(eqc_eyeq6h_south_plls),
- .plls = eqc_eyeq6h_south_plls,
-
- .div_count = ARRAY_SIZE(eqc_eyeq6h_south_divs),
- .divs = eqc_eyeq6h_south_divs,
+ .clk_count = ARRAY_SIZE(eqc_eyeq6h_south_clks),
+ .clks = eqc_eyeq6h_south_clks,
};
-static const struct eqc_pll eqc_eyeq6h_ddr0_plls[] = {
- { .index = 0, .name = "pll-ddr0", .reg64 = 0x074 },
+static const struct eqc_clock eqc_eyeq6h_ddr0_clks[] = {
+ PLL_FRACG(0, PARENT_BY_FWNAME, "pll-ddr0", "ref", 0x074),
};
static const struct eqc_match_data eqc_eyeq6h_ddr0_match_data = {
- .pll_count = ARRAY_SIZE(eqc_eyeq6h_ddr0_plls),
- .plls = eqc_eyeq6h_ddr0_plls,
+ .clk_count = ARRAY_SIZE(eqc_eyeq6h_ddr0_clks),
+ .clks = eqc_eyeq6h_ddr0_clks,
};
-static const struct eqc_pll eqc_eyeq6h_ddr1_plls[] = {
- { .index = 0, .name = "pll-ddr1", .reg64 = 0x074 },
+static const struct eqc_clock eqc_eyeq6h_ddr1_clks[] = {
+ PLL_FRACG(0, PARENT_BY_FWNAME, "pll-ddr1", "ref", 0x074),
};
static const struct eqc_match_data eqc_eyeq6h_ddr1_match_data = {
- .pll_count = ARRAY_SIZE(eqc_eyeq6h_ddr1_plls),
- .plls = eqc_eyeq6h_ddr1_plls,
+ .clk_count = ARRAY_SIZE(eqc_eyeq6h_ddr1_clks),
+ .clks = eqc_eyeq6h_ddr1_clks,
};
-static const struct eqc_pll eqc_eyeq6h_acc_plls[] = {
- { .index = EQ6HC_ACC_PLL_XNN, .name = "pll-xnn", .reg64 = 0x040 },
- { .index = EQ6HC_ACC_PLL_VMP, .name = "pll-vmp", .reg64 = 0x050 },
- { .index = EQ6HC_ACC_PLL_PMA, .name = "pll-pma", .reg64 = 0x05C },
- { .index = EQ6HC_ACC_PLL_MPC, .name = "pll-mpc", .reg64 = 0x068 },
- { .index = EQ6HC_ACC_PLL_NOC, .name = "pll-noc", .reg64 = 0x070 },
+static const struct eqc_clock eqc_eyeq6h_acc_clks[] = {
+ PLL_FRACG(EQ6HC_ACC_PLL_XNN, PARENT_BY_FWNAME, "pll-xnn", "ref", 0x040),
+ PLL_FRACG(EQ6HC_ACC_PLL_VMP, PARENT_BY_FWNAME, "pll-vmp", "ref", 0x050),
+ PLL_FRACG(EQ6HC_ACC_PLL_PMA, PARENT_BY_FWNAME, "pll-pma", "ref", 0x05C),
+ PLL_FRACG(EQ6HC_ACC_PLL_MPC, PARENT_BY_FWNAME, "pll-mpc", "ref", 0x068),
+ PLL_FRACG(EQ6HC_ACC_PLL_NOC, PARENT_BY_FWNAME, "pll-noc", "ref", 0x070),
};
static const struct eqc_match_data eqc_eyeq6h_acc_match_data = {
- .pll_count = ARRAY_SIZE(eqc_eyeq6h_acc_plls),
- .plls = eqc_eyeq6h_acc_plls,
+ .clk_count = ARRAY_SIZE(eqc_eyeq6h_acc_clks),
+ .clks = eqc_eyeq6h_acc_clks,
.reset_auxdev_name = "reset_acc",
};
@@ -914,38 +840,28 @@ static struct platform_driver eqc_driver = {
builtin_platform_driver(eqc_driver);
/* Required early for GIC timer. */
-static const struct eqc_pll eqc_eyeq6h_central_early_plls[] = {
- { .index = EQ6HC_CENTRAL_PLL_CPU, .name = "pll-cpu", .reg64 = 0x02C },
-};
+static const struct eqc_clock eqc_eyeq6h_central_early_clks[] = {
+ PLL_FRACG(EQ6HC_CENTRAL_PLL_CPU, PARENT_BY_FWNAME, "pll-cpu", "ref", 0x02C),
-static const struct eqc_fixed_factor eqc_eyeq6h_central_early_fixed_factors[] = {
- { EQ6HC_CENTRAL_CPU_OCC, "occ-cpu", 1, 1, EQ6HC_CENTRAL_PLL_CPU },
+ FF(EQ6HC_CENTRAL_CPU_OCC, EQ6HC_CENTRAL_PLL_CPU, "occ-cpu", NULL, 1, 1),
};
static const struct eqc_early_match_data eqc_eyeq6h_central_early_match_data __initconst = {
- .early_pll_count = ARRAY_SIZE(eqc_eyeq6h_central_early_plls),
- .early_plls = eqc_eyeq6h_central_early_plls,
-
- .early_fixed_factor_count = ARRAY_SIZE(eqc_eyeq6h_central_early_fixed_factors),
- .early_fixed_factors = eqc_eyeq6h_central_early_fixed_factors,
+ .early_clk_count = ARRAY_SIZE(eqc_eyeq6h_central_early_clks),
+ .early_clks = eqc_eyeq6h_central_early_clks,
};
/* Required early for UART. */
-static const struct eqc_pll eqc_eyeq6h_west_early_plls[] = {
- { .index = EQ6HC_WEST_PLL_PER, .name = "pll-west", .reg64 = 0x074 },
-};
+static const struct eqc_clock eqc_eyeq6h_west_early_clks[] = {
+ PLL_FRACG(EQ6HC_WEST_PLL_PER, PARENT_BY_FWNAME, "pll-west", "ref", 0x074),
-static const struct eqc_fixed_factor eqc_eyeq6h_west_early_fixed_factors[] = {
- { EQ6HC_WEST_PER_OCC, "west-per-occ", 1, 10, EQ6HC_WEST_PLL_PER },
- { EQ6HC_WEST_PER_UART, "west-per-uart", 1, 1, EQ6HC_WEST_PER_OCC },
+ FF(EQ6HC_WEST_PER_OCC, EQ6HC_WEST_PLL_PER, "west-per-occ", NULL, 1, 10),
+ FF(EQ6HC_WEST_PER_UART, EQ6HC_WEST_PER_OCC, "west-per-uart", NULL, 1, 1),
};
static const struct eqc_early_match_data eqc_eyeq6h_west_early_match_data __initconst = {
- .early_pll_count = ARRAY_SIZE(eqc_eyeq6h_west_early_plls),
- .early_plls = eqc_eyeq6h_west_early_plls,
-
- .early_fixed_factor_count = ARRAY_SIZE(eqc_eyeq6h_west_early_fixed_factors),
- .early_fixed_factors = eqc_eyeq6h_west_early_fixed_factors,
+ .early_clk_count = ARRAY_SIZE(eqc_eyeq6h_west_early_clks),
+ .early_clks = eqc_eyeq6h_west_early_clks,
};
static void __init eqc_early_init(struct device_node *np,
--
2.54.0
^ permalink raw reply related
* [PATCH v7 6/9] clk: eyeq: Introduce a generic clock type
From: Benoît Monin @ 2026-05-22 12:31 UTC (permalink / raw)
To: Vladimir Kondratiev, Gregory CLEMENT, Théo Lebrun,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd, Brian Masney, Philipp Zabel
Cc: Benoît Monin, Thomas Petazzoni, linux-mips, devicetree,
linux-kernel, linux-clk
In-Reply-To: <20260522-clk-eyeq7-v7-0-14ad6c2c5213@bootlin.com>
Currently, the clocks contained in the OLB are represented as three
separate structures: PLL, dividers and fixed factors. These clock objects
are stored in three separate arrays in the match data and registered in
a fixed order: first the PLL, then the dividers, and finally the fixed
factors. While this is sufficient for the clocks found in the OLB of
the EyeQ5 and EyeQ6, it does not allow declaring the more complex clock
interdependencies for those found in the OLB of the EyeQ7H.
We add a new type of clock represented by the struct eqc_clock that covers
all types of clocks found in OLB. It contains the clock index and its
name, alongside the parent clock index and name. The index refers to
the position in the array of clk_hw in the struct clk_hw_onecell_data
that is filled when registering the clocks. The parent name is optional
and can refer to the parent clock either via the device tree or via
its globally unique name. Two special index values are used to select
which type of lookup is done. The function eqc_fill_parent_data() fill
a clk_parent_data structure based on the parent index and name values.
The struct eqc_clock also contains two function pointers: .probe()
and .unregister(). The probe() function parses the eqc_clock structure,
registers a new clock as a clk_hw and adds it to the clk_hw_onecell_data
structure. It can be called during probe and early init. The unregister()
function unregisters the clk_hw. This patch adds the probe functions
for the PLLs, the dividers and the fixed factors found in the EyeQ OLB.
Finally, a union is also part of the eqc_clock structure to store the
data specific to each type of clock.
To help in declaring struct eqc_clock, three macros are added. They set
the correct function pointers for .probe() and .unregister() based on
the type of clock being declared.
An array of eqc_clock is added to the match data and early match
data. They are parsed during probe and early initialization respectively.
There is no user yet of the eqc_clock structure.
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
drivers/clk/clk-eyeq.c | 215 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 212 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index e4e690a12a23..7b8de08388d3 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -71,6 +71,13 @@
#define FRACG_PCSR1_DOWN_SPREAD BIT(11)
#define FRACG_PCSR1_FRAC_IN GENMASK(31, 12)
+/*
+ * Special index values to lookup a parent clock by its name
+ * from the device tree or by its globally unique name.
+ */
+#define PARENT_BY_FWNAME (-1)
+#define PARENT_BY_NAME (-2)
+
struct eqc_pll {
unsigned int index;
const char *name;
@@ -98,6 +105,33 @@ struct eqc_fixed_factor {
unsigned int parent;
};
+struct eqc_clock {
+ int index;
+ int parent_idx;
+ const char *name;
+ const char *parent_name;
+ int (*probe)(struct device *dev, struct device_node *np,
+ const struct eqc_clock *clk, void __iomem *base,
+ struct clk_hw_onecell_data *cells);
+ void (*unregister)(struct clk_hw *hw);
+ union {
+ struct {
+ unsigned int reg;
+ u8 shift;
+ u8 width;
+ unsigned long flags;
+ const struct clk_div_table *table;
+ } div;
+ struct {
+ unsigned int mult;
+ unsigned int div;
+ } ff;
+ struct {
+ unsigned int reg;
+ } pll;
+ };
+};
+
struct eqc_match_data {
unsigned int pll_count;
const struct eqc_pll *plls;
@@ -108,6 +142,9 @@ struct eqc_match_data {
unsigned int fixed_factor_count;
const struct eqc_fixed_factor *fixed_factors;
+ unsigned int clk_count;
+ const struct eqc_clock *clks;
+
const char *reset_auxdev_name;
const char *pinctrl_auxdev_name;
const char *eth_phy_auxdev_name;
@@ -122,6 +159,9 @@ struct eqc_early_match_data {
unsigned int early_fixed_factor_count;
const struct eqc_fixed_factor *early_fixed_factors;
+ unsigned int early_clk_count;
+ const struct eqc_clock *early_clks;
+
/*
* We want our of_xlate callback to EPROBE_DEFER instead of dev_err()
* and EINVAL. For that, we must know the total clock count.
@@ -336,6 +376,102 @@ static void eqc_auxdev_create_optional(struct device *dev, void __iomem *base,
}
}
+static int eqc_fill_parent_data(const struct eqc_clock *clk,
+ struct clk_hw_onecell_data *cells,
+ struct clk_parent_data *parent_data)
+{
+ int pidx = clk->parent_idx;
+
+ memset(parent_data, 0, sizeof(struct clk_parent_data));
+
+ if (pidx == PARENT_BY_FWNAME) {
+ /* lookup the parent clock by its fw_name */
+ parent_data->index = -1;
+ parent_data->fw_name = clk->parent_name;
+ } else if (pidx == PARENT_BY_NAME) {
+ /* lookup the parent clock by its global name */
+ parent_data->index = -1;
+ parent_data->name = clk->parent_name;
+ } else if (pidx >= 0 && pidx < cells->num && !IS_ERR(cells->hws[pidx])) {
+ /* get the parent hw directly */
+ parent_data->hw = cells->hws[pidx];
+ } else {
+ /* no parent lookup by index: explicitly fail */
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int eqc_probe_divider(struct device *dev, struct device_node *np,
+ const struct eqc_clock *clk, void __iomem *base,
+ struct clk_hw_onecell_data *cells)
+{
+ struct clk_parent_data parent_data;
+ struct clk_hw *hw;
+ int ret;
+
+ ret = eqc_fill_parent_data(clk, cells, &parent_data);
+ if (ret)
+ return ret;
+
+ hw = clk_hw_register_divider_table_parent_data(dev, clk->name,
+ &parent_data, 0, base + clk->div.reg, clk->div.shift,
+ clk->div.width, clk->div.flags, clk->div.table, NULL);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
+ cells->hws[clk->index] = hw;
+ return 0;
+}
+
+static int eqc_probe_fixed_factor(struct device *dev, struct device_node *np,
+ const struct eqc_clock *clk, void __iomem *base,
+ struct clk_hw_onecell_data *cells)
+{
+ struct clk_parent_data parent_data;
+ struct clk_hw *hw;
+ int ret;
+
+ ret = eqc_fill_parent_data(clk, cells, &parent_data);
+ if (ret)
+ return ret;
+
+ hw = clk_hw_register_fixed_factor_pdata(dev, np, clk->name, &parent_data, 0,
+ clk->ff.mult, clk->ff.div, 0, 0);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
+ cells->hws[clk->index] = hw;
+ return 0;
+}
+
+static int eqc_probe_pll_fracg(struct device *dev, struct device_node *np,
+ const struct eqc_clock *clk, void __iomem *base,
+ struct clk_hw_onecell_data *cells)
+{
+ struct clk_parent_data parent_data;
+ unsigned long mult, div, acc;
+ struct clk_hw *hw;
+ int ret;
+
+ ret = eqc_pll_parse_fracg(base + clk->pll.reg, &mult, &div, &acc);
+ if (ret)
+ return ret;
+
+ ret = eqc_fill_parent_data(clk, cells, &parent_data);
+ if (ret)
+ return ret;
+
+ hw = clk_hw_register_fixed_factor_pdata(dev, np, clk->name, &parent_data, 0, mult,
+ div, acc, CLK_FIXED_FACTOR_FIXED_ACCURACY);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
+ cells->hws[clk->index] = hw;
+ return 0;
+}
+
static int eqc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -345,6 +481,7 @@ static int eqc_probe(struct platform_device *pdev)
unsigned int i, clk_count;
struct resource *res;
void __iomem *base;
+ int ret;
data = device_get_match_data(dev);
if (!data)
@@ -363,11 +500,12 @@ static int eqc_probe(struct platform_device *pdev)
eqc_auxdev_create_optional(dev, base, data->pinctrl_auxdev_name);
eqc_auxdev_create_optional(dev, base, data->eth_phy_auxdev_name);
- if (data->pll_count + data->div_count + data->fixed_factor_count == 0)
+ if (data->pll_count + data->div_count + data->fixed_factor_count + data->clk_count == 0)
return 0; /* Zero clocks, we are done. */
clk_count = data->pll_count + data->div_count +
- data->fixed_factor_count + data->early_clk_count;
+ data->fixed_factor_count + data->clk_count +
+ data->early_clk_count;
cells = kzalloc_flex(*cells, hws, clk_count);
if (!cells)
return -ENOMEM;
@@ -384,9 +522,59 @@ static int eqc_probe(struct platform_device *pdev)
eqc_probe_init_fixed_factors(dev, data, cells);
+ for (i = 0; i < data->clk_count; i++) {
+ const struct eqc_clock *clk = &data->clks[i];
+
+ if (clk->probe)
+ ret = clk->probe(dev, NULL, clk, base, cells);
+ else
+ ret = -EINVAL;
+ if (ret)
+ dev_warn(dev, "failed probing clock %s: %d\n", clk->name, ret);
+ }
+
return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, cells);
}
+#define DIV(_index, _parent_idx, _name, _parent_name, \
+ _reg, _shift, _width) \
+ { \
+ .index = _index, \
+ .parent_idx = _parent_idx, \
+ .name = _name, \
+ .parent_name = _parent_name, \
+ .probe = eqc_probe_divider, \
+ .unregister = clk_hw_unregister_divider, \
+ .div.reg = _reg, \
+ .div.shift = _shift, \
+ .div.width = _width, \
+ .div.flags = CLK_DIVIDER_EVEN_INTEGERS, \
+ .div.table = NULL, \
+ }
+
+#define FF(_index, _parent_idx, _name, _parent_name, _mult, _div) \
+ { \
+ .index = _index, \
+ .parent_idx = _parent_idx, \
+ .name = _name, \
+ .parent_name = _parent_name, \
+ .probe = eqc_probe_fixed_factor, \
+ .unregister = clk_hw_unregister_fixed_factor, \
+ .ff.mult = _mult, \
+ .ff.div = _div, \
+ }
+
+#define PLL_FRACG(_index, _parent_idx, _name, _parent_name, _reg) \
+ { \
+ .index = _index, \
+ .parent_idx = _parent_idx, \
+ .name = _name, \
+ .parent_name = _parent_name, \
+ .probe = eqc_probe_pll_fracg, \
+ .unregister = clk_hw_unregister_fixed_factor, \
+ .pll.reg = _reg, \
+ }
+
/* Required early for GIC timer (pll-cpu) and UARTs (pll-per). */
static const struct eqc_pll eqc_eyeq5_early_plls[] = {
{ .index = EQ5C_PLL_CPU, .name = "pll-cpu", .reg64 = 0x02C },
@@ -769,7 +957,7 @@ static void __init eqc_early_init(struct device_node *np,
int ret;
clk_count = early_data->early_pll_count + early_data->early_fixed_factor_count +
- early_data->late_clk_count;
+ early_data->early_clk_count + early_data->late_clk_count;
cells = kzalloc_flex(*cells, hws, clk_count);
if (!cells) {
ret = -ENOMEM;
@@ -831,6 +1019,19 @@ static void __init eqc_early_init(struct device_node *np,
}
}
+ for (i = 0; i < early_data->early_clk_count; i++) {
+ const struct eqc_clock *clk = &early_data->early_clks[i];
+
+ if (clk->probe)
+ ret = clk->probe(NULL, np, clk, base, cells);
+ else
+ ret = -EINVAL;
+ if (ret) {
+ pr_err("failed registering %s\n", clk->name);
+ goto err;
+ }
+ }
+
ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, cells);
if (ret) {
pr_err("failed registering clk provider: %d\n", ret);
@@ -860,6 +1061,14 @@ static void __init eqc_early_init(struct device_node *np,
clk_hw_unregister_fixed_factor(hw);
}
+ for (i = 0; i < early_data->early_clk_count; i++) {
+ const struct eqc_clock *clk = &early_data->early_clks[i];
+ struct clk_hw *hw = cells->hws[clk->index];
+
+ if (!IS_ERR_OR_NULL(hw) && clk->unregister)
+ clk->unregister(hw);
+ }
+
kfree(cells);
}
}
--
2.54.0
^ permalink raw reply related
* [PATCH v7 2/9] reset: eyeq: Add EyeQ7H compatibles
From: Benoît Monin @ 2026-05-22 12:31 UTC (permalink / raw)
To: Vladimir Kondratiev, Gregory CLEMENT, Théo Lebrun,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd, Brian Masney, Philipp Zabel
Cc: Benoît Monin, Thomas Petazzoni, linux-mips, devicetree,
linux-kernel, linux-clk, Sari Khoury
In-Reply-To: <20260522-clk-eyeq7-v7-0-14ad6c2c5213@bootlin.com>
Add support for the reset controllers found in the EyeQ7H OLB. For
this, three new types of reset domain are added to the driver.
The EQR_EYEQ7H_ACRP reset domain is similar to the EQR_EYEQ5_ACRP domain,
sharing the same register address calculation but featuring a different
register layout. When writing to the register, MBIST bits are set to
zero to ensure normal device operation.
The EQR_EYEQ7H_CFG reset domain is similar to the EQR_EYEQ5_PCIE domain,
with two bits per device instead of one. These two bits, clock enable and
nreset, are kept in sync when asserting and deasserting the device reset.
The EQR_EYEQ7H_ACC reset domain is similar to the EQR_EYEQ6H_SARCR domain,
with a different registers layout and no busy waiting.
Alongside these new reset domains, add EQR_NB_DOM_TYPES at the end of the
eqr_domain_type enumeration and use it to declare the eqr_timings array.
This ensures that we have the expected number of entries when using the
timings in eqr_busy_wait_locked().
Add and order the auxiliary_device_id entries in eqr_id_table.
Originally-by: Sari Khoury <sari.khoury@mobileye.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
drivers/reset/reset-eyeq.c | 268 +++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 259 insertions(+), 9 deletions(-)
diff --git a/drivers/reset/reset-eyeq.c b/drivers/reset/reset-eyeq.c
index 1a3857983897..381237d50f06 100644
--- a/drivers/reset/reset-eyeq.c
+++ b/drivers/reset/reset-eyeq.c
@@ -1,10 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Reset driver for the Mobileye EyeQ5, EyeQ6L and EyeQ6H platforms.
+ * Reset driver for the Mobileye EyeQ5, EyeQ6L, EyeQ6H and EyeQ7H platforms.
*
* Controllers live in a shared register region called OLB. EyeQ5 and EyeQ6L
* have a single OLB instance for a single reset controller. EyeQ6H has seven
- * OLB instances; three host reset controllers.
+ * OLB instances; three host reset controllers. EyeQ7H has fourteen OLB instances;
+ * eleven host reset controllers.
*
* Each reset controller has one or more domain. Domains are of a given type
* (see enum eqr_domain_type), with a valid offset mask (up to 32 resets per
@@ -73,6 +74,40 @@
* 9. PMA0 10. PMA1 11. MPC0 12. MPC1
* 13. MPC2 14. MPC3 15. PERIPH
*
+ * Known resets in EyeQ7H acc domain 0 (type EQR_EYEQ7H_ACRP)
+ * 1. VMP0 2. XVMP1 3. VMP2 4. VMP3
+ * 5. MPC0 6. MPC1 7. PMA0 8. PMA1
+ *
+ * Known resets in EyeQ7H acc domain 1 (type EQR_EYEQ7H_ACC)
+ * 1. NCORE0 2. NCORE1 3. NCORE0_M 4. NCORE1_M
+ * 5. NCORE_NOC 6. VMP_NOC 7. MPC_NOC 8. PMA_NOC
+ *
+ * Known resets in EyeQ7H ddr (type EQR_EYEQ7H_CFG)
+ * 0. APB 2. DMI 3. DFI 4. PHY_SMS
+ * 5. CTL_SMS
+ *
+ * Known resets in EyeQ7H east (type EQR_EYEQ7H_CFG)
+ * 0. ISP 2. VEU 3. LBIST
+ *
+ * Known resets in EyeQ7H periph (type EQR_EYEQ6H_SARCR)
+ * 0. gpio 1.EXT TIMER 3.UART 4. SPI
+ * 5. I2C0 6. I2C1 7.I2C2 8. I2S
+ *
+ * Known resets in EyeQ7H south (type EQR_EYEQ7H_CFG)
+ * 0. PCI_PHY 1. PCI_CTL 2. S_NOC 3. GBE_PHY
+ * 4. GBE_CTL 5. XSPI 6. UFS 7. VDIO
+ *
+ * Known resets in EyeQ7H west (type EQR_EYEQ7H_CFG)
+ * 0. GPU 1. CAU 2. LBIST 3. GPU_LBIST
+ *
+ * Known resets in EyeQ7H xnn domain 0 (type EQR_EYEQ7H_ACRP)
+ * 1. XNN0 2. XNN1 3.XNN2
+ *
+ * Known resets in EyeQ7H xnn domain 1 (type EQR_EYEQ7H_ACC)
+ * 1. XNN0 2. XNN1 3. XNN2 4. XNN3
+ * 5. NCORE 6. I2_0 7. I2_1 8. SMS_0
+ * 9. SMS_1
+ *
* Abbreviations:
* - PMA: Programmable Macro Array
* - MPC: Multi-threaded Processing Clusters
@@ -114,6 +149,11 @@ enum eqr_domain_type {
EQR_EYEQ5_ACRP,
EQR_EYEQ5_PCIE,
EQR_EYEQ6H_SARCR,
+ EQR_EYEQ7H_ACC,
+ EQR_EYEQ7H_ACRP,
+ EQR_EYEQ7H_CFG,
+
+ EQR_NB_DOM_TYPES /* number of domain types, keep at the end */
};
/*
@@ -138,16 +178,34 @@ enum eqr_domain_type {
#define EQR_EYEQ6H_SARCR_RST_STATUS (0x008)
#define EQR_EYEQ6H_SARCR_CLK_REQUEST (0x00C)
+/*
+ * Domain type EQR_EYEQ7H_ACC register offsets.
+ */
+#define EQR_EYEQ7H_ACC_CLK_EN (0x000)
+#define EQR_EYEQ7H_ACC_RST_EN (0x004)
+
+/*
+ * Domain type EQR_EYEQ7H_ACRP register masks.
+ * Registers are: base + 4 * offset.
+ */
+#define EQR_EYEQ7H_ACRP_PD_REQ BIT(0)
+#define EQR_EYEQ7H_ACRP_MBIST_CFG GENMASK(3, 1)
+#define EQR_EYEQ7H_ACRP_ST_POWER_DOWN BIT(13)
+#define EQR_EYEQ7H_ACRP_ST_ACTIVE BIT(14)
+
struct eqr_busy_wait_timings {
unsigned long sleep_us;
unsigned long timeout_us;
};
-static const struct eqr_busy_wait_timings eqr_timings[] = {
+static const struct eqr_busy_wait_timings eqr_timings[EQR_NB_DOM_TYPES] = {
[EQR_EYEQ5_SARCR] = {1, 10},
[EQR_EYEQ5_ACRP] = {1, 40 * USEC_PER_MSEC}, /* LBIST implies long timeout. */
/* EQR_EYEQ5_PCIE does no busy waiting. */
[EQR_EYEQ6H_SARCR] = {1, 400},
+ /* EQR_EYEQ7H_ACC does no busy waiting. */
+ [EQR_EYEQ7H_ACRP] = {1, 40 * USEC_PER_MSEC},
+ /* EQR_EYEQ7H_CFG does no busy waiting. */
};
#define EQR_MAX_DOMAIN_COUNT 3
@@ -221,10 +279,6 @@ static int eqr_busy_wait_locked(struct eqr_private *priv, struct device *dev,
sleep_us, timeout_us);
break;
- case EQR_EYEQ5_PCIE:
- ret = 0; /* No busy waiting. */
- break;
-
case EQR_EYEQ6H_SARCR:
/*
* Wait until both bits change:
@@ -241,6 +295,23 @@ static int eqr_busy_wait_locked(struct eqr_private *priv, struct device *dev,
&rst_status, &clk_status);
break;
+ case EQR_EYEQ7H_ACRP:
+ reg = base + 4 * offset;
+ if (assert)
+ mask = EQR_EYEQ7H_ACRP_ST_POWER_DOWN;
+ else
+ mask = EQR_EYEQ7H_ACRP_ST_ACTIVE;
+
+ ret = readl_poll_timeout(reg, val, !!(val & mask),
+ sleep_us, timeout_us);
+ break;
+
+ case EQR_EYEQ5_PCIE:
+ case EQR_EYEQ7H_ACC:
+ case EQR_EYEQ7H_CFG:
+ ret = 0; /* No busy waiting. */
+ break;
+
default:
WARN_ON(1);
ret = -EINVAL;
@@ -285,6 +356,28 @@ static void eqr_assert_locked(struct eqr_private *priv, u32 domain, u32 offset)
writel(val, base + EQR_EYEQ6H_SARCR_CLK_REQUEST);
break;
+ case EQR_EYEQ7H_ACC:
+ /* RST_REQUEST and CLK_REQUEST must be kept in sync. */
+ val = readl(base + EQR_EYEQ7H_ACC_RST_EN);
+ val &= ~BIT(offset);
+ writel(val, base + EQR_EYEQ7H_ACC_RST_EN);
+ writel(val, base + EQR_EYEQ7H_ACC_CLK_EN);
+ break;
+
+ case EQR_EYEQ7H_ACRP:
+ /* set powerdown and leave MBIST bits at zero */
+ reg = base + 4 * offset;
+ val = readl(reg) & ~EQR_EYEQ7H_ACRP_MBIST_CFG;
+ writel(val | EQR_EYEQ7H_ACRP_PD_REQ, reg);
+ break;
+
+ case EQR_EYEQ7H_CFG:
+ /* clear clock enable and NRESET bits */
+ val = readl(base);
+ val &= ~GENMASK(2 * offset + 1, 2 * offset);
+ writel(val, base);
+ break;
+
default:
WARN_ON(1);
break;
@@ -339,6 +432,28 @@ static void eqr_deassert_locked(struct eqr_private *priv, u32 domain,
writel(val, base + EQR_EYEQ6H_SARCR_CLK_REQUEST);
break;
+ case EQR_EYEQ7H_ACC:
+ /* RST_REQUEST and CLK_REQUEST must be kept in sync. */
+ val = readl(base + EQR_EYEQ7H_ACC_RST_EN);
+ val |= BIT(offset);
+ writel(val, base + EQR_EYEQ7H_ACC_RST_EN);
+ writel(val, base + EQR_EYEQ7H_ACC_CLK_EN);
+ break;
+
+ case EQR_EYEQ7H_ACRP:
+ /* clear powerdown and leave MBIST bits at zero */
+ reg = base + 4 * offset;
+ val = readl(reg) & ~EQR_EYEQ7H_ACRP_MBIST_CFG;
+ writel(val & ~EQR_EYEQ7H_ACRP_PD_REQ, reg);
+ break;
+
+ case EQR_EYEQ7H_CFG:
+ /* set clock enable and NRESET bits */
+ val = readl(base);
+ val |= GENMASK(2 * offset + 1, 2 * offset);
+ writel(val, base);
+ break;
+
default:
WARN_ON(1);
break;
@@ -385,6 +500,14 @@ static int eqr_status(struct reset_controller_dev *rcdev, unsigned long id)
case EQR_EYEQ6H_SARCR:
reg = base + EQR_EYEQ6H_SARCR_RST_STATUS;
return !(readl(reg) & BIT(offset));
+ case EQR_EYEQ7H_ACC:
+ reg = base + EQR_EYEQ7H_ACC_RST_EN;
+ return !(readl(reg) & BIT(offset));
+ case EQR_EYEQ7H_ACRP:
+ reg = base + 4 * offset;
+ return !(readl(reg) & EQR_EYEQ7H_ACRP_ST_ACTIVE);
+ case EQR_EYEQ7H_CFG:
+ return !(readl(base) & BIT(2 * offset));
default:
return -EINVAL;
}
@@ -558,6 +681,113 @@ static const struct eqr_match_data eqr_eyeq6h_acc_data = {
.domains = eqr_eyeq6h_acc_domains,
};
+static const struct eqr_domain_descriptor eqr_eyeq7h_acc_domains[] = {
+ {
+ .type = EQR_EYEQ7H_ACRP,
+ .valid_mask = 0xFF,
+ .offset = 0x000,
+ },
+ {
+ .type = EQR_EYEQ7H_ACC,
+ .valid_mask = 0xFF,
+ .offset = 0x060,
+ },
+};
+
+static const struct eqr_match_data eqr_eyeq7h_acc_data = {
+ .domain_count = ARRAY_SIZE(eqr_eyeq7h_acc_domains),
+ .domains = eqr_eyeq7h_acc_domains,
+};
+
+static const struct eqr_domain_descriptor eqr_eyeq7h_ddr_domains[] = {
+ {
+ .type = EQR_EYEQ7H_CFG,
+ .valid_mask = 0x1F,
+ .offset = 0x008,
+ },
+};
+
+static const struct eqr_match_data eqr_eyeq7h_ddr_data = {
+ .domain_count = ARRAY_SIZE(eqr_eyeq7h_ddr_domains),
+ .domains = eqr_eyeq7h_ddr_domains,
+};
+
+static const struct eqr_domain_descriptor eqr_eyeq7h_east_domains[] = {
+ {
+ .type = EQR_EYEQ7H_CFG,
+ .valid_mask = 0x7,
+ .offset = 0x060,
+ },
+};
+
+static const struct eqr_match_data eqr_eyeq7h_east_data = {
+ .domain_count = ARRAY_SIZE(eqr_eyeq7h_east_domains),
+ .domains = eqr_eyeq7h_east_domains,
+};
+
+/* Periph OLBs each have an instance. */
+static const struct eqr_domain_descriptor eqr_eyeq7h_per_domains[] = {
+ {
+ .type = EQR_EYEQ6H_SARCR,
+ .valid_mask = 0xFF,
+ .offset = 0x030,
+ },
+};
+
+static const struct eqr_match_data eqr_eyeq7h_per_data = {
+ .domain_count = ARRAY_SIZE(eqr_eyeq7h_per_domains),
+ .domains = eqr_eyeq7h_per_domains,
+};
+
+static const struct eqr_domain_descriptor eqr_eyeq7h_south_domains[] = {
+ {
+ .type = EQR_EYEQ7H_CFG,
+ .valid_mask = 0x1F,
+ .offset = 0x070,
+ },
+ {
+ .type = EQR_EYEQ7H_CFG,
+ .valid_mask = 0x7,
+ .offset = 0x074,
+ },
+};
+
+static const struct eqr_match_data eqr_eyeq7h_south_data = {
+ .domain_count = ARRAY_SIZE(eqr_eyeq7h_south_domains),
+ .domains = eqr_eyeq7h_south_domains,
+};
+
+static const struct eqr_domain_descriptor eqr_eyeq7h_west_domains[] = {
+ {
+ .type = EQR_EYEQ7H_CFG,
+ .valid_mask = 0xf,
+ .offset = 0x068,
+ },
+};
+
+static const struct eqr_match_data eqr_eyeq7h_west_data = {
+ .domain_count = ARRAY_SIZE(eqr_eyeq7h_west_domains),
+ .domains = eqr_eyeq7h_west_domains,
+};
+
+static const struct eqr_domain_descriptor eqr_eyeq7h_xnn_domains[] = {
+ {
+ .type = EQR_EYEQ7H_ACRP,
+ .valid_mask = 0x7,
+ .offset = 0x000,
+ },
+ {
+ .type = EQR_EYEQ7H_ACC,
+ .valid_mask = 0x1FF,
+ .offset = 0x060,
+ },
+};
+
+static const struct eqr_match_data eqr_eyeq7h_xnn_data = {
+ .domain_count = ARRAY_SIZE(eqr_eyeq7h_xnn_domains),
+ .domains = eqr_eyeq7h_xnn_domains,
+};
+
/*
* Table describes OLB system-controller compatibles.
* It does not get used to match against devicetree node.
@@ -569,15 +799,35 @@ static const struct of_device_id eqr_match_table[] = {
{ .compatible = "mobileye,eyeq6h-west-olb", .data = &eqr_eyeq6h_we_data },
{ .compatible = "mobileye,eyeq6h-east-olb", .data = &eqr_eyeq6h_we_data },
{ .compatible = "mobileye,eyeq6h-acc-olb", .data = &eqr_eyeq6h_acc_data },
+ { .compatible = "mobileye,eyeq7h-acc0-olb", .data = &eqr_eyeq7h_acc_data },
+ { .compatible = "mobileye,eyeq7h-acc1-olb", .data = &eqr_eyeq7h_acc_data },
+ { .compatible = "mobileye,eyeq7h-ddr0-olb", .data = &eqr_eyeq7h_ddr_data },
+ { .compatible = "mobileye,eyeq7h-ddr1-olb", .data = &eqr_eyeq7h_ddr_data },
+ { .compatible = "mobileye,eyeq7h-east-olb", .data = &eqr_eyeq7h_east_data },
+ { .compatible = "mobileye,eyeq7h-periph-east-olb", .data = &eqr_eyeq7h_per_data },
+ { .compatible = "mobileye,eyeq7h-periph-west-olb", .data = &eqr_eyeq7h_per_data },
+ { .compatible = "mobileye,eyeq7h-south-olb", .data = &eqr_eyeq7h_south_data },
+ { .compatible = "mobileye,eyeq7h-west-olb", .data = &eqr_eyeq7h_west_data },
+ { .compatible = "mobileye,eyeq7h-xnn0-olb", .data = &eqr_eyeq7h_xnn_data },
+ { .compatible = "mobileye,eyeq7h-xnn1-olb", .data = &eqr_eyeq7h_xnn_data },
{}
};
MODULE_DEVICE_TABLE(of, eqr_match_table);
static const struct auxiliary_device_id eqr_id_table[] = {
{ .name = "clk_eyeq.reset" },
- { .name = "clk_eyeq.reset_west" },
- { .name = "clk_eyeq.reset_east" },
{ .name = "clk_eyeq.reset_acc" },
+ { .name = "clk_eyeq.reset_acc0" },
+ { .name = "clk_eyeq.reset_acc1" },
+ { .name = "clk_eyeq.reset_ddr0" },
+ { .name = "clk_eyeq.reset_ddr1" },
+ { .name = "clk_eyeq.reset_east" },
+ { .name = "clk_eyeq.reset_periph_east" },
+ { .name = "clk_eyeq.reset_periph_west" },
+ { .name = "clk_eyeq.reset_south" },
+ { .name = "clk_eyeq.reset_west" },
+ { .name = "clk_eyeq.reset_xnn0" },
+ { .name = "clk_eyeq.reset_xnn1" },
{}
};
MODULE_DEVICE_TABLE(auxiliary, eqr_id_table);
--
2.54.0
^ permalink raw reply related
* [PATCH v7 5/9] clk: eyeq: Prefix the PLL registers with the PLL type
From: Benoît Monin @ 2026-05-22 12:31 UTC (permalink / raw)
To: Vladimir Kondratiev, Gregory CLEMENT, Théo Lebrun,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd, Brian Masney, Philipp Zabel
Cc: Benoît Monin, Thomas Petazzoni, linux-mips, devicetree,
linux-kernel, linux-clk
In-Reply-To: <20260522-clk-eyeq7-v7-0-14ad6c2c5213@bootlin.com>
Rename the PLL registers to make room for other PLL types that are
present in the eyeQ7H.
Move the access to the PLL register inside the function parsing it
as both call sites were doing the same thing.
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
drivers/clk/clk-eyeq.c | 76 +++++++++++++++++++++++---------------------------
1 file changed, 35 insertions(+), 41 deletions(-)
diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index d9303c2c7aa5..e4e690a12a23 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -48,28 +48,28 @@
#include <dt-bindings/clock/mobileye,eyeq6lplus-clk.h>
/* In frac mode, it enables fractional noise canceling DAC. Else, no function. */
-#define PCSR0_DAC_EN BIT(0)
+#define FRACG_PCSR0_DAC_EN BIT(0)
/* Fractional or integer mode */
-#define PCSR0_DSM_EN BIT(1)
-#define PCSR0_PLL_EN BIT(2)
+#define FRACG_PCSR0_DSM_EN BIT(1)
+#define FRACG_PCSR0_PLL_EN BIT(2)
/* All clocks output held at 0 */
-#define PCSR0_FOUTPOSTDIV_EN BIT(3)
-#define PCSR0_POST_DIV1 GENMASK(6, 4)
-#define PCSR0_POST_DIV2 GENMASK(9, 7)
-#define PCSR0_REF_DIV GENMASK(15, 10)
-#define PCSR0_INTIN GENMASK(27, 16)
-#define PCSR0_BYPASS BIT(28)
+#define FRACG_PCSR0_FOUTPOSTDIV_EN BIT(3)
+#define FRACG_PCSR0_POST_DIV1 GENMASK(6, 4)
+#define FRACG_PCSR0_POST_DIV2 GENMASK(9, 7)
+#define FRACG_PCSR0_REF_DIV GENMASK(15, 10)
+#define FRACG_PCSR0_INTIN GENMASK(27, 16)
+#define FRACG_PCSR0_BYPASS BIT(28)
/* Bits 30..29 are reserved */
-#define PCSR0_PLL_LOCKED BIT(31)
+#define FRACG_PCSR0_PLL_LOCKED BIT(31)
-#define PCSR1_RESET BIT(0)
-#define PCSR1_SSGC_DIV GENMASK(4, 1)
+#define FRACG_PCSR1_RESET BIT(0)
+#define FRACG_PCSR1_SSGC_DIV GENMASK(4, 1)
/* Spread amplitude (% = 0.1 * SPREAD[4:0]) */
-#define PCSR1_SPREAD GENMASK(9, 5)
-#define PCSR1_DIS_SSCG BIT(10)
+#define FRACG_PCSR1_SPREAD GENMASK(9, 5)
+#define FRACG_PCSR1_DIS_SSCG BIT(10)
/* Down-spread or center-spread */
-#define PCSR1_DOWN_SPREAD BIT(11)
-#define PCSR1_FRAC_IN GENMASK(31, 12)
+#define FRACG_PCSR1_DOWN_SPREAD BIT(11)
+#define FRACG_PCSR1_FRAC_IN GENMASK(31, 12)
struct eqc_pll {
unsigned int index;
@@ -162,34 +162,40 @@ static void eqc_pll_downshift_factors(unsigned long *mult, unsigned long *div)
*div >>= shift;
}
-static int eqc_pll_parse_registers(u32 r0, u32 r1, unsigned long *mult,
- unsigned long *div, unsigned long *acc)
+static int eqc_pll_parse_fracg(void __iomem *base, unsigned long *mult,
+ unsigned long *div, unsigned long *acc)
{
unsigned long spread;
+ u32 r0, r1;
+ u64 val;
- if (r0 & PCSR0_BYPASS) {
+ val = readq(base);
+ r0 = val;
+ r1 = val >> 32;
+
+ if (r0 & FRACG_PCSR0_BYPASS) {
*mult = 1;
*div = 1;
*acc = 0;
return 0;
}
- if (!(r0 & PCSR0_PLL_LOCKED))
+ if (!(r0 & FRACG_PCSR0_PLL_LOCKED))
return -EINVAL;
- *mult = FIELD_GET(PCSR0_INTIN, r0);
- *div = FIELD_GET(PCSR0_REF_DIV, r0);
+ *mult = FIELD_GET(FRACG_PCSR0_INTIN, r0);
+ *div = FIELD_GET(FRACG_PCSR0_REF_DIV, r0);
/* Fractional mode, in 2^20 (0x100000) parts. */
- if (r0 & PCSR0_DSM_EN) {
+ if (r0 & FRACG_PCSR0_DSM_EN) {
*div *= (1ULL << 20);
- *mult = *mult * (1ULL << 20) + FIELD_GET(PCSR1_FRAC_IN, r1);
+ *mult = *mult * (1ULL << 20) + FIELD_GET(FRACG_PCSR1_FRAC_IN, r1);
}
if (!*mult || !*div)
return -EINVAL;
- if (r1 & (PCSR1_RESET | PCSR1_DIS_SSCG)) {
+ if (r1 & (FRACG_PCSR1_RESET | FRACG_PCSR1_DIS_SSCG)) {
*acc = 0;
return 0;
}
@@ -204,10 +210,10 @@ static int eqc_pll_parse_registers(u32 r0, u32 r1, unsigned long *mult,
*
* Care is taken to avoid overflowing or losing precision.
*/
- spread = FIELD_GET(PCSR1_SPREAD, r1);
+ spread = FIELD_GET(FRACG_PCSR1_SPREAD, r1);
*acc = DIV_ROUND_CLOSEST(spread * 1000000000, 1024 * 2);
- if (r1 & PCSR1_DOWN_SPREAD) {
+ if (r1 & FRACG_PCSR1_DOWN_SPREAD) {
/*
* Downspreading: the central frequency is half a
* spread lower.
@@ -232,18 +238,12 @@ static void eqc_probe_init_plls(struct device *dev, const struct eqc_match_data
const struct eqc_pll *pll;
struct clk_hw *hw;
unsigned int i;
- u32 r0, r1;
- u64 val;
int ret;
for (i = 0; i < data->pll_count; i++) {
pll = &data->plls[i];
- val = readq(base + pll->reg64);
- r0 = val;
- r1 = val >> 32;
-
- ret = eqc_pll_parse_registers(r0, r1, &mult, &div, &acc);
+ ret = eqc_pll_parse_fracg(base + pll->reg64, &mult, &div, &acc);
if (ret) {
dev_warn(dev, "failed parsing state of %s\n", pll->name);
cells->hws[pll->index] = ERR_PTR(ret);
@@ -799,14 +799,8 @@ static void __init eqc_early_init(struct device_node *np,
const struct eqc_pll *pll = &early_data->early_plls[i];
unsigned long mult, div, acc;
struct clk_hw *hw;
- u32 r0, r1;
- u64 val;
- val = readq(base + pll->reg64);
- r0 = val;
- r1 = val >> 32;
-
- ret = eqc_pll_parse_registers(r0, r1, &mult, &div, &acc);
+ ret = eqc_pll_parse_fracg(base + pll->reg64, &mult, &div, &acc);
if (ret) {
pr_err("failed parsing state of %s\n", pll->name);
goto err;
--
2.54.0
^ permalink raw reply related
* [PATCH v7 1/9] dt-bindings: soc: mobileye: Add EyeQ7H OLB
From: Benoît Monin @ 2026-05-22 12:31 UTC (permalink / raw)
To: Vladimir Kondratiev, Gregory CLEMENT, Théo Lebrun,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd, Brian Masney, Philipp Zabel
Cc: Benoît Monin, Thomas Petazzoni, linux-mips, devicetree,
linux-kernel, linux-clk, Krzysztof Kozlowski
In-Reply-To: <20260522-clk-eyeq7-v7-0-14ad6c2c5213@bootlin.com>
The Other Logic Blocks (OLB) found in Mobileye SoCs contain hardware
sub-functions grouped in a logical device.
The EyeQ7H features 14 such OLB. The main differences with the previous
generation of SoC are that some blocks have two clock sources instead
of one and that the clock source can be the one of the clock output of
another OLB instead of the main oscillator.
For the blocks with a single parent clock, the name of that clock is
"ref", similar to what is done for the OLB of the previous SoC. The
blocks with two parent clocks use either "ref" for the main oscillator,
"ref_100p0" for a 100MHz reference clock or "ref_106p6" for 106.6MHz
reference clock.
Some OLB also contain a reset controller with one or more reset domain,
like the blocks found in the EyeQ6H.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
.../bindings/soc/mobileye/mobileye,eyeq7h-olb.yaml | 192 +++++++++++++++++++++
include/dt-bindings/clock/mobileye,eyeq7h-clk.h | 119 +++++++++++++
2 files changed, 311 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq7h-olb.yaml b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq7h-olb.yaml
new file mode 100644
index 000000000000..2958ca9e330b
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq7h-olb.yaml
@@ -0,0 +1,192 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq7h-olb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mobileye EyeQ7H SoC system controller
+
+maintainers:
+ - Benoît Monin <benoit.monin@bootlin.com>
+ - Grégory Clement <gregory.clement@bootlin.com>
+ - Théo Lebrun <theo.lebrun@bootlin.com>
+ - Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
+
+description:
+ OLB ("Other Logic Block") is a hardware system controller grouping
+ smaller blocks. Clocks and resets are generated by those blocks and
+ used by internal controllers of the SoC. The EyeQ7H SoC hosts 14
+ different OLB.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mobileye,eyeq7h-acc0-olb
+ - mobileye,eyeq7h-acc1-olb
+ - mobileye,eyeq7h-ddr0-olb
+ - mobileye,eyeq7h-ddr1-olb
+ - mobileye,eyeq7h-east-olb
+ - mobileye,eyeq7h-mips0-olb
+ - mobileye,eyeq7h-mips1-olb
+ - mobileye,eyeq7h-mips2-olb
+ - mobileye,eyeq7h-periph-east-olb
+ - mobileye,eyeq7h-periph-west-olb
+ - mobileye,eyeq7h-south-olb
+ - mobileye,eyeq7h-west-olb
+ - mobileye,eyeq7h-xnn0-olb
+ - mobileye,eyeq7h-xnn1-olb
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ '#reset-cells':
+ description:
+ First cell is domain and optional if compatible has a single reset domain.
+ Second cell is reset index inside that domain.
+ enum: [ 1, 2 ]
+
+ '#clock-cells':
+ const: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - clocks
+ - clock-names
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mobileye,eyeq7h-ddr0-olb
+ - mobileye,eyeq7h-ddr1-olb
+ - mobileye,eyeq7h-mips0-olb
+ - mobileye,eyeq7h-mips1-olb
+ - mobileye,eyeq7h-mips2-olb
+ - mobileye,eyeq7h-periph-east-olb
+ - mobileye,eyeq7h-south-olb
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Reference input clock.
+ clock-names:
+ items:
+ - const: ref
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mobileye,eyeq7h-east-olb
+ - mobileye,eyeq7h-west-olb
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Reference input clock from the main oscillator.
+ - description: 100MHz reference input clock.
+ clock-names:
+ items:
+ - const: ref
+ - const: ref_100p0
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mobileye,eyeq7h-acc0-olb
+ - mobileye,eyeq7h-acc1-olb
+ - mobileye,eyeq7h-periph-west-olb
+ - mobileye,eyeq7h-xnn0-olb
+ - mobileye,eyeq7h-xnn1-olb
+ then:
+ properties:
+ clocks:
+ items:
+ - description: 100MHz reference input clock.
+ - description: 106.6MHz reference input clock.
+ clock-names:
+ items:
+ - const: ref_100p0
+ - const: ref_106p6
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mobileye,eyeq7h-ddr0-olb
+ - mobileye,eyeq7h-ddr1-olb
+ - mobileye,eyeq7h-east-olb
+ - mobileye,eyeq7h-periph-east-olb
+ - mobileye,eyeq7h-periph-west-olb
+ - mobileye,eyeq7h-west-olb
+ then:
+ properties:
+ '#reset-cells':
+ const: 1
+ required:
+ - '#reset-cells'
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mobileye,eyeq7h-acc0-olb
+ - mobileye,eyeq7h-acc1-olb
+ - mobileye,eyeq7h-south-olb
+ - mobileye,eyeq7h-xnn0-olb
+ - mobileye,eyeq7h-xnn1-olb
+ then:
+ properties:
+ '#reset-cells':
+ const: 2
+ required:
+ - '#reset-cells'
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mobileye,eyeq7h-mips0-olb
+ - mobileye,eyeq7h-mips1-olb
+ - mobileye,eyeq7h-mips2-olb
+ then:
+ properties:
+ '#reset-cells': false
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ system-controller0@45000000 {
+ compatible = "mobileye,eyeq7h-acc0-olb", "syscon";
+ reg = <0x0 0x45000000 0x0 0x1000>;
+ #reset-cells = <2>;
+ #clock-cells = <1>;
+ clocks = <&olb_south 7>, <&olb_east 5>;
+ clock-names = "ref_100p0", "ref_106p6";
+ };
+ };
diff --git a/include/dt-bindings/clock/mobileye,eyeq7h-clk.h b/include/dt-bindings/clock/mobileye,eyeq7h-clk.h
new file mode 100644
index 000000000000..76e06a0abd02
--- /dev/null
+++ b/include/dt-bindings/clock/mobileye,eyeq7h-clk.h
@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2025 Mobileye Vision Technologies Ltd.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ7H_CLK_H
+#define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ7H_CLK_H
+
+/* ACC0 and ACC1 OLBs PLL and dividers */
+#define EQ7HC_ACC_PLL_VMP 0
+#define EQ7HC_ACC_PLL_MPC 1
+#define EQ7HC_ACC_PLL_PMA 2
+#define EQ7HC_ACC_PLL_NOC 3
+#define EQ7HC_ACC_DIV_PMA 4
+#define EQ7HC_ACC_DIV_NCORE 5
+#define EQ7HC_ACC_DIV_CFG 6
+
+/* DDR0 and DDR1 OLBs PLL and dividers */
+#define EQ7HC_DDR_PLL 0
+#define EQ7HC_DDR_DIV_APB 1
+#define EQ7HC_DDR_DIV_PLLREF 2
+#define EQ7HC_DDR_DIV_DFI 3
+
+/* east OLB PLL and dividers */
+#define EQ7HC_EAST_PLL_106P6 0
+#define EQ7HC_EAST_DIV_REF_106P6 1
+#define EQ7HC_EAST_PLL_NOC 2
+#define EQ7HC_EAST_PLL_ISP 3
+#define EQ7HC_EAST_PLL_VEU 4
+#define EQ7HC_EAST_DIV_REF_DDR_PHY 5
+#define EQ7HC_EAST_DIV_CORE 6
+#define EQ7HC_EAST_DIV_CORE_MBIST 7
+#define EQ7HC_EAST_DIV_ISRAM_MBIST 8
+#define EQ7HC_EAST_DIV_CFG 9
+#define EQ7HC_EAST_DIV_VEU_CORE 10
+#define EQ7HC_EAST_DIV_VEU_MBIST 11
+#define EQ7HC_EAST_DIV_VEU_OCP 12
+#define EQ7HC_EAST_DIV_LBITS 13
+#define EQ7HC_EAST_DIV_ISP0_CORE 14
+
+/* MIPS0, MIPS1 and MIPS2 OLBs PLL and dividers */
+#define EQ7HC_MIPS_PLL_CPU 0
+#define EQ7HC_MIPS_DIV_CM 1
+
+/* periph east OLB PLL and dividers */
+#define EQ7HC_PERIPH_EAST_PLL_PER 0
+#define EQ7HC_PERIPH_EAST_DIV_PER 1
+
+/* periph west OLB PLL and dividers */
+#define EQ7HC_PERIPH_WEST_PLL_PER 0
+#define EQ7HC_PERIPH_WEST_PLL_I2S 1
+#define EQ7HC_PERIPH_WEST_DIV_PER 2
+#define EQ7HC_PERIPH_WEST_DIV_I2S 3
+
+/* south OLB PLL and dividers */
+#define EQ7HC_SOUTH_PLL_100P0 0
+#define EQ7HC_SOUTH_DIV_REF_100P0 1
+#define EQ7HC_SOUTH_PLL_XSPI 2
+#define EQ7HC_SOUTH_PLL_VDIO 3
+#define EQ7HC_SOUTH_PLL_PER 4
+#define EQ7HC_SOUTH_DIV_VDO_DSI_SYS 5
+#define EQ7HC_SOUTH_DIV_PMA_CMN_REF 6
+#define EQ7HC_SOUTH_DIV_REF_UFS 7
+#define EQ7HC_SOUTH_DIV_XSPI_SYS 8
+#define EQ7HC_SOUTH_DIV_XSPI_MBIST 9
+#define EQ7HC_SOUTH_DIV_NOC_S 10
+#define EQ7HC_SOUTH_DIV_PCIE_SYS 11
+#define EQ7HC_SOUTH_DIV_PCIE_SYS_MBIST 12
+#define EQ7HC_SOUTH_DIV_PCIE_GBE_PHY 13
+#define EQ7HC_SOUTH_DIV_UFS_CORE 14
+#define EQ7HC_SOUTH_DIV_UFS_SMS 15
+#define EQ7HC_SOUTH_DIV_UFS_ROM_SMS 16
+#define EQ7HC_SOUTH_DIV_ETH_SYS 17
+#define EQ7HC_SOUTH_DIV_ETH_MBIST 18
+#define EQ7HC_SOUTH_DIV_CFG_S 19
+#define EQ7HC_SOUTH_DIV_TSU 20
+#define EQ7HC_SOUTH_DIV_VDIO 21
+#define EQ7HC_SOUTH_DIV_VDIO_CORE 22
+#define EQ7HC_SOUTH_DIV_VDIO_CORE_MBIST 23
+#define EQ7HC_SOUTH_DIV_VDO_CORE_MBIST 24
+#define EQ7HC_SOUTH_DIV_VDO_P 25
+#define EQ7HC_SOUTH_DIV_VDIO_CFG 26
+#define EQ7HC_SOUTH_DIV_VDIO_TXCLKESC 27
+
+/* west OLB PLL and dividers */
+#define EQ7HC_WEST_PLL_106P6 0
+#define EQ7HC_WEST_DIV_REF_106P6 1
+#define EQ7HC_WEST_PLL_NOC 2
+#define EQ7HC_WEST_PLL_GPU 3
+#define EQ7HC_WEST_PLL_SSI 4
+#define EQ7HC_WEST_DIV_GPU 5
+#define EQ7HC_WEST_DIV_GPU_MBIST 6
+#define EQ7HC_WEST_DIV_LBITS 7
+#define EQ7HC_WEST_DIV_MIPS_TIMER 8
+#define EQ7HC_WEST_DIV_SSI_CORE 9
+#define EQ7HC_WEST_DIV_SSI_CORE_MBIST 10
+#define EQ7HC_WEST_DIV_SSI_ROM 11
+#define EQ7HC_WEST_DIV_SSI_ROM_MBIST 12
+#define EQ7HC_WEST_DIV_REF_DDR_PHY 13
+#define EQ7HC_WEST_DIV_CORE 14
+#define EQ7HC_WEST_DIV_CORE_MBIST 15
+#define EQ7HC_WEST_DIV_CFG 16
+#define EQ7HC_WEST_DIV_CAU 17
+#define EQ7HC_WEST_DIV_CAU_MBIST 18
+
+/* XNN0 and XNN1 OLBs PLL and dividers */
+#define EQ7HC_XNN_PLL_XNN0 0
+#define EQ7HC_XNN_PLL_XNN1 1
+#define EQ7HC_XNN_PLL_XNN2 2
+#define EQ7HC_XNN_PLL_CLSTR 3
+#define EQ7HC_XNN_DIV_XNN0 4
+#define EQ7HC_XNN_DIV_XNN1 5
+#define EQ7HC_XNN_DIV_XNN2 6
+#define EQ7HC_XNN_DIV_CLSTR 7
+#define EQ7HC_XNN_DIV_I2 8
+#define EQ7HC_XNN_DIV_I2_SMS 9
+#define EQ7HC_XNN_DIV_CFG 10
+
+#endif
--
2.54.0
^ permalink raw reply related
* [PATCH v7 4/9] clk: fixed-factor: Export __clk_hw_register_fixed_factor()
From: Benoît Monin @ 2026-05-22 12:31 UTC (permalink / raw)
To: Vladimir Kondratiev, Gregory CLEMENT, Théo Lebrun,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd, Brian Masney, Philipp Zabel
Cc: Benoît Monin, Thomas Petazzoni, linux-mips, devicetree,
linux-kernel, linux-clk
In-Reply-To: <20260522-clk-eyeq7-v7-0-14ad6c2c5213@bootlin.com>
Make the base registration function for fixed-factor clocks public and
re-implement the various registration functions that are a direct call
to __clk_hw_register_fixed_factor() as macros.
This is similar to how the registration functions of divider, mux and
other clocks are implemented.
Add a new macro clk_hw_register_fixed_factor_pdata() to register
a fixed-factor clock with its parent clock passed as a struct
clk_parent_data.
Reviewed-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
drivers/clk/clk-fixed-factor.c | 52 ++-------------------------------------
include/linux/clk-provider.h | 56 +++++++++++++++++++++++++++++++++---------
2 files changed, 46 insertions(+), 62 deletions(-)
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index 60e32482d347..ae473e0af903 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -94,7 +94,7 @@ static void devm_clk_hw_register_fixed_factor_release(struct device *dev, void *
clk_hw_unregister(&fix->hw);
}
-static struct clk_hw *
+struct clk_hw *
__clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
const char *name, const char *parent_name,
const struct clk_hw *parent_hw, const struct clk_parent_data *pdata,
@@ -152,6 +152,7 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
return hw;
}
+EXPORT_SYMBOL_GPL(__clk_hw_register_fixed_factor);
/**
* devm_clk_hw_register_fixed_factor_index - Register a fixed factor clock with
@@ -177,46 +178,6 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev,
}
EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_index);
-/**
- * devm_clk_hw_register_fixed_factor_parent_hw - Register a fixed factor clock with
- * pointer to parent clock
- * @dev: device that is registering this clock
- * @name: name of this clock
- * @parent_hw: pointer to parent clk
- * @flags: fixed factor flags
- * @mult: multiplier
- * @div: divider
- *
- * Return: Pointer to fixed factor clk_hw structure that was registered or
- * an error pointer.
- */
-struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev,
- const char *name, const struct clk_hw *parent_hw,
- unsigned long flags, unsigned int mult, unsigned int div)
-{
- return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw,
- NULL, flags, mult, div, 0, 0, true);
-}
-EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_parent_hw);
-
-struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev,
- const char *name, const struct clk_hw *parent_hw,
- unsigned long flags, unsigned int mult, unsigned int div)
-{
- return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw,
- NULL, flags, mult, div, 0, 0, false);
-}
-EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_parent_hw);
-
-struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
- const char *name, const char *parent_name, unsigned long flags,
- unsigned int mult, unsigned int div)
-{
- return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL,
- NULL, flags, mult, div, 0, 0, false);
-}
-EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor);
-
struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev,
struct device_node *np, const char *name, const char *fw_name,
unsigned long flags, unsigned int mult, unsigned int div)
@@ -290,15 +251,6 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw)
}
EXPORT_SYMBOL_GPL(clk_hw_unregister_fixed_factor);
-struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
- const char *name, const char *parent_name, unsigned long flags,
- unsigned int mult, unsigned int div)
-{
- return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL,
- NULL, flags, mult, div, 0, 0, true);
-}
-EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor);
-
struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev,
struct device_node *np, const char *name, const char *fw_name,
unsigned long flags, unsigned int mult, unsigned int div)
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index b01a38fef8cf..aba71f5dcc21 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -1152,13 +1152,16 @@ struct clk_fixed_factor {
#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
extern const struct clk_ops clk_fixed_factor_ops;
+struct clk_hw *
+__clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
+ const char *name, const char *parent_name,
+ const struct clk_hw *parent_hw, const struct clk_parent_data *pdata,
+ unsigned long flags, unsigned int mult, unsigned int div,
+ unsigned long acc, unsigned int fixflags, bool devm);
struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
unsigned int mult, unsigned int div);
void clk_unregister_fixed_factor(struct clk *clk);
-struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
- const char *name, const char *parent_name, unsigned long flags,
- unsigned int mult, unsigned int div);
struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev,
struct device_node *np, const char *name, const char *fw_name,
unsigned long flags, unsigned int mult, unsigned int div);
@@ -1170,9 +1173,6 @@ struct clk_hw *clk_hw_register_fixed_factor_index(struct device *dev,
const char *name, unsigned int index, unsigned long flags,
unsigned int mult, unsigned int div);
void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
-struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
- const char *name, const char *parent_name, unsigned long flags,
- unsigned int mult, unsigned int div);
struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev,
struct device_node *np, const char *name, const char *fw_name,
unsigned long flags, unsigned int mult, unsigned int div);
@@ -1184,13 +1184,45 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev,
const char *name, unsigned int index, unsigned long flags,
unsigned int mult, unsigned int div);
-struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev,
- const char *name, const struct clk_hw *parent_hw,
- unsigned long flags, unsigned int mult, unsigned int div);
+#define clk_hw_register_fixed_factor(dev, name, parent_name, \
+ flags, mult, div) \
+ __clk_hw_register_fixed_factor((dev), NULL, (name), (parent_name), \
+ NULL, NULL, (flags), (mult), (div), \
+ 0, 0, false)
+#define clk_hw_register_fixed_factor_pdata(dev, np, name, pdata, \
+ flags, mult, div, acc, fixflags) \
+ __clk_hw_register_fixed_factor((dev), (np), (name), NULL, NULL, \
+ (pdata), (flags), (mult), (div), \
+ (acc), (fixflags), false)
+#define devm_clk_hw_register_fixed_factor(dev, name, parent_name, flags, \
+ mult, div) \
+ __clk_hw_register_fixed_factor((dev), NULL, (name), (parent_name), \
+ NULL, NULL, (flags), (mult), (div), 0, \
+ 0, true)
+/**
+ * devm_clk_hw_register_fixed_factor_parent_hw - Register a fixed factor clock with
+ * pointer to parent clock
+ * @dev: device that is registering this clock
+ * @name: name of this clock
+ * @parent_hw: pointer to parent clk
+ * @flags: fixed factor flags
+ * @mult: multiplier
+ * @div: divider
+ *
+ * Return: Pointer to fixed factor clk_hw structure that was registered or
+ * an error pointer.
+ */
+#define devm_clk_hw_register_fixed_factor_parent_hw(dev, name, parent_hw, \
+ flags, mult, div) \
+ __clk_hw_register_fixed_factor((dev), NULL, (name), NULL, \
+ (parent_hw), NULL, (flags), (mult), \
+ (div), 0, 0, true)
-struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev,
- const char *name, const struct clk_hw *parent_hw,
- unsigned long flags, unsigned int mult, unsigned int div);
+#define clk_hw_register_fixed_factor_parent_hw(dev, name, parent_hw, flags, \
+ mult, div) \
+ __clk_hw_register_fixed_factor((dev), NULL, (name), NULL, \
+ (parent_hw), NULL, (flags), (mult), \
+ (div), 0, 0, false)
/**
* struct clk_fractional_divider - adjustable fractional divider clock
*
--
2.54.0
^ permalink raw reply related
* [PATCH v7 0/9] Add clock and reset support for Mobileye EyeQ7H
From: Benoît Monin @ 2026-05-22 12:31 UTC (permalink / raw)
To: Vladimir Kondratiev, Gregory CLEMENT, Théo Lebrun,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd, Brian Masney, Philipp Zabel
Cc: Benoît Monin, Thomas Petazzoni, linux-mips, devicetree,
linux-kernel, linux-clk, Krzysztof Kozlowski, Sari Khoury
This patchset brings the support of the Other Logic Blocks (OLB)
found in the first Mobileye SoC based on the RISC-V architecture, the
EyeQ7H. Despite the change from MIPS to RISC-V, the Other Logic Blocks
provide similar clock and reset functions to the controllers of the
chip. This series introduces the device tree bindings of the SoC and
the necessary changes to the clock and reset eyeq drivers.
Since this series affects drivers used on Mobileye MIPS SoCs, mainly
clk-eyeq, I tested that it does not introduce regressions on EyeQ5,
EyeQ6H, and EyeQ6Lplus evaluation boards.
In detail, the first patch adds the dt-bindings yaml and headers for
the EyeQ7H OLB.
Patch 2 adds the compatible entries to the reset-eyeq driver, and the
necessary changes for the reset domains found in the EyeQ7H OLB.
Patches 3 and 4 rework the handling of parent clocks in
__clk_hw_register_fixed_factor() to make it identical to other clock types
like divider or gate. This allows simplifying the registration functions
built on top of the now exported __clk_hw_register_fixed_factor(). A
new clk_hw_register_fixed_factor_pdata() is added that will be used in
clk-eyeq later in the series.
Patch 5 renames the defines and functions related to the PLL with the
PLL type fracg, to make room for the other types of PLL found the in
EyeQ7H OLB.
Patch 6 introduces a new generic type of clock structure that can
represents all clocks found in OLB. Then patch 7 and 8 converts all
clocks defined in the driver to the new struct eqc_clock and remove all
the previous separate clocks structures.
Patch 9 adds the list of clocks as match data for the 14 OLB present
in the EyeQ7H SoC, and the functions needed to probe the two PLL types
found in the chip.
This series is based on v7.1-rc3 as all the prerequisites have been
merged. It also applies cleanly on the clk-next branch.
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
Changes in v7:
- Fixed DDR OLB reset controller type (the comment and sashiko were right)
and the comment for the reset offsets for west OLB in reset-eyeq.
- Made sure the parent clock is valid before accessing it
in clk_factor_determine_rate().
- Fixed error paths mistakenly returning IS_ERR(ret) instead of PTR_ERR(ret)
in clk-eyeq.
- Declared the DDR OLB dividers as read-only.
- Ensured that the mult and div computed in eqc_pll_parse_fracg() fit in 32 bits.
- Link to v6: https://patch.msgid.link/20260512-clk-eyeq7-v6-0-0540cce18fb2@bootlin.com
Changes in v6:
- Rebased on v7.1-rc3.
- Dropped the MAINTAINER update for now, this will go with the SoC series.
- Link to v5: https://lore.kernel.org/r/20260317-clk-eyeq7-v5-0-6f6daa2c2367@bootlin.com
Changes in v5:
- Rebased in v7.0-rc1 + version 4 of eyeq6plus series.
- Remove an superfluous whitespace and tidy up macros in clk-provider.h.
- Link to v4: https://lore.kernel.org/r/20260304-clk-eyeq7-v4-0-9d6bd9d24bec@bootlin.com
Changes in v4:
- Rebased on v7.0-rc1 + version 3 of eyeq6plus series.
- Link to v3: https://lore.kernel.org/r/20260114-clk-eyeq7-v3-0-8ebdba7b0133@bootlin.com
Changes in v3:
- Fix eyeq7h-olb DT bindings following Krzysztof review.
- Link to v2: https://lore.kernel.org/r/20251224-clk-eyeq7-v2-0-81744d1025d9@bootlin.com
Changes in v2:
- Move the dt-bindings to their own files and sort the compatibles.
- Reorder the changes in reset-eyeq and make the register access more
readable.
- Drop the validity check on even divider. Unnecessary since it is
always called from a clock .set_rate().
- Drop the parameters check on divider registration. Will be posted
separately.
- Switch to a new generic struct for describing the clocks.
- Add an entry to MAINTAINERS.
- Link to v1: https://lore.kernel.org/r/20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com
To: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
To: Benoît Monin <benoit.monin@bootlin.com>
To: Gregory CLEMENT <gregory.clement@bootlin.com>
To: Théo Lebrun <theo.lebrun@bootlin.com>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>
To: Stephen Boyd <sboyd@kernel.org>
To: Brian Masney <bmasney@redhat.com>
To: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-clk@vger.kernel.org
---
Benoît Monin (9):
dt-bindings: soc: mobileye: Add EyeQ7H OLB
reset: eyeq: Add EyeQ7H compatibles
clk: fixed-factor: Rework initialization with parent clocks
clk: fixed-factor: Export __clk_hw_register_fixed_factor()
clk: eyeq: Prefix the PLL registers with the PLL type
clk: eyeq: Introduce a generic clock type
clk: eyeq: Convert clocks declaration to eqc_clock
clk: eyeq: Drop PLL, dividers, and fixed factors structs
clk: eyeq: Add EyeQ7H compatibles
.../bindings/soc/mobileye/mobileye,eyeq7h-olb.yaml | 192 +++
drivers/clk/clk-eyeq.c | 1262 +++++++++++++-------
drivers/clk/clk-fixed-factor.c | 78 +-
drivers/reset/reset-eyeq.c | 268 ++++-
include/dt-bindings/clock/mobileye,eyeq7h-clk.h | 119 ++
include/linux/clk-provider.h | 56 +-
6 files changed, 1480 insertions(+), 495 deletions(-)
---
base-commit: bb1459368dd795c43380057523f571d5eb0ddded
change-id: 20250807-clk-eyeq7-f9c6ea43d138
Best regards,
--
Benoît Monin, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* [PATCH v7 3/9] clk: fixed-factor: Rework initialization with parent clocks
From: Benoît Monin @ 2026-05-22 12:31 UTC (permalink / raw)
To: Vladimir Kondratiev, Gregory CLEMENT, Théo Lebrun,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd, Brian Masney, Philipp Zabel
Cc: Benoît Monin, Thomas Petazzoni, linux-mips, devicetree,
linux-kernel, linux-clk
In-Reply-To: <20260522-clk-eyeq7-v7-0-14ad6c2c5213@bootlin.com>
Use the same sequence as clk-divider, clk-gate and other to set the
parent_names, parent_hws and parent_data in the init struct when
registering a fixed-factor clock. The number of parent clocks is now
only set to one if a parent clock is provided.
Previously the number of parent clocks was always one, forcing callers
of __clk_hw_register_fixed_factor() to provide a dummy parent_data
struct with an invalid clock index in case they were not provided with
a non-NULL parent_name or parent_hw. Drop this dummy parent_data as is
not necessary anymore.
This change only has a small impact on mis-configured fixed-factor. Now a
call to clk_hw_register_fixed_factor() with a NULL parent will register
a fixed-factor with zero parent while previously it was registered with
one invalid parent. In both cases the rate of the fixed-factor is 0Hz
but it is no longer shown as orphaned.
This has no impact on properly configured fixed-factors clocks which
have a valid parent set.
In clk_factor_determine_rate(), make sure the parent clock is valid
before accessing it because the mis-configured fixed-factor now have a
NULL parent.
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
drivers/clk/clk-fixed-factor.c | 34 +++++++++++++++-------------------
1 file changed, 15 insertions(+), 19 deletions(-)
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index 850e8b95f352..60e32482d347 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -36,10 +36,14 @@ static int clk_factor_determine_rate(struct clk_hw *hw,
struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
+ struct clk_hw *parent_hw = clk_hw_get_parent(hw);
unsigned long best_parent;
+ if (!parent_hw)
+ return -EINVAL;
+
best_parent = (req->rate / fix->mult) * fix->div;
- req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
+ req->best_parent_rate = clk_hw_round_rate(parent_hw, best_parent);
}
req->rate = (req->best_parent_rate / fix->div) * fix->mult;
@@ -124,13 +128,13 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
init.name = name;
init.ops = &clk_fixed_factor_ops;
init.flags = flags;
- if (parent_name)
- init.parent_names = &parent_name;
- else if (parent_hw)
- init.parent_hws = &parent_hw;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.parent_hws = parent_hw ? &parent_hw : NULL;
+ init.parent_data = pdata;
+ if (parent_name || parent_hw || pdata)
+ init.num_parents = 1;
else
- init.parent_data = pdata;
- init.num_parents = 1;
+ init.num_parents = 0;
hw = &fix->hw;
if (dev)
@@ -190,10 +194,8 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev,
const char *name, const struct clk_hw *parent_hw,
unsigned long flags, unsigned int mult, unsigned int div)
{
- const struct clk_parent_data pdata = { .index = -1 };
-
return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw,
- &pdata, flags, mult, div, 0, 0, true);
+ NULL, flags, mult, div, 0, 0, true);
}
EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_parent_hw);
@@ -201,10 +203,8 @@ struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev,
const char *name, const struct clk_hw *parent_hw,
unsigned long flags, unsigned int mult, unsigned int div)
{
- const struct clk_parent_data pdata = { .index = -1 };
-
return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw,
- &pdata, flags, mult, div, 0, 0, false);
+ NULL, flags, mult, div, 0, 0, false);
}
EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_parent_hw);
@@ -212,10 +212,8 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
const char *name, const char *parent_name, unsigned long flags,
unsigned int mult, unsigned int div)
{
- const struct clk_parent_data pdata = { .index = -1 };
-
return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL,
- &pdata, flags, mult, div, 0, 0, false);
+ NULL, flags, mult, div, 0, 0, false);
}
EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor);
@@ -296,10 +294,8 @@ struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
const char *name, const char *parent_name, unsigned long flags,
unsigned int mult, unsigned int div)
{
- const struct clk_parent_data pdata = { .index = -1 };
-
return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL,
- &pdata, flags, mult, div, 0, 0, true);
+ NULL, flags, mult, div, 0, 0, true);
}
EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor);
--
2.54.0
^ permalink raw reply related
* Re: [PATCH 7/9] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document the I3C standby property
From: Wolfram Sang @ 2026-05-22 12:30 UTC (permalink / raw)
To: Claudiu Beznea
Cc: geert+renesas, linusw, robh, krzk+dt, conor+dt, magnus.damm,
claudiu.beznea, linux-renesas-soc, linux-gpio, devicetree,
linux-kernel, Claudiu Beznea
In-Reply-To: <20260522102251.1723392-8-claudiu.beznea@kernel.org>
[-- Attachment #1: Type: text/plain, Size: 507 bytes --]
Hi all,
> + renesas,i3c-standby:
> + description:
> + Controls the standby mode of the I3C interface when operating in I2C mode.
> + When standby mode is selected, the output is fixed at Hi-Z and no data is
> + transferred internally, even if data is received from outside.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1]
I commented on patch 9 to discuss if this binding is really needed.
Happy hacking,
Wolfram
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH 9/9] arm64: dts: renesas: rzg3s-smarc-som: Enable I3C
From: Wolfram Sang @ 2026-05-22 12:29 UTC (permalink / raw)
To: Claudiu Beznea
Cc: geert+renesas, linusw, robh, krzk+dt, conor+dt, magnus.damm,
claudiu.beznea, linux-renesas-soc, linux-gpio, devicetree,
linux-kernel, Claudiu Beznea
In-Reply-To: <20260522102251.1723392-10-claudiu.beznea@kernel.org>
[-- Attachment #1: Type: text/plain, Size: 731 bytes --]
Hi Claudiu,
> + i3c_pins: i3c {
> + pins = "I3C_SDA", "I3C_SCL";
> +#if SW_CONFIG4 == SW_ON
> + power-source = <1200>;
> +#else
> + power-source = <1800>;
> +#endif
> + input-enable;
> + renesas,i3c-standby = <0>;
> + };
> +
> + i3c_standby_pins: i3c-standby {
> + pins = "I3C_SDA", "I3C_SCL";
> +#if SW_CONFIG4 == SW_ON
> + power-source = <1200>;
> +#else
> + power-source = <1800>;
> +#endif
> + renesas,i3c-standby = <1>;
> + };
That doesn't look like HW description to me because the pins are the
same for regular and standby mode. Their state is changed when powering
down, but that should not need DT encoding, I'd think. The driver should
know what to do, or? Am I missing something?
Happy hacking,
Wolfram
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH 2/2] arm64: dts: qcom: ipq5210: Enable PCIe support
From: Konrad Dybcio @ 2026-05-22 12:24 UTC (permalink / raw)
To: Varadarajan Narayanan, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, linux-pci, devicetree, linux-kernel
In-Reply-To: <20260514-pci-ipq5210-v1-2-a09436200b35@oss.qualcomm.com>
On 5/14/26 6:13 AM, Varadarajan Narayanan wrote:
> Add DT entries to enable the PCIe controllers found in ipq5210.
>
> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
> ---
[...]
> &tlmm {
> + pcie0_default_state: pcie0-default-state {
> + pins = "gpio32";
> + function = "gpio";
> + drive-strength = <6>;
> + bias-pull-down;
> + output-low;
> + };
> +
> + pcie1_default_state: pcie1-default-state {
> + pins = "gpio29";
> + function = "gpio";
> + drive-strength = <6>;
> + bias-pull-down;
> + output-low;
You shouldn't need output-low in either of these definitions (+ sorting
by GPIO idx would be extra neat)
[...]
> clocks {
> + pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <250000000>;
> + #clock-cells = <0>;
> + };
> +
> + pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <250000000>;
> + #clock-cells = <0>;
> + };
Why do these exist? Just pass the QMPPHY reference straight to GCC
[...]
> + pcie0_phy: phy@84000 {
> + compatible = "qcom,ipq5210-qmp-gen3x1-pcie-phy",
> + "qcom,ipq9574-qmp-gen3x1-pcie-phy";
> + reg = <0x0 0x00084000 0x0 0x1000>;
> +
> + clocks = <&gcc GCC_PCIE0_AUX_CLK>,
> + <&gcc GCC_PCIE0_AHB_CLK>,
> + <&gcc GCC_PCIE0_PIPE_CLK>;
> + clock-names = "aux", "cfg_ahb", "pipe";
> +
> + assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
> + assigned-clock-rates = <20000000>;
Is this clock supposed to be fixed at that rate, regardless of the link
speed? And is the default rate incorrect?
> +
> + resets = <&gcc GCC_PCIE0_PHY_BCR>,
> + <&gcc GCC_PCIE0PHY_PHY_BCR>;
> + reset-names = "phy", "common";
> +
> + #clock-cells = <0>;
> + clock-output-names = "gcc_pcie0_pipe_clk_src";
Having a gcc_ prefix here smells fishy..
[...]
> + clocks = <&gcc GCC_PCIE1_AXI_M_CLK>,
> + <&gcc GCC_PCIE1_AXI_S_CLK>,
> + <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>,
> + <&gcc GCC_PCIE1_RCHNG_CLK>,
> + <&gcc GCC_PCIE1_AHB_CLK>,
> + <&gcc GCC_PCIE1_AUX_CLK>;
> +
> + clock-names = "axi_m",
stray \n above, also in resets
[...]
> + pcie1_rp: pcie@0 {
pcie1_port0 for consistency with other DTs, please
Same comments for the other port
Konrad
^ permalink raw reply
* Re: [PATCH 2/2] iio: adc: ad4080: add support for AD4884
From: sashiko-bot @ 2026-05-22 12:20 UTC (permalink / raw)
To: Antoniu Miclaus; +Cc: devicetree, robh, conor+dt
In-Reply-To: <20260522115337.18188-3-antoniu.miclaus@analog.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [High] Incorrect IIO scale calculation results in a factor of 1000 error for exposed voltage scales.
--
commit ec9f31937338c4b8462c0623182623b90d6e39ad
Author: Antoniu Miclaus <antoniu.miclaus@analog.com>
iio: adc: ad4080: add support for AD4884
Add support for the AD4884, a dual-channel, 16-bit, 40 MSPS SAR ADC.
> diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c
> index 265d85ac171a9..764d49eca9e0e 100644
> --- a/drivers/iio/adc/ad4080.c
> +++ b/drivers/iio/adc/ad4080.c
[ ... ]
> @@ -541,6 +542,11 @@ static const struct iio_chan_spec ad4880_channels[] = {
> AD4880_CHANNEL_DEFINE(20, 32, 1),
> };
>
> +static const struct iio_chan_spec ad4884_channels[] = {
> + AD4880_CHANNEL_DEFINE(16, 16, 0),
> + AD4880_CHANNEL_DEFINE(16, 16, 1),
> +};
> +
[Severity: High]
This isn't a bug introduced by this patch, but I noticed that when the channel
exposes the scale attribute, the calculation in ad4080_get_scale() seems
mathematically incorrect:
drivers/iio/adc/ad4080.c:ad4080_get_scale() {
unsigned int tmp;
tmp = (st->info->scale_table[0][0] * 1000000ULL) >>
st->info->channels[0].scan_type.realbits;
*val = tmp / 1000000;
*val2 = tmp % 1000000;
return IIO_VAL_INT_PLUS_NANO;
}
Since the fraction is calculated by multiplying by 1,000,000 and then using
modulo 1,000,000, val2 holds micro units.
However, IIO_VAL_INT_PLUS_NANO tells the IIO core to format val2 as nano
units (billionths).
Does this mismatch cause the sysfs scale attribute to expose a value that is
exactly 1000 times smaller than intended for these channels?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260522115337.18188-1-antoniu.miclaus@analog.com?part=2
^ permalink raw reply
* Re: [PATCH 3/5] arm64: dts: freescale: imx95-toradex-smarc: move CM7 node to SoC DTSI
From: sashiko-bot @ 2026-05-22 12:18 UTC (permalink / raw)
To: Laurentiu Mihalcea; +Cc: devicetree, imx, conor+dt, Frank.Li, robh
In-Reply-To: <20260522111849.783-4-laurentiumihalcea111@gmail.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The patch implicitly disables the CM7 remoteproc on all Verdin platforms and leaves a redundant, uncleaned node.
--
commit f431dd9d8aa9dbff4c66eec7fa35574389600cc9
Author: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
arm64: dts: freescale: imx95-toradex-smarc: move CM7 node to SoC DTSI
This commit moves the CM7 remoteproc configuration from the Toradex SMARC
Device Tree to the common i.MX95 SoC Device Tree. It also splits the
mailbox channels into separate array entries.
> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
> index 3e35c956a4d7a..f8760ac067faf 100644
> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> @@ -272,6 +272,13 @@ opp-1000000000 {
> };
> };
>
> + cm7: remoteproc-cm7 {
> + compatible = "fsl,imx95-cm7";
> + mboxes = <&mu7 0 1>, <&mu7 1 1>, <&mu7 3 1>;
> + mbox-names = "tx", "rx", "rxdb";
> + status = "disabled";
[Severity: High]
Does this implicitly disable the CM7 remoteproc on Verdin platforms?
Since imx95-verdin.dtsi includes imx95.dtsi and defines its own
cm7: remoteproc-cm7 node without setting a status property, it appears it
will inherit this status = "disabled" property, whereas it was previously
implicitly enabled.
Additionally, does imx95-verdin.dtsi need to be updated to match these
changes? It currently retains the unsplit mboxes array format
(mboxes = <&mu7 0 1 &mu7 1 1 &mu7 3 1>;), which will override the split
format introduced here.
> + };
> +
> clk_ext1: clock-ext1 {
> compatible = "fixed-clock";
> #clock-cells = <0>;
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260522111849.783-1-laurentiumihalcea111@gmail.com?part=3
^ permalink raw reply
* Re: [PATCH v2 3/4] arm64: dts: qcom: sm6115: add venus device
From: Konrad Dybcio @ 2026-05-22 12:14 UTC (permalink / raw)
To: Dmitry Baryshkov, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Vikash Garodia, Dikshita Agarwal,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jorge Ramirez-Ortiz,
Konrad Dybcio
Cc: linux-arm-msm, linux-clk, linux-kernel, linux-media, devicetree
In-Reply-To: <20260515-iris-sm6115-v2-3-2ab75229de61@oss.qualcomm.com>
On 5/15/26 1:59 PM, Dmitry Baryshkov wrote:
> Define the video en/decoding device present on the SM6115 platform. The
> core, AR50LT, is mostly compatible with the one present on the Agatti
> devices, so it uses qcom,qcm2290-venus as a fallback.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* Re: [PATCH 2/2] remoteproc: qcom: pas: Add Shikra remoteproc support
From: Konrad Dybcio @ 2026-05-22 12:13 UTC (permalink / raw)
To: Komal Bajaj, Dmitry Baryshkov
Cc: Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, Bibek Kumar Patro
In-Reply-To: <fd67b063-a986-4d34-99e6-fe55e72d0187@oss.qualcomm.com>
On 5/19/26 5:03 PM, Komal Bajaj wrote:
> On 5/14/2026 12:48 AM, Dmitry Baryshkov wrote:
>> On Thu, May 14, 2026 at 12:17:31AM +0530, Komal Bajaj wrote:
>>> From: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
>>>
>>> Add the CDSP, LPAICP and MPSS Peripheral Authentication Service support
>>> for the Qualcomm Shikra SoC.
>>>
>>> Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
>>> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
>>> ---
[...]
> Ack, I'll address it in next revision.
>
>> point you can use sc8180x_mpss_resource instead.
>
> minidump_id is required for Shikra. (decrypt_shutdown is not applicable and will be removed in the next revision.)
> For minidump_id, we still need to use shikra_mpss_resource instead of sc8180x_mpss_resource. <?>
Is there a chance the same ID would be applicable to 8180 as well,
just that we missed it in the past?
Konrad
^ permalink raw reply
* Re: [PATCH v2 3/3] arm64: dts: qcom: Add Eliza CQS EVK board
From: Konrad Dybcio @ 2026-05-22 12:11 UTC (permalink / raw)
To: Abel Vesa, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260519-eliza-dts-qcs-evk-v2-3-ad7303659d24@oss.qualcomm.com>
On 5/19/26 6:09 PM, Abel Vesa wrote:
> The Eliza CQS EVK board combines the CQ7790S-based (Eliza) SoM with the
> common Eliza EVK base board, which provides connectors for different
> peripherals.
>
> Add a common Eliza EVK dtsi for the base board bits that can be reused
> alongside other Eliza SoM variants. Then, add the final Eliza CQS EVK dts,
> including the CQS SoM and common EVK dtsi.
>
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/eliza-cqs-evk.dts | 20 ++++++++++++++++++++
> arch/arm64/boot/dts/qcom/eliza-evk.dtsi | 20 ++++++++++++++++++++
> 3 files changed, 41 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 795cee4757ab..e244e808a647 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -14,6 +14,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
> dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
> dtb-$(CONFIG_ARCH_QCOM) += apq8096sg-db820c.dtb
> dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += eliza-cqs-evk.dtb
> dtb-$(CONFIG_ARCH_QCOM) += eliza-mtp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += glymur-crd.dtb
> dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk.dtb
> diff --git a/arch/arm64/boot/dts/qcom/eliza-cqs-evk.dts b/arch/arm64/boot/dts/qcom/eliza-cqs-evk.dts
> new file mode 100644
> index 000000000000..d1cf08ce19d1
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/eliza-cqs-evk.dts
> @@ -0,0 +1,20 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +/dts-v1/;
> +
> +#include "eliza-cqs-som.dtsi"
> +#include "eliza-evk.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. Eliza CQS EVK";
> + compatible = "qcom,eliza-cqs-evk", "qcom,eliza-cqs-som", "qcom,eliza";
> +};
> +
> +&tlmm {
> + gpio-reserved-ranges = <20 4>, /* NFC SPI */
> + <111 2>, /* WCN UART1 */
> + <118 1>; /* NFC Secure I/O */
Are these going to be specific to the CQS-EVK?
Otherwise
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* Re: [PATCH v2 2/3] arm64: dts: qcom: Add Eliza CQS SoM platform
From: Konrad Dybcio @ 2026-05-22 12:11 UTC (permalink / raw)
To: Abel Vesa, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260519-eliza-dts-qcs-evk-v2-2-ad7303659d24@oss.qualcomm.com>
On 5/19/26 6:09 PM, Abel Vesa wrote:
> The Eliza CQS (CQ7790S) System-on-Module is designed to be connected to
> an Eliza EVK base board. The SoM provides the SoC, PMICs, LPDDR and eMMC,
> while the EVK base board provides connectors for a multitude of
> peripherals.
>
> Add the Eliza CQS SoM DTSI so it can be included by the EVK board DTS.
> Describe the regulators and board clocks, enable eMMC support through
> SDHC1, specify the ADSP firmware and enable the ADSP remoteproc.
>
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* Re: [PATCH 5/5] arm64: dts: freescale: add DT overlay for MX95-15x15-FRDM RPMSG usage
From: Daniel Baluta @ 2026-05-22 12:11 UTC (permalink / raw)
To: Laurentiu Mihalcea, Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Frank Li, Sascha Hauer,
Peng Fan, Fabio Estevam
Cc: Pengutronix Kernel Team, linux-remoteproc, devicetree, imx,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260522111849.783-6-laurentiumihalcea111@gmail.com>
On 5/22/26 14:18, Laurentiu Mihalcea wrote:
> From: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
>
> Add RPMSG DT overlay for the MX95-15x15-FRDM board. This overlay is meant
> to be used with the mx95evkrpmsg system manager configuration for
> remoteproc and audio over rpmsg-usecases.
>
> Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/Makefile | 3 +
> .../dts/freescale/imx95-15x15-frdm-rpmsg.dtso | 65 +++++++++++++++++++
> 2 files changed, 68 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx95-15x15-frdm-rpmsg.dtso
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 513f61eb27b8..a30a99e42426 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -521,6 +521,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx943-evk-pcie0-ep.dtb imx943-evk-pcie1-ep.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-ab2.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-frdm.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-frdm-rpmsg.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb
> @@ -539,6 +540,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-mallow.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-yavia.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-zinnia.dtb
>
> +imx95-15x15-frdm-rpmsg-dtbs = imx95-15x15-frdm.dtb imx95-15x15-frdm-rpmsg.dtbo
> +
> imx95-15x15-evk-pcie-dtbs += imx95-15x15-evk.dtb imx-m2-pcie.dtbo
> dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie.dtb
>
> diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-frdm-rpmsg.dtso b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm-rpmsg.dtso
> new file mode 100644
> index 000000000000..b39444dde66e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm-rpmsg.dtso
> @@ -0,0 +1,65 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2026 NXP
> + *
> + * This DT overlay is meant to be used alongside the mx95evkrpmsg SM
> + * configuration for remoteproc and audio over rpmsg.
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +&{/} {
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + vdev0vring0: memory@88000000 {
> + reg = <0 0x88000000 0 0x8000>;
> + no-map;
> + };
> +
> + vdev0vring1: memory@88008000 {
> + reg = <0 0x88008000 0 0x8000>;
> + no-map;
> + };
> +
> + vdev0buffer: memory@88020000 {
> + compatible = "shared-dma-pool";
> + reg = <0 0x88020000 0 0x100000>;
> + no-map;
> + };
> +
> + rsc_table: memory@88220000 {
> + reg = <0 0x88220000 0 0x1000>;
> + no-map;
> + };
> + };
> +
> + sound-micfil {
> + status = "disabled";
> + };
> +};
> +
> +&cm7 {
> + memory-region = <&vdev0buffer>, <&vdev0vring0>,
> + <&vdev0vring1>, <&rsc_table>;
> + memory-region-names = "vdev0buffer", "vdev0vring0",
> + "vdev0vring1", "rsc-table";
> + status = "okay";
> +};
> +
> +&edma1 {
> + /* reserved for M7 */
> + dma-channel-mask = <0x40>;
> +};
> +
> +&edma2 {
> + /* reserved for M7 and V2X */
> + dma-channel-mask = <0xf>;
> +};
> +
> +&micfil {
> + /* reserved for M7 */
> + status = "disabled";
> +};
For this usecase usually status needs to be set to "reserved".
Otherwise,
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
^ permalink raw reply
* Re: [PATCH v2 03/10] arm64: dts: qcom: sc8280xp-arcata: add USB-C orientation GPIOs
From: Konrad Dybcio @ 2026-05-22 12:07 UTC (permalink / raw)
To: jerome.debretagne, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Johan Hovold
Cc: linux-arm-msm, devicetree, linux-kernel, Krzysztof Kozlowski
In-Reply-To: <20260522-surface-sp9-5g-for-next-v2-3-dd9d477407f5@gmail.com>
On 5/22/26 12:43 PM, Jérôme de Bretagne via B4 Relay wrote:
> From: Jérôme de Bretagne <jerome.debretagne@gmail.com>
>
> Define the USB-C orientation GPIOs so that the orientation is known
> for the two USB-C ports on the left-side.
>
> Signed-off-by: Jérôme de Bretagne <jerome.debretagne@gmail.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox