* [PATCH v3 01/17] ACPI: GTDT: Account for GTDTv3 size when walking the platform timer descriptors
From: Marc Zyngier @ 2026-05-23 14:02 UTC (permalink / raw)
To: linux-arm-kernel, linux-acpi, linux-kernel, devicetree
Cc: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J. Wysocki, Mark Rutland, Daniel Lezcano,
Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Ge Gordon,
BST Linux Kernel Upstream Group, Jesper Nilsson, Lars Persson,
Alim Akhtar, Ivaylo Ivanov, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Matthias Brugger, AngeloGioacchino Del Regno, Thierry Reding,
Jonathan Hunter, Bjorn Andersson, Konrad Dybcio,
Andreas Färber, Yu-Chun Lin [林祐君],
Heiko Stuebner, Shawn Lin, Orson Zhai, Baolin Wang, Michal Simek
In-Reply-To: <20260523140242.586031-1-maz@kernel.org>
Since ARMv8.1, the architecture has grown an EL2-private virtual
timer. This has been described in ACPI since ACPI v6.3 and revision
3 of the GTDT table.
An aditional structure was added in ACPICA, though in a rather
bizarre way, and merged in v5.1 as 8f5a14d053100 ("ACPICA: ACPI 6.3:
add GTDT Revision 3 support").
Finally plug the table parsing in GTDT, and correct the parsing of
the platform timer subtables to account for the expanded size of
the base table. This also comes with some extra sanitisation of
the table, in the unlikely case someone got it wrong...
Suggested-by: Sudeep Holla <sudeep.holla@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
drivers/acpi/arm64/gtdt.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/acpi/arm64/gtdt.c b/drivers/acpi/arm64/gtdt.c
index ffc867bac2d60..950d5efdf85ea 100644
--- a/drivers/acpi/arm64/gtdt.c
+++ b/drivers/acpi/arm64/gtdt.c
@@ -34,14 +34,25 @@ struct acpi_gtdt_descriptor {
void *platform_timer;
};
+struct gtdt_v3 {
+ struct acpi_table_gtdt gtdt_v2;
+ struct acpi_gtdt_el2 el2_vtimer;
+};
+
static struct acpi_gtdt_descriptor acpi_gtdt_desc __initdata;
static __init bool platform_timer_valid(void *platform_timer)
{
struct acpi_gtdt_header *gh = platform_timer;
+ void *platform_timer_begin;
- return (platform_timer >= (void *)(acpi_gtdt_desc.gtdt + 1) &&
- platform_timer < acpi_gtdt_desc.gtdt_end &&
+ if (acpi_gtdt_desc.gtdt->header.revision >= 3)
+ platform_timer_begin = container_of(acpi_gtdt_desc.gtdt, struct gtdt_v3, gtdt_v2) + 1;
+ else
+ platform_timer_begin = acpi_gtdt_desc.gtdt + 1;
+
+ return (platform_timer >= platform_timer_begin &&
+ platform_timer + sizeof(*gh) <= acpi_gtdt_desc.gtdt_end &&
gh->length != 0 &&
platform_timer + gh->length <= acpi_gtdt_desc.gtdt_end);
}
@@ -166,6 +177,13 @@ int __init acpi_gtdt_init(struct acpi_table_header *table,
u32 cnt = 0;
gtdt = container_of(table, struct acpi_table_gtdt, header);
+
+ if ((gtdt->header.revision >= 3 && gtdt->header.length < sizeof(struct gtdt_v3)) ||
+ (gtdt->header.revision == 2 && gtdt->header.length < sizeof(*gtdt))) {
+ pr_err(FW_BUG "GTDT with invalid size %d\n", gtdt->header.length);
+ return -EINVAL;
+ }
+
acpi_gtdt_desc.gtdt = gtdt;
acpi_gtdt_desc.gtdt_end = (void *)table + table->length;
acpi_gtdt_desc.platform_timer = NULL;
--
2.47.3
^ permalink raw reply related
* [PATCH v3 00/17] arm64: Use EL2 virtual timer when running VHE
From: Marc Zyngier @ 2026-05-23 14:02 UTC (permalink / raw)
To: linux-arm-kernel, linux-acpi, linux-kernel, devicetree
Cc: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J. Wysocki, Mark Rutland, Daniel Lezcano,
Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Ge Gordon,
BST Linux Kernel Upstream Group, Jesper Nilsson, Lars Persson,
Alim Akhtar, Ivaylo Ivanov, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Matthias Brugger, AngeloGioacchino Del Regno, Thierry Reding,
Jonathan Hunter, Bjorn Andersson, Konrad Dybcio,
Andreas Färber, Yu-Chun Lin [林祐君],
Heiko Stuebner, Shawn Lin, Orson Zhai, Baolin Wang, Michal Simek
This is the third version of the series initially posted at [1],
which
- updates the ACPI GTDT parsing to deal the v3 layout and the EL2
virtual timer,
- moves the architected timer driver to use it when running VHE,
- fixes a number of DTs to reflect the reality of the HW.
This results in significant performance uplift in deeper nested virt
scenarios, at no overhead to the host.
Patches based on -rc3, tested on Amlogic SM1, QC X1E, Ampere Altra,
and Apple M2, as well as KVM NV guests.
* From v2 [2]:
- Add more consistency checks to the GTDT parsing
- Match the virtual counter when using the KVM PTP backend
- Drop a number of changes to Qualcomm DTs, being only tangentially
related and that will be posted separately
- Fix the Realtek Kent platform, which had the GICv3 maintenance
interrupt advertised as the EL2 virtual timer
- Collected TBs and RBs, with thanks
* From v1 [2]:
- Now also using the EL2 virtual counter, which further improve
things when running at a deeper nesting level
- Updated consistency checks for the platform timers when finding a
GTDTv3
- Collected ABs and RBs, with thanks
[1] https://lore.kernel.org/r/20260507125544.2903406-1-maz@kernel.org
[2] https://lore.kernel.org/r/20260514150945.3917510-1-maz@kernel.org
Marc Zyngier (17):
ACPI: GTDT: Account for GTDTv3 size when walking the platform timer
descriptors
ACPI: GTDT: Parse information related to the EL2 virtual timer
clocksource/drivers/arm_arch_timer: Default to EL2 virtual timer when
running VHE
dt-bindings: timer: arm,arch_timer: Fix requirements for interrupt
description
arm64: dts: allwinner: Add EL2 virtual timer interrupt
arm64: dts: amlogic: Add EL2 virtual timer interrupt
arm64: dts: bst: Add EL2 virtual timer interrupt
arm64: dts: exynos: Add EL2 virtual timer interrupt
arm64: dts: freescale: Add EL2 virtual timer interrupt
arm64: dts: intel: Add EL2 virtual timer interrupt
arm64: dts: mediatek: Add EL2 virtual timer interrupt
arm64: dts: nvidia: Add EL2 virtual timer interrupt
arm64: dts: qcom: Add EL2 virtual timer interrupt
arm64: dts: realtek: Add EL2 virtual timer interrupt
arm64: dts: rockchip: Add EL2 virtual timer interrupt
arm64: dts: sprd: Add EL2 virtual timer interrupt
arm64: dts: xilinx: Add EL2 virtual timer interrupt
.../bindings/timer/arm,arch_timer.yaml | 21 +++----
.../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 3 +-
.../boot/dts/amlogic/amlogic-a4-common.dtsi | 8 ---
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 8 +++
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 9 +++
arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi | 3 +-
arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi | 3 +-
arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi | 3 +-
.../boot/dts/amlogic/meson-g12-common.dtsi | 13 -----
arch/arm64/boot/dts/amlogic/meson-g12.dtsi | 9 +++
arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 10 ++++
arch/arm64/boot/dts/bst/bstc1200.dtsi | 3 +-
arch/arm64/boot/dts/exynos/axis/artpec9.dtsi | 3 +-
arch/arm64/boot/dts/exynos/exynos2200.dtsi | 3 +-
arch/arm64/boot/dts/exynos/exynos990.dtsi | 3 +-
arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 3 +-
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 3 +-
.../boot/dts/freescale/imx91_93_common.dtsi | 3 +-
arch/arm64/boot/dts/freescale/imx94.dtsi | 3 +-
arch/arm64/boot/dts/freescale/imx95.dtsi | 3 +-
arch/arm64/boot/dts/freescale/imx952.dtsi | 3 +-
arch/arm64/boot/dts/freescale/s32n79.dtsi | 3 +-
.../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 3 +-
arch/arm64/boot/dts/mediatek/mt6779.dtsi | 3 +-
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 3 +-
arch/arm64/boot/dts/mediatek/mt8188.dtsi | 3 +-
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 3 +-
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 3 +-
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 +
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 3 +-
arch/arm64/boot/dts/qcom/eliza.dtsi | 3 +-
arch/arm64/boot/dts/qcom/hamoa.dtsi | 3 +-
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 3 +-
arch/arm64/boot/dts/qcom/kodiak.dtsi | 3 +-
arch/arm64/boot/dts/qcom/lemans.dtsi | 3 +-
arch/arm64/boot/dts/qcom/monaco.dtsi | 3 +-
arch/arm64/boot/dts/qcom/sar2130p.dtsi | 3 +-
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 3 +-
arch/arm64/boot/dts/qcom/sm4450.dtsi | 3 +-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 3 +-
arch/arm64/boot/dts/qcom/sm8350.dtsi | 3 +-
arch/arm64/boot/dts/qcom/sm8450.dtsi | 3 +-
arch/arm64/boot/dts/qcom/sm8550.dtsi | 3 +-
arch/arm64/boot/dts/qcom/sm8650.dtsi | 3 +-
arch/arm64/boot/dts/qcom/sm8750.dtsi | 3 +-
arch/arm64/boot/dts/realtek/kent.dtsi | 2 +-
arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 3 +-
arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 3 +-
arch/arm64/boot/dts/sprd/sc9863a.dtsi | 3 +-
arch/arm64/boot/dts/sprd/ums512.dtsi | 3 +-
arch/arm64/boot/dts/sprd/ums9620.dtsi | 3 +-
arch/arm64/boot/dts/xilinx/versal-net.dtsi | 3 +-
drivers/acpi/arm64/gtdt.c | 42 +++++++++++++-
drivers/clocksource/arm_arch_timer.c | 55 +++++++++++--------
54 files changed, 206 insertions(+), 102 deletions(-)
--
2.47.3
^ permalink raw reply
* [PATCH v3 02/17] ACPI: GTDT: Parse information related to the EL2 virtual timer
From: Marc Zyngier @ 2026-05-23 14:02 UTC (permalink / raw)
To: linux-arm-kernel, linux-acpi, linux-kernel, devicetree
Cc: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J. Wysocki, Mark Rutland, Daniel Lezcano,
Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Ge Gordon,
BST Linux Kernel Upstream Group, Jesper Nilsson, Lars Persson,
Alim Akhtar, Ivaylo Ivanov, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Matthias Brugger, AngeloGioacchino Del Regno, Thierry Reding,
Jonathan Hunter, Bjorn Andersson, Konrad Dybcio,
Andreas Färber, Yu-Chun Lin [林祐君],
Heiko Stuebner, Shawn Lin, Orson Zhai, Baolin Wang, Michal Simek
In-Reply-To: <20260523140242.586031-1-maz@kernel.org>
Now that we have a way to identify GTDTv3, allow the information
related to the EL2 virtual timer to be retrieved by the interface
used by the architected timer driver.
Reviewed-by: Sudeep Holla <sudeep.holla@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
drivers/acpi/arm64/gtdt.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/acpi/arm64/gtdt.c b/drivers/acpi/arm64/gtdt.c
index 950d5efdf85ea..00158c8aa6d90 100644
--- a/drivers/acpi/arm64/gtdt.c
+++ b/drivers/acpi/arm64/gtdt.c
@@ -41,6 +41,14 @@ struct gtdt_v3 {
static struct acpi_gtdt_descriptor acpi_gtdt_desc __initdata;
+static __init struct acpi_gtdt_el2 *gtdt_to_el2_vtimer(struct acpi_table_gtdt *gtdt)
+{
+ if (gtdt->header.revision < 3)
+ return NULL;
+
+ return &container_of(gtdt, struct gtdt_v3, gtdt_v2)->el2_vtimer;
+}
+
static __init bool platform_timer_valid(void *platform_timer)
{
struct acpi_gtdt_header *gh = platform_timer;
@@ -112,6 +120,7 @@ static int __init map_gt_gsi(u32 interrupt, u32 flags)
int __init acpi_gtdt_map_ppi(int type)
{
struct acpi_table_gtdt *gtdt = acpi_gtdt_desc.gtdt;
+ struct acpi_gtdt_el2 *el2_vtimer = gtdt_to_el2_vtimer(gtdt);
switch (type) {
case ARCH_TIMER_PHYS_NONSECURE_PPI:
@@ -124,6 +133,12 @@ int __init acpi_gtdt_map_ppi(int type)
case ARCH_TIMER_HYP_PPI:
return map_gt_gsi(gtdt->non_secure_el2_interrupt,
gtdt->non_secure_el2_flags);
+ case ARCH_TIMER_HYP_VIRT_PPI:
+ if (el2_vtimer && el2_vtimer->virtual_el2_timer_gsiv)
+ return map_gt_gsi(el2_vtimer->virtual_el2_timer_gsiv,
+ el2_vtimer->virtual_el2_timer_flags);
+
+ return 0;
default:
pr_err("Failed to map timer interrupt: invalid type.\n");
}
@@ -141,6 +156,7 @@ int __init acpi_gtdt_map_ppi(int type)
bool __init acpi_gtdt_c3stop(int type)
{
struct acpi_table_gtdt *gtdt = acpi_gtdt_desc.gtdt;
+ struct acpi_gtdt_el2 *el2_vtimer = gtdt_to_el2_vtimer(gtdt);
switch (type) {
case ARCH_TIMER_PHYS_NONSECURE_PPI:
@@ -152,6 +168,10 @@ bool __init acpi_gtdt_c3stop(int type)
case ARCH_TIMER_HYP_PPI:
return !(gtdt->non_secure_el2_flags & ACPI_GTDT_ALWAYS_ON);
+ case ARCH_TIMER_HYP_VIRT_PPI:
+ return el2_vtimer && el2_vtimer->virtual_el2_timer_gsiv &&
+ !(el2_vtimer->virtual_el2_timer_flags & ACPI_GTDT_ALWAYS_ON);
+
default:
pr_err("Failed to get c3stop info: invalid type.\n");
}
--
2.47.3
^ permalink raw reply related
* [PATCH v3 03/17] clocksource/drivers/arm_arch_timer: Default to EL2 virtual timer when running VHE
From: Marc Zyngier @ 2026-05-23 14:02 UTC (permalink / raw)
To: linux-arm-kernel, linux-acpi, linux-kernel, devicetree
Cc: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J. Wysocki, Mark Rutland, Daniel Lezcano,
Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Ge Gordon,
BST Linux Kernel Upstream Group, Jesper Nilsson, Lars Persson,
Alim Akhtar, Ivaylo Ivanov, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Matthias Brugger, AngeloGioacchino Del Regno, Thierry Reding,
Jonathan Hunter, Bjorn Andersson, Konrad Dybcio,
Andreas Färber, Yu-Chun Lin [林祐君],
Heiko Stuebner, Shawn Lin, Orson Zhai, Baolin Wang, Michal Simek
In-Reply-To: <20260523140242.586031-1-maz@kernel.org>
When running with at EL2 with VHE enabled, the architecture provides
two EL2 timer/counters, dubbed physical and virtual. Apart from their
names, they are strictly identical.
However, they don't get virtualised the same way, specially when
it comes to adding arbitrary offsets to the timers. When running as
a guest, the host CNTVOFF_EL2 does apply to the guest's view of
CNTHV*_El2. This is not true for CNTPOFF_EL2 and CNTHP*_EL2, as
the architecture is broken past the first level of virtualisation
(it lacks some essential mechanisms to be usable, despite what
the ARM ARM pretends).
This means that when running as a L2 guest hypervisor, using the
physical timer results in traps to L0, which are then forwarded to
L1 in order to emulate the offset, leading to even worse performance
due to massive trap amplification (the combination of register and
ERET trapping is absolutely lethal).
Switch the arch timer code to using the virtual timer when running
in VHE by default, only using the physical timer if the interrupt
is not correctly described in the firmware tables (which seems
to be an unfortunately common case). This comes as no impact on
bare-metal, and slightly improves the situation in the virtualised
case.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
drivers/clocksource/arm_arch_timer.c | 55 +++++++++++++++++-----------
1 file changed, 33 insertions(+), 22 deletions(-)
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 90aeff44a2764..4adf756423de9 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -688,6 +688,7 @@ static void __arch_timer_setup(struct clock_event_device *clk)
clk->irq = arch_timer_ppi[arch_timer_uses_ppi];
switch (arch_timer_uses_ppi) {
case ARCH_TIMER_VIRT_PPI:
+ case ARCH_TIMER_HYP_VIRT_PPI:
clk->set_state_shutdown = arch_timer_shutdown_virt;
clk->set_state_oneshot_stopped = arch_timer_shutdown_virt;
sne = erratum_handler(set_next_event_virt);
@@ -879,7 +880,7 @@ static void __init arch_timer_banner(void)
pr_info("cp15 timer running at %lu.%02luMHz (%s).\n",
(unsigned long)arch_timer_rate / 1000000,
(unsigned long)(arch_timer_rate / 10000) % 100,
- (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) ? "virt" : "phys");
+ arch_timer_ppi_names[arch_timer_uses_ppi]);
}
u32 arch_timer_get_rate(void)
@@ -912,7 +913,8 @@ static void __init arch_counter_register(void)
int width;
if ((IS_ENABLED(CONFIG_ARM64) && !is_hyp_mode_available()) ||
- arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) {
+ arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI ||
+ arch_timer_uses_ppi == ARCH_TIMER_HYP_VIRT_PPI) {
if (arch_timer_counter_has_wa()) {
rd = arch_counter_get_cntvct_stable;
scr = raw_counter_get_cntvct_stable;
@@ -1023,6 +1025,7 @@ static int __init arch_timer_register(void)
ppi = arch_timer_ppi[arch_timer_uses_ppi];
switch (arch_timer_uses_ppi) {
case ARCH_TIMER_VIRT_PPI:
+ case ARCH_TIMER_HYP_VIRT_PPI:
err = request_percpu_irq(ppi, arch_timer_handler_virt,
"arch_timer", arch_timer_evt);
break;
@@ -1090,25 +1093,34 @@ static int __init arch_timer_common_init(void)
/**
* arch_timer_select_ppi() - Select suitable PPI for the current system.
*
- * If HYP mode is available, we know that the physical timer
- * has been configured to be accessible from PL1. Use it, so
- * that a guest can use the virtual timer instead.
+ * On AArch32, if HYP mode is available, we know that the physical
+ * timer has been configured to be accessible from PL1. Use it, so
+ * that a guest can use the virtual timer instead (though KVM host
+ * support has long been removed).
*
- * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE
- * accesses to CNTP_*_EL1 registers are silently redirected to
- * their CNTHP_*_EL2 counterparts, and use a different PPI
- * number.
+ * On ARMv8.1 with FEAT_VHE, the kernel runs in EL2. Accesses to
+ * CNTV_*_EL1 registers are silently redirected to their CNTHV_*_EL2
+ * counterparts, and the timer uses a different PPI number. Similar
+ * thing happen when using the EL2 physical timer. Note that a bunch
+ * of DTs out there omit the virtual EL2 timer, so fallback gracefully
+ * on the physical timer.
+ *
+ * Without VHE, if no interrupt provided for virtual timer, we'll have
+ * to stick to the physical timer. It'd better be accessible...
*
- * If no interrupt provided for virtual timer, we'll have to
- * stick to the physical timer. It'd better be accessible...
* For arm64 we never use the secure interrupt.
*
* Return: a suitable PPI type for the current system.
*/
static enum arch_timer_ppi_nr __init arch_timer_select_ppi(void)
{
- if (is_kernel_in_hyp_mode())
+ if (is_kernel_in_hyp_mode()) {
+ if (arch_timer_ppi[ARCH_TIMER_HYP_VIRT_PPI])
+ return ARCH_TIMER_HYP_VIRT_PPI;
+
+ pr_warn_once(FW_BUG "VHE-capable CPU without EL2 virtual timer interrupt\n");
return ARCH_TIMER_HYP_PPI;
+ }
if (!is_hyp_mode_available() && arch_timer_ppi[ARCH_TIMER_VIRT_PPI])
return ARCH_TIMER_VIRT_PPI;
@@ -1200,14 +1212,9 @@ static int __init arch_timer_acpi_init(struct acpi_table_header *table)
if (ret)
return ret;
- arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI] =
- acpi_gtdt_map_ppi(ARCH_TIMER_PHYS_NONSECURE_PPI);
-
- arch_timer_ppi[ARCH_TIMER_VIRT_PPI] =
- acpi_gtdt_map_ppi(ARCH_TIMER_VIRT_PPI);
-
- arch_timer_ppi[ARCH_TIMER_HYP_PPI] =
- acpi_gtdt_map_ppi(ARCH_TIMER_HYP_PPI);
+ /* The GTDT parser can't be bothered with the secure timer */
+ for (int i = ARCH_TIMER_PHYS_NONSECURE_PPI; i < ARCH_TIMER_MAX_TIMER_PPI; i++)
+ arch_timer_ppi[i] = acpi_gtdt_map_ppi(i);
arch_timer_populate_kvm_info();
@@ -1253,10 +1260,14 @@ int kvm_arch_ptp_get_crosststamp(u64 *cycle, struct timespec64 *ts,
if (!IS_ENABLED(CONFIG_HAVE_ARM_SMCCC_DISCOVERY))
return -EOPNOTSUPP;
- if (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI)
+ switch (arch_timer_uses_ppi) {
+ case ARCH_TIMER_VIRT_PPI:
+ case ARCH_TIMER_HYP_VIRT_PPI:
ptp_counter = KVM_PTP_VIRT_COUNTER;
- else
+ break;
+ default:
ptp_counter = KVM_PTP_PHYS_COUNTER;
+ }
arm_smccc_1_1_invoke(ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID,
ptp_counter, &hvc_res);
--
2.47.3
^ permalink raw reply related
* [PATCH v3 04/17] dt-bindings: timer: arm,arch_timer: Fix requirements for interrupt description
From: Marc Zyngier @ 2026-05-23 14:02 UTC (permalink / raw)
To: linux-arm-kernel, linux-acpi, linux-kernel, devicetree
Cc: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J. Wysocki, Mark Rutland, Daniel Lezcano,
Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Ge Gordon,
BST Linux Kernel Upstream Group, Jesper Nilsson, Lars Persson,
Alim Akhtar, Ivaylo Ivanov, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Matthias Brugger, AngeloGioacchino Del Regno, Thierry Reding,
Jonathan Hunter, Bjorn Andersson, Konrad Dybcio,
Andreas Färber, Yu-Chun Lin [林祐君],
Heiko Stuebner, Shawn Lin, Orson Zhai, Baolin Wang, Michal Simek
In-Reply-To: <20260523140242.586031-1-maz@kernel.org>
The arm,arch_timer DT binding is extremely imprecise in describing
the requirements for interrupts.
Follow the architecture by making it explicit that:
- the EL1 secure timer irq is required if EL3 is implemented
- the EL1 physical timer irq is always required
- the EL1 virtual timer irq is always required
- the EL2 physical timer irq is required if EL2 is implemented
- the EL2 virtual timer irq is required if FEAT_VHE is implemented
The consequence of the above is that the minimum number of interrupts
to be described is 2, and not 1.
Finally, clean up the description which made the assumption that
the timers are plugged into a GIC (unfortunately, that's not always
true), drop the MMIO nonsense that has long be moved to a separate
binding, and use the architectural terminology to describe the various
interrupts.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
.../bindings/timer/arm,arch_timer.yaml | 21 +++++++------------
1 file changed, 8 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
index c5fc3b6c8bd0b..c65e48a155ab6 100644
--- a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
+++ b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
@@ -10,13 +10,8 @@ maintainers:
- Marc Zyngier <marc.zyngier@arm.com>
- Mark Rutland <mark.rutland@arm.com>
description: |+
- ARM cores may have a per-core architected timer, which provides per-cpu timers,
- or a memory mapped architected timer, which provides up to 8 frames with a
- physical and optional virtual timer per frame.
-
- The per-core architected timer is attached to a GIC to deliver its
- per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
- to deliver its interrupts via SPIs.
+ The per-core architected timer is expected to deliver per-CPU interrupts
+ (commonly to a GIC to deliver its per-processor interrupts as PPIs).
properties:
compatible:
@@ -33,13 +28,13 @@ properties:
- const: arm,armv7-timer
interrupts:
- minItems: 1
+ minItems: 2
items:
- - description: secure timer irq
- - description: non-secure timer irq
- - description: virtual timer irq
- - description: hypervisor timer irq
- - description: hypervisor virtual timer irq
+ - description: EL1 secure physical timer irq, if EL3 is implemented
+ - description: EL1 non-secure physical timer irq
+ - description: EL1 virtual timer irq
+ - description: EL2 physical timer irq, if EL2 is implemented
+ - description: EL2 virtual timer irq, if FEAT_VHE is implemented
interrupt-names:
oneOf:
--
2.47.3
^ permalink raw reply related
* [PATCH v3 05/17] arm64: dts: allwinner: Add EL2 virtual timer interrupt
From: Marc Zyngier @ 2026-05-23 14:02 UTC (permalink / raw)
To: linux-arm-kernel, linux-acpi, linux-kernel, devicetree
Cc: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J. Wysocki, Mark Rutland, Daniel Lezcano,
Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Ge Gordon,
BST Linux Kernel Upstream Group, Jesper Nilsson, Lars Persson,
Alim Akhtar, Ivaylo Ivanov, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Matthias Brugger, AngeloGioacchino Del Regno, Thierry Reding,
Jonathan Hunter, Bjorn Andersson, Konrad Dybcio,
Andreas Färber, Yu-Chun Lin [林祐君],
Heiko Stuebner, Shawn Lin, Orson Zhai, Baolin Wang, Michal Simek,
Andre Przywara
In-Reply-To: <20260523140242.586031-1-maz@kernel.org>
The ARMv8.2 based CPUs used in the A523 SoC (and derivatives)
are missing the EL2 virtual timer interrupt. Add it.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
index 5afa8d92acbfb..d3c47966e8fc8 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
@@ -101,7 +101,8 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
};
soc {
--
2.47.3
^ permalink raw reply related
* [PATCH v3 07/17] arm64: dts: bst: Add EL2 virtual timer interrupt
From: Marc Zyngier @ 2026-05-23 14:02 UTC (permalink / raw)
To: linux-arm-kernel, linux-acpi, linux-kernel, devicetree
Cc: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J. Wysocki, Mark Rutland, Daniel Lezcano,
Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Ge Gordon,
BST Linux Kernel Upstream Group, Jesper Nilsson, Lars Persson,
Alim Akhtar, Ivaylo Ivanov, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Matthias Brugger, AngeloGioacchino Del Regno, Thierry Reding,
Jonathan Hunter, Bjorn Andersson, Konrad Dybcio,
Andreas Färber, Yu-Chun Lin [林祐君],
Heiko Stuebner, Shawn Lin, Orson Zhai, Baolin Wang, Michal Simek
In-Reply-To: <20260523140242.586031-1-maz@kernel.org>
The ARMv8.2 based CPUs used in the bst c1200 SoC are missing the EL2
virtual timer interrupt. Add it.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/boot/dts/bst/bstc1200.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/bst/bstc1200.dtsi b/arch/arm64/boot/dts/bst/bstc1200.dtsi
index dd13c6bfc3c89..104ecf76ced10 100644
--- a/arch/arm64/boot/dts/bst/bstc1200.dtsi
+++ b/arch/arm64/boot/dts/bst/bstc1200.dtsi
@@ -92,6 +92,7 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
};
};
--
2.47.3
^ permalink raw reply related
* [PATCH v3 06/17] arm64: dts: amlogic: Add EL2 virtual timer interrupt
From: Marc Zyngier @ 2026-05-23 14:02 UTC (permalink / raw)
To: linux-arm-kernel, linux-acpi, linux-kernel, devicetree
Cc: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J. Wysocki, Mark Rutland, Daniel Lezcano,
Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Ge Gordon,
BST Linux Kernel Upstream Group, Jesper Nilsson, Lars Persson,
Alim Akhtar, Ivaylo Ivanov, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Matthias Brugger, AngeloGioacchino Del Regno, Thierry Reding,
Jonathan Hunter, Bjorn Andersson, Konrad Dybcio,
Andreas Färber, Yu-Chun Lin [林祐君],
Heiko Stuebner, Shawn Lin, Orson Zhai, Baolin Wang, Michal Simek
In-Reply-To: <20260523140242.586031-1-maz@kernel.org>
The ARMv8.2 based CPUs used in a number of Amlogic SoCs are missing
the EL2 virtual timer interrupt. Add it.
This requires some surgery in the "common" files to move the timer
node to locations that makes it possible to add the interrupt only
where it is actually implemented.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi | 8 --------
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 8 ++++++++
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 9 +++++++++
arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi | 3 ++-
arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi | 3 ++-
arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi | 3 ++-
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 13 -------------
arch/arm64/boot/dts/amlogic/meson-g12.dtsi | 9 +++++++++
arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 10 ++++++++++
9 files changed, 42 insertions(+), 24 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi
index 54d7a2d56ef64..6f559e4dd9ee9 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi
@@ -7,14 +7,6 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
/ {
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
psci {
compatible = "arm,psci-1.0";
method = "smc";
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
index fce45933fa28b..c28fc7fcbae7f 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
@@ -86,6 +86,14 @@ pwrc: power-controller {
#power-domain-cells = <1>;
};
};
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
};
&apb {
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
index 2b12d8284594f..c22c0acb4807e 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
@@ -49,6 +49,15 @@ pwrc: power-controller {
#power-domain-cells = <1>;
};
};
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
};
&apb {
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi
index ab3acef2b147e..853d32929ff46 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi
@@ -56,7 +56,8 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
};
psci {
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
index a3faf4d188e11..bfaac5f3e22da 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
@@ -94,7 +94,8 @@ timer {
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
psci {
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi
index 0c4417bcd6827..32d8683059964 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi
@@ -58,7 +58,8 @@ timer {
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
psci {
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
index 00609d2da6743..a911a5181a88d 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
@@ -2579,19 +2579,6 @@ map {
};
};
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
- arm,no-tick-in-suspend;
- };
-
xtal: xtal-clk {
compatible = "fixed-clock";
clock-frequency = <24000000>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12.dtsi
index 664912d1beaab..866fc07d1b0ae 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12.dtsi
@@ -43,6 +43,15 @@ tdmif_c: audio-controller-2 {
clock-names = "sclk", "lrclk", "mclk";
status = "disabled";
};
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
+ arm,no-tick-in-suspend;
+ };
};
&apb {
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
index 8f5b850b1774f..77c72936ffdd3 100644
--- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
@@ -128,6 +128,16 @@ l2: l2-cache0 {
};
};
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 12 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
+ arm,no-tick-in-suspend;
+ };
+
cpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-shared;
--
2.47.3
^ permalink raw reply related
* [PATCH v3 08/17] arm64: dts: exynos: Add EL2 virtual timer interrupt
From: Marc Zyngier @ 2026-05-23 14:02 UTC (permalink / raw)
To: linux-arm-kernel, linux-acpi, linux-kernel, devicetree
Cc: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J. Wysocki, Mark Rutland, Daniel Lezcano,
Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Ge Gordon,
BST Linux Kernel Upstream Group, Jesper Nilsson, Lars Persson,
Alim Akhtar, Ivaylo Ivanov, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Matthias Brugger, AngeloGioacchino Del Regno, Thierry Reding,
Jonathan Hunter, Bjorn Andersson, Konrad Dybcio,
Andreas Färber, Yu-Chun Lin [林祐君],
Heiko Stuebner, Shawn Lin, Orson Zhai, Baolin Wang, Michal Simek
In-Reply-To: <20260523140242.586031-1-maz@kernel.org>
A bunch of Samsung SoCs are missing the EL2 virtual timer interrupt
despite using ARMv8.1+ CPUs. Add the missing interrupt, except for
those broken designs where the interrupt is documented as not being
wired.
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/boot/dts/exynos/axis/artpec9.dtsi | 3 ++-
arch/arm64/boot/dts/exynos/exynos2200.dtsi | 3 ++-
arch/arm64/boot/dts/exynos/exynos990.dtsi | 3 ++-
arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 3 ++-
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 3 ++-
5 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/axis/artpec9.dtsi b/arch/arm64/boot/dts/exynos/axis/artpec9.dtsi
index f8ed43c6e8258..cd46aaf056287 100644
--- a/arch/arm64/boot/dts/exynos/axis/artpec9.dtsi
+++ b/arch/arm64/boot/dts/exynos/axis/artpec9.dtsi
@@ -272,6 +272,7 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/dts/exynos/exynos2200.dtsi
index 6487ccb58ae76..59662f9bdb98f 100644
--- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi
@@ -1911,7 +1911,8 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0>;
/*
* Non-updatable, broken stock Samsung bootloader does not
* configure CNTFRQ_EL0
diff --git a/arch/arm64/boot/dts/exynos/exynos990.dtsi b/arch/arm64/boot/dts/exynos/exynos990.dtsi
index f8e2a31b4b751..2e6fb24a3c928 100644
--- a/arch/arm64/boot/dts/exynos/exynos990.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos990.dtsi
@@ -405,7 +405,8 @@ timer {
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
/*
* Non-updatable, broken stock Samsung bootloader does not
diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
index 66628cb32776e..2c34a2b30ad02 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
@@ -148,7 +148,8 @@ timer {
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
fixed-rate-clocks {
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index d085f9fb0f62a..86933f22647b7 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -1856,7 +1856,8 @@ timer {
<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>;
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
+ <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>;
};
};
--
2.47.3
^ permalink raw reply related
* [PATCH v3 09/17] arm64: dts: freescale: Add EL2 virtual timer interrupt
From: Marc Zyngier @ 2026-05-23 14:02 UTC (permalink / raw)
To: linux-arm-kernel, linux-acpi, linux-kernel, devicetree
Cc: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J. Wysocki, Mark Rutland, Daniel Lezcano,
Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Ge Gordon,
BST Linux Kernel Upstream Group, Jesper Nilsson, Lars Persson,
Alim Akhtar, Ivaylo Ivanov, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Matthias Brugger, AngeloGioacchino Del Regno, Thierry Reding,
Jonathan Hunter, Bjorn Andersson, Konrad Dybcio,
Andreas Färber, Yu-Chun Lin [林祐君],
Heiko Stuebner, Shawn Lin, Orson Zhai, Baolin Wang, Michal Simek
In-Reply-To: <20260523140242.586031-1-maz@kernel.org>
The ARMv8.2 based CPUs used in a number of NXP/FSL SoCs are missing
the EL2 virtual timer interrupt. Add it.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/boot/dts/freescale/imx91_93_common.dtsi | 3 ++-
arch/arm64/boot/dts/freescale/imx94.dtsi | 3 ++-
arch/arm64/boot/dts/freescale/imx95.dtsi | 3 ++-
arch/arm64/boot/dts/freescale/imx952.dtsi | 3 ++-
arch/arm64/boot/dts/freescale/s32n79.dtsi | 3 ++-
5 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi
index 46a5d2df074d5..679b9a6f7160f 100644
--- a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi
@@ -82,7 +82,8 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <24000000>;
arm,no-tick-in-suspend;
interrupt-parent = <&gic>;
diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi
index c460ece6070f8..7431ce293625b 100644
--- a/arch/arm64/boot/dts/freescale/imx94.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx94.dtsi
@@ -147,7 +147,8 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <24000000>;
interrupt-parent = <&gic>;
arm,no-tick-in-suspend;
diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index 71394871d8dd0..e318048dc755b 100644
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -524,7 +524,8 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <24000000>;
arm,no-tick-in-suspend;
interrupt-parent = <&gic>;
diff --git a/arch/arm64/boot/dts/freescale/imx952.dtsi b/arch/arm64/boot/dts/freescale/imx952.dtsi
index b30707837f353..7c65956bc72dc 100644
--- a/arch/arm64/boot/dts/freescale/imx952.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx952.dtsi
@@ -298,7 +298,8 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <24000000>;
arm,no-tick-in-suspend;
interrupt-parent = <&gic>;
diff --git a/arch/arm64/boot/dts/freescale/s32n79.dtsi b/arch/arm64/boot/dts/freescale/s32n79.dtsi
index 94ab58783fdc8..fb40abec4c5cd 100644
--- a/arch/arm64/boot/dts/freescale/s32n79.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32n79.dtsi
@@ -357,6 +357,7 @@ timer: timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
};
};
--
2.47.3
^ permalink raw reply related
* [PATCH v3 10/17] arm64: dts: intel: Add EL2 virtual timer interrupt
From: Marc Zyngier @ 2026-05-23 14:02 UTC (permalink / raw)
To: linux-arm-kernel, linux-acpi, linux-kernel, devicetree
Cc: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J. Wysocki, Mark Rutland, Daniel Lezcano,
Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Ge Gordon,
BST Linux Kernel Upstream Group, Jesper Nilsson, Lars Persson,
Alim Akhtar, Ivaylo Ivanov, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Matthias Brugger, AngeloGioacchino Del Regno, Thierry Reding,
Jonathan Hunter, Bjorn Andersson, Konrad Dybcio,
Andreas Färber, Yu-Chun Lin [林祐君],
Heiko Stuebner, Shawn Lin, Orson Zhai, Baolin Wang, Michal Simek
In-Reply-To: <20260523140242.586031-1-maz@kernel.org>
The ARMv8.2 based CPUs used in the agilex5 SoC are missing the EL2 virtual
timer interrupt. Add it.
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 02e62d954e949..6db2d48b9bad3 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -155,7 +155,8 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
};
usbphy0: usbphy {
--
2.47.3
^ permalink raw reply related
* [PATCH v3 11/17] arm64: dts: mediatek: Add EL2 virtual timer interrupt
From: Marc Zyngier @ 2026-05-23 14:02 UTC (permalink / raw)
To: linux-arm-kernel, linux-acpi, linux-kernel, devicetree
Cc: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J. Wysocki, Mark Rutland, Daniel Lezcano,
Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Ge Gordon,
BST Linux Kernel Upstream Group, Jesper Nilsson, Lars Persson,
Alim Akhtar, Ivaylo Ivanov, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Matthias Brugger, AngeloGioacchino Del Regno, Thierry Reding,
Jonathan Hunter, Bjorn Andersson, Konrad Dybcio,
Andreas Färber, Yu-Chun Lin [林祐君],
Heiko Stuebner, Shawn Lin, Orson Zhai, Baolin Wang, Michal Simek
In-Reply-To: <20260523140242.586031-1-maz@kernel.org>
The ARMv8.1+ based CPUs used in a number of Mediatek SoCs are missing
the EL2 virtual timer interrupt. Add it.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/boot/dts/mediatek/mt6779.dtsi | 3 ++-
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 3 ++-
arch/arm64/boot/dts/mediatek/mt8188.dtsi | 3 ++-
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 3 ++-
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 3 ++-
5 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
index 70f3375916e8c..106df7603d533 100644
--- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
@@ -108,7 +108,8 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0>;
};
soc {
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index b91f88ffae0e8..a4621ce370d8e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -815,7 +815,8 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0>;
};
soc {
diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index 75133794cec38..614e75f46c72d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -918,7 +918,8 @@ timer: timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
clock-frequency = <13000000>;
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 9f8f115edd4cc..873c4fae6afc9 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -328,7 +328,8 @@ timer: timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
clock-frequency = <13000000>;
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index c72e34c57629d..3c9a7a08612b9 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -451,7 +451,8 @@ timer: timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
};
soc {
--
2.47.3
^ permalink raw reply related
* [PATCH v3 12/17] arm64: dts: nvidia: Add EL2 virtual timer interrupt
From: Marc Zyngier @ 2026-05-23 14:02 UTC (permalink / raw)
To: linux-arm-kernel, linux-acpi, linux-kernel, devicetree
Cc: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J. Wysocki, Mark Rutland, Daniel Lezcano,
Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Ge Gordon,
BST Linux Kernel Upstream Group, Jesper Nilsson, Lars Persson,
Alim Akhtar, Ivaylo Ivanov, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Matthias Brugger, AngeloGioacchino Del Regno, Thierry Reding,
Jonathan Hunter, Bjorn Andersson, Konrad Dybcio,
Andreas Färber, Yu-Chun Lin [林祐君],
Heiko Stuebner, Shawn Lin, Orson Zhai, Baolin Wang, Michal Simek
In-Reply-To: <20260523140242.586031-1-maz@kernel.org>
The ARMv8.2 based CPUs used in a number of nvidia SoCs are missing
the EL2 virtual timer interrupt. Add it.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 ++
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 3 ++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 849694f751d90..45cc180ac9973 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -3163,6 +3163,8 @@ timer {
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 12
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&gic>;
always-on;
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 04a95b6658caa..ab9813f9ba30c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -5872,7 +5872,8 @@ timer {
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&gic>;
always-on;
};
--
2.47.3
^ permalink raw reply related
* [PATCH v3 14/17] arm64: dts: realtek: Add EL2 virtual timer interrupt
From: Marc Zyngier @ 2026-05-23 14:02 UTC (permalink / raw)
To: linux-arm-kernel, linux-acpi, linux-kernel, devicetree
Cc: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J. Wysocki, Mark Rutland, Daniel Lezcano,
Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Ge Gordon,
BST Linux Kernel Upstream Group, Jesper Nilsson, Lars Persson,
Alim Akhtar, Ivaylo Ivanov, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Matthias Brugger, AngeloGioacchino Del Regno, Thierry Reding,
Jonathan Hunter, Bjorn Andersson, Konrad Dybcio,
Andreas Färber, Yu-Chun Lin [林祐君],
Heiko Stuebner, Shawn Lin, Orson Zhai, Baolin Wang, Michal Simek
In-Reply-To: <20260523140242.586031-1-maz@kernel.org>
The ARMv8.2 based CPUs used in a number of Realtek SoCs are missing
the EL2 virtual timer interrupt. Add it.
Furthermore, the "kent" platform appears to assign PPI9 to both the
EL2 virtual timer and the GIC Maintenance Interrupt, which can't be
right. Attempt a fix by setting the former to PPI12, as PPI9 is
traditionally wired to the GIC itself.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/boot/dts/realtek/kent.dtsi | 2 +-
arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/realtek/kent.dtsi b/arch/arm64/boot/dts/realtek/kent.dtsi
index ae006ce244205..4147e4269247a 100644
--- a/arch/arm64/boot/dts/realtek/kent.dtsi
+++ b/arch/arm64/boot/dts/realtek/kent.dtsi
@@ -23,7 +23,7 @@ timer {
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
};
cpus {
diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
index 3a7f6e35b7f74..43b13d133c324 100644
--- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
@@ -105,7 +105,8 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
};
arm_pmu: pmu {
--
2.47.3
^ permalink raw reply related
* [PATCH v3 13/17] arm64: dts: qcom: Add EL2 virtual timer interrupt
From: Marc Zyngier @ 2026-05-23 14:02 UTC (permalink / raw)
To: linux-arm-kernel, linux-acpi, linux-kernel, devicetree
Cc: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J. Wysocki, Mark Rutland, Daniel Lezcano,
Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Ge Gordon,
BST Linux Kernel Upstream Group, Jesper Nilsson, Lars Persson,
Alim Akhtar, Ivaylo Ivanov, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Matthias Brugger, AngeloGioacchino Del Regno, Thierry Reding,
Jonathan Hunter, Bjorn Andersson, Konrad Dybcio,
Andreas Färber, Yu-Chun Lin [林祐君],
Heiko Stuebner, Shawn Lin, Orson Zhai, Baolin Wang, Michal Simek
In-Reply-To: <20260523140242.586031-1-maz@kernel.org>
The ARMv8.1+ based CPUs used in a number of Qualcomm SoCs are missing
the EL2 virtual timer interrupt. Add it when it is obvious that the
PPI layout is the "standard" one.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/boot/dts/qcom/eliza.dtsi | 3 ++-
arch/arm64/boot/dts/qcom/hamoa.dtsi | 3 ++-
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 3 ++-
arch/arm64/boot/dts/qcom/kodiak.dtsi | 3 ++-
arch/arm64/boot/dts/qcom/lemans.dtsi | 3 ++-
arch/arm64/boot/dts/qcom/monaco.dtsi | 3 ++-
arch/arm64/boot/dts/qcom/sar2130p.dtsi | 3 ++-
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 3 ++-
arch/arm64/boot/dts/qcom/sm4450.dtsi | 3 ++-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 3 ++-
arch/arm64/boot/dts/qcom/sm8350.dtsi | 3 ++-
arch/arm64/boot/dts/qcom/sm8450.dtsi | 3 ++-
arch/arm64/boot/dts/qcom/sm8550.dtsi | 3 ++-
arch/arm64/boot/dts/qcom/sm8650.dtsi | 3 ++-
arch/arm64/boot/dts/qcom/sm8750.dtsi | 3 ++-
15 files changed, 30 insertions(+), 15 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi
index 4a7a0ac40ce62..7267e0ec44b2b 100644
--- a/arch/arm64/boot/dts/qcom/eliza.dtsi
+++ b/arch/arm64/boot/dts/qcom/eliza.dtsi
@@ -1880,6 +1880,7 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
index 051dee0764167..cc638b9162c25 100644
--- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
+++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
@@ -8982,7 +8982,8 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
};
thermal_zones: thermal-zones {
diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index 7cc326aa1a1aa..149275828f1bc 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -6953,7 +6953,8 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
};
tpdm-cdsp-llm {
diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index 988ca5f7c8a0e..8e0a1ca0125d1 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -7876,6 +7876,7 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index fe6e763518230..cd9c964e884f3 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -8585,7 +8585,8 @@ arch_timer: timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
};
turing-llm-tpdm {
diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index 7b1d57460f1e6..38e54b91f0d81 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -8312,6 +8312,7 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
index d65ad0df68652..11ea2330f3ac5 100644
--- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
@@ -3165,7 +3165,8 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
};
thermal-zones {
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 761f229e8f472..e5fc52e6f613e 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -7043,6 +7043,7 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
index 696e2e0841ad9..c7890f5ab8f13 100644
--- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
@@ -681,6 +681,7 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 7076720413ab2..ad44ab7d89fdb 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -6293,7 +6293,8 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
};
thermal-zones {
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index c830953156ec6..63081dcc94aac 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -4542,6 +4542,7 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 03bf30b53f289..e7a890dc2e57f 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -6327,7 +6327,8 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <19200000>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 912525e9bca6f..4958b653678ae 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -6806,6 +6806,7 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 1604bc8cff373..24714688b50af 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -8599,6 +8599,7 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 18fb52c14acd7..e9192b806f9f0 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -6796,7 +6796,8 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
};
tpdm-cdsp-llm {
--
2.47.3
^ permalink raw reply related
* [PATCH v3 16/17] arm64: dts: sprd: Add EL2 virtual timer interrupt
From: Marc Zyngier @ 2026-05-23 14:02 UTC (permalink / raw)
To: linux-arm-kernel, linux-acpi, linux-kernel, devicetree
Cc: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J. Wysocki, Mark Rutland, Daniel Lezcano,
Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Ge Gordon,
BST Linux Kernel Upstream Group, Jesper Nilsson, Lars Persson,
Alim Akhtar, Ivaylo Ivanov, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Matthias Brugger, AngeloGioacchino Del Regno, Thierry Reding,
Jonathan Hunter, Bjorn Andersson, Konrad Dybcio,
Andreas Färber, Yu-Chun Lin [林祐君],
Heiko Stuebner, Shawn Lin, Orson Zhai, Baolin Wang, Michal Simek
In-Reply-To: <20260523140242.586031-1-maz@kernel.org>
The ARMv8.2 based CPUs used in a number of Unisoc SoCs are missing
the EL2 virtual timer interrupt. Add it.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/boot/dts/sprd/sc9863a.dtsi | 3 ++-
arch/arm64/boot/dts/sprd/ums512.dtsi | 3 ++-
arch/arm64/boot/dts/sprd/ums9620.dtsi | 3 ++-
3 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/sprd/sc9863a.dtsi b/arch/arm64/boot/dts/sprd/sc9863a.dtsi
index 31799579d7f2e..18e61c25aa36f 100644
--- a/arch/arm64/boot/dts/sprd/sc9863a.dtsi
+++ b/arch/arm64/boot/dts/sprd/sc9863a.dtsi
@@ -130,7 +130,8 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */
- <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>, /* Hypervisor physical PPI */
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>; /* Hypervisor virtual PPI */
};
pmu {
diff --git a/arch/arm64/boot/dts/sprd/ums512.dtsi b/arch/arm64/boot/dts/sprd/ums512.dtsi
index efa14309cc4ef..4105647aabd17 100644
--- a/arch/arm64/boot/dts/sprd/ums512.dtsi
+++ b/arch/arm64/boot/dts/sprd/ums512.dtsi
@@ -133,7 +133,8 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */
- <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>, /* Hypervisor physical PPI */
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>; /* Hypervisor virtual PPI */
};
pmu-a55 {
diff --git a/arch/arm64/boot/dts/sprd/ums9620.dtsi b/arch/arm64/boot/dts/sprd/ums9620.dtsi
index 2458071320c9b..037e3401d4991 100644
--- a/arch/arm64/boot/dts/sprd/ums9620.dtsi
+++ b/arch/arm64/boot/dts/sprd/ums9620.dtsi
@@ -141,7 +141,8 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */
- <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>, /* Hypervisor physical PPI */
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>; /* Hypervisor virtual PPI */
};
pmu-a55 {
--
2.47.3
^ permalink raw reply related
* [PATCH v3 15/17] arm64: dts: rockchip: Add EL2 virtual timer interrupt
From: Marc Zyngier @ 2026-05-23 14:02 UTC (permalink / raw)
To: linux-arm-kernel, linux-acpi, linux-kernel, devicetree
Cc: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J. Wysocki, Mark Rutland, Daniel Lezcano,
Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Ge Gordon,
BST Linux Kernel Upstream Group, Jesper Nilsson, Lars Persson,
Alim Akhtar, Ivaylo Ivanov, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Matthias Brugger, AngeloGioacchino Del Regno, Thierry Reding,
Jonathan Hunter, Bjorn Andersson, Konrad Dybcio,
Andreas Färber, Yu-Chun Lin [林祐君],
Heiko Stuebner, Shawn Lin, Orson Zhai, Baolin Wang, Michal Simek
In-Reply-To: <20260523140242.586031-1-maz@kernel.org>
The ARMv8.2 based CPUs used in a number of Rockchip SoCs are missing
the EL2 virtual timer interrupt. Add it.
Acked-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
index 64bdd8b7754b5..a5832895bd392 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
@@ -195,7 +195,8 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
arm,no-tick-in-suspend;
};
--
2.47.3
^ permalink raw reply related
* [PATCH v3 17/17] arm64: dts: xilinx: Add EL2 virtual timer interrupt
From: Marc Zyngier @ 2026-05-23 14:02 UTC (permalink / raw)
To: linux-arm-kernel, linux-acpi, linux-kernel, devicetree
Cc: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J. Wysocki, Mark Rutland, Daniel Lezcano,
Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Ge Gordon,
BST Linux Kernel Upstream Group, Jesper Nilsson, Lars Persson,
Alim Akhtar, Ivaylo Ivanov, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Matthias Brugger, AngeloGioacchino Del Regno, Thierry Reding,
Jonathan Hunter, Bjorn Andersson, Konrad Dybcio,
Andreas Färber, Yu-Chun Lin [林祐君],
Heiko Stuebner, Shawn Lin, Orson Zhai, Baolin Wang, Michal Simek
In-Reply-To: <20260523140242.586031-1-maz@kernel.org>
The ARMv8.2 based CPUs used in the versal SoC are missing the EL2 virtual
timer interrupt. Add it.
Acked-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/boot/dts/xilinx/versal-net.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/xilinx/versal-net.dtsi b/arch/arm64/boot/dts/xilinx/versal-net.dtsi
index 15f767608e67f..0aac93675ad77 100644
--- a/arch/arm64/boot/dts/xilinx/versal-net.dtsi
+++ b/arch/arm64/boot/dts/xilinx/versal-net.dtsi
@@ -728,7 +728,8 @@ fpga: fpga-region {
timer: timer {
compatible = "arm,armv8-timer";
- interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>;
+ interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>,
+ <1 12 4>;
};
versal_fpga: versal-fpga {
--
2.47.3
^ permalink raw reply related
* Re: [PATCH v2 1/2] dt-bindings: ufs: Document static TX Equalization settings properties
From: Manivannan Sadhasivam @ 2026-05-23 14:14 UTC (permalink / raw)
To: Can Guo
Cc: bvanassche, beanhuo, peter.wang, martin.petersen, linux-scsi,
Alim Akhtar, Avri Altman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Ram Kumar Dwivedi, Zhaoming Luo,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <20260523134711.323425-2-can.guo@oss.qualcomm.com>
On Sat, May 23, 2026 at 06:47:10AM -0700, Can Guo wrote:
> UFS v5.0/UFSHCI v5.0 add HS-G6 support (46.6 Gbps/lane) via UniPro v3.0
> and M-PHY v6.0. In these specs, TX Equalization is defined for all High
> Speed Gears (not only HS-G6) to compensate channel loss and improve signal
> integrity at high speed operation.
>
> For HS-G6, M-PHY uses PAM4 1b1b line coding, Pre-Coding may also be
> required depending on channel characteristics.
>
> Add vendor-neutral DT patternProperties:
> txeq-settings-g[1-6]
>
> Each property is a uint32 array of per-lane tuples:
> (PreShoot, DeEmphasis, PrecodeEn)
>
I don't think combining all EQ settings (PreShoot, DeEmphasis, PrecodeEn) in a
single property as opaque tuples is the right approach. These are three
semantically distinct parameters with independent value ranges. So packing
them into a uint32 array makes validation impossible in the schema.
AFACIS, PrecodeEn is applicable only to HS-G6 (PAM4), but the proposed
patternProperties forces it into G1-G5 tuples as well, which is semantically
wrong.
PCIe binding defines one property per data rate for EQ presets:
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/pci/pci-bus-common.yaml#L193
Similarly, UFS should define one property per gear per (like, txeq-preshoot-g6,
txeq-deemphasis-g6, txeq-precode-enable-g6,...) rather than clubbing everything
into opaque tuples.
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply
* Re: [PATCH v4 2/4] hwmon: (pmbus/tps25990): Rework TPS25990 direct conversion handling
From: Guenter Roeck @ 2026-05-23 14:17 UTC (permalink / raw)
To: Stoyan Bogdanov, jbrunet, robh, krzk+dt, conor+dt, corbet, skhan
Cc: linux-hwmon, devicetree, linux-doc, linux-kernel
In-Reply-To: <20260522082349.2749970-3-sbogdanov@baylibre.com>
On 5/22/26 01:23, Stoyan Bogdanov wrote:
> Rework the existing implementation of direct format conversion for
> TPS25990 non-standard parameters to improve code reusability and
> integration with the PMBus direct conversion helpers.
>
> Changes include:
> - Add an enum describing the supported parameters
> - Add structure to hold m, b, R per-device coefficients
> - Add data structures for pmbus_driver_info and local direct values
> - Use the generic PMBus conversion helpers:
> pmbus_reg2data_direct_calc()
> pmbus_data2reg_direct_calc()
> - Replace previously used defines with structured data
>
> This reduces duplicated conversion logic and makes handling of
> non-standard parameters more maintainable.
>
> Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
> ---
> drivers/hwmon/pmbus/tps25990.c | 197 +++++++++++++++++++++------------
> 1 file changed, 127 insertions(+), 70 deletions(-)
>
> diff --git a/drivers/hwmon/pmbus/tps25990.c b/drivers/hwmon/pmbus/tps25990.c
> index 05c6288ecafc..1e252844217b 100644
> --- a/drivers/hwmon/pmbus/tps25990.c
> +++ b/drivers/hwmon/pmbus/tps25990.c
> @@ -36,17 +36,63 @@
> #define TPS25990_UNLOCKED BIT(7)
>
> #define TPS25990_8B_SHIFT 2
> -#define TPS25990_VIN_OVF_NUM 525100
> -#define TPS25990_VIN_OVF_DIV 10163
> -#define TPS25990_VIN_OVF_OFF 155
> -#define TPS25990_IIN_OCF_NUM 953800
> -#define TPS25990_IIN_OCF_DIV 129278
> -#define TPS25990_IIN_OCF_OFF 157
>
> #define PK_MIN_AVG_RST_MASK (PK_MIN_AVG_RST_PEAK | \
> PK_MIN_AVG_RST_AVG | \
> PK_MIN_AVG_RST_MIN)
>
> +enum chips {
> + tps25990,
> +};
> +
> +enum tps25990_parameters {
> + TPS25990_VIN_OVF = 0, /* VIN over volatage fault */
> + TPS25990_IIN_OCF, /* IIN Over currect fault */
> + TPS25990_DIRECT_VALUES_COUNT,
> +};
> +
> +struct tps25990_local_direct_value {
> + int m[TPS25990_DIRECT_VALUES_COUNT]; /* mantissa */
> + int b[TPS25990_DIRECT_VALUES_COUNT]; /* offset */
> + int R[TPS25990_DIRECT_VALUES_COUNT]; /* exponent */
> +};
> +
> +struct tps25990_data {
> + struct pmbus_driver_info info;
> + struct tps25990_local_direct_value info_local;
> +};
> +
> +static s64 tps25990_reg2data_direct(struct i2c_client *client, int param, s32 raw)
> +{
> + struct pmbus_driver_info *info = i2c_get_clientdata(client);
> + struct tps25990_data *data = container_of(info, struct tps25990_data, info);
> + struct tps25990_local_direct_value *info_local = &data->info_local;
> + s64 b, val;
> + s32 m, R;
> +
> + val = (s16)raw;
> + m = info_local->m[param];
> + b = info_local->b[param];
> + R = info_local->R[param];
> +
> + return pmbus_reg2data_direct_calc(val, b, m, R);
> +}
> +
> +static u16 tps25990_data2reg_direct(struct i2c_client *client, int param, s64 val)
> +{
> + struct pmbus_driver_info *info = i2c_get_clientdata(client);
> + struct tps25990_data *data = container_of(info, struct tps25990_data, info);
> + struct tps25990_local_direct_value *info_local = &data->info_local;
> + s32 m, R;
> + s64 b;
> +
> + m = info_local->m[param];
> + b = info_local->b[param];
> + R = info_local->R[param];
> +
> + return pmbus_data2reg_direct_calc(val, b, m, R);
> +}
> +
> /*
> * Arbitrary default Rimon value: 1kOhm
> * This correspond to an overcurrent limit of 55A, close to the specified limit
> @@ -184,9 +230,7 @@ static int tps25990_read_word_data(struct i2c_client *client,
> ret = pmbus_read_word_data(client, page, phase, reg);
> if (ret < 0)
> break;
> - ret = DIV_ROUND_CLOSEST(ret * TPS25990_VIN_OVF_NUM,
> - TPS25990_VIN_OVF_DIV);
> - ret += TPS25990_VIN_OVF_OFF;
> + ret = tps25990_reg2data_direct(client, TPS25990_VIN_OVF, ret);
The result is again evaluated by the PMBus core as direct register value,
not as calculated fault limit. I don't think this works as expected.
This isn't about converting a register value to a voltage, it is about
converting one direct format into another. Using (or trying to use)
reg2data_direct is at the very least misleading, if not completely wrong.
The m/b/R parameters below are the coefficients from the datasheet to convert
the register values into voltages. The PMBus core will take that value and
convert it again into a voltage, this time using the m/b/R coefficients
for input voltages. This can not be correct. To be technically correct,
the core would have to convert the register value to a voltage using one
set of m/b/R coefficients and then convert it back to direct format using
the other set of m/b/R coefficients. The current code does that by adjusting
the values directly. I don't think changing is really beneficial. If anything,
documenting it would be more helpful.
Thanks,
Guenter
^ permalink raw reply
* Re: [PATCH v3 14/17] arm64: dts: realtek: Add EL2 virtual timer interrupt
From: sashiko-bot @ 2026-05-23 14:20 UTC (permalink / raw)
To: Marc Zyngier; +Cc: devicetree, robh, conor+dt
In-Reply-To: <20260523140242.586031-15-maz@kernel.org>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The EL2 virtual timer interrupt (PPI 12) in `kent.dtsi` is incorrectly configured with an active-high trigger type (`IRQ_TYPE_LEVEL_HIGH`).
--
commit f079ad98f64e8cdedfbfede9fd625a2762e0efa9
Author: Marc Zyngier <maz@kernel.org>
arm64: dts: realtek: Add EL2 virtual timer interrupt
This commit adds the missing EL2 virtual timer interrupt for ARMv8.2 based
Realtek SoCs. It also addresses a conflict on the kent platform by changing
the EL2 virtual timer assignment from PPI9 to PPI12.
> diff --git a/arch/arm64/boot/dts/realtek/kent.dtsi b/arch/arm64/boot/dts/realtek/kent.dtsi
> index ae006ce244205..4147e4269247a 100644
> --- a/arch/arm64/boot/dts/realtek/kent.dtsi
> +++ b/arch/arm64/boot/dts/realtek/kent.dtsi
> @@ -23,7 +23,7 @@ timer {
> <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
> - <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
[Severity: High]
Should this interrupt be configured as active-low?
ARM architected timer interrupts are universally active-low, as seen in the
other interrupts for this timer and the newly added PPI 12 in rtd16xx.dtsi.
It appears the update changed the interrupt number but kept the
IRQ_TYPE_LEVEL_HIGH polarity that was used for the GIC maintenance interrupt.
Could configuring the GIC with the incorrect trigger type lead to missed EL2
virtual timer interrupts or an interrupt storm?
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260523140242.586031-1-maz@kernel.org?part=14
^ permalink raw reply
* Re: [PATCH v3 04/17] dt-bindings: timer: arm,arch_timer: Fix requirements for interrupt description
From: sashiko-bot @ 2026-05-23 14:24 UTC (permalink / raw)
To: Marc Zyngier; +Cc: devicetree, robh, conor+dt
In-Reply-To: <20260523140242.586031-5-maz@kernel.org>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The new `minItems: 2` constraint in the `interrupts` array maps to the wrong interrupts due to the static `items` list, contradicting the commit message's stated requirements.
--
commit 5eb08d516ae8d3fb049e6d6f31c8f0dd7d3f7165
Author: Marc Zyngier <maz@kernel.org>
dt-bindings: timer: arm,arch_timer: Fix requirements for interrupt description
This commit updates the arm,arch_timer binding to explicitly define the
requirements for interrupts based on the architecture. It increases the
minimum number of interrupts from 1 to 2, clarifies architectural
terminology for the interrupts, and removes outdated descriptions.
> diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
> index c5fc3b6c8bd0b..c65e48a155ab6 100644
> --- a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
> +++ b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
[ ... ]
> @@ -33,13 +28,13 @@ properties:
> - const: arm,armv7-timer
>
> interrupts:
> - minItems: 1
> + minItems: 2
> items:
> - - description: secure timer irq
> - - description: non-secure timer irq
> - - description: virtual timer irq
> - - description: hypervisor timer irq
> - - description: hypervisor virtual timer irq
> + - description: EL1 secure physical timer irq, if EL3 is implemented
> + - description: EL1 non-secure physical timer irq
> + - description: EL1 virtual timer irq
> + - description: EL2 physical timer irq, if EL2 is implemented
> + - description: EL2 virtual timer irq, if FEAT_VHE is implemented
[Severity: Medium]
Does changing this to minItems: 2 while keeping a static items list cause
the first two provided interrupts to always be validated against the
"EL1 secure physical" and "EL1 non-secure physical" descriptions?
JSON schema array validation maps elements sequentially by index. If a
device tree node only provides 2 interrupts (the always-required EL1
non-secure physical and EL1 virtual timers), they will be mapped to the
first two indices.
Since the EL1 secure physical timer is optional (only if EL3 is
implemented), should interrupts use a oneOf block with separate lists,
mirroring the existing structure of interrupt-names, to correctly model
when the first element is omitted?
>
> interrupt-names:
> oneOf:
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260523140242.586031-1-maz@kernel.org?part=4
^ permalink raw reply
* Re: [PATCH v3 01/17] ACPI: GTDT: Account for GTDTv3 size when walking the platform timer descriptors
From: sashiko-bot @ 2026-05-23 14:40 UTC (permalink / raw)
To: Marc Zyngier; +Cc: robh, conor+dt, devicetree
In-Reply-To: <20260523140242.586031-2-maz@kernel.org>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
Pre-existing issues:
- [High] Missing minimum length validation for platform timer subtables can lead to out-of-bounds memory accesses when parsing malformed ACPI tables.
- [High] The patch adds size validation for GTDT revisions 2 and 3, but misses length validation for GTDT revision 1 tables.
--
commit 6795242683ef78c0e32a77285ea86c559ab6c178
Author: Marc Zyngier <maz@kernel.org>
ACPI: GTDT: Account for GTDTv3 size when walking the platform timer descriptors
This commit updates the GTDT table parsing to support the expanded size of
GTDT revision 3, which includes an EL2-private virtual timer. It adjusts
the platform timer start offset based on the revision and adds a length
validation check for the base table.
> diff --git a/drivers/acpi/arm64/gtdt.c b/drivers/acpi/arm64/gtdt.c
> --- a/drivers/acpi/arm64/gtdt.c
> +++ b/drivers/acpi/arm64/gtdt.c
> @@ -34,14 +34,25 @@ struct acpi_gtdt_descriptor {
[ ... ]
> static __init bool platform_timer_valid(void *platform_timer)
> {
> struct acpi_gtdt_header *gh = platform_timer;
> + void *platform_timer_begin;
>
> - return (platform_timer >= (void *)(acpi_gtdt_desc.gtdt + 1) &&
> - platform_timer < acpi_gtdt_desc.gtdt_end &&
> + if (acpi_gtdt_desc.gtdt->header.revision >= 3)
> + platform_timer_begin = container_of(acpi_gtdt_desc.gtdt, struct gtdt_v3, gtdt_v2) + 1;
> + else
> + platform_timer_begin = acpi_gtdt_desc.gtdt + 1;
> +
> + return (platform_timer >= platform_timer_begin &&
> + platform_timer + sizeof(*gh) <= acpi_gtdt_desc.gtdt_end &&
> gh->length != 0 &&
> platform_timer + gh->length <= acpi_gtdt_desc.gtdt_end);
> }
[Severity: High]
This is a pre-existing issue, but does this validation fully protect against
malformed ACPI tables?
While it checks that the subtable's declared length fits within the main
GTDT table, it does not verify that the length is large enough to contain
the specific subtable structure being parsed.
If a malformed GTDT table provides a subtable with a truncated length,
parser functions like is_non_secure_watchdog() might read fields past the
end of the provided table data. Could this lead to out-of-bounds memory
accesses when reading fields like wd->timer_flags?
[ ... ]
> @@ -166,6 +177,13 @@ int __init acpi_gtdt_init(struct acpi_table_header *table,
> u32 cnt = 0;
>
> gtdt = container_of(table, struct acpi_table_gtdt, header);
> +
> + if ((gtdt->header.revision >= 3 && gtdt->header.length < sizeof(struct gtdt_v3)) ||
> + (gtdt->header.revision == 2 && gtdt->header.length < sizeof(*gtdt))) {
> + pr_err(FW_BUG "GTDT with invalid size %d\n", gtdt->header.length);
> + return -EINVAL;
> + }
> +
[Severity: High]
This isn't a bug introduced by this patch, but since we are adding length
validation for revisions 2 and 3, should we also validate the length for
revision 1 tables?
If a system provides a malformed revision 1 GTDT table that is smaller than
its baseline required size, the initialization could succeed. Later accesses
to fields in acpi_gtdt_map_ppi() might read out-of-bounds memory.
Would it be safer to ensure all supported revisions meet their minimum
required sizes?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260523140242.586031-1-maz@kernel.org?part=1
^ permalink raw reply
* Re: [PATCH 2/2] iommu/arm-smmu: Add interconnect bandwidth voting support
From: Bibek Kumar Patro @ 2026-05-23 14:41 UTC (permalink / raw)
To: sashiko-reviews; +Cc: conor+dt, robh, krzk+dt, devicetree
In-Reply-To: <20260516130251.DED6AC2BCB3@smtp.kernel.org>
On 5/16/2026 6:32 PM, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
> - [High] Dead code `-ENODATA` check in `arm_smmu_icc_get()` causes probe failure on platforms without interconnects.
> - [High] Shared IRQ handlers access SMMU hardware registers while the device might be runtime suspended.
> - [Medium] Interconnect bandwidth vote is not released during system shutdown if Runtime PM is disabled.
> --
>
> commit efe802bf0c93309aa584a5eb41c34c9788a6e837
> Author: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
>
> iommu/arm-smmu: Add interconnect bandwidth voting support
>
> This commit adds support for an optional interconnect path to the arm-smmu
> driver. It votes for bandwidth while the SMMU is active to prevent register
> access failures during transitions. The bandwidth vote is enabled during
> probe and runtime resume, and released during runtime suspend and errors.
>
>> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c
>> index 0bd21d206eb3e..aedf5edf8f9b2 100644
>> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
>> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
> [ ... ]
>> @@ -86,6 +91,36 @@ static inline void arm_smmu_rpm_put(struct arm_smmu_device *smmu)
>> }
>> }
>>
>> +static int arm_smmu_icc_get(struct arm_smmu_device *smmu)
>> +{
>> + smmu->icc_path = devm_of_icc_get(smmu->dev, NULL);
>> + if (IS_ERR(smmu->icc_path)) {
>> + int err = PTR_ERR(smmu->icc_path);
>> +
>> + if (err == -ENODATA) {
>
> Is this -ENODATA check correct for handling missing interconnects?
>
> Looking at devm_of_icc_get(), it relies on of_icc_get(), which returns
> -ENOENT when the interconnects DT property is missing, or -ENODEV on ACPI
> platforms where dev->of_node is NULL. It appears it never returns -ENODATA.
>
> Will this cause the driver to unconditionally call dev_err_probe() and fail
> to probe on all ACPI platforms and DT platforms that do not define
> interconnect properties?
>
ACK, good catch.
I will fix this in the next revision. Instead of checking for -ENODATA,
the code should handle -ENODEV to correctly cover the case where the
interconnect path is not available, and emit a non-fatal warning
accordingly.
>> + smmu->icc_path = NULL;
>> + return 0;
>> + }
>> + return dev_err_probe(smmu->dev, err,
>> + "failed to get interconnect path\n");
>> + }
>> + return 0;
>> +}
>> +
>> +static void arm_smmu_icc_enable(struct arm_smmu_device *smmu)
>> +{
>> + if (smmu->icc_path)
>> + WARN_ON(icc_set_bw(smmu->icc_path, ARM_SMMU_ICC_AVG_BW,
>> + ARM_SMMU_ICC_PEAK_BW_HIGH));
>> +}
>> +
>> +static void arm_smmu_icc_disable(struct arm_smmu_device *smmu)
>> +{
>> + if (smmu->icc_path)
>> + WARN_ON(icc_set_bw(smmu->icc_path, ARM_SMMU_ICC_AVG_BW,
>> + ARM_SMMU_ICC_PEAK_BW_LOW));
>> +}
>
> Should arm_smmu_icc_disable() also be called during system shutdown?
>
> In arm_smmu_device_shutdown(), if pm_runtime_enabled(smmu->dev) is false,
> the driver manually disables the SMMU clocks via clk_bulk_disable().
> However, a corresponding call to drop the interconnect vote doesn't appear
> to be added to that branch.
>
> Could this leave the bandwidth vote permanently held at
> ARM_SMMU_ICC_PEAK_BW_HIGH during system halt or kexec?
>
ACK, adding this in the shutdown path would be safer.
It should also be includes alongside clk_bulk_disable() in the "non-RPM"
else {} path of arm_smmu_device_shutdown().
> [ ... ]
>> @@ -2308,6 +2358,7 @@ static int __maybe_unused arm_smmu_runtime_suspend(struct device *dev)
>> struct arm_smmu_device *smmu = dev_get_drvdata(dev);
>>
>> clk_bulk_disable(smmu->num_clks, smmu->clks);
>> + arm_smmu_icc_disable(smmu);
>>
>> return 0;
>> }
>
> With the clocks disabled and the interconnect vote dropped here, is there a
> risk of a bus hang if a shared IRQ fires while the device is suspended?
>
> The driver registers its global_fault and context_fault handlers as
> IRQF_SHARED. If another device on the same IRQ line triggers an interrupt
> while the SMMU is in RPM_SUSPENDED, the handler might attempt to read
> hardware registers (such as calling arm_smmu_gr0_read()) while the SMMU is
> powered down without an active clock or interconnect vote.
>
> Should the interrupt handlers use pm_runtime_get_if_active() before
> accessing registers, and should this suspend callback use synchronize_irq()?
>
Seems like this issue predates the interconnect voting patch and is not
introduced by this series.
The clk_bulk_disable() call in arm_smmu_runtime_suspend() was already
present prior to this change. Introducing arm_smmu_icc_disable() does
not alter the risk of the race condition mentioned above.
So as per my understanding this comment can be ignored for the series,
Will raise a separate patch with the proposed fix on this suspected race
condition.
Thanks & regards,
Bibek
^ permalink raw reply
* Re: [PATCH v8 1/3] PCI: mediatek: Use actual physical address instead of virt_to_phys()
From: Manivannan Sadhasivam @ 2026-05-23 14:43 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Caleb James DeLisle, linux-pci, linux-mips, naseefkm, ryder.lee,
lpieralisi, kwilczynski, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ansuelsmth, linux-mediatek, devicetree,
linux-kernel, Manivannan Sadhasivam
In-Reply-To: <20260522224325.GA195169@bhelgaas>
On Fri, May 22, 2026 at 05:43:25PM -0500, Bjorn Helgaas wrote:
> On Thu, May 21, 2026 at 10:44:51AM +0530, Manivannan Sadhasivam wrote:
> > On Wed, May 20, 2026 at 02:59:00PM -0500, Bjorn Helgaas wrote:
> > > On Wed, May 20, 2026 at 09:17:35PM +0200, Caleb James DeLisle wrote:
> > > >
> > > > On 20/05/2026 20:55, Bjorn Helgaas wrote:
> > > > > On Wed, May 20, 2026 at 06:38:25PM +0000, Caleb James DeLisle wrote:
> > > > > > From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> > > > > >
> > > > > > The driver previously used virt_to_phys() on the ioremapped register base
> > > > > > (port->base) to compute the MSI message address. Using virt_to_phys() on an
> > > > > > IO mapped address is incorrect because it expects a kernel virtual address.
> > > > > >
> > > > > > To fix it, store the physical start of the I/O register region in
> > > > > > mtk_pcie_port->phys_base and use it to build the MSI address. This replaces
> > > > > > the incorrect virt_to_phys() usage and ensures MSI addresses are generated
> > > > > > correctly.
> > > > > >
> > > > > > Fixes: 43e6409db64d ("PCI: mediatek: Add MSI support for MT2712 and MT7622")
> > > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> > > > > > Tested-by: Caleb James DeLisle <cjd@cjdns.fr>
> > > > > > ---
> > > > > > drivers/pci/controller/pcie-mediatek.c | 16 +++++++++++++---
> > > > > > 1 file changed, 13 insertions(+), 3 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
> > > > > > index 75722524fe74..c503fbd774d0 100644
> > > > > > --- a/drivers/pci/controller/pcie-mediatek.c
> > > > > > +++ b/drivers/pci/controller/pcie-mediatek.c
> > > > > > @@ -175,6 +175,7 @@ struct mtk_pcie_soc {
> > > > > > /**
> > > > > > * struct mtk_pcie_port - PCIe port information
> > > > > > * @base: IO mapped register base
> > > > > > + * @phys_base: Physical address of the I/O register base region
> > > > > > * @list: port list
> > > > > > * @pcie: pointer to PCIe host info
> > > > > > * @reset: pointer to port reset control
> > > > > > @@ -196,6 +197,7 @@ struct mtk_pcie_soc {
> > > > > > */
> > > > > > struct mtk_pcie_port {
> > > > > > void __iomem *base;
> > > > > > + phys_addr_t phys_base;
> > > > > > struct list_head list;
> > > > > > struct mtk_pcie *pcie;
> > > > > > struct reset_control *reset;
> > > > > > @@ -405,7 +407,7 @@ static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
> > > > > > phys_addr_t addr;
> > > > > > /* MT2712/MT7622 only support 32-bit MSI addresses */
> > > > > > - addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
> > > > > > + addr = port->phys_base + PCIE_MSI_VECTOR;
> > > > >
> > > > > This doesn't look right because the MSI address is a PCI bus address,
> > > > > and port->phys_base is a CPU physical address. Often a PCI bus
> > > > > address is the same as the CPU physical address, but not always.
> > > > > I think the DT 'ranges' property tells you the translation.
> > >
> > > Oops, sorry, I muddied the waters here.
> > >
> > > 'ranges' tells you the translation applied by a bridge, e.g., when
> > > a CPU does a load/store, the PCI host bridge turns it into a PCI
> > > read/write transaction. The bridge might add an offset to the CPU
> > > load/store physical address to get the PCI read/write bus address.
> > >
> > > But that's not the issue here. The MSI is basically a DMA write
> > > performed by the PCI device, not a store done by a CPU, so I don't
> > > think 'ranges' is the right thing to look at.
> >
> > Yeah, it is so easy to confuse both. To summarise, 'ranges'
> > describes the outbound translation and 'dma-ranges' describes the
> > inbound translation from host perspective.
> >
> > > Based on this:
> > > https://elinux.org/Device_Tree_Usage#PCI_DMA_Address_Translation I
> > > think 'dma-ranges' is the relevant property. I don't think your
> > > DT includes a 'dma-ranges' property, and in that case the default
> > > is that the system bus (CPU) address is the same as the PCI
> > > address.
> > >
> > > So I think this patch works because it assumes DMA addresses like
> > > the MSI address are mapped to identical system bus addresses.
> > >
> > > It still seems to me that drivers should be prepared for the
> > > presence of dma-ranges and use it when computing the MSI target
> > > address. But I don't think any drivers really do that, so for now
> > > I think you should pretend that I never responded about this
> > > patch.
> >
> > Your observations are correct. This driver assumes that the
> > identical mapping exists between CPU and PCI bus addresses. Usually,
> > the drivers make use of phys_to_dma() to handle the translations.
>
> What does this look like in the native host bridge drivers? I don't
> see any direct calls of phys_to_dma(), but there are some higher-level
> interfaces that use it.
>
> I don't really see a consistent style of constructing MSI addresses,
> e.g., in *_compose_msi_msg() implementations.
>
That's because, each driver may use different methods for constructing the MSI
address. Two commonly used methods are:
1. Using a pre-defined MSI address in the MMIO range (like the pcie-mediatek
driver). The PCIe controller hardware decodes MWr TLPs targeting this address
and raises an interrupt to the CPU via the platform interrupt controller (e.g.
GIC).
2. Allocating coherent memory using dma_alloc_coherent() and programming it
into platform MMIO registers (like pcie-designware-host driver). The Root
Complex inbound ATU matches writes to this address and raises an interrupt to
the CPU.
> > This API internally makes use of the 'dma_range_map' which gets
> > populated by the OF core based on the 'dma-ranges' property (if
> > present in DT).
> >
> > But it makes sense to use it irrespective of whether the platform
> > supports non-identical DMA/inbound translation or not. Since this
> > API behaves like a no-op and returns the CPU physical address if
> > there is an identical mapping, there is literally zero overhead in
> > using it.
>
> Thanks for rescuing me.
>
> I wonder if there should be something in
> Documentation/core-api/dma-api* about this. I guess that is mostly
> oriented toward things like PCI device drivers, not so much PCI host
> bridge drivers. But it would be nice to have a little intro to
> dma-ranges and maybe even the restricted DMA usage.
>
I think this information should belong to the PCI host controller documentation.
I started writing it, but didn't get time to finish and post it. Maybe I'll
atleast post an initial version and add more info on top.
- Mani
--
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