* [PATCH 0/5] Minor dt warnings fixes
From: Konrad Dybcio @ 2026-06-10 11:43 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, André Apitzsch, Luca Weiss, Gabriela David
Cc: linux-arm-msm, devicetree, linux-kernel, Konrad Dybcio
Nothing particularly of note, mechanical fixes
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
Konrad Dybcio (5):
arm64: dts: qcom: msm8998-sony-yoshino: Drop extra bias-disable
arm64: dts: qcom: msm8976-longcheer-l9360: Fix accidental node override
arm64: dts: qcom: sdm632-motorola-ocean: Fix LED default trigger property
arm64: dts: qcom: qcs8300-ride: Fix BT RFA supply name
arm64: dts: qcom: talos-evk-som: Fix BT RFA supply name
arch/arm64/boot/dts/qcom/msm8976-longcheer-l9360.dts | 4 ++--
arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 4 ----
arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 2 +-
arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts | 2 +-
arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 2 +-
5 files changed, 5 insertions(+), 9 deletions(-)
---
base-commit: 49e02880ec0a8c378e811bc9d85da188d7c6204c
change-id: 20260610-topic-june26_dts_fixes-c32e3cf85fdf
Best regards,
--
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH 2/3] tty: serial: Add UART driver for Cortina-Access platform
From: sashiko-bot @ 2026-06-10 11:40 UTC (permalink / raw)
To: Jason Li; +Cc: robh, devicetree, conor+dt
In-Reply-To: <20260610112821.3030099-4-jason.li@cortina-access.com>
Thank you for your contribution! Sashiko AI review found 10 potential issue(s) to consider:
- [High] Global array allocation, port slot selection, and cleanup lack synchronization, leading to race conditions, memory leaks, and UAF.
- [High] Kernel panic in `cortina_console_setup()` due to NULL pointer dereference when called for an unprobed UART index.
- [High] `cortina_poll_put_char()` uses `jiffies` for timeout calculations, resulting in an infinite loop and system hang.
- [High] Read-modify-write operations on the CFG register are performed without holding the port lock, leading to TOCTOU state corruption.
- [High] The console write function disables hardware interrupts and then takes a sleeping spinlock, triggering a lockdep splat on PREEMPT_RT.
- [Medium] The RX interrupt handler incorrectly applies a single, one-time error status to all characters drained from the FIFO.
- [Medium] Failed probes permanently leak port slots from the global `cortina_uart_ports` array.
- [Medium] The wakeup source initialized during probe is never disabled, causing a memory leak when the driver is unbound or fails to probe.
- [Medium] The `cortina_uart_shutdown` callback performs read-modify-write operations on the Interrupt Enable (IE) register without holding the port lock.
- [Low] The console write function transmits an incorrect LF-CR (`\n\r`) sequence instead of the standard CR-LF (`\r\n`).
--
commit fd0d487faa14545601b1e17f9d5e8a68bcd53bfd
Author: Jason Li <jason.lee651024@gmail.com>
Subject: tty: serial: Add UART driver for Cortina-Access platform
This commit introduces a new UART driver for the Cortina-Access SoC platform,
adding support for the CAXXXX family along with earlycon and console
functionality.
> diff --git a/drivers/tty/serial/serial_cortina-access.c b/drivers/tty/serial/serial_cortina-access.c
> new file mode 100644
> index 0000000000000..f25eae987ccdc
> --- /dev/null
> +++ b/drivers/tty/serial/serial_cortina-access.c
[ ... ]
> +static void cortina_uart_shutdown(struct uart_port *port)
> +{
> + cortina_uart_stop_tx(port);
> + cortina_uart_stop_rx(port);
[Severity: Medium]
Could this corrupt the IE register state? The serial core calls the shutdown
callback without holding the port lock, but the stop_tx and stop_rx functions
perform read-modify-write operations on the IE register.
> + free_irq(port->irq, port);
> +}
[ ... ]
> +static void cortina_uart_set_termios(struct uart_port *port,
> + struct ktermios *termios,
> + const struct ktermios *old)
> +{
> + unsigned long flags;
> + int baud;
> + unsigned int reg_v, sample_freq = 0;
> +
> + baud = uart_get_baud_rate(port, termios, old, 0, 230400);
> + reg_v = readl(port->membase + CFG);
[Severity: High]
Is the CFG register read vulnerable to TOCTOU corruption here? The CFG
register is read into a local variable outside the port lock, but it is
written inside the lock later. If another context acquires the lock and
modifies CFG concurrently, it seems this could overwrite and lose those
changes.
> + /* mask off the baud settings */
> + reg_v &= 0xff;
[ ... ]
> +static void cortina_access_power(struct uart_port *port, unsigned int state,
> + unsigned int oldstate)
> +{
> + unsigned int reg_v;
> +
> + reg_v = readl(port->membase + CFG);
[Severity: High]
Does this need to hold the port lock? The CFG register is read and written
here with no locking, which might race with other register accesses.
> + switch (state) {
> + case UART_PM_STATE_ON:
> + reg_v |= CFG_UART_EN;
> + break;
[ ... ]
> +#ifdef CONFIG_CONSOLE_POLL
> +static int cortina_poll_get_char(struct uart_port *port)
> +{
> + if (readl(port->membase + INFO) & INFO_RX_EMPTY)
> + return NO_POLL_CHAR;
> +
> + return readl(port->membase + RX_DAT);
> +}
> +
> +static void cortina_poll_put_char(struct uart_port *port, unsigned char c)
> +{
> + unsigned long time_out;
> +
> + time_out = jiffies + usecs_to_jiffies(TX_TIMEOUT);
> +
> + while (time_before(jiffies, time_out) &&
> + (readl(port->membase + INFO) & INFO_TX_FULL))
> + cpu_relax();
[Severity: High]
Will this loop hang the system? Since this polling function is called from the
kgdb framework with local hardware interrupts disabled, jiffies will not
increment. Should atomic polling loops use udelay and an iteration counter
instead?
> +
> + /* Give up if FIFO stuck! */
> + if (readl(port->membase + INFO) & INFO_TX_FULL)
> + return;
[ ... ]
> +static inline void cortina_uart_interrupt_rx_chars(struct uart_port *port,
> + unsigned long status)
> +{
[ ... ]
> + /* Read characters while FIFO is not empty */
> + do {
> + flg = TTY_NORMAL;
> + port->icount.rx++;
> + ch = readl(port->membase + RX_DAT);
> + if (status & RX_PARITY_ERRE) {
[Severity: Medium]
Could this artificially inflate error statistics? The status argument is read
once before the loop, but it is evaluated against every character drained from
the FIFO. If an error bit was set initially, it looks like every subsequent
valid character in the batch is flagged as an error.
> + port->icount.parity++;
> + flg = TTY_PARITY;
> + }
[ ... ]
> +#ifdef CONFIG_SERIAL_CORTINA_ACCESS_CONSOLE
> +static void cortina_console_write(struct console *co, const char *s,
> + unsigned int count)
> +{
> + struct uart_port *port;
> + struct cortina_uart_port *pca_port;
> + unsigned int i, previous;
> + unsigned long flags;
> + int locked;
> +
> + pca_port = cortina_uart_get_port(co->index);
> + port = &pca_port->uart;
> +
> + local_irq_save(flags);
> + if (port->sysrq) {
> + locked = 0;
> + } else if (oops_in_progress) {
> + locked = spin_trylock(&port->lock);
> + } else {
> + spin_lock(&port->lock);
[Severity: High]
Will this cause a sleeping-while-atomic lockdep warning on PREEMPT_RT?
Disabling hardware interrupts and then acquiring a sleeping lock (like
spinlock_t on RT kernels) is not allowed. Should this use
uart_port_lock_irqsave instead?
> + locked = 1;
> + }
[ ... ]
> + /* Write all the chars */
> + for (i = 0; i < count; i++) {
> + /* Wait for the TX buffer to be empty */
> + while (!(readl(port->membase + INFO) & INFO_TX_EMPTY))
> + cpu_relax();
> +
> + writel(*s, port->membase + TX_DAT);
> +
> + /* CR/LF handling */
> + if (*s++ == '\n') {
[Severity: Low]
Does this transmit an incorrect LF-CR sequence instead of the standard CR-LF?
It writes the current character and then appends a carriage return if the
character was a newline. Could this be simplified by using uart_console_write?
> + while (!(readl(port->membase + INFO) & INFO_TX_EMPTY))
> + cpu_relax();
> + writel('\r', port->membase + TX_DAT);
> + }
> + }
[ ... ]
> +static int __init cortina_console_setup(struct console *co, char *options)
> +{
> + struct uart_port *port;
> + struct cortina_uart_port *pca_port;
> + int baud = 115200;
> + int bits = 8;
> + int parity = 'n';
> + int flow = 'n';
> +
> + if (co->index < 0 || co->index >= UART_NR)
> + return -ENODEV;
> +
> + pca_port = cortina_uart_get_port(co->index);
> + port = &pca_port->uart;
> +
> + if (options)
> + uart_parse_options(options, &baud, &parity, &bits, &flow);
> +
> + return uart_set_options(port, co, baud, parity, bits, flow);
[Severity: High]
Can this cause a kernel panic if a console is requested on an unprobed port
index (e.g. via the command line)? It looks like this fetches a potentially
zero-initialized port from the global array and passes it to uart_set_options,
which will unconditionally dereference the port operations.
> +}
[ ... ]
> +static int serial_cortina_probe(struct platform_device *pdev)
> +{
> + struct device_node *np = pdev->dev.of_node;
> + struct cortina_uart_port *port;
> + struct resource *res;
> + struct clk *pclk_info;
> + int uart_idx;
> + int irq;
> + int ret;
> +
> + if (!cortina_uart_ports) {
> + cortina_uart_ports = kcalloc(UART_NR, sizeof(*cortina_uart_ports),
> + GFP_KERNEL);
[Severity: High]
Is there a race condition with this global array allocation? The
cortina_uart_ports array is allocated and searched without any locking. Could
concurrent probing of multiple instances lead to a double allocation and
memory leak?
> + if (!cortina_uart_ports)
> + return -ENOMEM;
> + }
> +
> + port = cortina_uart_ports;
> + for (uart_idx = 0; uart_idx < UART_NR; ++uart_idx) {
> + /* Find first empty slot */
> + if (strlen(port->name) == 0)
> + break;
> + port++;
> + }
> +
> + if (uart_idx >= UART_NR)
> + return -ENODEV;
> +
> + snprintf(port->name, sizeof(port->name),
> + "Cortina-Access UART%d", uart_idx);
[Severity: Medium]
If a subsequent initialization step fails in the probe function, does this
permanently leak the port slot? The name is assigned to claim the slot, but
it doesn't appear to be cleared on the error paths.
[ ... ]
> + if (of_property_read_bool(np, "wakeup-source"))
> + port->may_wakeup = true;
> + if (of_property_read_bool(np, "break-indicator"))
> + port->has_bi = true;
> +
> + if (port->may_wakeup)
> + device_init_wakeup(&pdev->dev, true);
[Severity: Medium]
Does this leak the wakeup source memory? device_init_wakeup is called to
enable the wakeup source, but it is never disabled on the probe error path or
in the removal callback.
> +
> + ret = uart_add_one_port(&cortina_uart_driver, &port->uart);
[ ... ]
> +static void serial_cortina_remove(struct platform_device *pdev)
> +{
> + struct cortina_uart_port *pca_port = platform_get_drvdata(pdev);
> +
> + if (pca_port) {
> + memset(pca_port->name, 0, CA_UART_NAME_LEN);
> + uart_remove_one_port(&cortina_uart_driver, &pca_port->uart);
[Severity: High]
Does clearing the slot name before unregistering the port open a race
condition? If the name is cleared early, a concurrent probe might hijack the
slot and overwrite the port state during active teardown.
> + }
> +
> + platform_set_drvdata(pdev, NULL);
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260610112821.3030099-1-jason.li@cortina-access.com?part=2
^ permalink raw reply
* [PATCH v4 2/2] ARM: dts: qcom: msm8926-sony-xperia-yukon-eagle: add initial device tree
From: Erikas Bitovtas @ 2026-06-10 11:38 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
~postmarketos/upstreaming, phone-devel, Erikas Bitovtas,
Dmitry Baryshkov, Konrad Dybcio
In-Reply-To: <20260610-yukon-eagle-v4-0-763d5698bd2c@gmail.com>
Add device tree for Sony Xperia M2 (sony-eagle) smartphone
based on the Qualcomm MSM8926 SoC.
Initial features:
- Framebuffer
- GPIO buttons (Volume Down and Camera)
- Regulators
- Internal storage
- SD card
- Accelerometer
- Ambient Light/Proximity sensor
- NFC
- pm8226_resin (Volume Up)
- Vibrator
- USB/Charger
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Erikas Bitovtas <xerikasxx@gmail.com>
---
arch/arm/boot/dts/qcom/Makefile | 1 +
.../dts/qcom/msm8926-sony-xperia-yukon-eagle.dts | 407 +++++++++++++++++++++
2 files changed, 408 insertions(+)
diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile
index 32a44b02d2fa..6b471a346d82 100644
--- a/arch/arm/boot/dts/qcom/Makefile
+++ b/arch/arm/boot/dts/qcom/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_QCOM) += \
msm8226-motorola-falcon.dtb \
+ msm8926-sony-xperia-yukon-eagle.dtb \
qcom-apq8016-sbc.dtb \
qcom-apq8026-asus-sparrow.dtb \
qcom-apq8026-huawei-sturgeon.dtb \
diff --git a/arch/arm/boot/dts/qcom/msm8926-sony-xperia-yukon-eagle.dts b/arch/arm/boot/dts/qcom/msm8926-sony-xperia-yukon-eagle.dts
new file mode 100644
index 000000000000..b3ef39726b86
--- /dev/null
+++ b/arch/arm/boot/dts/qcom/msm8926-sony-xperia-yukon-eagle.dts
@@ -0,0 +1,407 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2026 Erikas Bitovtas <xerikasxx@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "msm8926.dtsi"
+#include "pm8226.dtsi"
+
+/delete-node/ &adsp_region;
+/delete-node/ &mba_region;
+/delete-node/ &mpss_region;
+/delete-node/ &smem_region;
+
+/ {
+ model = "Sony Xperia M2";
+ compatible = "sony,eagle", "qcom,msm8926", "qcom,msm8226";
+ chassis-type = "handset";
+
+ aliases {
+ mmc0 = &sdhc_1;
+ mmc1 = &sdhc_2;
+ display0 = &framebuffer0;
+ };
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ stdout-path = "display0";
+
+ framebuffer0: framebuffer@3201000 {
+ compatible = "simple-framebuffer";
+ reg = <0x03201000 0x800000>;
+ width = <540>;
+ height = <960>;
+ stride = <(540 * 3)>;
+ format = "r8g8b8";
+
+ clocks = <&mmcc MDSS_AHB_CLK>,
+ <&mmcc MDSS_AXI_CLK>,
+ <&mmcc MDSS_BYTE0_CLK>,
+ <&mmcc MDSS_MDP_CLK>,
+ <&mmcc MDSS_PCLK0_CLK>,
+ <&mmcc MDSS_VSYNC_CLK>;
+ power-domains = <&mmcc MDSS_GDSC>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&gpio_keys_default>;
+ pinctrl-names = "default";
+
+ button-camera-focus {
+ label = "Camera Focus";
+ gpios = <&tlmm 108 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_CAMERA_FOCUS>;
+ debounce-interval = <15>;
+ };
+
+ button-camera-snapshot {
+ label = "Camera Snapshot";
+ gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_CAMERA>;
+ debounce-interval = <15>;
+ };
+
+ button-volume-down {
+ label = "Volume Down";
+ gpios = <&tlmm 106 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ debounce-interval = <15>;
+ };
+ };
+
+ reserved-memory {
+ framebuffer@3201000 {
+ reg = <0x03201000 0x800000>;
+ no-map;
+ };
+
+ mpss_region: mpss@8000000 {
+ reg = <0x08000000 0x4d00000>;
+ no-map;
+ };
+
+ reserved@cd00000 {
+ reg = <0x0cd00000 0x200000>;
+ no-map;
+ };
+
+ mba_region: mba@d100000 {
+ reg = <0x0d100000 0x3a000>;
+ no-map;
+ };
+
+ reserved@d13a000 {
+ reg = <0x0d13a000 0xc6000>;
+ no-map;
+ };
+
+ wcnss_region: wcnss@d200000 {
+ reg = <0x0d200000 0x5ae000>;
+ no-map;
+ };
+
+ reserved@d850000 {
+ reg = <0x0d850000 0x3b0000>;
+ no-map;
+ };
+
+ adsp_region: adsp@dc00000 {
+ reg = <0x0dc00000 0x1400000>;
+ no-map;
+ };
+
+ reserved@f000000 {
+ reg = <0x0f000000 0x500000>;
+ no-map;
+ };
+
+ venus_region: venus@f500000 {
+ reg = <0x0f500000 0x500000>;
+ no-map;
+ };
+
+ smem_region: smem@fa00000 {
+ reg = <0x0fa00000 0x100000>;
+ no-map;
+ };
+
+ reserved@fb00000 {
+ reg = <0x0fb00000 0x280000>;
+ no-map;
+ };
+
+ rmtfs@fd80000 {
+ compatible = "qcom,rmtfs-mem";
+ reg = <0x0fd80000 0x180000>;
+ no-map;
+
+ qcom,client-id = <1>;
+ };
+ };
+};
+
+&blsp1_i2c2 {
+ status = "okay";
+
+ accelerometer@f {
+ compatible = "kionix,kxtj21009";
+ reg = <0x0f>;
+
+ interrupts-extended = <&tlmm 49 IRQ_TYPE_EDGE_RISING>;
+
+ vdd-supply = <&pm8226_l19>;
+ vddio-supply = <&pm8226_lvs1>;
+
+ mount-matrix = "0", "1", "0",
+ "-1", "0", "0",
+ "0", "0", "1";
+ };
+
+ light-sensor@48 {
+ compatible = "sensortek,stk3310";
+ reg = <0x48>;
+
+ interrupts-extended = <&tlmm 65 IRQ_TYPE_EDGE_FALLING>;
+
+ proximity-near-level = <1700>;
+ };
+};
+
+&blsp1_i2c3 {
+ status = "okay";
+
+ nfc@28 {
+ compatible = "nxp,pn547", "nxp,nxp-nci-i2c";
+ reg = <0x28>;
+
+ interrupts-extended = <&tlmm 21 IRQ_TYPE_EDGE_RISING>;
+
+ enable-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>;
+ firmware-gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&pm8226_resin {
+ linux,code = <KEY_VOLUMEUP>;
+
+ status = "okay";
+};
+
+&pm8226_vib {
+ status = "okay";
+};
+
+&rpm_requests {
+ regulators {
+ compatible = "qcom,rpm-pm8226-regulators";
+
+ pm8226_s3: s3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ pm8226_s4: s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2200000>;
+ };
+
+ pm8226_s5: s5 {
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+ };
+
+ pm8226_l1: l1 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8226_l2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l3: l3 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1287500>;
+ };
+
+ pm8226_l4: l4 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l5: l5 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l7: l7 {
+ regulator-min-microvolt = <1850000>;
+ regulator-max-microvolt = <1850000>;
+ };
+
+ pm8226_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l9: l9 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pm8226_l10: l10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l14: l14 {
+ regulator-min-microvolt = <2750000>;
+ regulator-max-microvolt = <2750000>;
+ };
+
+ pm8226_l15: l15 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ pm8226_l16: l16 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3350000>;
+ };
+
+ pm8226_l17: l17 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l18: l18 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+
+ regulator-system-load = <200000>;
+ regulator-allow-set-load;
+ };
+
+ pm8226_l19: l19 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pm8226_l20: l20 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+
+ pm8226_l21: l21 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-allow-set-load;
+ };
+
+ pm8226_l22: l22 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l23: l23 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l24: l24 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ pm8226_l25: l25 {
+ regulator-min-microvolt = <1775000>;
+ regulator-max-microvolt = <2125000>;
+ };
+
+ pm8226_l26: l26 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8226_l27: l27 {
+ regulator-min-microvolt = <2100000>;
+ regulator-max-microvolt = <2100000>;
+ };
+
+ pm8226_l28: l28 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_lvs1: lvs1 {};
+ };
+};
+
+&smbb {
+ qcom,fast-charge-current-limit = <1500000>;
+ qcom,fast-charge-safe-voltage = <4250000>;
+ qcom,minimum-input-voltage = <4200000>;
+
+ status = "okay";
+};
+
+&sdhc_1 {
+ vmmc-supply = <&pm8226_l17>;
+ vqmmc-supply = <&pm8226_l6>;
+
+ bus-width = <8>;
+ non-removable;
+
+ status = "okay";
+};
+
+&sdhc_2 {
+ vmmc-supply = <&pm8226_l18>;
+ vqmmc-supply = <&pm8226_l21>;
+
+ bus-width = <4>;
+ cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+};
+
+&tlmm {
+ gpio_keys_default: gpio-keys-default-state {
+ pins = "gpio106", "gpio107", "gpio108";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+};
+
+&usb {
+ extcon = <&smbb>;
+ dr_mode = "peripheral";
+
+ status = "okay";
+};
+
+&usb_hs_phy {
+ extcon = <&smbb>;
+ v1p8-supply = <&pm8226_l10>;
+ v3p3-supply = <&pm8226_l20>;
+};
--
2.54.0
^ permalink raw reply related
* [PATCH v4 1/2] dt-bindings: arm: qcom: Add Sony Xperia M2
From: Erikas Bitovtas @ 2026-06-10 11:38 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
~postmarketos/upstreaming, phone-devel, Erikas Bitovtas,
Krzysztof Kozlowski
In-Reply-To: <20260610-yukon-eagle-v4-0-763d5698bd2c@gmail.com>
Document the Sony Xperia M2, which is a smartphone based on the
Qualcomm MSM8926 SoC.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Erikas Bitovtas <xerikasxx@gmail.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 50cc18a6ec5e..851d1b4d74eb 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -99,6 +99,7 @@ properties:
- microsoft,tesla
- motorola,peregrine
- samsung,matisselte
+ - sony,eagle
- const: qcom,msm8926
- const: qcom,msm8226
--
2.54.0
^ permalink raw reply related
* [PATCH v4 0/2] ARM: dts: qcom: msm8926-sony-xperia-yukon-eagle: add initial device tree
From: Erikas Bitovtas @ 2026-06-10 11:38 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
~postmarketos/upstreaming, phone-devel, Erikas Bitovtas,
Krzysztof Kozlowski, Dmitry Baryshkov, Konrad Dybcio
Sony Xperia M2 is a smartphone released in 2014 based on the Qualcomm
Snapdragon 400 (MSM8926) platform.
Add initial device tree for Sony Xperia M2 with support for:
- Framebuffer
- GPIO buttons (Volume Down and Camera)
- Regulators
- Internal storage
- SD card
- Accelerometer
- Ambient Light/Proximity sensor
- NFC
- pm8226_resin (Volume Up)
- Vibrator
- USB/Charger
Signed-off-by: Erikas Bitovtas <xerikasxx@gmail.com>
---
Changes in v4:
- Defined pinctrl for GPIO buttons.
- Aligned quotation marks in mount-matrix for the accelerator.
- Dropped magnetometer from the patch. It probes, but fails to read its
revision if reset GPIO is not defined, and this model does not have a
reset GPIO. Nevertheless, even if one is defined, the probe fails with
a timeout. Needs further investigation.
- Link to v3: https://patch.msgid.link/20260604-yukon-eagle-v3-0-9e3b57d306a8@gmail.com
Changes in v3:
- Changed incorrect "chassis" to "chassis-type" in the device tree.
- Mentioned added vibrator in the commit message.
- Link to v2: https://patch.msgid.link/20260603-yukon-eagle-v2-0-f86b440583f5@gmail.com
Changes in v2:
- Dropped `regulator-always-on` for l3, l6 and l8.
- Mentioned added GPIO buttons and reset input in the commit message.
- Link to v1: https://patch.msgid.link/20260527-yukon-eagle-v1-0-98119d64a71b@gmail.com
To: Bjorn Andersson <andersson@kernel.org>
To: Konrad Dybcio <konradybcio@kernel.org>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
Erikas Bitovtas (2):
dt-bindings: arm: qcom: Add Sony Xperia M2
ARM: dts: qcom: msm8926-sony-xperia-yukon-eagle: add initial device tree
Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
arch/arm/boot/dts/qcom/Makefile | 1 +
.../dts/qcom/msm8926-sony-xperia-yukon-eagle.dts | 407 +++++++++++++++++++++
3 files changed, 409 insertions(+)
---
base-commit: 49e02880ec0a8c378e811bc9d85da188d7c6204c
change-id: 20260526-yukon-eagle-658f2f81a14d
Best regards,
--
Erikas Bitovtas <xerikasxx@gmail.com>
^ permalink raw reply
* Re: [PATCH 3/3] arm64: dts: cortina-access: Add DTS for CA8289 SoC and Venus board
From: sashiko-bot @ 2026-06-10 11:37 UTC (permalink / raw)
To: Jason Li; +Cc: robh, conor+dt, devicetree
In-Reply-To: <20260610112821.3030099-5-jason.li@cortina-access.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Use of discouraged `clock-frequency` property in the ARMv8 timer node.
- [Low] Missing root `#address-cells` and `#size-cells` in SoC DTSI.
--
commit bb6d4b41e4c489bdce2ba3142178fa3654514276
Author: Jason Li <jason.lee651024@gmail.com>
arm64: dts: cortina-access: Add DTS for CA8289 SoC and Venus board
Add SoC DTSI for the Cortina-Access CA8289 (Venus) and a board DTS for
the Venus engineering board. The description covers the minimum set of
hardware nodes needed to boot a kernel with an INITRD rootfs.
> diff --git a/arch/arm64/boot/dts/cortina-access/ca8289-soc.dtsi b/arch/arm64/boot/dts/cortina-access/ca8289-soc.dtsi
> new file mode 100644
> index 0000000000000..8e7ffcf4ccab4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/cortina-access/ca8289-soc.dtsi
> @@ -0,0 +1,118 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * dts file for Cortina Access CA8289 SoC
> + *
> + * Copyright (C) 2026, Cortina Access Inc.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
[Severity: Low]
Should the root node of this DTSI include its own #address-cells and
#size-cells declarations?
While the top-level ca8289-engboard.dts provides these, defining several
top-level nodes (like gic, uart0, uart1) that use 64-bit addresses relies
on the board file to satisfy the DTSI's cell size requirements. Could
these be added to the DTSI root node so it remains self-contained?
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
[ ... ]
> + /* See Documentation/devicetree/bindings/timer/arm,arch_timer.yaml */
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> + clock-frequency = <25000000>;
[Severity: Medium]
Is this clock-frequency property strictly necessary for this new SoC?
For ARMv8 architectures, the system timer frequency should typically be
programmed into the CNTFRQ_EL0 register by the boot firmware (e.g., TF-A)
on all CPUs.
The devicetree clock-frequency property is generally treated as a workaround
for legacy firmware that cannot be modified. For new SoC ports, can the boot
firmware be updated to properly initialize CNTFRQ_EL0 instead?
> + };
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260610112821.3030099-1-jason.li@cortina-access.com?part=3
^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: serial: Add binding for Cortina-Access UART
From: sashiko-bot @ 2026-06-10 11:36 UTC (permalink / raw)
To: Jason Li; +Cc: robh, conor+dt, devicetree
In-Reply-To: <20260610112821.3030099-3-jason.li@cortina-access.com>
Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [Medium] The board compatible strings restrict the array to a single string, forbidding the required generic SoC fallback.
- [Low] The UART binding example defines a 4-cell `reg` property without specifying the parent bus `#address-cells` and `#size-cells`, which causes `dt_binding_check` to fail.
- [Low] Alphabetical sorting violation in `vendor-prefixes.yaml` and `MAINTAINERS`, breaking devicetree tooling and sorting guidelines.
- [Low] The UART binding uses a generic device class compatible string instead of a specific implementation string.
--
commit 32a23126a643cf7b114be8e3c3826bc3ea97f447
Author: Jason Li <jason.lee651024@gmail.com>
dt-bindings: serial: Add binding for Cortina-Access UART
This commit adds a new device tree binding schema for the Cortina-Access
UART controller, targeting the CAXXXX SoC family. It also introduces the
vendor prefix for Cortina Access and a top-level ARM board binding for the
CA8289 (Venus) SoC.
> diff --git a/Documentation/devicetree/bindings/arm/cortina-access.yaml b/Documentation/devicetree/bindings/arm/cortina-access.yaml
> new file mode 100644
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/cortina-access.yaml
[ ... ]
> +properties:
> + $nodename:
> + const: /
> + compatible:
> + oneOf:
> + - description: Cortina-Access CA8289 (Venus) engineering board
> + const: cortina-access,ca8289-engboard
[Severity: Medium]
Will rigidly enforcing a single compatible string cause dtbs_check to fail
on standard board device trees?
Standard ARM platform device trees typically define the board compatible as
an array containing the specific board followed by the generic SoC string.
Should this use an items array to explicitly define and allow both the
board string and the required SoC fallback string instead of const?
> +
> + - description: Cortina-Access CA8289 (Venus) reference board
> + const: cortina-access,ca8289-refboard
[ ... ]
> diff --git a/Documentation/devicetree/bindings/serial/cortina-access,serial.yaml b/Documentation/devicetree/bindings/serial/cortina-access,serial.yaml
> new file mode 100644
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/serial/cortina-access,serial.yaml
[ ... ]
> +properties:
> + compatible:
> + const: cortina-access,serial
[Severity: Low]
Is this compatible string too generic?
The Devicetree specification generally advises against using generic device
class names in compatible strings. Would it be better to name the
compatible string after the first specific SoC implementation, such as
cortina-access,ca8289-uart, and use that as the generic fallback?
> +
> + reg:
> + maxItems: 1
[ ... ]
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + serial@f4329188 {
> + compatible = "cortina-access,serial";
> + reg = <0 0xf4329188 0 0x30>;
[Severity: Low]
Does this example fail dt_binding_check?
The schema restricts the reg property to maxItems: 1. Because no parent bus
node is defined, the dt-extract-example tool wraps this in a default root
node with 1-cell address and size. This causes the 4-cell reg array here to
be parsed as two distinct register regions, violating the maxItems constraint.
> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&apb_pclk>;
> + };
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -367,6 +367,8 @@ patternProperties:
> description: Chengdu Corpro Technology Co., Ltd.
> "^corechips,.*":
> description: Shenzhen Corechips Microelectronics Co., Ltd.
> + "^cortina-access,.*":
> + description: Cortina Access, Inc.
[Severity: Low]
Could this insertion break schema validation due to alphabetical sorting?
The vendor-prefixes.yaml file enforces strict ASCII alphabetical sorting.
A comma (ASCII 44) is less than a hyphen (ASCII 45), so ^cortina,.* should
precede ^cortina-access,.*.
> "^cortina,.*":
> description: Cortina Systems, Inc.
> "^cosmic,.*":
> diff --git a/MAINTAINERS b/MAINTAINERS
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2749,6 +2749,13 @@ F: tools/perf/tests/shell/lib/*coresight*
> F: tools/perf/util/cs-etm-decoder/*
> F: tools/perf/util/cs-etm.*
>
> +ARM/CORTINA-ACCESS VENUS ARM ARCHITECTURE
> +M: Jason Li <jason.li@cortina-access.com>
> +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> +S: Maintained
> +F: Documentation/devicetree/bindings/arm/cortina-access.yaml
> +F: Documentation/devicetree/bindings/serial/cortina-access,serial.yaml
> +
[Severity: Low]
Does this entry violate the alphabetical sorting guidelines for the
MAINTAINERS file?
A space (ASCII 32) is less than a hyphen (ASCII 45), so ARM/CORTINA SYSTEMS
should appear before ARM/CORTINA-ACCESS.
> ARM/CORTINA SYSTEMS GEMINI ARM ARCHITECTURE
> M: Hans Ulli Kroll <ulli.kroll@googlemail.com>
> M: Linus Walleij <linusw@kernel.org>
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260610112821.3030099-1-jason.li@cortina-access.com?part=1
^ permalink raw reply
* Re: [Question] Enabling CoreSight TRBE in firmware on CIX Orion O6
From: Leo Yan @ 2026-06-10 11:34 UTC (permalink / raw)
To: Gary Yang
Cc: Yunseong Kim, Peter Chen, Fugang Duan, Guomin Chen, Hans Zhang,
Joakim Zhang, Jerry Zhu, CIX Linux Kernel Upstream Group,
devicetree, linux-arm-kernel, linux-kernel@vger.kernel.org,
Yunseong Kim, Yunseong Kim
In-Reply-To: <aikVYZDMYuPscIKR@gary-System-Product-Name>
On Wed, Jun 10, 2026 at 03:42:25PM +0800, Gary Yang wrote:
[...]
> > (2) Or expose the full CoreSight topology in ACPI:
> > - Add ARMHC97C (TMC-ETR) device with MMIO base address
> > - Add ARMHC502 (funnel) devices if applicable
> > - Reference: ARM DEN0067 (CoreSight Architecture ACPI bindings)
The CPUs on O6 support ETE + TRBE, you don't need to use ETR or funnel
modules.
> The firmware (TF-A) for the Radxa O6 is provided and maintained by Radxa. We
> will forward your request to the Radxa firmware team and ask them to evaluate
> enabling TRBE access from non-secure EL1/EL2 (i.e. setting MDCR_EL3.NSTBE = 1
> in TF-A), as you suggested.
The issue is caused by ACPI: the APIC table does not contain a TRBE
interrupt, and the SSDT is missing ETE nodes (ETE node should be
present for each CPU):
Device (CPU0)
{
...
Device ( ETE0 ) {
Name (_UID, Zero)
Name (_HID , "ARMHC500")
}
}
Thanks,
Leo
^ permalink raw reply
* [PATCH 3/3] arm64: dts: cortina-access: Add DTS for CA8289 SoC and Venus board
From: Jason Li @ 2026-06-10 11:28 UTC (permalink / raw)
To: jason.li, Greg Kroah-Hartman, Jiri Slaby
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Catalin Marinas,
Will Deacon, Arnd Bergmann, linux-serial, linux-arm-kernel,
devicetree, linux-kernel
In-Reply-To: <20260610112821.3030099-1-jason.li@cortina-access.com>
Add SoC DTSI for the Cortina-Access CA8289 (Venus) and a board DTS for
the Venus engineering board. The description covers the minimum set of
hardware nodes needed to boot a kernel with an INITRD rootfs: CPUs,
GIC, timer, PSCI, fixed clock and UART.
Signed-off-by: Jason Li <jason.li@cortina-access.com>
Assisted-by: Claude:claude-opus-4-8
---
MAINTAINERS | 1 +
arch/arm64/Kconfig.platforms | 10 ++
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/cortina-access/Makefile | 2 +
.../dts/cortina-access/ca8289-engboard.dts | 31 +++++
.../boot/dts/cortina-access/ca8289-soc.dtsi | 118 ++++++++++++++++++
6 files changed, 163 insertions(+)
create mode 100644 arch/arm64/boot/dts/cortina-access/Makefile
create mode 100644 arch/arm64/boot/dts/cortina-access/ca8289-engboard.dts
create mode 100644 arch/arm64/boot/dts/cortina-access/ca8289-soc.dtsi
diff --git a/MAINTAINERS b/MAINTAINERS
index 515d89d96472..ebfdb9c267cc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2826,6 +2826,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/arm/cortina-access.yaml
F: Documentation/devicetree/bindings/serial/cortina-access,serial.yaml
+F: arch/arm64/boot/dts/cortina-access/
ARM/CORTINA SYSTEMS GEMINI ARM ARCHITECTURE
M: Hans Ulli Kroll <ulli.kroll@googlemail.com>
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index dc995a732117..ba6dda0660c3 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -134,6 +134,16 @@ config ARCH_CIX
This enables support for the Cixtech SoC family,
like P1(sky1).
+config ARCH_CORTINA_ACCESS
+ bool "Cortina-Access SoC Family"
+ select GPIOLIB
+ select PINCTRL
+ help
+ This enables support for Cortina-Access SoCs. The family
+ includes ARMv8-based devices targeting networking and access
+ applications.
+ If you have a Cortina-Access board, say Y here.
+
config ARCH_EXYNOS
bool "Samsung Exynos SoC family"
select COMMON_CLK_SAMSUNG
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 98ec8f1b76e4..a599f525fb9a 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -16,6 +16,7 @@ subdir-y += broadcom
subdir-y += bst
subdir-y += cavium
subdir-y += cix
+subdir-y += cortina-access
subdir-y += exynos
subdir-y += freescale
subdir-y += hisilicon
diff --git a/arch/arm64/boot/dts/cortina-access/Makefile b/arch/arm64/boot/dts/cortina-access/Makefile
new file mode 100644
index 000000000000..554893f381fe
--- /dev/null
+++ b/arch/arm64/boot/dts/cortina-access/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_CORTINA_ACCESS) += ca8289-engboard.dtb
diff --git a/arch/arm64/boot/dts/cortina-access/ca8289-engboard.dts b/arch/arm64/boot/dts/cortina-access/ca8289-engboard.dts
new file mode 100644
index 000000000000..c8289a0f8269
--- /dev/null
+++ b/arch/arm64/boot/dts/cortina-access/ca8289-engboard.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Cortina Access Venus Engineering Board
+ *
+ * Copyright (C) 2026, Cortina Access Inc.
+ *
+ */
+
+/dts-v1/;
+
+#include "ca8289-soc.dtsi"
+
+/ {
+ model = "Cortina Access Venus Engineering Board";
+ compatible = "cortina-access,ca8289-engboard";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 { /* 512MB */
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x0 0x20000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/cortina-access/ca8289-soc.dtsi b/arch/arm64/boot/dts/cortina-access/ca8289-soc.dtsi
new file mode 100644
index 000000000000..8e7ffcf4ccab
--- /dev/null
+++ b/arch/arm64/boot/dts/cortina-access/ca8289-soc.dtsi
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Cortina Access CA8289 SoC
+ *
+ * Copyright (C) 2026, Cortina Access Inc.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a55", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+ cpu1: cpu@100 {
+ compatible = "arm,cortex-a55", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ };
+ cpu2: cpu@200 {
+ compatible = "arm,cortex-a55", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ };
+ cpu3: cpu@300 {
+ compatible = "arm,cortex-a55", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ };
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ gic: interrupt-controller@4f8000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ #redistributor-regions = <1>;
+ reg = <0x00000004 0xF8000000 0 0x10000>,
+ <0x00000004 0xF8040000 0 0x80000>;
+ };
+
+ apb_pclk: apb-pclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* TrustZone reserved region; must not be mapped by the kernel */
+ tz_pool: tz-buffer@f000000 {
+ reg = <0x0 0x0F000000 0x0 0x1000000>;
+ no-map;
+ };
+ };
+
+ /* See Documentation/devicetree/bindings/timer/arm,arch_timer.yaml */
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ clock-frequency = <25000000>;
+ };
+
+ uart0: serial@f4329188 {
+ device_type = "serial";
+ compatible = "cortina-access,serial";
+ reg = <0x00000000 0xf4329188 0x0 0x30>;
+ clocks = <&apb_pclk>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ uart1: serial@f43291b8 {
+ device_type = "serial";
+ compatible = "cortina-access,serial";
+ reg = <0x00000000 0xf43291b8 0x0 0x30>;
+ clocks = <&apb_pclk>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
--
2.39.5
^ permalink raw reply related
* [PATCH 2/3] tty: serial: Add UART driver for Cortina-Access platform
From: Jason Li @ 2026-06-10 11:28 UTC (permalink / raw)
To: jason.li, Greg Kroah-Hartman, Jiri Slaby
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Catalin Marinas,
Will Deacon, Arnd Bergmann, linux-serial, linux-arm-kernel,
devicetree, linux-kernel
In-Reply-To: <20260610112821.3030099-1-jason.li@cortina-access.com>
This driver supports Cortina Access UART IP integrated
in most CAXXXX line of SoCs. Earlycon is also supported.
Signed-off-by: Jason Li <jason.li@cortina-access.com>
Assisted-by: Claude:claude-opus-4-8
---
MAINTAINERS | 6 +
drivers/tty/serial/Kconfig | 21 +
drivers/tty/serial/Makefile | 1 +
drivers/tty/serial/serial_cortina-access.c | 755 +++++++++++++++++++++
4 files changed, 783 insertions(+)
create mode 100644 drivers/tty/serial/serial_cortina-access.c
diff --git a/MAINTAINERS b/MAINTAINERS
index cc261888fae0..515d89d96472 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6687,6 +6687,12 @@ S: Maintained
F: Documentation/hwmon/corsair-psu.rst
F: drivers/hwmon/corsair-psu.c
+CORTINA-ACCESS SERIAL CONSOLE DRIVER
+M: Jason Li <jason.li@cortina-access.com>
+L: linux-serial@vger.kernel.org
+S: Supported
+F: drivers/tty/serial/serial_cortina-access.c
+
COUNTER SUBSYSTEM
M: William Breathitt Gray <wbg@kernel.org>
L: linux-iio@vger.kernel.org
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index cf7dba473b20..99a1c9308395 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1592,6 +1592,27 @@ config SERIAL_NUVOTON_MA35D1_CONSOLE
but you can alter that using a kernel command line option such as
"console=ttyNVTx".
+config SERIAL_CORTINA_ACCESS
+ tristate "Cortina-Access serial port support"
+ depends on OF
+ select SERIAL_CORE
+ help
+ This driver is for the Cortina-Access SoC UART, present in the
+ CA8289 (Venus) and related CAXXXX family of SoCs. If you have a
+ machine based on the Cortina-Access SoC and wish to use the serial
+ port, say 'Y' here. Otherwise, say 'N'.
+
+config SERIAL_CORTINA_ACCESS_CONSOLE
+ bool "Console on Cortina-Access serial port"
+ depends on SERIAL_CORTINA_ACCESS=y
+ select SERIAL_CORE_CONSOLE
+ select SERIAL_EARLYCON
+ help
+ Say 'Y' here if you wish to use the Cortina-Access UART as the system
+ console (the device which receives all kernel messages and warnings
+ and which allows logins in single user mode).
+ /dev/ttyS* is the default device node.
+
endmenu
config SERIAL_MCTRL_GPIO
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index bba7b21a4a1d..54866c419714 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -98,3 +98,4 @@ obj-$(CONFIG_SERIAL_MCTRL_GPIO) += serial_mctrl_gpio.o
obj-$(CONFIG_KGDB_SERIAL_CONSOLE) += kgdboc.o
obj-$(CONFIG_SERIAL_NUVOTON_MA35D1) += ma35d1_serial.o
+obj-$(CONFIG_SERIAL_CORTINA_ACCESS) += serial_cortina-access.o
diff --git a/drivers/tty/serial/serial_cortina-access.c b/drivers/tty/serial/serial_cortina-access.c
new file mode 100644
index 000000000000..f25eae987ccd
--- /dev/null
+++ b/drivers/tty/serial/serial_cortina-access.c
@@ -0,0 +1,755 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * UART driver for Cortina-Access SoC platform
+ * Copyright (C) 2026 Cortina-Access Inc.
+ */
+#include <linux/clk.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/sysrq.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+
+/***************************************
+ * UART Related registers
+ ****************************************/
+/* register definitions */
+#define CFG 0x00
+#define FC 0x04
+#define RX_SAMPLE 0x08
+#define RT_TUNE 0x0C
+#define TX_DAT 0x10
+#define RX_DAT 0x14
+#define INFO 0x18
+#define IE 0x1C
+#define INT 0x24
+#define STATUS 0x2C
+
+/* CFG */
+#define CFG_STOP_2BIT BIT(2)
+#define CFG_PARITY_EVEN BIT(3)
+#define CFG_PARITY_EN BIT(4)
+#define CFG_TX_EN BIT(5)
+#define CFG_RX_EN BIT(6)
+#define CFG_UART_EN BIT(7)
+#define CFG_BAUD_SART_SHIFT 8
+
+/* INFO */
+#define INFO_TX_EMPTY BIT(3)
+#define INFO_TX_FULL BIT(2)
+#define INFO_RX_EMPTY BIT(1)
+#define INFO_RX_FULL BIT(0)
+
+/* Interrupt */
+#define RX_BREAK BIT(7)
+#define RX_FIFO_NONEMPTYE BIT(6)
+#define TX_FIFO_EMPTYE BIT(5)
+#define RX_FIFO_UNDERRUNE BIT(4)
+#define RX_FIFO_OVERRUNE BIT(3)
+#define RX_PARITY_ERRE BIT(2)
+#define RX_STOP_ERRE BIT(1)
+#define TX_FIFO_OVERRUNE BIT(0)
+
+#define TX_TIMEOUT 5000
+#define UART_NR 4
+#define CA_UART_NAME_LEN 32
+
+struct cortina_uart_port {
+ struct uart_port uart;
+ char name[CA_UART_NAME_LEN];
+ char has_bi;
+ unsigned int may_wakeup;
+};
+
+static struct cortina_uart_port *cortina_uart_ports;
+
+static irqreturn_t cortina_uart_interrupt(int irq, void *dev_id);
+static inline void cortina_uart_interrupt_tx_chars(struct uart_port *port);
+
+/* Return uart_port pointer based on index */
+static struct cortina_uart_port *cortina_uart_get_port(unsigned int index)
+{
+ struct cortina_uart_port *pca_port = cortina_uart_ports;
+
+ if (index >= UART_NR)
+ index = 0;
+
+ pca_port += index;
+
+ return pca_port;
+}
+
+/* uart_ops functions */
+static unsigned int cortina_uart_tx_empty(struct uart_port *port)
+{
+ /* Return 0 on FIFO full condition, TIOCSER_TEMT otherwise */
+ return (readl(port->membase + INFO) & INFO_TX_EMPTY) ? TIOCSER_TEMT : 0;
+}
+
+static void cortina_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+ /*
+ * Even if we do not support configuring the modem control lines, this
+ * function must be provided to the serial core.
+ * port->ops->set_mctrl() is called in uart_configure_port()
+ */
+}
+
+static unsigned int cortina_uart_get_mctrl(struct uart_port *port)
+{
+ /* Unimplemented signals asserted, per Documentation/serial/driver */
+ return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
+}
+
+static void cortina_uart_stop_tx(struct uart_port *port)
+{
+ /* Turn off Tx interrupts. The port lock is held at this point */
+ unsigned int reg_v;
+
+ reg_v = readl(port->membase + IE);
+ writel(reg_v & ~TX_FIFO_EMPTYE, port->membase + IE);
+}
+
+static void cortina_uart_start_tx(struct uart_port *port)
+{
+ /* Turn on Tx interrupts. The port lock is held at this point */
+ unsigned int reg_v;
+
+ reg_v = readl(port->membase + IE);
+ writel(reg_v | TX_FIFO_EMPTYE, port->membase + IE);
+
+ reg_v = readl(port->membase + CFG);
+ writel(reg_v | CFG_TX_EN, port->membase + CFG);
+
+ /*
+ * If TX FIFO is already empty the TX_FIFO_EMPTY interrupt may be
+ * edge-triggered and won't fire again. Kick-start the transmission
+ * explicitly so the first character is not lost.
+ */
+ if (readl(port->membase + INFO) & INFO_TX_EMPTY)
+ cortina_uart_interrupt_tx_chars(port);
+}
+
+static void cortina_uart_stop_rx(struct uart_port *port)
+{
+ /* Turn off Rx interrupts. The port lock is held at this point */
+ unsigned int reg_v;
+
+ reg_v = readl(port->membase + IE);
+ writel(reg_v & ~RX_FIFO_NONEMPTYE, port->membase + IE);
+}
+
+static void cortina_uart_enable_ms(struct uart_port *port)
+{
+ /* Nope, you really can't hope to attach a modem to this */
+}
+
+static int cortina_uart_startup(struct uart_port *port)
+{
+ unsigned int reg_v;
+ int retval;
+ unsigned long flags;
+
+ /* Disable interrupts */
+ writel(0, port->membase + IE);
+
+ retval = request_irq(port->irq, cortina_uart_interrupt, 0,
+ "cortina_uart", port);
+ if (retval)
+ return retval;
+
+ spin_lock_irqsave(&port->lock, flags);
+
+ reg_v = readl(port->membase + CFG);
+ reg_v |= (CFG_UART_EN | CFG_TX_EN | CFG_RX_EN | 0x3 /* 8-bits data */);
+ writel(reg_v, port->membase + CFG);
+ reg_v = readl(port->membase + IE);
+ writel(reg_v | RX_FIFO_NONEMPTYE | TX_FIFO_EMPTYE, port->membase + IE);
+
+ spin_unlock_irqrestore(&port->lock, flags);
+ return 0;
+}
+
+static void cortina_uart_shutdown(struct uart_port *port)
+{
+ cortina_uart_stop_tx(port);
+ cortina_uart_stop_rx(port);
+ free_irq(port->irq, port);
+}
+
+static void cortina_uart_set_termios(struct uart_port *port,
+ struct ktermios *termios,
+ const struct ktermios *old)
+{
+ unsigned long flags;
+ int baud;
+ unsigned int reg_v, sample_freq = 0;
+
+ baud = uart_get_baud_rate(port, termios, old, 0, 230400);
+ reg_v = readl(port->membase + CFG);
+ /* mask off the baud settings */
+ reg_v &= 0xff;
+ reg_v |= (port->uartclk / baud) << CFG_BAUD_SART_SHIFT;
+
+ /* Sampling rate should be half of baud count */
+ sample_freq = (reg_v >> CFG_BAUD_SART_SHIFT) / 2;
+
+ /* See include/uapi/asm-generic/termbits.h for CSIZE definition */
+ /* mask off the data width */
+ reg_v &= 0xfffffffc;
+ switch (termios->c_cflag & CSIZE) {
+ case CS5:
+ reg_v |= 0x0;
+ break;
+ case CS6:
+ reg_v |= 0x1;
+ break;
+ case CS7:
+ reg_v |= 0x2;
+ break;
+ case CS8:
+ default:
+ reg_v |= 0x3;
+ break;
+ }
+
+ /* mask off Stop bits */
+ reg_v &= ~(CFG_STOP_2BIT);
+ if (termios->c_cflag & CSTOPB)
+ reg_v |= CFG_STOP_2BIT;
+
+ /* Parity */
+ reg_v &= ~(CFG_PARITY_EN);
+ reg_v |= CFG_PARITY_EVEN;
+ if (termios->c_cflag & PARENB) {
+ reg_v |= CFG_PARITY_EN;
+ if (termios->c_cflag & PARODD)
+ reg_v &= ~(CFG_PARITY_EVEN);
+ }
+
+ spin_lock_irqsave(&port->lock, flags);
+ writel(reg_v, port->membase + CFG);
+ writel(sample_freq, port->membase + RX_SAMPLE);
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static const char *cortina_uart_type(struct uart_port *port)
+{
+ return container_of(port, struct cortina_uart_port, uart)->name;
+}
+
+static void cortina_uart_config_port(struct uart_port *port, int flags)
+{
+ /*
+ * Driver core for serial ports forces a non-zero value for port type.
+ * Write an arbitrary value here to accommodate the serial core driver,
+ * as ID part of UAPI is redundant.
+ */
+ port->type = 1;
+}
+
+static int cortina_uart_verify_port(struct uart_port *port,
+ struct serial_struct *ser)
+{
+ if (ser->type != PORT_UNKNOWN && ser->type != 1)
+ return -EINVAL;
+ return 0;
+}
+
+static void cortina_access_power(struct uart_port *port, unsigned int state,
+ unsigned int oldstate)
+{
+ unsigned int reg_v;
+
+ reg_v = readl(port->membase + CFG);
+ switch (state) {
+ case UART_PM_STATE_ON:
+ reg_v |= CFG_UART_EN;
+ break;
+ case UART_PM_STATE_OFF:
+ reg_v &= ~CFG_UART_EN;
+ break;
+ default:
+ pr_err("cortina-access serial: Unknown PM state %d\n", state);
+ }
+ writel(reg_v, port->membase + CFG);
+}
+
+#ifdef CONFIG_CONSOLE_POLL
+static int cortina_poll_get_char(struct uart_port *port)
+{
+ if (readl(port->membase + INFO) & INFO_RX_EMPTY)
+ return NO_POLL_CHAR;
+
+ return readl(port->membase + RX_DAT);
+}
+
+static void cortina_poll_put_char(struct uart_port *port, unsigned char c)
+{
+ unsigned long time_out;
+
+ time_out = jiffies + usecs_to_jiffies(TX_TIMEOUT);
+
+ while (time_before(jiffies, time_out) &&
+ (readl(port->membase + INFO) & INFO_TX_FULL))
+ cpu_relax();
+
+ /* Give up if FIFO stuck! */
+ if (readl(port->membase + INFO) & INFO_TX_FULL)
+ return;
+
+ writel(c, port->membase + TX_DAT);
+}
+#endif /* CONFIG_CONSOLE_POLL */
+
+static const struct uart_ops cortina_uart_ops = {
+ .tx_empty = cortina_uart_tx_empty,
+ .set_mctrl = cortina_uart_set_mctrl,
+ .get_mctrl = cortina_uart_get_mctrl,
+ .stop_tx = cortina_uart_stop_tx,
+ .start_tx = cortina_uart_start_tx,
+ .stop_rx = cortina_uart_stop_rx,
+ .enable_ms = cortina_uart_enable_ms,
+ .startup = cortina_uart_startup,
+ .shutdown = cortina_uart_shutdown,
+ .set_termios = cortina_uart_set_termios,
+ .type = cortina_uart_type,
+ .config_port = cortina_uart_config_port,
+ .verify_port = cortina_uart_verify_port,
+ .pm = cortina_access_power,
+#ifdef CONFIG_CONSOLE_POLL
+ .poll_get_char = cortina_poll_get_char,
+ .poll_put_char = cortina_poll_put_char,
+#endif
+};
+
+static inline void cortina_uart_interrupt_rx_chars(struct uart_port *port,
+ unsigned long status)
+{
+ struct tty_port *ttyport = &port->state->port;
+ unsigned int ch;
+ unsigned int rx, flg;
+ struct cortina_uart_port *pca_port;
+
+ rx = readl(port->membase + INFO);
+ if (INFO_RX_EMPTY & rx)
+ return;
+
+ if (status & RX_FIFO_OVERRUNE)
+ port->icount.overrun++;
+
+ pca_port = cortina_uart_get_port(port->line);
+
+ /* Read characters while FIFO is not empty */
+ do {
+ flg = TTY_NORMAL;
+ port->icount.rx++;
+ ch = readl(port->membase + RX_DAT);
+ if (status & RX_PARITY_ERRE) {
+ port->icount.parity++;
+ flg = TTY_PARITY;
+ }
+
+ if (pca_port->has_bi) {
+ if (status & RX_BREAK) {
+ port->icount.brk++;
+ if (uart_handle_break(port))
+ goto ignore;
+ }
+ } else {
+ /* Treat stop err as BI */
+ if (status & RX_STOP_ERRE) {
+ port->icount.brk++;
+ if (uart_handle_break(port))
+ goto ignore;
+ }
+ }
+ if (!(ch & 0x100)) /* RX char is not valid */
+ goto ignore;
+
+ if (uart_handle_sysrq_char(port, (unsigned char)ch))
+ goto ignore;
+
+ tty_insert_flip_char(ttyport, ch, flg);
+ignore:
+ rx = readl(port->membase + INFO);
+ } while (!(INFO_RX_EMPTY & rx));
+
+ spin_unlock(&port->lock);
+ tty_flip_buffer_push(ttyport);
+ spin_lock(&port->lock);
+}
+
+static inline void cortina_uart_interrupt_tx_chars(struct uart_port *port)
+{
+ u8 ch;
+
+ /*
+ * uart_port_tx() drains the kfifo xmit buffer, handles x_char,
+ * calls uart_write_wakeup() and stop_tx() when the buffer empties.
+ */
+ uart_port_tx(port, ch,
+ !(readl(port->membase + INFO) & INFO_TX_FULL),
+ writel(ch, port->membase + TX_DAT));
+}
+
+static irqreturn_t cortina_uart_interrupt(int irq, void *dev_id)
+{
+ struct uart_port *port = (struct uart_port *)dev_id;
+ unsigned int irq_status;
+
+ spin_lock(&port->lock);
+
+ /* Clear interrupt */
+ irq_status = readl(port->membase + INT);
+ writel(irq_status, port->membase + INT);
+
+ /* Process any Rx chars first */
+ cortina_uart_interrupt_rx_chars(port, irq_status);
+ /* Then use any Tx space */
+ cortina_uart_interrupt_tx_chars(port);
+
+ spin_unlock(&port->lock);
+
+ return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_SERIAL_CORTINA_ACCESS_CONSOLE
+static void cortina_console_write(struct console *co, const char *s,
+ unsigned int count)
+{
+ struct uart_port *port;
+ struct cortina_uart_port *pca_port;
+ unsigned int i, previous;
+ unsigned long flags;
+ int locked;
+
+ pca_port = cortina_uart_get_port(co->index);
+ port = &pca_port->uart;
+
+ local_irq_save(flags);
+ if (port->sysrq) {
+ locked = 0;
+ } else if (oops_in_progress) {
+ locked = spin_trylock(&port->lock);
+ } else {
+ spin_lock(&port->lock);
+ locked = 1;
+ }
+
+ /* Save current state */
+ previous = readl(port->membase + IE);
+ /* Disable Tx interrupts so this all goes out in one go */
+ cortina_uart_stop_tx(port);
+
+ /* Write all the chars */
+ for (i = 0; i < count; i++) {
+ /* Wait for the TX buffer to be empty */
+ while (!(readl(port->membase + INFO) & INFO_TX_EMPTY))
+ cpu_relax();
+
+ writel(*s, port->membase + TX_DAT);
+
+ /* CR/LF handling */
+ if (*s++ == '\n') {
+ while (!(readl(port->membase + INFO) & INFO_TX_EMPTY))
+ cpu_relax();
+ writel('\r', port->membase + TX_DAT);
+ }
+ }
+
+ writel(previous, port->membase + IE); /* Restore interrupt state */
+
+ if (locked)
+ spin_unlock(&port->lock);
+ local_irq_restore(flags);
+}
+
+static int __init cortina_console_setup(struct console *co, char *options)
+{
+ struct uart_port *port;
+ struct cortina_uart_port *pca_port;
+ int baud = 115200;
+ int bits = 8;
+ int parity = 'n';
+ int flow = 'n';
+
+ if (co->index < 0 || co->index >= UART_NR)
+ return -ENODEV;
+
+ pca_port = cortina_uart_get_port(co->index);
+ port = &pca_port->uart;
+
+ if (options)
+ uart_parse_options(options, &baud, &parity, &bits, &flow);
+
+ return uart_set_options(port, co, baud, parity, bits, flow);
+}
+
+static struct uart_driver cortina_uart_driver;
+
+static struct console cortina_console = {
+ .name = "ttyS",
+ .write = cortina_console_write,
+ .device = uart_console_device,
+ .setup = cortina_console_setup,
+ .flags = CON_PRINTBUFFER,
+ .index = -1,
+ .data = &cortina_uart_driver,
+};
+
+#define CORTINA_CONSOLE (&cortina_console)
+
+/* Support EARLYCON */
+static void cortina_putc(struct uart_port *port, unsigned char c)
+{
+ unsigned int tmout = TX_TIMEOUT;
+
+ /* No jiffies at early boot stage; wait up to TX_TIMEOUT us */
+ while (--tmout) {
+ if (!(readl(port->membase + INFO) & INFO_TX_FULL))
+ break;
+ udelay(1);
+ }
+
+ /* Give up if FIFO stuck */
+ if (readl(port->membase + INFO) & INFO_TX_FULL)
+ return;
+
+ writel(c, port->membase + TX_DAT);
+}
+
+static void cortina_early_write(struct console *con, const char *s,
+ unsigned int n)
+{
+ struct earlycon_device *dev = con->data;
+
+ uart_console_write(&dev->port, s, n, cortina_putc);
+}
+
+static int __init cortina_early_console_setup(struct earlycon_device *device,
+ const char *opt)
+{
+ u32 reg_v;
+
+ if (!device->port.membase)
+ return -ENODEV;
+
+ device->con->write = cortina_early_write;
+
+ /*
+ * If the bootloader did not enable the UART, initialise it here
+ * at 115200 baud so that early boot messages are not lost.
+ * The magic constant mirrors the reference BSP setting:
+ * CFG[31:8] = baud divisor for 115200, CFG[7] = UART_EN,
+ * CFG[6:5] = RX_EN|TX_EN, CFG[1:0] = 8-bit data.
+ */
+ reg_v = readl(device->port.membase + CFG);
+ if (!(reg_v & CFG_UART_EN)) {
+ writel(0x00043de3, device->port.membase + CFG);
+ writel(0x00043d / 2, device->port.membase + RX_SAMPLE);
+ }
+
+ return 0;
+}
+
+EARLYCON_DECLARE(ca_serial, cortina_early_console_setup);
+OF_EARLYCON_DECLARE(ca_serial, "cortina-access,serial",
+ cortina_early_console_setup);
+#else
+#define CORTINA_CONSOLE NULL
+#endif /* CONFIG_SERIAL_CORTINA_ACCESS_CONSOLE */
+
+static struct uart_driver cortina_uart_driver = {
+ .owner = THIS_MODULE,
+ .driver_name = "cortina-access_uart",
+ .dev_name = "ttyS",
+ .major = TTY_MAJOR,
+ .minor = 64,
+ .nr = UART_NR,
+ .cons = CORTINA_CONSOLE,
+};
+
+/* Match table for of_platform binding */
+static const struct of_device_id cortina_uart_of_match[] = {
+ { .compatible = "cortina-access,serial" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, cortina_uart_of_match);
+
+static int serial_cortina_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct cortina_uart_port *port;
+ struct resource *res;
+ struct clk *pclk_info;
+ int uart_idx;
+ int irq;
+ int ret;
+
+ if (!cortina_uart_ports) {
+ cortina_uart_ports = kcalloc(UART_NR, sizeof(*cortina_uart_ports),
+ GFP_KERNEL);
+ if (!cortina_uart_ports)
+ return -ENOMEM;
+ }
+
+ port = cortina_uart_ports;
+ for (uart_idx = 0; uart_idx < UART_NR; ++uart_idx) {
+ /* Find first empty slot */
+ if (strlen(port->name) == 0)
+ break;
+ port++;
+ }
+
+ if (uart_idx >= UART_NR)
+ return -ENODEV;
+
+ snprintf(port->name, sizeof(port->name),
+ "Cortina-Access UART%d", uart_idx);
+
+ /* Retrieve HW base address and reserve the I/O region */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -EINVAL;
+
+ port->uart.mapbase = res->start;
+ port->uart.membase = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(port->uart.membase))
+ return PTR_ERR(port->uart.membase);
+
+ /* Retrieve IRQ */
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return irq;
+
+ port->uart.irq = irq;
+
+ pclk_info = devm_clk_get_enabled(&pdev->dev, NULL);
+ if (IS_ERR(pclk_info)) {
+ dev_err(&pdev->dev, "failed to get clock\n");
+ return PTR_ERR(pclk_info);
+ }
+
+ port->uart.uartclk = clk_get_rate(pclk_info);
+ port->uart.ops = &cortina_uart_ops;
+ port->uart.dev = &pdev->dev;
+ port->uart.line = uart_idx;
+ port->uart.iotype = UPIO_MEM32;
+ port->uart.type = 1;
+ port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_CORTINA_ACCESS_CONSOLE);
+
+ if (of_property_read_bool(np, "wakeup-source"))
+ port->may_wakeup = true;
+ if (of_property_read_bool(np, "break-indicator"))
+ port->has_bi = true;
+
+ if (port->may_wakeup)
+ device_init_wakeup(&pdev->dev, true);
+
+ ret = uart_add_one_port(&cortina_uart_driver, &port->uart);
+ if (ret)
+ return ret;
+
+ platform_set_drvdata(pdev, port);
+
+ return 0;
+}
+
+static void serial_cortina_remove(struct platform_device *pdev)
+{
+ struct cortina_uart_port *pca_port = platform_get_drvdata(pdev);
+
+ if (pca_port) {
+ memset(pca_port->name, 0, CA_UART_NAME_LEN);
+ uart_remove_one_port(&cortina_uart_driver, &pca_port->uart);
+ }
+
+ platform_set_drvdata(pdev, NULL);
+
+ /*
+ * Free the port array when the last port is removed, i.e. when
+ * all slots are empty again.
+ */
+ if (cortina_uart_ports) {
+ int i;
+
+ for (i = 0; i < UART_NR; i++) {
+ if (strlen(cortina_uart_ports[i].name) != 0)
+ return;
+ }
+ kfree(cortina_uart_ports);
+ cortina_uart_ports = NULL;
+ }
+}
+
+#ifdef CONFIG_PM
+static int serial_cortina_suspend(struct platform_device *pdev,
+ pm_message_t state)
+{
+ struct cortina_uart_port *p = platform_get_drvdata(pdev);
+
+ uart_suspend_port(&cortina_uart_driver, &p->uart);
+
+ return 0;
+}
+
+static int serial_cortina_resume(struct platform_device *pdev)
+{
+ struct cortina_uart_port *p = platform_get_drvdata(pdev);
+
+ uart_resume_port(&cortina_uart_driver, &p->uart);
+
+ return 0;
+}
+#else
+#define serial_cortina_suspend NULL
+#define serial_cortina_resume NULL
+#endif
+
+static struct platform_driver serial_cortina_driver = {
+ .probe = serial_cortina_probe,
+ .remove = serial_cortina_remove,
+#ifdef CONFIG_PM
+ .suspend = serial_cortina_suspend,
+ .resume = serial_cortina_resume,
+#endif
+ .driver = {
+ .name = "cortina-access_serial",
+ .of_match_table = cortina_uart_of_match,
+ },
+};
+
+static int __init cortina_uart_init(void)
+{
+ int ret;
+
+ ret = uart_register_driver(&cortina_uart_driver);
+ if (ret)
+ return ret;
+
+ ret = platform_driver_register(&serial_cortina_driver);
+ if (ret)
+ uart_unregister_driver(&cortina_uart_driver);
+
+ return ret;
+}
+
+static void __exit cortina_uart_exit(void)
+{
+ platform_driver_unregister(&serial_cortina_driver);
+ uart_unregister_driver(&cortina_uart_driver);
+}
+
+module_init(cortina_uart_init);
+module_exit(cortina_uart_exit);
+
+MODULE_AUTHOR("Cortina-Access Inc.");
+MODULE_DESCRIPTION("Cortina-Access UART driver");
+MODULE_LICENSE("GPL");
--
2.39.5
^ permalink raw reply related
* [PATCH 1/3] dt-bindings: serial: Add binding for Cortina-Access UART
From: Jason Li @ 2026-06-10 11:28 UTC (permalink / raw)
To: jason.li, Greg Kroah-Hartman, Jiri Slaby
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Catalin Marinas,
Will Deacon, Arnd Bergmann, linux-serial, linux-arm-kernel,
devicetree, linux-kernel
In-Reply-To: <20260610112821.3030099-1-jason.li@cortina-access.com>
Add DT binding schema for the Cortina-Access UART controller.
This IP is integrated into most CAXXXX SoC family members.
Also add the vendor prefix for Cortina Access, Inc. and the
top-level ARM board binding document for the CA8289 (Venus) SoC.
Signed-off-by: Jason Li <jason.li@cortina-access.com>
Assisted-by: Claude:claude-opus-4-8
---
.../bindings/arm/cortina-access.yaml | 29 ++++++++++++
.../serial/cortina-access,serial.yaml | 46 +++++++++++++++++++
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 7 +++
4 files changed, 84 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/cortina-access.yaml
create mode 100644 Documentation/devicetree/bindings/serial/cortina-access,serial.yaml
diff --git a/Documentation/devicetree/bindings/arm/cortina-access.yaml b/Documentation/devicetree/bindings/arm/cortina-access.yaml
new file mode 100644
index 000000000000..ec0320ed0c0b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cortina-access.yaml
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/cortina-access.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cortina-Access SoC boards
+
+maintainers:
+ - Jason Li <jason.li@cortina-access.com>
+
+description:
+ Boards based on Cortina-Access ARMv8 SoCs targeting networking and
+ access applications.
+
+properties:
+ $nodename:
+ const: /
+ compatible:
+ oneOf:
+ - description: Cortina-Access CA8289 (Venus) engineering board
+ const: cortina-access,ca8289-engboard
+
+ - description: Cortina-Access CA8289 (Venus) reference board
+ const: cortina-access,ca8289-refboard
+
+additionalProperties: true
+
+...
diff --git a/Documentation/devicetree/bindings/serial/cortina-access,serial.yaml b/Documentation/devicetree/bindings/serial/cortina-access,serial.yaml
new file mode 100644
index 000000000000..5d7fdd954491
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/cortina-access,serial.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/cortina-access,serial.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cortina-Access UART controller
+
+maintainers:
+ - Jason Li <jason.li@cortina-access.com>
+
+allOf:
+ - $ref: serial.yaml#
+
+properties:
+ compatible:
+ const: cortina-access,serial
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ serial@f4329188 {
+ compatible = "cortina-access,serial";
+ reg = <0 0xf4329188 0 0x30>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb_pclk>;
+ };
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index dd94c50e97f9..837e2a92e7e8 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -367,6 +367,8 @@ patternProperties:
description: Chengdu Corpro Technology Co., Ltd.
"^corechips,.*":
description: Shenzhen Corechips Microelectronics Co., Ltd.
+ "^cortina-access,.*":
+ description: Cortina Access, Inc.
"^cortina,.*":
description: Cortina Systems, Inc.
"^cosmic,.*":
diff --git a/MAINTAINERS b/MAINTAINERS
index 20bd55913b2d..cc261888fae0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2820,6 +2820,13 @@ F: tools/perf/tests/shell/lib/*coresight*
F: tools/perf/util/cs-etm-decoder/*
F: tools/perf/util/cs-etm.*
+ARM/CORTINA-ACCESS VENUS ARM ARCHITECTURE
+M: Jason Li <jason.li@cortina-access.com>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S: Maintained
+F: Documentation/devicetree/bindings/arm/cortina-access.yaml
+F: Documentation/devicetree/bindings/serial/cortina-access,serial.yaml
+
ARM/CORTINA SYSTEMS GEMINI ARM ARCHITECTURE
M: Hans Ulli Kroll <ulli.kroll@googlemail.com>
M: Linus Walleij <linusw@kernel.org>
--
2.39.5
^ permalink raw reply related
* [PATCH 0/3] tty: serial: Add Cortina-Access UART driver and platform support
From: Jason Li @ 2026-06-10 11:28 UTC (permalink / raw)
To: jason.li, Greg Kroah-Hartman, Jiri Slaby
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Catalin Marinas,
Will Deacon, Arnd Bergmann, linux-serial, linux-arm-kernel,
devicetree, linux-kernel
In-Reply-To: <20260610112821.3030099-1-jason.li@cortina-access.com>
This series adds Linux kernel support for the UART controller integrated
in Cortina-Access SoCs, with CA8289 (Venus) as the first supported device.
Patch 1 adds the DT binding schema for the UART controller and the
top-level ARM board binding document for the Cortina-Access SoC family,
along with the vendor prefix.
Patch 2 introduces the serial driver (serial_cortina-access.c). The
UART IP has a simple FIFO-based design with a single interrupt line.
The driver uses uart_port_tx() for TX, handles earlycon initialisation
when the bootloader leaves the UART disabled, and provides a TX FIFO
kick-start in start_tx() to work around edge-triggered interrupt
behaviour. Clock frequency is obtained exclusively via the clk
framework.
Patch 3 adds the device tree sources for the CA8289 SoC and its
engineering board, covering the minimal hardware description needed to
boot a kernel with an INITRD rootfs.
Tested on CA8289 engineering board; console and earlycon both verified
at 115200 baud.
Jason Li (3):
dt-bindings: serial: Add binding for Cortina-Access UART
tty: serial: Add UART driver for Cortina-Access platform
arm64: dts: cortina-access: Add DTS for CA8289 SoC and Venus board
.../bindings/arm/cortina-access.yaml | 29 +
.../serial/cortina-access,serial.yaml | 46 ++
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 14 +
arch/arm64/Kconfig.platforms | 10 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/cortina-access/Makefile | 2 +
.../dts/cortina-access/ca8289-engboard.dts | 31 +
.../boot/dts/cortina-access/ca8289-soc.dtsi | 118 +++
drivers/tty/serial/Kconfig | 21 +
drivers/tty/serial/Makefile | 1 +
drivers/tty/serial/serial_cortina-access.c | 755 ++++++++++++++++++
12 files changed, 1030 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/cortina-access.yaml
create mode 100644 Documentation/devicetree/bindings/serial/cortina-access,serial.yaml
create mode 100644 arch/arm64/boot/dts/cortina-access/Makefile
create mode 100644 arch/arm64/boot/dts/cortina-access/ca8289-engboard.dts
create mode 100644 arch/arm64/boot/dts/cortina-access/ca8289-soc.dtsi
create mode 100644 drivers/tty/serial/serial_cortina-access.c
--
2.39.5
^ permalink raw reply
* [PATCH 0/3] tty: serial: Add Cortina-Access UART driver and platform support
From: Jason Li @ 2026-06-10 11:28 UTC (permalink / raw)
To: jason.li, Greg Kroah-Hartman, Jiri Slaby
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Catalin Marinas,
Will Deacon, Arnd Bergmann, linux-serial, linux-arm-kernel,
devicetree, linux-kernel
Patch 1 adds the DT binding schema for the UART controller and the
top-level ARM board binding document for the Cortina-Access SoC family,
along with the vendor prefix.
Patch 2 introduces the serial driver (serial_cortina-access.c). The
UART IP has a simple FIFO-based design with a single interrupt line.
The driver uses uart_port_tx() for TX, handles earlycon initialisation
when the bootloader leaves the UART disabled, and provides a TX FIFO
kick-start in start_tx() to work around edge-triggered interrupt
behaviour. Clock frequency is obtained exclusively via the clk
framework.
Patch 3 adds the device tree sources for the CA8289 SoC and its
engineering board, covering the minimal hardware description needed to
boot a kernel with an INITRD rootfs.
Tested on CA8289 engineering board; console and earlycon both verified
at 115200 baud.
Any feedback or comments are highly appreciated.
Jason Li (3):
dt-bindings: serial: Add binding for Cortina-Access UART
tty: serial: Add UART driver for Cortina-Access platform
arm64: dts: cortina-access: Add DTS for CA8289 SoC and Venus board
.../bindings/arm/cortina-access.yaml | 29 +
.../serial/cortina-access,serial.yaml | 46 ++
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 14 +
arch/arm64/Kconfig.platforms | 10 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/cortina-access/Makefile | 2 +
.../dts/cortina-access/ca8289-engboard.dts | 31 +
.../boot/dts/cortina-access/ca8289-soc.dtsi | 118 +++
drivers/tty/serial/Kconfig | 21 +
drivers/tty/serial/Makefile | 1 +
drivers/tty/serial/serial_cortina-access.c | 755 ++++++++++++++++++
12 files changed, 1030 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/cortina-access.yaml
create mode 100644 Documentation/devicetree/bindings/serial/cortina-access,serial.yaml
create mode 100644 arch/arm64/boot/dts/cortina-access/Makefile
create mode 100644 arch/arm64/boot/dts/cortina-access/ca8289-engboard.dts
create mode 100644 arch/arm64/boot/dts/cortina-access/ca8289-soc.dtsi
create mode 100644 drivers/tty/serial/serial_cortina-access.c
--
2.39.5
^ permalink raw reply
* Re: [PATCH 3/4] arm64: dts: qcom: Add SD Card support for Glymur SoC
From: sashiko-bot @ 2026-06-10 11:26 UTC (permalink / raw)
To: Monish Chunara; +Cc: conor+dt, devicetree, robh
In-Reply-To: <20260610111508.3941207-4-mchunara@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Missing `resets` hardware reset property for the `sdhc_2` node
--
commit 3328d962d23c195e0ded6a5fa736fc357bc968ef
Author: Monish Chunara <monish.chunara@oss.qualcomm.com>
arm64: dts: qcom: Add SD Card support for Glymur SoC
This commit adds support for the SD card on the Glymur SoC and enables
the required pinctrl configurations.
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index 20b49af7298e9..0989fe39e7ef7 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
[ ... ]
> @@ -3927,6 +3927,57 @@ lpass_ag_noc: interconnect@7e40000 {
> #interconnect-cells = <2>;
> };
>
> + sdhc_2: mmc@8804000 {
> + compatible = "qcom,glymur-sdhci", "qcom,sdhci-msm-v5";
> +
[Severity: Medium]
Should this node include the resets = <&gcc GCC_SDCC2_BCR>; property?
The SDHCI-MSM driver typically uses the core_reset (fetched via the resets
device tree property) to explicitly reset the SDHC hardware block during probe,
ensuring it is in a clean and known state.
Although the driver requests the reset as optional, omitting it means the
kernel cannot reset the controller. Could this lead to unpredictable controller
behavior or probe failures if the bootloader leaves the block in an
inconsistent state?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260610111508.3941207-1-mchunara@oss.qualcomm.com?part=3
^ permalink raw reply
* Re: [PATCH v6 2/2] ARM: dts: aspeed: ventura2: Add Meta ventura2 BMC
From: Andrew Jeffery @ 2026-06-10 11:22 UTC (permalink / raw)
To: Kyle Hsieh, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel
In-Reply-To: <20260610-ventura2_initial_dts-v6-2-375d8e9d7ebf@gmail.com>
Hi Kyle,
On Wed, 2026-06-10 at 09:22 +0800, Kyle Hsieh wrote:
> Add linux device tree entry related to the Meta(Facebook) rmc-node.
> The system uses an AT2600 BMC.
> This node is named "ventura2".
>
> Signed-off-by: Kyle Hsieh <kylehsieh1995@gmail.com>
I have some comments on v5 that are applicable here too.
https://lore.kernel.org/all/3d56889c004fc2d11b76ace6033c7ccfb8a37d03.camel@codeconstruct.com.au/
Andrew
^ permalink raw reply
* Re: [PATCH 2/2] riscv: dts: sophgo: Add Milk-V Duo 256M board support
From: sashiko-bot @ 2026-06-10 11:19 UTC (permalink / raw)
To: Chen-Yu Yeh; +Cc: devicetree, robh, conor+dt
In-Reply-To: <20260610111136.1514155-2-chenyou910331@gmail.com>
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [Low] The device tree references a non-existent `&porte` phandle, which will cause a fatal `dtc` compilation error.
- [Low] The device tree references a non-existent `&usb` phandle, which will cause a fatal `dtc` compilation error.
- [Low] An unnecessary trailing blank line is added to the Makefile.
--
commit 789d472cb56d573e2ba1106b883551407093dd43
Author: Chen-Yu Yeh <chenyou910331@gmail.com>
riscv: dts: sophgo: Add Milk-V Duo 256M board support
This commit adds basic device tree support for the Milk-V Duo 256M board,
based on the Sophgo SG2002 SoC. It configures the UART console, SD/MMC
controller, USB host, and a status LED.
> diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
> index 6f65526d4193b..e49c8233ae1ff 100644
> --- a/arch/riscv/boot/dts/sophgo/Makefile
> +++ b/arch/riscv/boot/dts/sophgo/Makefile
[ ... ]
> @@ -2,7 +2,9 @@
> dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb
> +dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-milkv-duo256m.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v1.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v2.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += sg2044-sophgo-srd3-10.dtb
> +
[Severity: Low]
This isn't a bug, but is this trailing blank line intended? It adds
unnecessary whitespace at the end of the Makefile.
> diff --git a/arch/riscv/boot/dts/sophgo/sg2002-milkv-duo256m.dts b/arch/riscv/boot/dts/sophgo/sg2002-milkv-duo256m.dts
> new file mode 100644
> index 0000000000000..882fba441396b
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/sg2002-milkv-duo256m.dts
[ ... ]
> + leds {
> + compatible = "gpio-leds";
> +
> + led-blue {
> + label = "milkv:blue:status";
> + gpios = <&porte 2 GPIO_ACTIVE_HIGH>;
[Severity: Low]
Will this compile successfully? It appears the porte phandle is not yet
defined in the parent dtsi files, which would cause a fatal dtc compilation
error.
[ ... ]
> +&uart0 {
> + pinctrl-0 = <&uart0_cfg>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&usb {
> + dr_mode = "host";
> + status = "okay";
> +};
[Severity: Low]
Similar to the porte phandle above, is the usb label defined in the
parent SoC dtsi files? Overriding an undefined label will also cause a
dtc build failure.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260610111136.1514155-1-chenyou910331@gmail.com?part=2
^ permalink raw reply
* Re: [PATCH 2/4] dt-bindings: mmc: sdhci-msm: Document the Glymur compatible
From: Krzysztof Kozlowski @ 2026-06-10 11:17 UTC (permalink / raw)
To: Monish Chunara, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Nitin Rawat, Pradeep Pragallapati, Komal Bajaj, Sachin,
linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260610111508.3941207-3-mchunara@oss.qualcomm.com>
On 10/06/2026 13:15, Monish Chunara wrote:
> From: Monish Chunara <monish.chunara@oss.qualcomm.com>
>
> Document the Glymur-specific SDHCI compatible in the sdhci-msm binding.
> Use "qcom,sdhci-msm-v5" as the fallback compatible for the MSM SDHCI v5
> controller used on Glymur.
Same questions as always... why? Don't explain what you did. Explain why
you did that way.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH v3 2/2] phy: qcom-qmp-pcie: Add support for ipq5210 PCIe phys
From: Varadarajan Narayanan @ 2026-06-10 11:16 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel,
Varadarajan Narayanan
In-Reply-To: <20260610-pcie-phy-v3-0-334011b378d6@oss.qualcomm.com>
Add support for a PCIe phys found on Qualcomm ipq5210 platform.
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 129 +++++++++++++++++++++++++++++++
1 file changed, 129 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 75afbd15aaf4..2bf00e0e125a 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -514,6 +514,89 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
};
+static const struct qmp_phy_init_tbl ipq5210_gen3x1_pcie_ep_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x23),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x23),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x10),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x10),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x19),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xfe),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xfe),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x10),
+};
+
+static const struct qmp_phy_init_tbl ipq5210_gen3x1_pcie_ep_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
+};
+
+static const struct qmp_phy_init_tbl ipq5210_gen3x1_pcie_ep_pcs_misc_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x04),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG1, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG4, 0xff),
+};
+
static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
@@ -3613,6 +3696,49 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
.phy_status = PHYSTATUS,
};
+static const struct qmp_phy_cfg ipq5210_gen3x1_pciephy_cfg = {
+ .lanes = 1,
+
+ .offsets = &qmp_pcie_offsets_v4x1,
+
+ .tbls = {
+ .serdes = ipq9574_gen3x1_pcie_serdes_tbl,
+ .serdes_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_serdes_tbl),
+ .tx = ipq8074_pcie_gen3_tx_tbl,
+ .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
+ .rx = ipq9574_pcie_rx_tbl,
+ .rx_num = ARRAY_SIZE(ipq9574_pcie_rx_tbl),
+ .pcs = ipq9574_gen3x1_pcie_pcs_tbl,
+ .pcs_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_tbl),
+ .pcs_misc = ipq9574_gen3x1_pcie_pcs_misc_tbl,
+ .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_misc_tbl),
+ },
+
+ .tbls_ep = &(const struct qmp_phy_cfg_tbls) {
+ .serdes = ipq5210_gen3x1_pcie_ep_serdes_tbl,
+ .serdes_num = ARRAY_SIZE(ipq5210_gen3x1_pcie_ep_serdes_tbl),
+ .tx = ipq6018_pcie_tx_tbl,
+ .tx_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
+ .rx = ipq5210_gen3x1_pcie_ep_rx_tbl,
+ .rx_num = ARRAY_SIZE(ipq5210_gen3x1_pcie_ep_rx_tbl),
+ .pcs = ipq6018_pcie_pcs_tbl,
+ .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
+ .pcs_misc = ipq5210_gen3x1_pcie_ep_pcs_misc_tbl,
+ .pcs_misc_num = ARRAY_SIZE(ipq5210_gen3x1_pcie_ep_pcs_misc_tbl),
+ },
+
+ .reset_list = ipq8074_pciephy_reset_l,
+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
+ .vreg_list = NULL,
+ .num_vregs = 0,
+ .regs = pciephy_v4_regs_layout,
+
+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+ .phy_status = PHYSTATUS,
+
+ .pipe_clock_rate = 250000000,
+};
+
static const struct qmp_phy_cfg ipq9574_gen3x1_pciephy_cfg = {
.lanes = 1,
@@ -5404,6 +5530,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = {
}, {
.compatible = "qcom,glymur-qmp-gen5x4-pcie-phy",
.data = &glymur_qmp_gen5x4_pciephy_cfg,
+ }, {
+ .compatible = "qcom,ipq5210-qmp-gen3x1-pcie-phy",
+ .data = &ipq5210_gen3x1_pciephy_cfg,
}, {
.compatible = "qcom,ipq6018-qmp-pcie-phy",
.data = &ipq6018_pciephy_cfg,
--
2.34.1
^ permalink raw reply related
* [PATCH v3 1/2] dt-bindings: phy: qcom,ipq8074-qmp-pcie: Document the ipq5210 QMP PCIe PHY
From: Varadarajan Narayanan @ 2026-06-10 11:16 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel,
Varadarajan Narayanan
In-Reply-To: <20260610-pcie-phy-v3-0-334011b378d6@oss.qualcomm.com>
Document the PCIe phys on the ipq5210 platform. The 2 lane phy uses the
ipq9574 as fallback. The single lane phy is documented separately.
The ipq5210 has one dual lane and one single lane PCIe phy.
The dual lane phy is similar to the dual lane phy present in ipq9574. Hence
qcom,ipq5210-qmp-gen3x2-pcie-phy is documented with ipq9574's dual lane phy
as fallback compatible.
The single lane phy (qcom,ipq5210-qmp-gen3x1-pcie-phy) is documented as
specific compatible.
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
---
Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
index f60804687412..fc155ad5fa6d 100644
--- a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
@@ -17,6 +17,7 @@ properties:
compatible:
oneOf:
- enum:
+ - qcom,ipq5210-qmp-gen3x1-pcie-phy
- qcom,ipq6018-qmp-pcie-phy
- qcom,ipq8074-qmp-gen3-pcie-phy
- qcom,ipq8074-qmp-pcie-phy
@@ -28,6 +29,7 @@ properties:
- const: qcom,ipq9574-qmp-gen3x1-pcie-phy
- items:
- enum:
+ - qcom,ipq5210-qmp-gen3x2-pcie-phy
- qcom,ipq5424-qmp-gen3x2-pcie-phy
- const: qcom,ipq9574-qmp-gen3x2-pcie-phy
--
2.34.1
^ permalink raw reply related
* [PATCH v3 0/2] Enable the QMP PCIe PHY present in Qualcomm ipq5210 SoC
From: Varadarajan Narayanan @ 2026-06-10 11:16 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel,
Varadarajan Narayanan
Document the bindings and update the driver to support
the PCIe phy present in Qualcomm ipq5210 SoC.
v3: Fix commit message for the bindings patch
Remove unused tables from the phy driver (ipq5210_gen3x1_pcie_ep_tx_tbl
and ipq5210_gen3x1_pcie_ep_pcs_tbl)
v2: https://lore.kernel.org/r/20260609-pcie-phy-v2-0-83bc80e79fa6@oss.qualcomm.com
Had incorrectly made both the phys as fallback. The single
lane phy is standalone and double lane uses ipq9574 as
fallback.
v1: https://lore.kernel.org/linux-arm-msm/20260514-pci-phy-v1-0-482429192746@oss.qualcomm.com/
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
---
Varadarajan Narayanan (2):
dt-bindings: phy: qcom,ipq8074-qmp-pcie: Document the ipq5210 QMP PCIe PHY
phy: qcom-qmp-pcie: Add support for ipq5210 PCIe phys
.../bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml | 2 +
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 129 +++++++++++++++++++++
2 files changed, 131 insertions(+)
---
base-commit: a87737435cfa134f9cdcc696ba3080759d04cf72
change-id: 20260609-pcie-phy-99fcf91a02fd
prerequisite-change-id: 20260514-icc-ipq5210-0ab03f3a3e83:v1
prerequisite-patch-id: 0b6145b6635b18fe79fbbff5815041b43778c5ed
prerequisite-patch-id: 924c6ff7baf4283ac7991ee94c803a00fc5cece4
prerequisite-patch-id: c2fe1800fe769dccd37f94c19860a07f979e3c4c
Best regards,
--
Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH] dt-bindings: iio: accel: Convert lis302 binding to YAML schema
From: sashiko-bot @ 2026-06-10 11:16 UTC (permalink / raw)
To: Md Shofiqul Islam; +Cc: conor+dt, robh, devicetree
In-Reply-To: <20260610110051.1228-1-shofiqtest@gmail.com>
Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [Medium] DT Binding ABI Break (Validation Regression) due to missing legacy property names
- [Medium] DT Schema Validation Regression for Compatible Strings (Array Format)
- [Medium] Architectural Conflict with Overlapping Bindings
- [Medium] Hardware Description Constraint Violation (`interrupts` property)
--
commit 32ffb2a415040f6cd59db09f02686f031f4414c1
Author: Md Shofiqul Islam <shofiqtest@gmail.com>
dt-bindings: iio: accel: Convert lis302 binding to YAML schema
Convert the STMicroelectronics LIS302DL/LIS3LV02D accelerometer device
tree binding from plain text format to YAML schema format.
> diff --git a/Documentation/devicetree/bindings/iio/accel/st,lis302dl.yaml b/Documentation/devicetree/bindings/iio/accel/st,lis302dl.yaml
> new file mode 100644
> index 0000000000000..befc419f7f397
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/accel/st,lis302dl.yaml
> @@ -0,0 +1,343 @@
[ ... ]
> +properties:
> + compatible:
> + enum:
> + - st,lis302dl-spi
> + - st,lis3lv02d
[Severity: Medium]
Will this strict enum definition cause a schema validation regression
by rejecting existing in-tree device trees that use a fallback list? Some
boards use an array format like compatible = "st,lis331dlh", "st,lis3lv02d";.
Could this be described using items and an enum instead so these arrays
are allowed?
[Severity: Medium]
These compatible strings are already documented and matched in
Documentation/devicetree/bindings/iio/st,st-sensors.yaml. Since
st,st-sensors.yaml uses additionalProperties: false, won't any node using
these compatibles fail dual-schema evaluation when properties like
st,click-single-x or Vdd-supply are evaluated by the other schema?
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
[Severity: Medium]
The hardware has two physical interrupt pins, which is reflected in the
routing properties defined below like st,irq1-click and st,irq2-click.
Does enforcing maxItems: 1 here cause validation failures on existing
valid boards that wire both interrupts?
[ ... ]
> + st,click-double-z:
> + type: boolean
> + description: Enable double-click detection on Z axis.
> +
> + st,click-threshold-x:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: Click detection threshold for X axis.
[Severity: Medium]
Since unevaluatedProperties: false is set at the end of the schema, could
defining strict new property names without supporting the legacy names
(st,click-thresh-x and st,click-click-time-limit) cause a regression in
dtbs_check validation for existing in-tree device trees that still use
the older names?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260610110051.1228-1-shofiqtest@gmail.com?part=1
^ permalink raw reply
* [PATCH 4/4] arm64: dts: qcom: Enable SD card for Glymur CRD
From: Monish Chunara @ 2026-06-10 11:15 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Nitin Rawat, Pradeep Pragallapati, Komal Bajaj, Sachin,
Monish Chunara, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260610111508.3941207-1-mchunara@oss.qualcomm.com>
From: Monish Chunara <monish.chunara@oss.qualcomm.com>
Enable SD card for Glymur CRD platform. Configure the vmmc/vqmmc
regulators and gpio-based card detection for the platform.
Co-developed-by: Sachin <ssachin@qti.qualcomm.com>
Signed-off-by: Sachin <ssachin@qti.qualcomm.com>
Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur-crd.dts | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
index c98dfb3941fa..f68d27429440 100644
--- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
@@ -427,3 +427,28 @@ &usb_mp_qmpphy1 {
status = "okay";
};
+
+&sdhc_2 {
+ vmmc-supply = <&vreg_l9b_e0_2p9>;
+ vqmmc-supply = <&vreg_l2b_e0_2p9>;
+
+ pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep_state &sdc2_card_det_n>;
+ pinctrl-names = "default", "sleep";
+
+ cd-gpios = <&tlmm 221 GPIO_ACTIVE_LOW>;
+
+ no-mmc;
+ no-sdio;
+
+ status = "okay";
+};
+
+&tlmm {
+ sdc2_card_det_n: sd-card-det-n-state {
+ pins = "gpio221";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
--
2.34.1
^ permalink raw reply related
* [PATCH 3/4] arm64: dts: qcom: Add SD Card support for Glymur SoC
From: Monish Chunara @ 2026-06-10 11:15 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Nitin Rawat, Pradeep Pragallapati, Komal Bajaj, Sachin,
Monish Chunara, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260610111508.3941207-1-mchunara@oss.qualcomm.com>
From: Monish Chunara <monish.chunara@oss.qualcomm.com>
Add support for SD card on Glymur SoC and enable the required pinctrl
configurations.
Co-developed-by: Sachin <ssachin@qti.qualcomm.com>
Signed-off-by: Sachin <ssachin@qti.qualcomm.com>
Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 91 ++++++++++++++++++++++++++++
1 file changed, 91 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index 20b49af7298e..0989fe39e7ef 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -3927,6 +3927,57 @@ lpass_ag_noc: interconnect@7e40000 {
#interconnect-cells = <2>;
};
+ sdhc_2: mmc@8804000 {
+ compatible = "qcom,glymur-sdhci", "qcom,sdhci-msm-v5";
+
+ reg = <0x0 0x08804000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq",
+ "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface",
+ "core",
+ "xo";
+
+ iommus = <&apps_smmu 0xd00 0>;
+ qcom,dll-config = <0x0007442c>;
+ qcom,ddr-config = <0x80040868>;
+
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
+
+ interconnects = <&aggre3_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "sdhc-ddr",
+ "cpu-sdhc";
+
+ bus-width = <4>;
+ dma-coherent;
+
+ status = "disabled";
+
+ sdhc2_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
usb_2_hsphy: phy@88e0000 {
compatible = "qcom,glymur-m31-eusb2-phy",
"qcom,sm8750-m31-eusb2-phy";
@@ -5714,6 +5765,46 @@ rx-pins {
bias-disable;
};
};
+
+ sdc2_default_state: sdc2-default-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_sleep_state: sdc2-sleep-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
};
stm: stm@10002000 {
--
2.34.1
^ permalink raw reply related
* [PATCH 2/4] dt-bindings: mmc: sdhci-msm: Document the Glymur compatible
From: Monish Chunara @ 2026-06-10 11:15 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Nitin Rawat, Pradeep Pragallapati, Komal Bajaj, Sachin,
Monish Chunara, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260610111508.3941207-1-mchunara@oss.qualcomm.com>
From: Monish Chunara <monish.chunara@oss.qualcomm.com>
Document the Glymur-specific SDHCI compatible in the sdhci-msm binding.
Use "qcom,sdhci-msm-v5" as the fallback compatible for the MSM SDHCI v5
controller used on Glymur.
Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com>
---
Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml
index bd558a11b792..6a8ef84617a9 100644
--- a/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml
+++ b/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml
@@ -38,6 +38,7 @@ properties:
- items:
- enum:
- qcom,eliza-sdhci
+ - qcom,glymur-sdhci
- qcom,hawi-sdhci
- qcom,ipq5018-sdhci
- qcom,ipq5210-sdhci
--
2.34.1
^ permalink raw reply related
* [PATCH 1/4] arm64: dts: qcom: glymur-crd: Update VREG l2b_e0 and l9b_e0 voltage for SD-card
From: Monish Chunara @ 2026-06-10 11:15 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Nitin Rawat, Pradeep Pragallapati, Komal Bajaj, Sachin,
Monish Chunara, linux-arm-msm, devicetree, linux-kernel,
Kamal Wadhwa
In-Reply-To: <20260610111508.3941207-1-mchunara@oss.qualcomm.com>
From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
SD cards may need 1.8v VDDIO also to be supported, to accommodate this
requirement reduce the min voltage to 1.8v for `vreg_l2b_e0` which
supplies to VDDIO pin of SD card.
NOTE - Since this SD card is the only client on this regulator, this
change should not have any side effect on any other clients.
moreover, SD card driver takes care to explicitly vote for the
regulator voltage based on the SD card detection sequence.
Also for stable operation of the SD card increase VDD voltage
supplied by `vreg_l9b_e0` to 2.96v.
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
index e784b538f42e..af6f42cdd39a 100644
--- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
@@ -228,7 +228,7 @@ vreg_l1b_e0_1p8: ldo1 {
vreg_l2b_e0_2p9: ldo2 {
regulator-name = "vreg_l2b_e0_2p9";
- regulator-min-microvolt = <2904000>;
+ regulator-min-microvolt = <1804000>;
regulator-max-microvolt = <2904000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
@@ -247,10 +247,10 @@ vreg_l8b_e0_1p50: ldo8 {
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
- vreg_l9b_e0_2p7: ldo9 {
- regulator-name = "vreg_l9b_e0_2p7";
- regulator-min-microvolt = <2704000>;
- regulator-max-microvolt = <2704000>;
+ vreg_l9b_e0_2p9: ldo9 {
+ regulator-name = "vreg_l9b_e0_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
--
2.34.1
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox