* Re: [PATCH v4 03/12] i3c: master: Support ACPI enumeration of child devices
From: Frank Li @ 2026-06-18 19:53 UTC (permalink / raw)
To: sashiko-reviews
Cc: Akhil R, linux-hwmon, conor+dt, linux-i3c, Frank.Li, devicetree,
robh
In-Reply-To: <20260616101515.34CA61F000E9@smtp.kernel.org>
On Tue, Jun 16, 2026 at 10:15:14AM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] devm_kzalloc allocated 'boardinfo' is leaked for every ACPI child node that is ignored because it lacks I2C/I3C resources.
> --
>
> commit 9a388c2056a553d628ce4b8b623a812d4aa08951
> Author: Akhil R <akhilrajeev@nvidia.com>
>
> i3c: master: Support ACPI enumeration of child devices
>
> This commit adds support for describing I3C and I2C devices via ACPI tables,
> rather than relying solely on the device tree reg property. It implements
> reading _ADR and LVR properties from ACPI resources to retrieve the static
> address and other device properties.
>
> > diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c
> > index 3b19a5e8f46d0..f0e05bcac26da 100644
> > --- a/drivers/i3c/master.c
> > +++ b/drivers/i3c/master.c
>
> [ ... ]
>
> > @@ -2708,6 +2762,74 @@ static int i3c_master_add_dev(struct i3c_master_controller *master,
> > return ret;
> > }
> >
> > +#ifdef CONFIG_ACPI
> > +static int i3c_master_add_acpi_dev(struct i3c_master_controller *master,
> > + struct fwnode_handle *fwnode)
> > +{
> > + struct acpi_device *adev = to_acpi_device_node(fwnode);
> > + acpi_bus_address adr;
> > + u32 reg[3] = { 0 };
> > + int ret;
> > +
> > + /*
> > + * If the ACPI table entry has _ADR method, it's an I3C device.
> > + * Otherwise it may be an I2C device described by an I2cSerialBus
> > + * resource. If no I2cSerialBus resource is found, ignore the entry.
> > + */
> > + if (!acpi_has_method(adev->handle, "_ADR")) {
> > + ret = i3c_master_add_i2c_boardinfo(master, fwnode, reg);
> > + if (ret == -ENODEV)
> > + return 0;
>
> [Severity: Medium]
> Does this leak the boardinfo allocated in i3c_master_add_i2c_boardinfo()?
>
> If an ACPI child lacks an _ADR method, i3c_master_add_i2c_boardinfo()
> unconditionally allocates boardinfo using devm_kzalloc().
>
> If the node also lacks an I2cSerialBus resource, i3c_acpi_add_i2c_boardinfo()
> returns -ENODEV. This causes i3c_master_add_i2c_boardinfo() to return -ENODEV
> without freeing the allocated boardinfo.
>
> Because we catch -ENODEV here and return 0, the overall bus probe continues
> and ultimately succeeds. This means the devres-allocated memory stays tied
> to the master device, leaking sizeof(struct i2c_dev_boardinfo) for every
> ignored ACPI child node.
Is it true?
Frank
>
> > +
> > + return ret;
> > + }
> > +
> > + adr = acpi_device_adr(adev);
>
> [ ... ]
>
> --
> Sashiko AI review · https://sashiko.dev/#/patchset/20260616095429.3947205-1-akhilrajeev@nvidia.com?part=3
^ permalink raw reply
* Re: [PATCH RFC v4 01/12] dt-bindings: clk: zte: Add zx297520v3 top clock and reset bindings
From: Conor Dooley @ 2026-06-18 19:54 UTC (permalink / raw)
To: Stefan Dösinger
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Brian Masney, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
In-Reply-To: <BXIzXc2sQ5SGynZ1chd-pw@gmail.com>
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On Thu, Jun 18, 2026 at 09:59:00PM +0300, Stefan Dösinger wrote:
> Am Donnerstag, 18. Juni 2026, 00:23:56 Ostafrikanische Zeit schrieben Sie:
>
> > Do you actually need an aux bus here though? Since you have to add
> > simple-mfd for your the syscon-reboot and simple-mfd is a real bus, can you
> > set the reset controller up with an mfd_cell + devm_mfd_add_devices()
> > instead?
>
> I'll have to read up on devm_mfd_add_devices; The aux bus was the suggestion
> of Philipp Zabel. At first sight it sounds to me like they do fairly similar
> things. I don't see any precedence for [devm_]mfd_add_devices in drivers/clk/.
I think you don't see it because the driver calling mfd_add_devices()
probably isn't in drivers/clk and probably also uses an mfd_cell for the
clock.
There's some in drivers/soc and some in drivers/mfd (I'll be honest and
admit to not knowing what actually drives the placement of the mfd
driver).
I think aux bus makes perfect sense when you have a clock/reset
controller, but once you start expanding past that and you have reboot
or hwmon or hwspinlock then mfd starts to make sense.
>
> Whatever way I go I'd like to use the same for all 3 clock/reset controllers.
> So far I only made topclk a simple-mfd. I recently stumbled upon spinlock
> registers in matrixclk, so I guess I can justify a simple-mfd there too. For
Just to note, simple-mfd is used when you have child nodes. You don't
need simple-mfd if a device fills multiple roles but doesn't have
children.
Your hwspinlock may not require a child node at all, you can just put
#hwlock-cells into the main node and use mfd_add_devices().
You'd then have topclock that is a syscon + simple-mfd, matrixclk that is
a syscon and lsp that's using the aux bus. The topclock and matrixclock
would have dedicated and trivial drivers somewhere that have the mfd_cells
and call mfd_add_devices(). The fact that topclock would be a simple-mfd
has basically no impact - I think the difference is that topclock will
call of_platform_populate() where matrixclk will not.
Probably the compatibles you've chosen start to make less sense at this
point though, but probably "topclk" and "matrixclk" are not what the
documentation for this device calls these register regions?
> lspclk all I can see is clocks and resets and I ran out of unknown registers
> in there.
I think the priority is having something that reflects the hardware
accurately, I wouldn't compromise on that just to have the same design
for all three drivers.
I guess the problem you have is that the reset driver is shared? You can
always have more than one way to probe a driver. Because I messed up
stuff in the past, reset-mpfs.c has both aux bus and mfd probing in it,
which could serve as an example for how to have both in one file.
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^ permalink raw reply
* Re: [PATCH v2 03/10] tests: asm: Introduce treehdr_vers macro
From: Herve Codina @ 2026-06-18 19:55 UTC (permalink / raw)
To: David Gibson
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ayush Singh,
Geert Uytterhoeven, devicetree-compiler, devicetree, linux-kernel,
devicetree-spec, Hui Pu, Ian Ray, Luca Ceresoli, Thomas Petazzoni
In-Reply-To: <ajPFLjQ96nmsPLp2@zatzit>
Hi David,
On Thu, 18 Jun 2026 20:15:10 +1000
David Gibson <david@gibson.dropbear.id.au> wrote:
> On Thu, Apr 09, 2026 at 01:54:19PM +0200, Herve Codina wrote:
> > tree.S is used to generate custom dtbs. It uses the treehdr macro to
> > build the header part.
> >
> > The current definition of this macro doesn't allow to set custom
> > settings related to version fields.
> >
> > In order to easily generate some dtb with custom version values without
> > duplicating the full header computation, introduce the treehdr_vers
> > macro.
> >
> > The modification doesn't introduce any functional changes.
> >
> > Signed-off-by: Herve Codina <herve.codina@bootlin.com>
>
> I just killed the not-very-portable trees.S in the main git tree, so
> this will need reworking for the new treegen.c system.
Killing trees.S has been a good idea.
Even if it implies more work on my side, I can only agree with this
decision.
Best regards,
Hervé
^ permalink raw reply
* Re: [PATCH v4 04/12] i3c: master: Add support for devices using SETAASA
From: Frank Li @ 2026-06-18 20:00 UTC (permalink / raw)
To: sashiko-reviews
Cc: Akhil R, robh, Frank.Li, linux-i3c, devicetree, linux-hwmon,
conor+dt
In-Reply-To: <20260616101919.299491F000E9@smtp.kernel.org>
On Tue, Jun 16, 2026 at 10:19:18AM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
>
> New issues:
> - [High] Missing CCC command whitelisting in I3C master drivers causes entire bus initialization to fail.
> - [High] Premature SETAASA broadcast preempts and breaks SETDASA initialization.
> - [High] Missing physical device address reset (RSTDAA) on SETAASA attach failure allows address collisions.
>
> Pre-existing issues:
> - [High] Bypassing PID validation allows duplicate PIDs, triggering a pre-existing Use-After-Free during teardown.
> --
>
> commit ef82dd52670ca8654bff7067823722f8e77933d1
> Author: Akhil R <akhilrajeev@nvidia.com>
>
> i3c: master: Add support for devices using SETAASA
>
> Add support for devices using SETAASA, such as SPD5118 and SPD5108
> attached to DDR5 memory modules that do not support ENTDAA. Follow the
> guidelines proposed by the MIPI Discovery and Configuration
> Specification [1] for discovering such devices.
>
> SETAASA (Set All Addresses to Static Address) differs from standard I3C
> address assignment that uses ENTDAA or SETDASA to assign dynamic
> addresses. Devices using SETAASA assign their pre-defined static addresses
> as their dynamic addresses during DAA, and it is not mandatory for these
> devices to implement standard CCC commands like GETPID, GETDCR, or GETBCR.
> For such devices, it is generally recommended to issue SETHID (specified
> by JEDEC JESD300) as a prerequisite for SETAASA to stop HID bit flipping.
>
> Link: https://www.mipi.org/mipi-disco-for-i3c-download
>
> > diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c
> > index f0e05bcac26da..557332d932576 100644
> > --- a/drivers/i3c/master.c
> > +++ b/drivers/i3c/master.c
>
> [ ... ]
>
> > @@ -1852,6 +1898,22 @@ static int i3c_master_early_i3c_dev_add(struct i3c_master_controller *master,
> > if (ret)
> > goto err_free_dev;
> >
> > + /*
> > + * For devices using SETAASA instead of ENTDAA, the address is statically
> > + * assigned. Update the dynamic address to the provided static address.
> > + * Reattach the I3C device after updating the dynamic address with the same
> > + * static address. It is not mandatory for such devices to implement CCC
> > + * commands like GETPID, GETDCR etc. Hence, we can return after reattaching.
> > + */
> > + if (i3cdev->boardinfo->static_addr_method & I3C_ADDR_METHOD_SETAASA) {
> > + i3cdev->info.dyn_addr = i3cdev->boardinfo->static_addr;
> > + ret = i3c_master_reattach_i3c_dev(i3cdev, 0);
> > + if (ret)
> > + goto err_detach_dev;
> ^^^^^^^^
>
> [Severity: High]
> Does skipping the physical device address reset (RSTDAA) here allow address
> collisions?
>
> If i3c_master_reattach_i3c_dev() fails for a SETAASA device, the code jumps to
> err_detach_dev. Unlike the SETDASA error path which jumps to err_rstdaa to
> issue a directed RSTDAA command and clear the dynamic address, this path
> leaves the physical device active at that address.
>
> Meanwhile, i3c_master_detach_i3c_dev() frees the address slot in the master's
> software state. During subsequent Dynamic Address Assignment (DAA), the master
> may assign this supposedly "free" address to another device, resulting in two
> physical devices responding to the same dynamic address.
Look AI correct, please check it.
Frank
>
> [ ... ]
>
> > @@ -2206,6 +2268,12 @@ static int i3c_master_bus_init(struct i3c_master_controller *master)
> > if (ret)
> > goto err_bus_cleanup;
> >
> > + if (master->addr_method & I3C_ADDR_METHOD_SETAASA) {
> > + ret = i3c_master_setaasa_locked(master);
> > + if (ret)
> > + goto err_bus_cleanup;
> > + }
> > +
>
> [Severity: High]
> Will this unconditional broadcast of SETAASA cause the entire bus initialization
> to fail on certain controllers?
>
> Several I3C master drivers (e.g., Cadence, SVC, Renesas) implement a strict
> whitelist via the supports_ccc_cmd callback. Because these whitelists were
> not updated to allow I3C_CCC_SETAASA (0x29) and I3C_CCC_VENDOR(0, true)
> (SETHID), the master driver returns -EOPNOTSUPP. This error propagates up
> through i3c_master_setaasa_locked(), causing i3c_master_bus_init() to
> immediately abort.
>
> [Severity: High]
> Does this premature SETAASA broadcast break SETDASA initialization?
>
> By broadcasting SETAASA before processing devices that require SETDASA:
>
> list_for_each_entry(i3cboardinfo, &master->boardinfo.i3c, node) {
> ...
> if (i3cboardinfo->static_addr)
> i3c_master_early_i3c_dev_add(master, i3cboardinfo);
> }
>
> any device with a static address will accept the broadcast and adopt its
> static address as its dynamic address. If a device was configured to use
> SETDASA, it will erroneously accept the SETAASA broadcast.
>
> When i3c_master_early_i3c_dev_add() subsequently attempts to issue the
> directed SETDASA command, the device already has an assigned dynamic address
> and will ignore the command. This causes the software state to desynchronize
> from the physical device state. The MIPI I3C spec explicitly mandates that
> SETDASA commands must be sent prior to the SETAASA command.
>
> > /*
> > * Reserve init_dyn_addr first, and then try to pre-assign dynamic
>
> [ ... ]
>
> > @@ -2724,6 +2799,9 @@ i3c_master_add_i3c_boardinfo(struct i3c_master_controller *master,
> > return -EINVAL;
> > }
> >
> > + /* Update the address methods required for device discovery */
> > + master->addr_method |= boardinfo->static_addr_method;
> > +
> > boardinfo->pid = ((u64)reg[1] << 32) | reg[2];
> >
> > if ((boardinfo->pid & GENMASK_ULL(63, 48)) ||
> ^^^^^^^^
>
> [Severity: High]
> This isn't a bug introduced by this patch, but does allowing duplicate PIDs
> (such as PID=0 for SETAASA devices) trigger a pre-existing Use-After-Free during
> teardown?
>
> Since SETAASA devices don't require standard CCC commands like GETPID,
> configuring multiple SETAASA devices with an identical dummy PID (like PID=0)
> passes the validation here.
>
> When i3c_master_register_new_i3c_devs() is called, dev_set_name() assigns
> identical sysfs names to these duplicate devices. device_register() then fails
> with -EEXIST. In the error path, put_device() is called, freeing desc->dev,
> but desc->dev is not set to NULL.
>
> During bus teardown in i3c_master_unregister_i3c_devs(), the core iterates
> over all devices, sees the non-NULL dangling pointer, and calls
> device_is_registered(&desc->dev->dev), leading to a Use-After-Free.
>
> --
> Sashiko AI review · https://sashiko.dev/#/patchset/20260616095429.3947205-1-akhilrajeev@nvidia.com?part=4
^ permalink raw reply
* Re: [PATCH] dt-bindings: spi: st,stm32-qspi: Add power-domains property
From: Mark Brown @ 2026-06-18 20:05 UTC (permalink / raw)
To: Patrice Chotard
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Christophe Kerello, linux-spi, devicetree,
linux-stm32, linux-arm-kernel, linux-kernel
In-Reply-To: <20260618-add_power_domain_for_qpsi-v1-1-4d7e57bcfb9a@foss.st.com>
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On Thu, Jun 18, 2026 at 08:46:35AM +0200, Patrice Chotard wrote:
> STM32 QSPI may be in a power domain. Allow a single 'power-domains'
> entry for STM32 QSPI.
Please submit patches using subject lines reflecting the style for the
subsystem, this makes it easier for people to identify relevant patches.
Look at what existing commits in the area you're changing are doing and
make sure your subject lines visually resemble what they're doing.
There's no need to resubmit to fix this alone.
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^ permalink raw reply
* Re: [PATCH v2 2/2] iio: magnetometer: add support for Melexis MLX90393
From: Nikhil Gautam @ 2026-06-18 20:22 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: linux-iio, jic23, dlechner, nuno.sa, andy, robh, krzk+dt,
conor+dt, devicetree, linux-kernel
In-Reply-To: <ajQpq1yzA-ig2c7s@monoceros>
On 18-06-2026 10:55 pm, Uwe Kleine-König wrote:
> Hello,
>
> On Thu, Jun 18, 2026 at 09:31:41PM +0530, Nikhil Gautam wrote:
> Please make that:
>
> { .name = "mlx90393" },
Thanks for pointing this out. I'll update it in v3.
> I guess you want
>
> .id_table = mlx90393_id,
Yes, that's correct. I'll add the missing .id_table entry in the next
version.
Thanks for the review!
Best regards,
Nikhil
^ permalink raw reply
* Re: [PATCH v2 0/2] iio: magnetometer: add support for Melexis MLX90393
From: Nikhil Gautam @ 2026-06-18 20:26 UTC (permalink / raw)
To: Andy Shevchenko
Cc: linux-iio, jic23, dlechner, nuno.sa, andy, robh, krzk+dt,
conor+dt, devicetree, linux-kernel
In-Reply-To: <ajQ_9uHMcTY2Hnmx@ashevche-desk.local>
On 19-06-2026 12:29 am, Andy Shevchenko wrote:
> On Thu, Jun 18, 2026 at 09:31:39PM +0530, Nikhil Gautam wrote:
>> Hi,
>>
>> This series adds initial Industrial I/O subsystem support for the
>> Melexis MLX90393 3-axis magnetometer and temperature sensor.
>>
>> The MLX90393 supports both I2C and SPI interfaces. This series
>> implements support for the I2C interface while keeping the driver
>> structure transport-independent to simplify future SPI support.
>>
>> Currently supported features:
>>
>> * Raw magnetic field measurements for X/Y/Z axes
>> * Raw temperature measurements
>> * Configurable gain/scale selection
>> * Configurable oversampling ratio
>> * Direct mode operation through the IIO subsystem
>> * I2C interface support
>>
>> The driver has been tested on Raspberry Pi 5 hardware using an
>> MLX90393 sensor connected over I2C. Magnetic field and temperature
>> measurements were verified through the IIO sysfs interface.
> This doesn't answer to two important questions:
> - why do we need a brand new driver?
> Can't one of the existing be updated to cover this HW?
>
> - where to find the datasheet? Any Links or other means to get it?
Hi Andy,
I looked at the existing magnetometer drivers in the IIO subsystem,
but none support the MLX90393 or a sufficiently similar register map and
command protocol.
The MLX90393 uses its own command-based interface and device-specific
configuration and conversion logic,
so extending an existing driver would require substantial changes with
little code reuse.
Therefore, I chose to implement it as a separate driver.
The datasheet is publicly available from Melexis:
Link:
https://media.melexis.com/-/media/files/documents/datasheets/mlx90393-datasheet-melexis.pdf
I'll include the datasheet link and clarify the rationale for introducing
a new driver in the cover letter of the next revision.
Thanks,
Nikhil
^ permalink raw reply
* Re: [PATCH v2 2/2] iio: magnetometer: add support for Melexis MLX90393
From: Nikhil Gautam @ 2026-06-18 21:06 UTC (permalink / raw)
To: Andy Shevchenko
Cc: linux-iio, jic23, dlechner, nuno.sa, andy, robh, krzk+dt,
conor+dt, devicetree, linux-kernel
In-Reply-To: <ajRGf0YT-fCZA1ih@ashevche-desk.local>
On 19-06-2026 12:56 am, Andy Shevchenko wrote:
> On Thu, Jun 18, 2026 at 09:31:41PM +0530, Nikhil Gautam wrote:
Hi Andy,
Thank you very much for taking the time to do such a thorough review of
this patch series.
Your detailed comments and suggestions are very helpful.
I'll address the issues you've pointed out, update the cover letter to
better explain the design decisions,
and incorporate the requested coding style and API changes in the next
revision.
I appreciate your review and feedback.
>> +config MLX90393
>> + tristate "MELEXIS MLX90393 3-axis magnetometer sensor"
>> + depends on I2C
> Why not a regmap?
The MLX90393 uses both register-based and command-based transactions.
Since regmap does not naturally model the command-based interface,
using it would require workarounds such as virtual registers or bypass
paths.
A custom transport abstraction is therefore simpler and better suited
for this device.
I already discussed this on thread, Link :
https://lore.kernel.org/linux-iio/20260423121834.4244-1-nikhilgtr@gmail.com/
>> +#ifndef MLX90393_H
>> +#define MLX90393_H
>>
>> +#include <linux/bitops.h>
>> +#include <linux/bits.h>
> Not required, it's covered by bitops.h.
Noted. Thanks
>> +#include <linux/types.h>
> ...
>
>> +#define MLX90393_MEASURE_ALL \
>> + (MLX90393_MEASURE_TEMP | MLX90393_MEASURE_X | \
>> + MLX90393_MEASURE_Y | MLX90393_MEASURE_Z)
> Split logically.
>
> #define MLX90393_MEASURE_ALL \
> (MLX90393_MEASURE_TEMP | \
> MLX90393_MEASURE_X | MLX90393_MEASURE_Y | MLX90393_MEASURE_Z)
>
> Or just a (long) single line.
Agreed. Thanks
>> + int (*xfer)(void *context, const u8 *tx, int tx_len,
>> + u8 *rx, int rx_len);
> One line, it's only 81 characters.
Agreed Thanks
>> +};
>> +
>> +int mlx90393_core_probe(struct device *dev,
> You want forward declaration for struct device.
Agreed, Thanks
> + array_size.h
> + bitfield.h // FIELD_GET()
>
>> +#include <linux/delay.h>
> + errno.h // -Exxx
>
>> +#include <linux/module.h>
>> +#include <linux/mutex.h>
> + types.h // uXX
>
>> +#include <linux/unaligned.h>
>> +#include <linux/units.h>
> IWYU, please (just pointed out a few missing above, there are more).
Sure, will do it.
>> +/* Datasheet: Table no.17 */
>> +static const int mlx90393_scale_table[MLX90393_AXIS_MAX]
>> + [MLX90393_GAIN_MAX]
>> + [MLX90393_RES_MAX] = {
> This is broken indentation.
Noted, Thanks
>> +/*
>> + * Calculate total conversion time in microseconds.
>> + *
>> + * Formula derived from datasheet timing equations.
> Which formula? Where is datasheet? What if I have no access to it?
> Always repeat the important details in the comment in the code.
Got it, will add all details from datasheet
>> + */
>> +
> Unneeded blank line.
Noted, Thanks
>> +static int mlx90393_get_tconv_us(struct mlx90393_data *data)
>> +{
>> + const int osr = data->osr;
>> + const int osr2 = data->osr2;
>> + const int df = data->dig_filt;
>> +
>> + int tconvm;
>> + int tconvt;
>> +
>> + int m = 3; /* X,Y,Z */
>> +
>> + /*
>> + * Datasheet:
> What chapter/section/table name? Page number?
Sure will add.
>> + * TCONVM = 67 + 64 * 2^OSR * (2 + 2^DIG_FILT)
> What does this cryptic message mean? Please, accompany this with more English
> plain text.
Agreed, Thanks
>> +static int mlx90393_xfer(struct mlx90393_data *data,
>> + const u8 *tx, int tx_len,
>> + u8 *rx, int rx_len)
>> +{
>> + return data->ops->xfer(data->bus_context,
>> + tx, tx_len,
>> + rx, rx_len);
> It's perfectly one line.
>
> Also you might want to have
>
> if (!...->xfer)
> return -E...;
>
>> +}
Noted, Thanks
>> +static int mlx90393_check_status(u8 cmd, u8 status)
>> +{
>> + /* Always validate error bit */
>> + if (status & MLX90393_STATUS_ERROR)
>> + return -EIO;
>> +
>> + switch (cmd & MLX90393_CMD_MASK) {
>> + case MLX90393_CMD_RM:
>> + /*
>> + * D1:D0 indicates response availability
>> + * 00 means invalid/no measurement
>> + */
>> + if ((status & MLX90393_STATUS_RESP) == 0)
>> + return -EIO;
>> + return 0;
>> + case MLX90393_CMD_RT:
>> + /* Reset acknowledge */
>> + if (!(status & MLX90393_STATUS_RT))
> For sake of consistency you might want to also compare to 0 here.
Thanks, I'll make that change.
>> +static int mlx90393_write_reg(struct mlx90393_data *data, u8 reg, u16 val)
> Here the variable is named 'reg' there is 'reg_addr'. As I can see the code is
> full of inconsistencies (like 2+ people with different style guidelines wrote
> it). Please. take your time and check the code and make it consistent.
Got it, will make it consistent across whole file.
>> +{
>> + u8 tx[4];
>> + u8 status;
>> + int ret;
>> +
>> + tx[0] = MLX90393_CMD_WR;
>> + put_unaligned_be16(val, &tx[1]);
>> + /* Register address is encoded in bits [7:2] */
>> + tx[3] = reg << 2;
>> +
>> + ret = mlx90393_xfer(data, tx, sizeof(tx), &status, 1);
>> + if (ret)
>> + return ret;
>> +
>> + return mlx90393_check_status(tx[0], status);
>> +}
>> +
>> +static int mlx90393_update_bits(struct mlx90393_data *data, u8 reg_addr,
>> + u16 mask, u16 val)
>> +{
>> + u16 reg;
>> + int ret;
>> +
>> + ret = mlx90393_read_reg(data, reg_addr, ®);
>> + if (ret)
>> + return ret;
>>
>> + reg &= ~mask;
>> + reg |= (val << __ffs(mask)) & mask;
> bitfield.h has macros for this.
Noted, Thanks
>> +static int mlx90393_find_osr(int val, int *osr)
>> +{
>> + for (unsigned int i = 0; i < MLX90393_OSR_MAX; i++)
>> + if (mlx90393_osr_avail[i] == val) {
>> + *osr = i;
>> + return 0;
>> + }
> Missing {}.
Agreed, removed intentionally as single statement, will add as per
guidelines all the places
where needed
>> +static int mlx90393_get_temp_osr2(struct mlx90393_data *data, int *val)
>> +{
>> + *val = mlx90393_osr2_avail[data->osr2];
> Missing blank line.
Noted, Thanks
>> int mlx90393_write_raw(struct iio_dev *indio_dev,
>> + const struct iio_chan_spec *chan,
>> + int val, int val2,
>> + long mask)
>> +{
>> + struct mlx90393_data *data = iio_priv(indio_dev);
>> + int ret;
> Not needed, return directly.
Agreed.
>> + /* Datasheet: 22124 millidegC/LSB */
>> + /* Datasheet: temperature offset */
> Again, at least put a page, better to have Section/Table/et cetera title.
Sure, will do it
> + *vals = mlx90393_osr_avail;
> + *type = IIO_VAL_INT;
> + *length = MLX90393_OSR_MAX;
> + }
> + return IIO_AVAIL_LIST;
> +
> + default:
> + return -EINVAL;
> + }
>> + return -EINVAL;
> Besides missing blank line, this is actually a dead code.
Correct, this will never be called. will fix
>> +static int mlx90393_init(struct mlx90393_data *data)
>> +{
>> + int ret;
>> + u16 reg;
>> +
>> + /* Exit mode */
>> + ret = mlx90393_write_cmd(data, MLX90393_CMD_EX);
>> + if (ret)
>> + return ret;
>> +
>> + /* Wait for device comes out of reset */
> Datasheet? Empirical?
Agreed, Thanks
>> + fsleep(1000);
> 1 * USEC_PER_MSEC
> (will require time.h to be included).
Noted, Thanks
>> + /* Reset device */
>> + ret = mlx90393_write_cmd(data, MLX90393_CMD_RT);
>> + if (ret)
>> + return ret;
>> +
>> + /* Wait for device to reset */
>> + fsleep(6000);
> As per above.
This delay is not 6000ms it is 1500ms as per datasheet, forgot to update
in code
Thanks for pointing out, will update all places delay requirement with
datasheet reference.
>> +int mlx90393_core_probe(struct device *dev,
>> + const struct mlx90393_transfer_ops *ops,
>> + void *context)
>> +{
>> + struct iio_dev *indio_dev;
>> + struct mlx90393_data *data;
>> + int ret;
>> +
>> + indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
>> + if (!indio_dev)
>> + return -ENOMEM;
>> +
>> + data = iio_priv(indio_dev);
>> + devm_mutex_init(dev, &data->lock);
> Nonsense. If we don't check the return code of devm_*(), there is a little
> reason to use it in the first place. But then one should not use devm further.
> Easy fix: check for returned errors.
Agreed, I'll fix this in the next revision.
>> + data->dev = dev;
>> + data->ops = ops;
>> + data->bus_context = context;
>> +
>> + indio_dev->name = "mlx90393";
>> + indio_dev->info = &mlx90393_info;
>> + indio_dev->modes = INDIO_DIRECT_MODE;
>> + indio_dev->channels = mlx90393_channels;
>> + indio_dev->num_channels = ARRAY_SIZE(mlx90393_channels);
>> +
>> + ret = mlx90393_init(data);
>> + if (ret)
>> + return dev_err_probe(dev, ret, "failed to initialize device\n");
>> +
>> + return devm_iio_device_register(dev, indio_dev);
>> +}
>> +EXPORT_SYMBOL_GPL(mlx90393_core_probe);
> Make it namespaces.
Okay, will do it
> + array_size.h
> + errno.h
>
>> +#include <linux/module.h>
>> +#include <linux/i2c.h>
>> +#include <linux/mod_devicetable.h>
> ...and so on.
>
> Same, follow the IWYU principle.
Got it, will take care
>> +/*
>> + * MLX90393 commands use repeated-start transfers where
>> + * every command is followed by a status/data response.
>> + */
>> +static int mlx90393_i2c_xfer(void *context,
>> + const u8 *tx, int tx_len,
>> + u8 *rx, int rx_len)
>> +{
>> + struct i2c_client *client = context;
>> + int ret;
>> + struct i2c_msg msgs[2] = {
>> + [0] = {
>> + .addr = client->addr,
>> + .len = tx_len,
>> + .buf = (u8 *)tx,
>> + },
>> + [1] = {
>> + .addr = client->addr,
>> + .flags = I2C_M_RD,
>> + .len = rx_len,
>> + .buf = rx,
>> + },
>> + };
>> +
>> + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
>> + if (ret != ARRAY_SIZE(msgs))
>> + return ret < 0 ? ret : -EIO;
> Please, make this to be the regular pattern
>
> if (ret < 0)
> return ret;
> if (ret != ARRAY_SIZE(msgs))
> return -EIO;
>
>> + return 0;
>> +}
Thanks, I'll make that change.
>> +static struct i2c_driver mlx90393_i2c_driver = {
>> + .driver = {
>> + .name = "mlx90393",
>> + .of_match_table = mlx90393_of_match,
>> + },
>> + .probe = mlx90393_i2c_probe,
>> +};
> Remove this blank line.
Noted
>> +module_i2c_driver(mlx90393_i2c_driver);
>>
Thanks & Regards,
Nikhil
^ permalink raw reply
* Re: [PATCH v1 2/2] ASoC: qcom: sc8280xp: add Shikra EVK machine variants
From: Srinivas Kandagatla @ 2026-06-18 21:34 UTC (permalink / raw)
To: Ajay Kumar Nandam, Srinivas Kandagatla, Liam Girdwood, Mark Brown,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-sound, linux-arm-msm, devicetree, linux-kernel,
Mohammad Rafi Shaik
In-Reply-To: <20260611112946.954172-3-ajay.nandam@oss.qualcomm.com>
On 6/11/26 12:29 PM, Ajay Kumar Nandam wrote:
> Add machine-driver support for Qualcomm Shikra EVK variants by matching
> dedicated compatible strings and applying board-specific audio behavior.
>
> Shikra platforms are available as CQM, CQS, and IQS variants with
> different audio components and processing architectures:
>
> - CQM/CQS use an I2S-based path with WSA885x amplifiers and
> PM4125 + Rouleur codec components.
> - CQM runs in DSP-bypass mode, where the complete audio pipeline runs
> on CPU only and no DSP is involved.
This patch is doing too many things you need to seperate them in to
seperate patches.
> - CQS uses modem-DSP based audio processing.
> - IQS uses a third-party MAX98091 codec with modem-DSP support.
>
> Introduce variant-specific handling so codec controls, DAPM widgets, and
> clock programming match the board design and avoid invalid clock setup on
> variants where it is not applicable.
>
> Co-developed-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
> Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
> Signed-off-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com>
> ---
> sound/soc/qcom/common.c | 2 ++
> sound/soc/qcom/sc8280xp.c | 58 +++++++++++++++++++++++++++++++++++++--
> sound/soc/qcom/sdw.c | 3 ++
> 3 files changed, 61 insertions(+), 2 deletions(-)
>
> diff --git a/sound/soc/qcom/common.c b/sound/soc/qcom/common.c
> index f42c98ded..32d6c09b2 100644
> --- a/sound/soc/qcom/common.c
> +++ b/sound/soc/qcom/common.c
> @@ -3,6 +3,7 @@
> // Copyright (c) 2018, The Linux Foundation. All rights reserved.
>
> #include <dt-bindings/sound/qcom,q6afe.h>
> +#include <dt-bindings/sound/qcom,qaif.h>
> #include <linux/module.h>
> #include <sound/jack.h>
> #include <linux/input-event-codes.h>
> @@ -430,6 +431,7 @@ int qcom_snd_wcd_jack_setup(struct snd_soc_pcm_runtime *rtd,
> }
>
> switch (cpu_dai->id) {
> + case QAIF_CDC_DMA_RX0:
> case TX_CODEC_DMA_TX_0:
> case TX_CODEC_DMA_TX_1:
> case TX_CODEC_DMA_TX_2:
> diff --git a/sound/soc/qcom/sc8280xp.c b/sound/soc/qcom/sc8280xp.c
> index e5d23e244..4c985f81c 100644
> --- a/sound/soc/qcom/sc8280xp.c
> +++ b/sound/soc/qcom/sc8280xp.c
> @@ -37,6 +37,25 @@ static struct snd_soc_dapm_widget sc8280xp_dapm_widgets[] = {
> SND_SOC_DAPM_SPK("DP7 Jack", NULL),
> };
>
> +static struct snd_soc_dapm_widget shikra_cqm_dapm_widgets[] = {
> + SND_SOC_DAPM_HP("Headphone Jack", NULL),
> + SND_SOC_DAPM_MIC("Mic Jack", NULL),
> +};
> +
> +static const struct snd_soc_dapm_widget shikra_iqs_dapm_widgets[] = {
> + SND_SOC_DAPM_HP("Headphone", NULL),
> + SND_SOC_DAPM_MIC("Headset Mic", NULL),
> + SND_SOC_DAPM_MIC("Int Mic", NULL),
> + SND_SOC_DAPM_SPK("Speaker", NULL),
> +};
> +
> +static const struct snd_kcontrol_new shikra_iqs_controls[] = {
> + SOC_DAPM_PIN_SWITCH("Headset Mic"),
> + SOC_DAPM_PIN_SWITCH("Headphone"),
> + SOC_DAPM_PIN_SWITCH("Int Mic"),
> + SOC_DAPM_PIN_SWITCH("Speaker"),
> +};
> +
> struct snd_soc_common {
> const char *driver_name;
> const struct snd_soc_dapm_widget *dapm_widgets;
> @@ -49,6 +68,7 @@ struct snd_soc_common {
> bool codec_sysclk_set;
> bool mi2s_mclk_enable;
> bool mi2s_bclk_enable;
> + bool dsp_bypass;
How is this related to this patch?
> };
>
> struct sc8280xp_snd_data {
> @@ -219,6 +239,10 @@ static int sc8280xp_snd_hw_params(struct snd_pcm_substream *substream,
> int mclk_freq = sc8280xp_get_mclk_freq(params);
> int bclk_freq = sc8280xp_get_bclk_freq(params);
>
> + /* Skip DSP configuration when operating in CPU-only (bypass) mode */
> + if (data->snd_soc_common_priv->dsp_bypass)
> + return 0;
> +
This has nothing to do with what this patch is doing.
> switch (cpu_dai->id) {
> case PRIMARY_MI2S_RX ... QUATERNARY_MI2S_TX:
> case QUINARY_MI2S_RX ... QUINARY_MI2S_TX:
> @@ -239,7 +263,7 @@ static int sc8280xp_snd_hw_params(struct snd_pcm_substream *substream,
> SND_SOC_CLOCK_IN);
>
> if (data->snd_soc_common_priv->codec_sysclk_set)
> - snd_soc_dai_set_sysclk(cpu_dai,
> + snd_soc_dai_set_sysclk(codec_dai,
this is not related to shikra support
> 0, mclk_freq,
> SND_SOC_CLOCK_IN);
> break;
> @@ -284,7 +308,7 @@ static void sc8280xp_add_be_ops(struct snd_soc_card *card)
> int i;
>
> for_each_card_prelinks(card, i, link) {
> - if (link->no_pcm == 1) {
> + if (link->no_pcm == 1 || link->num_codecs > 0) {
Looks like you are mixing multiple changes in single patch, please
seperate them.
> link->init = sc8280xp_snd_init;
> link->be_hw_params_fixup = sc8280xp_be_hw_params_fixup;
> link->ops = &sc8280xp_be_ops;
> @@ -375,6 +399,33 @@ static struct snd_soc_common sc8280xp_priv_data = {
> .num_dapm_widgets = ARRAY_SIZE(sc8280xp_dapm_widgets),
> };
>
> +static const struct snd_soc_common shikra_cqm_priv_data = {
> + .driver_name = "shikra",
> + .dapm_widgets = shikra_cqm_dapm_widgets,
> + .num_dapm_widgets = ARRAY_SIZE(shikra_cqm_dapm_widgets),
> + .dsp_bypass = true,
> +};
> +
> +static const struct snd_soc_common shikra_cqs_priv_data = {
> + .driver_name = "shikra",
> + .dapm_widgets = shikra_cqm_dapm_widgets,
> + .num_dapm_widgets = ARRAY_SIZE(shikra_cqm_dapm_widgets),
> + .mi2s_bclk_enable = true,
> + .codec_sysclk_set = true,
> +};
> +
> +static const struct snd_soc_common shikra_iqs_priv_data = {
> + .driver_name = "shikra",
> + .dapm_widgets = shikra_iqs_dapm_widgets,
> + .num_dapm_widgets = ARRAY_SIZE(shikra_iqs_dapm_widgets),
> + .controls = shikra_iqs_controls,
> + .num_controls = ARRAY_SIZE(shikra_iqs_controls),
> + .codec_dai_fmt = SND_SOC_DAIFMT_CBP_CFP |
> + SND_SOC_DAIFMT_NB_NF |
> + SND_SOC_DAIFMT_I2S,
> + .codec_sysclk_set = true,
> + .mi2s_bclk_enable = true,
> +};
> +
> static struct snd_soc_common sm8450_priv_data = {
> .driver_name = "sm8450",
> .dapm_widgets = sc8280xp_dapm_widgets,
> @@ -408,6 +459,9 @@ static const struct of_device_id snd_sc8280xp_dt_match[] = {
> {.compatible = "qcom,qcs9075-sndcard", .data = &qcs9100_priv_data},
> {.compatible = "qcom,qcs9100-sndcard", .data = &qcs9100_priv_data},
> {.compatible = "qcom,sc8280xp-sndcard", .data = &sc8280xp_priv_data},
> + {.compatible = "qcom,shikra-cqm-sndcard", .data = &shikra_cqm_priv_data},
> + {.compatible = "qcom,shikra-cqs-sndcard", .data = &shikra_cqs_priv_data},
> + {.compatible = "qcom,shikra-iqs-sndcard", .data = &shikra_iqs_priv_data},
> {.compatible = "qcom,sm8450-sndcard", .data = &sm8450_priv_data},
> {.compatible = "qcom,sm8550-sndcard", .data = &sm8550_priv_data},
> {.compatible = "qcom,sm8650-sndcard", .data = &sm8650_priv_data},
> diff --git a/sound/soc/qcom/sdw.c b/sound/soc/qcom/sdw.c
> index 6576b47a4..0be743cec 100644
> --- a/sound/soc/qcom/sdw.c
> +++ b/sound/soc/qcom/sdw.c
> @@ -4,6 +4,7 @@
>
> #include <dt-bindings/sound/qcom,lpass.h>
> #include <dt-bindings/sound/qcom,q6afe.h>
> +#include <dt-bindings/sound/qcom,qaif.h>
> #include <linux/module.h>
> #include <sound/soc.h>
> #include "sdw.h"
> @@ -41,6 +42,8 @@ static bool qcom_snd_is_sdw_dai(int id)
> switch (id) {
> case LPASS_CDC_DMA_TX3:
> case LPASS_CDC_DMA_RX0:
> + case QAIF_CDC_DMA_VA_TX0:
> + case QAIF_CDC_DMA_RX0:
> return true;
> default:
> break;
^ permalink raw reply
* Re: [PATCH RFC] dt-bindings: sound: Convert cirrus,cs35l36 to DT schema
From: Rhodes, David @ 2026-06-18 21:38 UTC (permalink / raw)
To: david, David Rhodes, Richard Fitzgerald, Liam Girdwood,
Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
patches, Bjorn Helgaas
Cc: linux-sound, devicetree, linux-kernel, phone-devel
In-Reply-To: <20260618-dt-cirrus-cs35l36-v1-1-1a43515666ad@ixit.cz>
On 6/18/26 9:33 AM, David Heidelberg via B4 Relay wrote:
> From: David Heidelberg <david@ixit.cz>
>
> Convert CS35L36 Speaker Amplifier.
>
> Changes:
> - maintainers email to the generic Cirrus email
> - Both the codec and downstream worked just fine without
> VP-supply provided. Align with datasheet for similar models.
> - add dai-common.yaml to cover for '#sound-dai-cells',
> 'sound-name-prefix'
>
> Co-developed-by: Rob Herring (Arm) <robh@kernel.org>
> Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
Reviewed-by: David Rhodes <David.Rhodes@cirrus.com>
Thanks,
David
^ permalink raw reply
* Re: [PATCH v1 3/3] ASoC: qcom: qdsp6: generalize GPR service domain
From: Srinivas Kandagatla @ 2026-06-18 21:45 UTC (permalink / raw)
To: Ajay Kumar Nandam, Srinivas Kandagatla, Liam Girdwood, Mark Brown,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela,
Takashi Iwai
Cc: linux-sound, linux-arm-msm, devicetree, linux-kernel,
mohammad.rafi.shaik, Pratyush Meduri
In-Reply-To: <20260609064038.492641-4-ajay.nandam@oss.qualcomm.com>
On 6/9/26 7:40 AM, Ajay Kumar Nandam wrote:
> Use each GPR domain advertised by the qcom APR/GPR layer when building
> APM/PRM packets and add explicit dest_domain parameters to all AudioReach
> alloc helpers.
> Legacy helpers fall back to ADSP while graphs, media-format, and
> shared-memory packets reuse gdev->domain_id for modem targets.
Why?
>
I dont understand what are you trying to do, commit log itself is not
clear and does explain the problem that you are solving or what exactly
> Co-developed-by: Pratyush Meduri <mpratyus@qti.qualcomm.com>
> Signed-off-by: Pratyush Meduri <mpratyus@qti.qualcomm.com>
> Signed-off-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com>
> ---
> sound/soc/qcom/qdsp6/audioreach.c | 112 +++++++++++++++++++++---------
> sound/soc/qcom/qdsp6/audioreach.h | 23 +++---
> sound/soc/qcom/qdsp6/q6apm.c | 48 +++++++++----
> sound/soc/qcom/qdsp6/q6prm.c | 19 ++---
> 4 files changed, 138 insertions(+), 64 deletions(-)
>
^ permalink raw reply
* [PATCH v3 0/4] phy: qcom: qmp-pcie: Add PCIe PHY support for Hawi
From: Matthew Leung @ 2026-06-18 21:54 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, Matthew Leung,
Krzysztof Kozlowski
This series adds QMP PCIe PHY support for the Qualcomm Hawi SoC. The Hawi
platform features two PCIe PHY configurations: Gen3 x2 and Gen4 x1.
The Gen3 x2 PHY uses v10 register definitions, while the Gen4 x1 PHY uses
v10.60 register definitions.
The series adds:
- device tree bindings
- v10 register offset headers
- v10.60 register offset headers
- driver support with PHY initialization tables for both configurations
Overlap:
The series has overlap with "phy: qcom: Introduce USB support for Hawi"
by Ronak Raheja (see link [1]). Both patch series introduce a subset of
v10 registers (this series for PCIe and Ronak's for USB). I have
coordinated with Ronak regarding the overlap, and we can update the
series to resolve any overlap based on the order of merging.
Link: https://lore.kernel.org/all/20260508213234.4643-1-ronak.raheja@oss.qualcomm.com/ [1]
Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
---
Changes in v3:
- Squashed v10 register offsets into a single change
- Squashed v10.60 register offsets into a single change
- Removed USB mentions from header comments; offsets are PCIe-specific
- Reused the tx offset for the v10.60 combined txrx module instead of
introducing a separate txrx offset
- Link to v2: https://patch.msgid.link/20260604-hawi-phy-pcie-v2-0-be908d3560db@oss.qualcomm.com
Changes in v2:
- Rebased onto v7.1-rc6
- Patch 1: no change (Reviewed-by carried forward)
- Patch 9: rename QPHY_PCIE_V10_60_PCS_PCS_TX_RX_CONFIG to
QPHY_PCIE_V10_60_PCS_TX_RX_CONFIG to be consistent with the
naming convention used in previous pcs-pcie headers
- Patch 10: update usage of renamed macro
- Link to v1: https://patch.msgid.link/20260508-hawi-phy-pcie-v1-0-237b894353fc@oss.qualcomm.com
To: Vinod Koul <vkoul@kernel.org>
To: Neil Armstrong <neil.armstrong@linaro.org>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-phy@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
Matthew Leung (4):
dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add Hawi compatibles
phy: qcom-qmp: Add v10 register offsets
phy: qcom-qmp: Add v10.60 register offsets
phy: qcom: qmp-pcie: Add QMP PCIe PHY support for Hawi
.../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 6 +
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 375 +++++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10.h | 18 +
.../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10_60.h | 26 ++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h | 22 ++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10_60.h | 23 ++
.../phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h | 49 +++
.../phy/qualcomm/phy-qcom-qmp-qserdes-com-v10_60.h | 55 +++
.../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h | 47 +++
.../qualcomm/phy-qcom-qmp-qserdes-txrx-v10_60.h | 109 ++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 10 +
11 files changed, 740 insertions(+)
---
base-commit: 8cd9520d35a6c38db6567e97dd93b1f11f185dc6
change-id: 20260506-hawi-phy-pcie-283933b4113e
Best regards,
--
Matthew Leung <matthew.leung@oss.qualcomm.com>
^ permalink raw reply
* [PATCH v3 1/4] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add Hawi compatibles
From: Matthew Leung @ 2026-06-18 21:54 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, Matthew Leung,
Krzysztof Kozlowski
In-Reply-To: <20260618-hawi-phy-pcie-v3-0-3fa42ca45ea4@oss.qualcomm.com>
Document the compatibles for the Gen3 x2 and Gen4 x1 QMP PCIe PHYs found
on the Hawi platform.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
---
.../devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
index 3a35120a77ec..9e9e34a63bef 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
@@ -18,6 +18,8 @@ properties:
enum:
- qcom,glymur-qmp-gen4x2-pcie-phy
- qcom,glymur-qmp-gen5x4-pcie-phy
+ - qcom,hawi-qmp-gen3x2-pcie-phy
+ - qcom,hawi-qmp-gen4x1-pcie-phy
- qcom,kaanapali-qmp-gen3x2-pcie-phy
- qcom,qcs615-qmp-gen3x1-pcie-phy
- qcom,qcs8300-qmp-gen4x2-pcie-phy
@@ -183,6 +185,8 @@ allOf:
enum:
- qcom,glymur-qmp-gen4x2-pcie-phy
- qcom,glymur-qmp-gen5x4-pcie-phy
+ - qcom,hawi-qmp-gen3x2-pcie-phy
+ - qcom,hawi-qmp-gen4x1-pcie-phy
- qcom,qcs8300-qmp-gen4x2-pcie-phy
- qcom,sa8775p-qmp-gen4x2-pcie-phy
- qcom,sa8775p-qmp-gen4x4-pcie-phy
@@ -208,6 +212,8 @@ allOf:
enum:
- qcom,glymur-qmp-gen4x2-pcie-phy
- qcom,glymur-qmp-gen5x4-pcie-phy
+ - qcom,hawi-qmp-gen3x2-pcie-phy
+ - qcom,hawi-qmp-gen4x1-pcie-phy
- qcom,kaanapali-qmp-gen3x2-pcie-phy
- qcom,sm8550-qmp-gen4x2-pcie-phy
- qcom,sm8650-qmp-gen4x2-pcie-phy
--
2.34.1
^ permalink raw reply related
* [PATCH v3 2/4] phy: qcom-qmp: Add v10 register offsets
From: Matthew Leung @ 2026-06-18 21:54 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, Matthew Leung
In-Reply-To: <20260618-hawi-phy-pcie-v3-0-3fa42ca45ea4@oss.qualcomm.com>
Hawi SoC uses v10 register definitions for PCIe Gen3 x2. Add the new
register offset headers for all four sub-blocks:
- QSERDES-COM offsets
- QSERDES TX/RX offsets
- PCS offsets
- PCS PCIe-specific offsets
Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 1 +
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10.h | 18 ++++++++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h | 22 ++++++++++
.../phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h | 49 ++++++++++++++++++++++
.../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h | 47 +++++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 5 +++
6 files changed, 142 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index fed2fc9bb311..ba17e53d000f 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -40,6 +40,7 @@
#include "phy-qcom-qmp-qserdes-com-v8.h"
#include "phy-qcom-qmp-pcs-pcie-v8.h"
#include "phy-qcom-qmp-qserdes-txrx-pcie-v8.h"
+#include "phy-qcom-qmp-pcs-pcie-v10.h"
#define PHY_INIT_COMPLETE_TIMEOUT 10000
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10.h
new file mode 100644
index 000000000000..2cdcc211bd93
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_PCIE_V10_H_
+#define QCOM_PHY_QMP_PCS_PCIE_V10_H_
+
+/* Only for QMP V10 PHY - PCIE PCS registers */
+#define QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG2 0x00c
+#define QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG4 0x014
+#define QPHY_PCIE_V10_PCS_ENDPOINT_REFCLK_DRIVE 0x020
+#define QPHY_PCIE_V10_PCS_OSC_DTCT_ACTIONS 0x094
+#define QPHY_PCIE_V10_PCS_EQ_CONFIG1 0x0a4
+#define QPHY_PCIE_V10_PCS_RXEQEVAL_TIME 0x0f4
+#define QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG6 0x0f8
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h
new file mode 100644
index 000000000000..165ce8a28f61
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_V10_H_
+#define QCOM_PHY_QMP_PCS_V10_H_
+
+/* Only for QMP V10 PHY - PCIe PCS registers */
+#define QPHY_V10_PCS_SW_RESET 0x000
+#define QPHY_V10_PCS_PCS_STATUS1 0x014
+#define QPHY_V10_PCS_POWER_DOWN_CONTROL 0x040
+#define QPHY_V10_PCS_START_CONTROL 0x044
+#define QPHY_V10_PCS_REFGEN_REQ_CONFIG1 0x0dc
+#define QPHY_V10_PCS_G12S1_TXDEEMPH_M6DB 0x168
+#define QPHY_V10_PCS_G3S2_PRE_GAIN 0x170
+#define QPHY_V10_PCS_RX_SIGDET_LVL 0x188
+#define QPHY_V10_PCS_RATE_SLEW_CNTRL1 0x198
+#define QPHY_V10_PCS_PCS_TX_RX_CONFIG 0x1d0
+#define QPHY_V10_PCS_EQ_CONFIG2 0x1e4
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h
new file mode 100644
index 000000000000..09199e7b4aac
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_COM_V10_H_
+#define QCOM_PHY_QMP_QSERDES_COM_V10_H_
+
+/* Only for QMP V10 PHY - QSERDES COM registers */
+#define QSERDES_V10_COM_SSC_STEP_SIZE1_MODE1 0x00
+#define QSERDES_V10_COM_SSC_STEP_SIZE2_MODE1 0x04
+#define QSERDES_V10_COM_CP_CTRL_MODE1 0x10
+#define QSERDES_V10_COM_PLL_RCTRL_MODE1 0x14
+#define QSERDES_V10_COM_PLL_CCTRL_MODE1 0x18
+#define QSERDES_V10_COM_CORECLK_DIV_MODE1 0x1c
+#define QSERDES_V10_COM_LOCK_CMP1_MODE1 0x20
+#define QSERDES_V10_COM_LOCK_CMP2_MODE1 0x24
+#define QSERDES_V10_COM_DEC_START_MODE1 0x28
+#define QSERDES_V10_COM_DIV_FRAC_START1_MODE1 0x30
+#define QSERDES_V10_COM_DIV_FRAC_START2_MODE1 0x34
+#define QSERDES_V10_COM_DIV_FRAC_START3_MODE1 0x38
+#define QSERDES_V10_COM_HSCLK_SEL_1 0x3c
+#define QSERDES_V10_COM_SSC_STEP_SIZE1_MODE0 0x60
+#define QSERDES_V10_COM_SSC_STEP_SIZE2_MODE0 0x64
+#define QSERDES_V10_COM_CP_CTRL_MODE0 0x70
+#define QSERDES_V10_COM_PLL_RCTRL_MODE0 0x74
+#define QSERDES_V10_COM_PLL_CCTRL_MODE0 0x78
+#define QSERDES_V10_COM_LOCK_CMP1_MODE0 0x80
+#define QSERDES_V10_COM_LOCK_CMP2_MODE0 0x84
+#define QSERDES_V10_COM_DEC_START_MODE0 0x88
+#define QSERDES_V10_COM_DIV_FRAC_START1_MODE0 0x90
+#define QSERDES_V10_COM_DIV_FRAC_START2_MODE0 0x94
+#define QSERDES_V10_COM_DIV_FRAC_START3_MODE0 0x98
+#define QSERDES_V10_COM_BG_TIMER 0xbc
+#define QSERDES_V10_COM_SSC_EN_CENTER 0xc0
+#define QSERDES_V10_COM_SSC_PER1 0xcc
+#define QSERDES_V10_COM_SSC_PER2 0xd0
+#define QSERDES_V10_COM_CLK_ENABLE1 0xe0
+#define QSERDES_V10_COM_SYS_CLK_CTRL 0xe4
+#define QSERDES_V10_COM_PLL_IVCO 0xf4
+#define QSERDES_V10_COM_SYSCLK_EN_SEL 0x110
+#define QSERDES_V10_COM_LOCK_CMP_EN 0x120
+#define QSERDES_V10_COM_VCO_TUNE_MAP 0x140
+#define QSERDES_V10_COM_CLK_SELECT 0x164
+#define QSERDES_V10_COM_CORE_CLK_EN 0x170
+#define QSERDES_V10_COM_CMN_CONFIG_1 0x174
+#define QSERDES_V10_COM_ADDITIONAL_MISC_3 0x1bc
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h
new file mode 100644
index 000000000000..d81ebdde0063
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V10_H_
+#define QCOM_PHY_QMP_QSERDES_TXRX_V10_H_
+
+#define QSERDES_V10_TX_RES_CODE_LANE_OFFSET_TX 0x03c
+#define QSERDES_V10_TX_RES_CODE_LANE_OFFSET_RX 0x040
+#define QSERDES_V10_TX_LANE_MODE_1 0x084
+#define QSERDES_V10_TX_LANE_MODE_3 0x08c
+#define QSERDES_V10_TX_LANE_MODE_4 0x090
+#define QSERDES_V10_TX_LANE_MODE_5 0x094
+#define QSERDES_V10_TX_PI_QEC_CTRL 0x0e4
+
+#define QSERDES_V10_RX_UCDR_FO_GAIN 0x008
+#define QSERDES_V10_RX_UCDR_SO_GAIN 0x014
+#define QSERDES_V10_RX_UCDR_SB2_THRESH1 0x04c
+#define QSERDES_V10_RX_UCDR_SB2_THRESH2 0x050
+#define QSERDES_V10_RX_TX_ADAPT_PRE_THRESH1 0x0c4
+#define QSERDES_V10_RX_TX_ADAPT_PRE_THRESH2 0x0c8
+#define QSERDES_V10_RX_TX_ADAPT_POST_THRESH 0x0cc
+#define QSERDES_V10_RX_VGA_CAL_CNTRL2 0x0d8
+#define QSERDES_V10_RX_GM_CAL 0x0dc
+#define QSERDES_V10_RX_RX_IDAC_TSETTLE_LOW 0x0f8
+#define QSERDES_V10_RX_SIGDET_ENABLES 0x118
+#define QSERDES_V10_RX_SIGDET_CNTRL 0x11c
+#define QSERDES_V10_RX_RX_MODE_00_LOW 0x15c
+#define QSERDES_V10_RX_RX_MODE_00_HIGH 0x160
+#define QSERDES_V10_RX_RX_MODE_00_HIGH2 0x164
+#define QSERDES_V10_RX_RX_MODE_00_HIGH3 0x168
+#define QSERDES_V10_RX_RX_MODE_00_HIGH4 0x16c
+#define QSERDES_V10_RX_RX_MODE_01_LOW 0x170
+#define QSERDES_V10_RX_RX_MODE_01_HIGH 0x174
+#define QSERDES_V10_RX_RX_MODE_01_HIGH2 0x178
+#define QSERDES_V10_RX_RX_MODE_01_HIGH3 0x17c
+#define QSERDES_V10_RX_RX_MODE_01_HIGH4 0x180
+#define QSERDES_V10_RX_RX_MODE_10_LOW 0x184
+#define QSERDES_V10_RX_RX_MODE_10_HIGH 0x188
+#define QSERDES_V10_RX_RX_MODE_10_HIGH2 0x18c
+#define QSERDES_V10_RX_RX_MODE_10_HIGH3 0x190
+#define QSERDES_V10_RX_RX_MODE_10_HIGH4 0x194
+#define QSERDES_V10_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
+#define QSERDES_V10_RX_SIGDET_CAL_TRIM 0x1f8
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index a873bdd7bffe..7af77572970e 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -39,6 +39,9 @@
#include "phy-qcom-qmp-qserdes-txrx-v8.h"
#include "phy-qcom-qmp-qserdes-lalb-v8.h"
+#include "phy-qcom-qmp-qserdes-com-v10.h"
+#include "phy-qcom-qmp-qserdes-txrx-v10.h"
+
#include "phy-qcom-qmp-qserdes-pll.h"
#include "phy-qcom-qmp-pcs-v2.h"
@@ -65,6 +68,8 @@
#include "phy-qcom-qmp-pcs-v8_50.h"
+#include "phy-qcom-qmp-pcs-v10.h"
+
/* QPHY_SW_RESET bit */
#define SW_RESET BIT(0)
/* QPHY_POWER_DOWN_CONTROL */
--
2.34.1
^ permalink raw reply related
* [PATCH v3 3/4] phy: qcom-qmp: Add v10.60 register offsets
From: Matthew Leung @ 2026-06-18 21:54 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, Matthew Leung
In-Reply-To: <20260618-hawi-phy-pcie-v3-0-3fa42ca45ea4@oss.qualcomm.com>
Hawi SoC uses v10.60 register definitions for PCIe Gen4 x1. Add the new
register offset headers for all four sub-blocks:
- QSERDES-COM offsets
- QSERDES TX/RX offsets
- PCS offsets
- PCS PCIe-specific offsets
Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 1 +
.../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10_60.h | 26 +++++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10_60.h | 23 +++++
.../phy/qualcomm/phy-qcom-qmp-qserdes-com-v10_60.h | 55 +++++++++++
.../qualcomm/phy-qcom-qmp-qserdes-txrx-v10_60.h | 109 +++++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 5 +
6 files changed, 219 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index ba17e53d000f..fb66e2a97ce0 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -41,6 +41,7 @@
#include "phy-qcom-qmp-pcs-pcie-v8.h"
#include "phy-qcom-qmp-qserdes-txrx-pcie-v8.h"
#include "phy-qcom-qmp-pcs-pcie-v10.h"
+#include "phy-qcom-qmp-pcs-pcie-v10_60.h"
#define PHY_INIT_COMPLETE_TIMEOUT 10000
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10_60.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10_60.h
new file mode 100644
index 000000000000..2df5a45010a4
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10_60.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_PCIE_V10_60_H_
+#define QCOM_PHY_QMP_PCS_PCIE_V10_60_H_
+
+/* Only for QMP V10_60 PHY - PCIE PCS registers */
+#define QPHY_PCIE_V10_60_PCS_POWER_STATE_CONFIG2 0x00c
+#define QPHY_PCIE_V10_60_PCS_TX_RX_CONFIG 0x018
+#define QPHY_PCIE_V10_60_PCS_ENDPOINT_REFCLK_DRIVE 0x01c
+#define QPHY_PCIE_V10_60_PCS_OSC_DTCT_ACTIONS 0x090
+#define QPHY_PCIE_V10_60_PCS_EQ_CONFIG1 0x0a0
+#define QPHY_PCIE_V10_60_PCS_G3_RXEQEVAL_TIME 0x0f0
+#define QPHY_PCIE_V10_60_PCS_G4_RXEQEVAL_TIME 0x0f4
+#define QPHY_PCIE_V10_60_PCS_G4_EQ_CONFIG5 0x108
+#define QPHY_PCIE_V10_60_PCS_G4_PRE_GAIN 0x15c
+#define QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG1 0x17c
+#define QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG3 0x184
+#define QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG5 0x18c
+#define QPHY_PCIE_V10_60_PCS_G3_FOM_EQ_CONFIG5 0x1ac
+#define QPHY_PCIE_V10_60_PCS_G4_FOM_EQ_CONFIG5 0x1c0
+#define QPHY_PCIE_V10_60_PCS_POWER_STATE_CONFIG6 0x1d0
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10_60.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10_60.h
new file mode 100644
index 000000000000..e4558b69489d
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10_60.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_V10_60_H_
+#define QCOM_PHY_QMP_PCS_V10_60_H_
+
+/* Only for QMP V10_60 PHY - PCIe PCS registers */
+#define QPHY_V10_60_PCS_SW_RESET 0x000
+#define QPHY_V10_60_PCS_PCS_STATUS1 0x014
+#define QPHY_V10_60_PCS_POWER_DOWN_CONTROL 0x040
+#define QPHY_V10_60_PCS_START_CONTROL 0x044
+#define QPHY_V10_60_PCS_G12S1_TXDEEMPH_M6DB 0x170
+#define QPHY_V10_60_PCS_G3S2_PRE_GAIN 0x178
+#define QPHY_V10_60_PCS_RX_SIGDET_LVL 0x190
+#define QPHY_V10_60_PCS_ELECIDLE_DLY_SEL 0x1b8
+#define QPHY_V10_60_PCS_PCS_TX_RX_CONFIG1 0x1dc
+#define QPHY_V10_60_PCS_PCS_TX_RX_CONFIG2 0x1e0
+#define QPHY_V10_60_PCS_EQ_CONFIG4 0x1f8
+#define QPHY_V10_60_PCS_EQ_CONFIG5 0x1fc
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10_60.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10_60.h
new file mode 100644
index 000000000000..39351bef8b63
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10_60.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_COM_V10_60_H_
+#define QCOM_PHY_QMP_QSERDES_COM_V10_60_H_
+
+/* Only for QMP V10_60 PHY - QSERDES COM registers */
+#define QSERDES_V10_60_COM_SSC_STEP_SIZE1_MODE1 0x00
+#define QSERDES_V10_60_COM_SSC_STEP_SIZE2_MODE1 0x04
+#define QSERDES_V10_60_COM_CP_CTRL_MODE1 0x10
+#define QSERDES_V10_60_COM_PLL_RCTRL_MODE1 0x14
+#define QSERDES_V10_60_COM_PLL_CCTRL_MODE1 0x18
+#define QSERDES_V10_60_COM_CORECLK_DIV_MODE1 0x1c
+#define QSERDES_V10_60_COM_LOCK_CMP1_MODE1 0x20
+#define QSERDES_V10_60_COM_LOCK_CMP2_MODE1 0x24
+#define QSERDES_V10_60_COM_DEC_START_MODE1 0x28
+#define QSERDES_V10_60_COM_DIV_FRAC_START1_MODE1 0x30
+#define QSERDES_V10_60_COM_DIV_FRAC_START2_MODE1 0x34
+#define QSERDES_V10_60_COM_DIV_FRAC_START3_MODE1 0x38
+#define QSERDES_V10_60_COM_HSCLK_SEL_1 0x3c
+#define QSERDES_V10_60_COM_SSC_STEP_SIZE1_MODE0 0x60
+#define QSERDES_V10_60_COM_SSC_STEP_SIZE2_MODE0 0x64
+#define QSERDES_V10_60_COM_CP_CTRL_MODE0 0x70
+#define QSERDES_V10_60_COM_PLL_RCTRL_MODE0 0x74
+#define QSERDES_V10_60_COM_PLL_CCTRL_MODE0 0x78
+#define QSERDES_V10_60_COM_CORECLK_DIV_MODE0 0x7c
+#define QSERDES_V10_60_COM_LOCK_CMP1_MODE0 0x80
+#define QSERDES_V10_60_COM_LOCK_CMP2_MODE0 0x84
+#define QSERDES_V10_60_COM_DEC_START_MODE0 0x88
+#define QSERDES_V10_60_COM_DIV_FRAC_START1_MODE0 0x90
+#define QSERDES_V10_60_COM_DIV_FRAC_START2_MODE0 0x94
+#define QSERDES_V10_60_COM_DIV_FRAC_START3_MODE0 0x98
+#define QSERDES_V10_60_COM_HSCLK_HS_SWITCH_SEL_1 0x9c
+#define QSERDES_V10_60_COM_BG_TIMER 0xbc
+#define QSERDES_V10_60_COM_SSC_PER1 0xcc
+#define QSERDES_V10_60_COM_SSC_PER2 0xd0
+#define QSERDES_V10_60_COM_BIAS_EN_CLKBUFLR_EN 0xdc
+#define QSERDES_V10_60_COM_CLK_ENABLE1 0xe0
+#define QSERDES_V10_60_COM_SYS_CLK_CTRL 0xe4
+#define QSERDES_V10_60_COM_PLL_IVCO 0xf4
+#define QSERDES_V10_60_COM_SYSCLK_EN_SEL 0x110
+#define QSERDES_V10_60_COM_LOCK_CMP_EN 0x120
+#define QSERDES_V10_60_COM_LOCK_CMP_CFG 0x124
+#define QSERDES_V10_60_COM_VCO_TUNE_MAP 0x140
+#define QSERDES_V10_60_COM_CLK_SELECT 0x164
+#define QSERDES_V10_60_COM_CORE_CLK_EN 0x170
+#define QSERDES_V10_60_COM_CMN_CONFIG_1 0x174
+#define QSERDES_V10_60_COM_CMN_MISC1 0x184
+#define QSERDES_V10_60_COM_CMN_MODE 0x188
+#define QSERDES_V10_60_COM_VCO_DC_LEVEL_CTRL 0x198
+#define QSERDES_V10_60_COM_PLL_SPARE_FOR_ECO 0x2b4
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10_60.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10_60.h
new file mode 100644
index 000000000000..3150a494685e
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10_60.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V10_60_H_
+#define QCOM_PHY_QMP_QSERDES_TXRX_V10_60_H_
+
+#define QSERDES_V10_60_TXRX_RES_CODE_LANE_OFFSET_TX 0x034
+#define QSERDES_V10_60_TXRX_RES_CODE_LANE_OFFSET_RX 0x038
+#define QSERDES_V10_60_TXRX_LANE_MODE_1 0x080
+#define QSERDES_V10_60_TXRX_LANE_MODE_2 0x084
+#define QSERDES_V10_60_TXRX_LANE_MODE_3 0x088
+#define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE1 0x0c8
+#define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x0cc
+#define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE3 0x0d0
+#define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x0d4
+#define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE1 0x0e0
+#define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE2 0x0e4
+#define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE3 0x0e8
+#define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x0ec
+#define QSERDES_V10_60_TXRX_UCDR_PI_CTRL1 0x12c
+#define QSERDES_V10_60_TXRX_UCDR_PI_CTRL2 0x130
+#define QSERDES_V10_60_TXRX_UCDR_PI_CTRL3 0x134
+#define QSERDES_V10_60_TXRX_UCDR_PI_CTRL4 0x138
+#define QSERDES_V10_60_TXRX_SVS_MODE_CTRL 0x19c
+#define QSERDES_V10_60_TXRX_RXCLK_DIV2_CTRL 0x1a0
+#define QSERDES_V10_60_TXRX_RX_BAND_CTRL0 0x1a4
+#define QSERDES_V10_60_TXRX_RX_TERM_BW_CTRL0 0x1ac
+#define QSERDES_V10_60_TXRX_RX_TERM_BW_CTRL1 0x1b0
+#define QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE1 0x1b8
+#define QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE2 0x1bc
+#define QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE3 0x1c0
+#define QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE4 0x1c4
+#define QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE1 0x1d0
+#define QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE2 0x1d4
+#define QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE3 0x1d8
+#define QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE4 0x1dc
+#define QSERDES_V10_60_TXRX_UCDR_PI_CONTROLS 0x1e4
+#define QSERDES_V10_60_TXRX_AUXDATA_BIN_RATE3 0x200
+#define QSERDES_V10_60_TXRX_AUXDATA_BIN_RATE4 0x204
+#define QSERDES_V10_60_TXRX_EOM_MAX_ERR_LIMIT_LSB 0x218
+#define QSERDES_V10_60_TXRX_EOM_MAX_ERR_LIMIT_MSB 0x21c
+#define QSERDES_V10_60_TXRX_VGA_CAL_CNTRL1 0x280
+#define QSERDES_V10_60_TXRX_VGA_CAL_MAN_VAL 0x288
+#define QSERDES_V10_60_TXRX_GM_CAL 0x29c
+#define QSERDES_V10_60_TXRX_RX_EQU_ADAPTOR_CNTRL6 0x2b8
+#define QSERDES_V10_60_TXRX_SIGDET_ENABLES 0x2d4
+#define QSERDES_V10_60_TXRX_SIGDET_CNTRL 0x2d8
+#define QSERDES_V10_60_TXRX_SIGDET_LVL 0x2dc
+#define QSERDES_V10_60_TXRX_SIGDET_DEGLITCH_CNTRL 0x2e0
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B0 0x314
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B1 0x318
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B2 0x31c
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B3 0x320
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B4 0x324
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B5 0x328
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B6 0x32c
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B7 0x330
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B8 0x334
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B9 0x338
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B10 0x33c
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B0 0x340
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B1 0x344
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B2 0x348
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B3 0x34c
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B4 0x350
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B5 0x354
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B6 0x358
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B7 0x35c
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B8 0x360
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B9 0x364
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B10 0x368
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B0 0x36c
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B1 0x370
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B2 0x374
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B3 0x378
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B4 0x37c
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B5 0x380
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B6 0x384
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B7 0x388
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B8 0x38c
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B9 0x390
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B10 0x394
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B0 0x398
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B1 0x39c
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B2 0x3a0
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B3 0x3a4
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B4 0x3a8
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B5 0x3ac
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B6 0x3b0
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B7 0x3b4
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B8 0x3b8
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B9 0x3bc
+#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B10 0x3c0
+#define QSERDES_V10_60_TXRX_Q_PI_INTRINSIC_BIAS_RATE32 0x478
+#define QSERDES_V10_60_TXRX_Q_PI_INTRINSIC_BIAS_RATE45 0x47c
+#define QSERDES_V10_60_TXRX_SIGDET_CAL_CTRL1 0x4c8
+#define QSERDES_V10_60_TXRX_SIGDET_CAL_CTRL2 0x4cc
+#define QSERDES_V10_60_TXRX_SIGDET_CAL_TRIM 0x4d0
+#define QSERDES_V10_60_TXRX_TX_BAND0 0x4e8
+#define QSERDES_V10_60_TXRX_TX_BAND1 0x4ec
+#define QSERDES_V10_60_TXRX_SEL_10B_8B 0x4f4
+#define QSERDES_V10_60_TXRX_SEL_20B_10B 0x4f8
+#define QSERDES_V10_60_TXRX_EQ_RCF_CTRL_RATE3 0x53c
+#define QSERDES_V10_60_TXRX_EQ_RCF_CTRL_RATE4 0x540
+#define QSERDES_V10_60_TXRX_PHPRE_CTRL 0x5e8
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 7af77572970e..3a4a0a9a9e4d 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -42,6 +42,9 @@
#include "phy-qcom-qmp-qserdes-com-v10.h"
#include "phy-qcom-qmp-qserdes-txrx-v10.h"
+#include "phy-qcom-qmp-qserdes-com-v10_60.h"
+#include "phy-qcom-qmp-qserdes-txrx-v10_60.h"
+
#include "phy-qcom-qmp-qserdes-pll.h"
#include "phy-qcom-qmp-pcs-v2.h"
@@ -70,6 +73,8 @@
#include "phy-qcom-qmp-pcs-v10.h"
+#include "phy-qcom-qmp-pcs-v10_60.h"
+
/* QPHY_SW_RESET bit */
#define SW_RESET BIT(0)
/* QPHY_POWER_DOWN_CONTROL */
--
2.34.1
^ permalink raw reply related
* [PATCH v3 4/4] phy: qcom: qmp-pcie: Add QMP PCIe PHY support for Hawi
From: Matthew Leung @ 2026-06-18 21:54 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, Matthew Leung
In-Reply-To: <20260618-hawi-phy-pcie-v3-0-3fa42ca45ea4@oss.qualcomm.com>
Add the QMP PCIe PHY support for the Gen3 x2 and Gen4 x1 PHY found on
the Hawi platform.
Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 373 +++++++++++++++++++++++++++++++
1 file changed, 373 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index fb66e2a97ce0..ca3a5d974422 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -118,6 +118,20 @@ static const unsigned int pciephy_v8_50_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V8_50_PCS_POWER_DOWN_CONTROL,
};
+static const unsigned int pciephy_v10_regs_layout[QPHY_LAYOUT_SIZE] = {
+ [QPHY_SW_RESET] = QPHY_V10_PCS_SW_RESET,
+ [QPHY_START_CTRL] = QPHY_V10_PCS_START_CONTROL,
+ [QPHY_PCS_STATUS] = QPHY_V10_PCS_PCS_STATUS1,
+ [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V10_PCS_POWER_DOWN_CONTROL,
+};
+
+static const unsigned int pciephy_v10_60_regs_layout[QPHY_LAYOUT_SIZE] = {
+ [QPHY_SW_RESET] = QPHY_V10_60_PCS_SW_RESET,
+ [QPHY_START_CTRL] = QPHY_V10_60_PCS_START_CONTROL,
+ [QPHY_PCS_STATUS] = QPHY_V10_60_PCS_PCS_STATUS1,
+ [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V10_60_PCS_POWER_DOWN_CONTROL,
+};
+
static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
@@ -3222,6 +3236,287 @@ static const struct qmp_phy_init_tbl kaanapali_qmp_gen3x2_pcie_pcs_misc_tbl[] =
QMP_PHY_INIT_CFG(QPHY_PCIE_V8_PCS_POWER_STATE_CONFIG6, 0x1f),
};
+static const struct qmp_phy_init_tbl hawi_qmp_gen3x2_pcie_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_EN_CENTER, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_PER1, 0x62),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_PER2, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_STEP_SIZE2_MODE0, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_STEP_SIZE1_MODE1, 0x93),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_STEP_SIZE2_MODE1, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_CLK_ENABLE1, 0x90),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SYS_CLK_CTRL, 0x82),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_IVCO, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_CP_CTRL_MODE0, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_CP_CTRL_MODE1, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_RCTRL_MODE1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_CCTRL_MODE0, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_CCTRL_MODE1, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SYSCLK_EN_SEL, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_BG_TIMER, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP_EN, 0x42),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP1_MODE0, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP2_MODE0, 0x0d),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP1_MODE1, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP2_MODE1, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DEC_START_MODE0, 0x41),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DEC_START_MODE1, 0x34),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START1_MODE0, 0xab),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START2_MODE0, 0xaa),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START3_MODE0, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START1_MODE1, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START2_MODE1, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START3_MODE1, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_VCO_TUNE_MAP, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_CLK_SELECT, 0x34),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_HSCLK_SEL_1, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_CORECLK_DIV_MODE1, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_CMN_CONFIG_1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_ADDITIONAL_MISC_3, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_CORE_CLK_EN, 0xa0),
+};
+
+static const struct qmp_phy_init_tbl hawi_qmp_gen3x2_pcie_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_GM_CAL, 0x11),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_HIGH, 0xbf),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_HIGH2, 0xbf),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_HIGH3, 0xb7),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_HIGH4, 0xec),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_LOW, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_HIGH, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_HIGH2, 0x49),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_HIGH3, 0x1b),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_HIGH4, 0x9c),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_LOW, 0xd1),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_10_HIGH, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_10_HIGH2, 0x49),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_10_HIGH3, 0x1b),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_10_HIGH4, 0x9c),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_10_LOW, 0xd1),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_TX_ADAPT_PRE_THRESH1, 0x3e),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_TX_ADAPT_PRE_THRESH2, 0x1e),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_TX_ADAPT_POST_THRESH, 0xd2),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_FO_GAIN, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SO_GAIN, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SB2_THRESH1, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SB2_THRESH2, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_VGA_CAL_CNTRL2, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_SIGDET_ENABLES, 0x1c),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_SIGDET_CNTRL, 0x60),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_IDAC_TSETTLE_LOW, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_SIGDET_CAL_TRIM, 0x08),
+};
+
+static const struct qmp_phy_init_tbl hawi_qmp_gen3x2_pcie_tx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_1, 0x25),
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_3, 0x10),
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_4, 0x31),
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_5, 0x7d),
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_PI_QEC_CTRL, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_RES_CODE_LANE_OFFSET_TX, 0x14),
+};
+
+static const struct qmp_phy_init_tbl hawi_qmp_gen3x2_pcie_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_REFGEN_REQ_CONFIG1, 0x05),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_RX_SIGDET_LVL, 0x77),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_RATE_SLEW_CNTRL1, 0x0b),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_EQ_CONFIG2, 0x0f),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_PCS_TX_RX_CONFIG, 0x8c),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_G12S1_TXDEEMPH_M6DB, 0x17),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_G3S2_PRE_GAIN, 0x2e),
+};
+
+static const struct qmp_phy_init_tbl hawi_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V10_PCS_EQ_CONFIG1, 0x1e),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V10_PCS_RXEQEVAL_TIME, 0x27),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG2, 0x1d),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG4, 0x07),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG6, 0x1f),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V10_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V10_PCS_OSC_DTCT_ACTIONS, 0x00),
+};
+
+static const struct qmp_phy_init_tbl hawi_qmp_gen4x1_pcie_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_SSC_STEP_SIZE1_MODE1, 0x93),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_SSC_STEP_SIZE2_MODE1, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CP_CTRL_MODE1, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_PLL_RCTRL_MODE1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_PLL_CCTRL_MODE1, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CORECLK_DIV_MODE1, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_LOCK_CMP1_MODE1, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_LOCK_CMP2_MODE1, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_DEC_START_MODE1, 0x34),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_DIV_FRAC_START1_MODE1, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_DIV_FRAC_START2_MODE1, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_DIV_FRAC_START3_MODE1, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_HSCLK_SEL_1, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_SSC_STEP_SIZE2_MODE0, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CP_CTRL_MODE0, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_PLL_CCTRL_MODE0, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CORECLK_DIV_MODE0, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_LOCK_CMP1_MODE0, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_LOCK_CMP2_MODE0, 0x0d),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_DEC_START_MODE0, 0x41),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_DIV_FRAC_START1_MODE0, 0xab),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_DIV_FRAC_START2_MODE0, 0xaa),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_DIV_FRAC_START3_MODE0, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_BG_TIMER, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_SSC_PER1, 0x62),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_SSC_PER2, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CLK_ENABLE1, 0x90),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_SYS_CLK_CTRL, 0x82),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_PLL_IVCO, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_SYSCLK_EN_SEL, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_LOCK_CMP_EN, 0x46),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_LOCK_CMP_CFG, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_VCO_TUNE_MAP, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CLK_SELECT, 0x34),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CORE_CLK_EN, 0xa0),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CMN_CONFIG_1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CMN_MISC1, 0x88),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CMN_MODE, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_VCO_DC_LEVEL_CTRL, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_PLL_SPARE_FOR_ECO, 0x02),
+};
+
+static const struct qmp_phy_init_tbl hawi_qmp_gen4x1_pcie_tx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RES_CODE_LANE_OFFSET_TX, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RES_CODE_LANE_OFFSET_RX, 0x12),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SIGDET_CAL_CTRL1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SIGDET_CAL_CTRL2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SIGDET_CAL_TRIM, 0x66),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_TX_BAND0, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_TX_BAND1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SEL_10B_8B, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SEL_20B_10B, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_EQ_RCF_CTRL_RATE3, 0x22),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_EQ_RCF_CTRL_RATE4, 0x22),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_PHPRE_CTRL, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE1, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE3, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE1, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE2, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE3, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_PI_CTRL1, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_PI_CTRL2, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_PI_CTRL3, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_PI_CTRL4, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SVS_MODE_CTRL, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RXCLK_DIV2_CTRL, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_BAND_CTRL0, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_TERM_BW_CTRL0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_TERM_BW_CTRL1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE1, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE2, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE3, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE4, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE1, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE2, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE3, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE4, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_PI_CONTROLS, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_AUXDATA_BIN_RATE3, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_AUXDATA_BIN_RATE4, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_EOM_MAX_ERR_LIMIT_LSB, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_EOM_MAX_ERR_LIMIT_MSB, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_VGA_CAL_CNTRL1, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_VGA_CAL_MAN_VAL, 0x8e),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_GM_CAL, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_EQU_ADAPTOR_CNTRL6, 0xca),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SIGDET_ENABLES, 0x1c),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SIGDET_CNTRL, 0x6f),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SIGDET_LVL, 0x84),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SIGDET_DEGLITCH_CNTRL, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_Q_PI_INTRINSIC_BIAS_RATE32, 0x11),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_Q_PI_INTRINSIC_BIAS_RATE45, 0x10),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B0, 0xc2),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B1, 0xc2),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B2, 0xd8),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B3, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B4, 0x98),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B5, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B6, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B7, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B8, 0xc0),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B9, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B10, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B0, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B1, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B2, 0xd8),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B3, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B4, 0x98),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B5, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B6, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B7, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B8, 0xc0),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B9, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B10, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B0, 0x13),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B1, 0xd3),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B2, 0xc0),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B3, 0x13),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B4, 0x13),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B5, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B6, 0x4c),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B7, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B8, 0xc0),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B9, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B10, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B0, 0x24),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B1, 0x24),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B2, 0xc0),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B3, 0x0b),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B4, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B5, 0x24),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B6, 0x2c),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B7, 0x86),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B8, 0x83),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B9, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B10, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_LANE_MODE_1, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_LANE_MODE_2, 0xc0),
+ QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_LANE_MODE_3, 0x00),
+};
+
+static const struct qmp_phy_init_tbl hawi_qmp_gen4x1_pcie_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V10_60_PCS_G12S1_TXDEEMPH_M6DB, 0x17),
+ QMP_PHY_INIT_CFG(QPHY_V10_60_PCS_G3S2_PRE_GAIN, 0x2e),
+ QMP_PHY_INIT_CFG(QPHY_V10_60_PCS_RX_SIGDET_LVL, 0xcc),
+ QMP_PHY_INIT_CFG(QPHY_V10_60_PCS_ELECIDLE_DLY_SEL, 0x40),
+ QMP_PHY_INIT_CFG(QPHY_V10_60_PCS_PCS_TX_RX_CONFIG1, 0x04),
+ QMP_PHY_INIT_CFG(QPHY_V10_60_PCS_PCS_TX_RX_CONFIG2, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V10_60_PCS_EQ_CONFIG4, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V10_60_PCS_EQ_CONFIG5, 0x22),
+};
+
+static const struct qmp_phy_init_tbl hawi_qmp_gen4x1_pcie_pcs_misc_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_POWER_STATE_CONFIG2, 0x1d),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_TX_RX_CONFIG, 0xc0),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_OSC_DTCT_ACTIONS, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_EQ_CONFIG1, 0x16),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_G3_RXEQEVAL_TIME, 0x27),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_G4_RXEQEVAL_TIME, 0x27),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_G4_EQ_CONFIG5, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_G4_PRE_GAIN, 0x2e),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG1, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG3, 0x28),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG5, 0x0f),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_G3_FOM_EQ_CONFIG5, 0xf2),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_G4_FOM_EQ_CONFIG5, 0xf2),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_POWER_STATE_CONFIG6, 0x1f),
+};
+
struct qmp_pcie_offsets {
u16 serdes;
u16 pcs;
@@ -3534,6 +3829,24 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v8_50 = {
.txrxz = 0xd000,
};
+static const struct qmp_pcie_offsets qmp_pcie_offsets_v10_0 = {
+ .serdes = 0x0000,
+ .pcs = 0x0400,
+ .pcs_misc = 0x0800,
+ .tx = 0x1000,
+ .rx = 0x1200,
+ .tx2 = 0x1800,
+ .rx2 = 0x1a00,
+};
+
+static const struct qmp_pcie_offsets qmp_pcie_offsets_v10_60 = {
+ .tx = 0x0000,
+ /* no .rx; tx and rx share the same register block */
+ .serdes = 0x1000,
+ .pcs = 0x1400,
+ .pcs_misc = 0x1800,
+};
+
static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
.lanes = 1,
@@ -4650,6 +4963,60 @@ static const struct qmp_phy_cfg glymur_qmp_gen4x2_pciephy_cfg = {
.phy_status = PHYSTATUS_4_20,
};
+static const struct qmp_phy_cfg hawi_qmp_gen3x2_pciephy_cfg = {
+ .lanes = 2,
+
+ .offsets = &qmp_pcie_offsets_v10_0,
+
+ .tbls = {
+ .serdes = hawi_qmp_gen3x2_pcie_serdes_tbl,
+ .serdes_num = ARRAY_SIZE(hawi_qmp_gen3x2_pcie_serdes_tbl),
+ .tx = hawi_qmp_gen3x2_pcie_tx_tbl,
+ .tx_num = ARRAY_SIZE(hawi_qmp_gen3x2_pcie_tx_tbl),
+ .rx = hawi_qmp_gen3x2_pcie_rx_tbl,
+ .rx_num = ARRAY_SIZE(hawi_qmp_gen3x2_pcie_rx_tbl),
+ .pcs = hawi_qmp_gen3x2_pcie_pcs_tbl,
+ .pcs_num = ARRAY_SIZE(hawi_qmp_gen3x2_pcie_pcs_tbl),
+ .pcs_misc = hawi_qmp_gen3x2_pcie_pcs_misc_tbl,
+ .pcs_misc_num = ARRAY_SIZE(hawi_qmp_gen3x2_pcie_pcs_misc_tbl),
+ },
+
+ .reset_list = sdm845_pciephy_reset_l,
+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = pciephy_v10_regs_layout,
+
+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+ .phy_status = PHYSTATUS,
+};
+
+static const struct qmp_phy_cfg hawi_qmp_gen4x1_pciephy_cfg = {
+ .lanes = 1,
+
+ .offsets = &qmp_pcie_offsets_v10_60,
+
+ .tbls = {
+ .serdes = hawi_qmp_gen4x1_pcie_serdes_tbl,
+ .serdes_num = ARRAY_SIZE(hawi_qmp_gen4x1_pcie_serdes_tbl),
+ .tx = hawi_qmp_gen4x1_pcie_tx_tbl,
+ .tx_num = ARRAY_SIZE(hawi_qmp_gen4x1_pcie_tx_tbl),
+ .pcs = hawi_qmp_gen4x1_pcie_pcs_tbl,
+ .pcs_num = ARRAY_SIZE(hawi_qmp_gen4x1_pcie_pcs_tbl),
+ .pcs_misc = hawi_qmp_gen4x1_pcie_pcs_misc_tbl,
+ .pcs_misc_num = ARRAY_SIZE(hawi_qmp_gen4x1_pcie_pcs_misc_tbl),
+ },
+
+ .reset_list = sdm845_pciephy_reset_l,
+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = pciephy_v10_60_regs_layout,
+
+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+ .phy_status = PHYSTATUS_4_20,
+};
+
static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
{
const struct qmp_phy_cfg *cfg = qmp->cfg;
@@ -5406,6 +5773,12 @@ static const struct of_device_id qmp_pcie_of_match_table[] = {
}, {
.compatible = "qcom,glymur-qmp-gen5x4-pcie-phy",
.data = &glymur_qmp_gen5x4_pciephy_cfg,
+ }, {
+ .compatible = "qcom,hawi-qmp-gen3x2-pcie-phy",
+ .data = &hawi_qmp_gen3x2_pciephy_cfg,
+ }, {
+ .compatible = "qcom,hawi-qmp-gen4x1-pcie-phy",
+ .data = &hawi_qmp_gen4x1_pciephy_cfg,
}, {
.compatible = "qcom,ipq6018-qmp-pcie-phy",
.data = &ipq6018_pciephy_cfg,
--
2.34.1
^ permalink raw reply related
* [PATCH v3 0/2] PCI: qcom: Add PCIe support for upcoming Hawi SoC
From: Matthew Leung @ 2026-06-18 22:00 UTC (permalink / raw)
To: Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson
Cc: linux-arm-msm, linux-pci, devicetree, linux-kernel, Matthew Leung
This series adds PCIe support for the Qualcomm Hawi SoC. The Hawi
platform features two PCIe controllers: one capable of Gen3 x2 operation
and one capable of Gen4 x1 operation. The first patch adds the device
tree bindings documentation for the Hawi PCIe controller, and the second
patch adds driver support by enabling the Hawi compatible string in the
existing qcom PCIe driver.
Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
---
Changes in v3:
- Updated binding example to use ephemeral values, removing cross-tree
dependencies
- Link to v2: https://patch.msgid.link/20260529-hawi-pcie-v2-0-de87c6cc230c@oss.qualcomm.com
Changes in v2:
- Rebased onto a newer linux-next snapshot
- Previously required dependency series are now queued on linux-next
- Added minItems constraint for clocks
- Moved description comments for clock-names, reg-names, and reset-names
into 'description' entries in the devicetree bindings.
- Removed maxItems constraint for clocks, regs, resets for the fixed
size 'items' list
- Link to v1: https://patch.msgid.link/20260508-hawi-pcie-v1-0-0c910906f7e5@oss.qualcomm.com
To: Lorenzo Pieralisi <lpieralisi@kernel.org>
To: Krzysztof Wilczyński <kwilczynski@kernel.org>
To: Manivannan Sadhasivam <mani@kernel.org>
To: Rob Herring <robh@kernel.org>
To: Bjorn Helgaas <bhelgaas@google.com>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Bjorn Andersson <andersson@kernel.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
Matthew Leung (2):
dt-bindings: PCI: qcom: Document the Hawi PCIe Controller
PCI: qcom: Add support for Hawi
.../devicetree/bindings/pci/qcom,hawi-pcie.yaml | 202 +++++++++++++++++++++
drivers/pci/controller/dwc/pcie-qcom.c | 1 +
2 files changed, 203 insertions(+)
---
base-commit: e2cae00c05d196491c318196792297f2dfbaa02c
change-id: 20260506-hawi-pcie-f61435ca420c
Best regards,
--
Matthew Leung <matthew.leung@oss.qualcomm.com>
^ permalink raw reply
* [PATCH v3 1/2] dt-bindings: PCI: qcom: Document the Hawi PCIe Controller
From: Matthew Leung @ 2026-06-18 22:00 UTC (permalink / raw)
To: Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson
Cc: linux-arm-msm, linux-pci, devicetree, linux-kernel, Matthew Leung
In-Reply-To: <20260618-hawi-pcie-v3-0-f31880bfb3ec@oss.qualcomm.com>
Add a dedicated schema for the PCIe controllers found on the Hawi
platform.
Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
---
.../devicetree/bindings/pci/qcom,hawi-pcie.yaml | 202 +++++++++++++++++++++
1 file changed, 202 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml
new file mode 100644
index 000000000000..fb3145f89f7f
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml
@@ -0,0 +1,202 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,hawi-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Hawi PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <mani@kernel.org>
+
+description:
+ Qualcomm Hawi SoC (and compatible) PCIe root complex controller is based on
+ the Synopsys DesignWare PCIe IP.
+
+properties:
+ compatible:
+ const: qcom,hawi-pcie
+
+ reg:
+ minItems: 5
+ items:
+ - description: Qualcomm specific registers
+ - description: DesignWare PCIe registers
+ - description: External local bus interface registers
+ - description: ATU address space
+ - description: PCIe configuration space
+ - description: MHI registers
+
+ reg-names:
+ minItems: 5
+ items:
+ - const: parf
+ - const: dbi
+ - const: elbi
+ - const: atu
+ - const: config
+ - const: mhi
+
+ clocks:
+ minItems: 6
+ items:
+ - description: PCIe Auxiliary clock
+ - description: PCIe Configuration clock
+ - description: PCIe Master AXI clock
+ - description: PCIe Slave AXI clock
+ - description: PCIe Slave Q2A AXI clock
+ - description: PCIe Aggre NoC AXI clock
+ - description: PCIe Config NoC AXI clock
+
+ clock-names:
+ minItems: 6
+ items:
+ - const: aux
+ - const: cfg
+ - const: bus_master
+ - const: bus_slave
+ - const: slave_q2a
+ - const: noc_aggr
+ - const: cnoc_sf_axi
+
+ interrupts:
+ minItems: 8
+ maxItems: 9
+
+ interrupt-names:
+ minItems: 8
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+ - const: global
+
+ resets:
+ minItems: 1
+ items:
+ - description: PCIe core reset
+ - description: PCIe link down reset
+
+ reset-names:
+ minItems: 1
+ items:
+ - const: pci
+ - const: link_down
+
+required:
+ - power-domains
+ - resets
+ - reset-names
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@1c00000 {
+ compatible = "qcom,hawi-pcie";
+ reg = <0 0x01c00000 0 0x3000>,
+ <0 0x40000000 0 0xf1d>,
+ <0 0x40000f20 0 0xa8>,
+ <0 0x40001000 0 0x1000>,
+ <0 0x40100000 0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
+ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x3d00000>;
+
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ num-lanes = <2>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ clocks = <&gcc_pcie_0_aux_clk>,
+ <&gcc_pcie_0_cfg_ahb_clk>,
+ <&gcc_pcie_0_mstr_axi_clk>,
+ <&gcc_pcie_0_slv_axi_clk>,
+ <&gcc_pcie_0_slv_q2a_axi_clk>,
+ <&gcc_aggre_noc_pcie_axi_clk>,
+ <&gcc_cnoc_pcie_sf_axi_clk>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "noc_aggr",
+ "cnoc_sf_axi";
+
+ dma-coherent;
+
+ interrupts = <GIC_ESPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 204 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7", "global";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_ESPI 213 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 0 GIC_ESPI 214 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 0 GIC_ESPI 215 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 0 GIC_ESPI 216 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ interconnects = <&pcie_anoc_master_pcie_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc_master_appss_proc QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_main_slave_pcie_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ iommu-map = <0x0 &apps_smmu 0x1000 0x1>,
+ <0x100 &apps_smmu 0x1001 0x1>;
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ power-domains = <&gcc_pcie_0_phy_gdsc>;
+
+ resets = <&gcc_pcie_0_bcr>,
+ <&gcc_pcie_0_link_down_bcr>;
+ reset-names = "pci", "link_down";
+
+ msi-map = <0x0 &gic_its 0x1000 0x1>,
+ <0x100 &gic_its 0x1001 0x1>;
+ msi-map-mask = <0xff00>;
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ phys = <&pcie0_phy>;
+ wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
+ };
+ };
+ };
--
2.34.1
^ permalink raw reply related
* [PATCH v3 2/2] PCI: qcom: Add support for Hawi
From: Matthew Leung @ 2026-06-18 22:00 UTC (permalink / raw)
To: Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson
Cc: linux-arm-msm, linux-pci, devicetree, linux-kernel, Matthew Leung
In-Reply-To: <20260618-hawi-pcie-v3-0-f31880bfb3ec@oss.qualcomm.com>
Add support for the Hawi platform which has two PCIe controllers: one
capable of Gen3 x2 operation and one capable of Gen4 x1 operation.
Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index d8eb52857f69..89ae006fb6c3 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -2282,6 +2282,7 @@ static int qcom_pcie_resume_noirq(struct device *dev)
}
static const struct of_device_id qcom_pcie_match[] = {
+ { .compatible = "qcom,hawi-pcie", .data = &cfg_1_9_0 },
{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
{ .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
{ .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v3 2/2] PCI: qcom: Add support for Hawi
From: sashiko-bot @ 2026-06-18 22:04 UTC (permalink / raw)
To: Matthew Leung; +Cc: conor+dt, robh, linux-pci, devicetree
In-Reply-To: <20260618-hawi-pcie-v3-2-f31880bfb3ec@oss.qualcomm.com>
> Add support for the Hawi platform which has two PCIe controllers: one
> capable of Gen3 x2 operation and one capable of Gen4 x1 operation.
>
> Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260618-hawi-pcie-v3-0-f31880bfb3ec@oss.qualcomm.com?part=2
^ permalink raw reply
* [PATCH v2 0/4] PCI: rcar-gen4: irqchip/gic-v3: Handle GIC ITS
From: Marek Vasut @ 2026-06-18 22:01 UTC (permalink / raw)
To: linux-pci
Cc: Marek Vasut, Krzysztof Wilczyński, Bjorn Helgaas,
Catalin Marinas, Conor Dooley, Geert Uytterhoeven,
Krzysztof Kozlowski, Lorenzo Pieralisi, Manivannan Sadhasivam,
Marc Zyngier, Rob Herring, Yoshihiro Shimoda, devicetree,
linux-arm-kernel, linux-doc, linux-kernel, linux-renesas-soc
Configure all R-Car Gen4 PCIe controller MSI registers fully, both in
case MSI are enabled and disabled.
Patch GIC ITS driver and add quirks for R-Car Gen4 GIC ITS, which is
configured to 32-bit address width for AXI or APB interface.
Switch R-Car V4H to use GIC ITS in its DT and describe the GIC ITS
implementation cacheable and shareable limitations.
Marek Vasut (4):
PCI: rcar-gen4: Configure AXIINTC if iMSI-RX not used
irqchip/gic-v3: Refactor GIC600 limited to 32bit PA erratum handling
irqchip/gic-v3: Add Renesas R-Car Gen4 erratum workaround
arm64: dts: renesas: r8a779g0: Add GICv3 ITS and update PCIe nodes
Documentation/arch/arm64/silicon-errata.rst | 1 +
arch/arm64/Kconfig | 9 ++
arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 31 +++--
drivers/irqchip/irq-gic-v3-its.c | 24 ++--
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 118 +++++++++++++++++++-
5 files changed, 162 insertions(+), 21 deletions(-)
---
Cc: "Krzysztof Wilczyński" <kwilczynski@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: Manivannan Sadhasivam <mani@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-doc@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
--
2.53.0
^ permalink raw reply
* [PATCH v2 2/4] irqchip/gic-v3: Refactor GIC600 limited to 32bit PA erratum handling
From: Marek Vasut @ 2026-06-18 22:02 UTC (permalink / raw)
To: linux-pci
Cc: Marek Vasut, Marc Zyngier, Krzysztof Wilczyński,
Bjorn Helgaas, Catalin Marinas, Conor Dooley, Geert Uytterhoeven,
Krzysztof Kozlowski, Lorenzo Pieralisi, Manivannan Sadhasivam,
Rob Herring, Yoshihiro Shimoda, devicetree, linux-arm-kernel,
linux-doc, linux-kernel, linux-renesas-soc
In-Reply-To: <20260618220427.14325-1-marek.vasut+renesas@mailbox.org>
The GIC600 implementation is now known to be used on multiple 64-bit
SoCs, where it has address width for AXI or APB interface configured
to 32 bit, and it can access only the first 4GiB of physical address
space.
Rework the handling of the quirk to work around this limitation such
that new entries can be added purely as new compatible strings, with
no need to add additional functions or new its_quirk array entries.
Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
V2: New patch
---
Cc: "Krzysztof Wilczyński" <kwilczynski@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: Manivannan Sadhasivam <mani@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-doc@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
---
drivers/irqchip/irq-gic-v3-its.c | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index b57d81ad33a0a..8ec2175b78288 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -4890,10 +4890,17 @@ static bool __maybe_unused its_enable_quirk_hip09_162100801(void *data)
return true;
}
-static bool __maybe_unused its_enable_rk3568002(void *data)
+static const char * const dma_32bit_impaired_platforms[] = {
+#ifdef CONFIG_ROCKCHIP_ERRATUM_3568002
+ "rockchip,rk3566",
+ "rockchip,rk3568",
+#endif
+ NULL,
+};
+
+static bool __maybe_unused its_enable_dma32(void *data)
{
- if (!of_machine_is_compatible("rockchip,rk3566") &&
- !of_machine_is_compatible("rockchip,rk3568"))
+ if (!of_machine_compatible_match(dma_32bit_impaired_platforms))
return false;
gfp_flags_quirk |= GFP_DMA32;
@@ -4968,14 +4975,12 @@ static const struct gic_quirk its_quirks[] = {
.property = "dma-noncoherent",
.init = its_set_non_coherent,
},
-#ifdef CONFIG_ROCKCHIP_ERRATUM_3568002
{
- .desc = "ITS: Rockchip erratum RK3568002",
+ .desc = "ITS: Broken GIC600 integration limited to 32bit PA",
.iidr = 0x0201743b,
.mask = 0xffffffff,
- .init = its_enable_rk3568002,
+ .init = its_enable_dma32,
},
-#endif
{
}
};
--
2.53.0
^ permalink raw reply related
* [PATCH v2 1/4] PCI: rcar-gen4: Configure AXIINTC if iMSI-RX not used
From: Marek Vasut @ 2026-06-18 22:01 UTC (permalink / raw)
To: linux-pci
Cc: Marek Vasut, Yoshihiro Shimoda, Krzysztof Wilczyński,
Bjorn Helgaas, Catalin Marinas, Conor Dooley, Geert Uytterhoeven,
Krzysztof Kozlowski, Lorenzo Pieralisi, Manivannan Sadhasivam,
Marc Zyngier, Rob Herring, devicetree, linux-arm-kernel,
linux-doc, linux-kernel, linux-renesas-soc
In-Reply-To: <20260618220427.14325-1-marek.vasut+renesas@mailbox.org>
In case MSI are enabled, but DWC built-in iMSI-RX is not in use, the
MSI are handled via GIC ITS. Configure all controller MSI registers
fully.
Set or clear MSI capability register MSICAP0 MSI enable MSIE bit and
PCIe Interrupt Status 0 Enable register PCIEINTSTS0EN MSI interrupt
enable MSI_CTRL_INT bit according to MSI enable state, set both bits
if MSI are enabled, clear both bits if MSI are disabled.
If MSI are disabled, or MSI are enabled and iMSI-RX is used, then
deconfigure AXIINTCADDR and AXIINTCCONT to 0, which disables any
pass through of MSI TLPs onto the AXI bus and then further into
GIC ITS translation registers.
If MSI are enabled and iMSI-RX is not used, the configure AXIINTCADDR
with target address of GIC ITS translation registers, and configure
AXIINTCCONT to enable MSI TLP pass through onto AXI bus and into the
GIC ITS. This specific configuration allows handling of MSI via the
GIC ITS instead of integrated iMSI-RX.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
NOTE: This would not be possible without prior work from Shimoda-san
---
Cc: "Krzysztof Wilczyński" <kwilczynski@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: Manivannan Sadhasivam <mani@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-doc@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
---
V2: Pull GITS_TRANSLATER address from DT, which also fixes missing +0x40
offset of the GITS_TRANSLATER register
---
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 118 +++++++++++++++++++-
1 file changed, 113 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
index 8b03c42f8c84c..6300ab4dc38b3 100644
--- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
@@ -13,8 +13,11 @@
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
+#include <linux/irqchip/arm-gic-v3.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
@@ -31,6 +34,10 @@
#define DEVICE_TYPE_RC BIT(4)
#define BIFUR_MOD_SET_ON BIT(0)
+/* MSI Capability */
+#define MSICAP0 0x0050
+#define MSICAP0_MSIE BIT(16)
+
/* PCIe Interrupt Status 0 */
#define PCIEINTSTS0 0x0084
@@ -55,6 +62,14 @@
#define APP_HOLD_PHY_RST BIT(16)
#define APP_LTSSM_ENABLE BIT(0)
+/* INTC address */
+#define AXIINTCADDR 0x0a00
+
+/* INTC control & mask */
+#define AXIINTCCONT 0x0a04
+#define INTC_EN BIT(31)
+#define INTC_MASK GENMASK(11, 2)
+
/* PCIe Power Management Control */
#define PCIEPWRMNGCTRL 0x0070
#define APP_CLK_REQ_N BIT(11)
@@ -305,13 +320,103 @@ static struct rcar_gen4_pcie *rcar_gen4_pcie_alloc(struct platform_device *pdev)
return rcar;
}
+static int rcar_gen4_pcie_host_msi_addr(struct dw_pcie_rp *pp, u32 *msi_addr)
+{
+ struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
+ struct device_node *msi_node = NULL;
+ struct device *dev = dw->dev;
+ struct resource res;
+ u64 addr;
+ int ret;
+
+ /*
+ * Either the "msi-parent" or the "msi-map" phandle needs to exist
+ * to obtain the MSI node.
+ */
+ of_msi_xlate(dev, &msi_node, 0);
+ if (!msi_node)
+ return -ENODEV;
+
+ /* Check if "msi-parent" or the "msi-map" points to ARM GICv3 ITS. */
+ if (!of_device_is_compatible(msi_node, "arm,gic-v3-its"))
+ return dev_err_probe(dev, -ENODEV, "Compatible MSI controller not found\n");
+
+ /* Derive GITS_TRANSLATER address from GICv3 */
+ ret = of_address_to_resource(msi_node, 0, &res);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "MSI controller resources not obtained\n");
+
+ addr = res.start + GITS_TRANSLATER;
+ if (addr >= SZ_4G)
+ return dev_err_probe(dev, -EINVAL, "MSI controller address above 32bit range\n");
+
+ *msi_addr = addr;
+ return 0;
+}
+
+static int rcar_gen4_pcie_host_msi_init(struct dw_pcie_rp *pp)
+{
+ struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
+ struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
+ u32 val;
+ int ret;
+
+ /* Make sure MSICAP0 MSIE is configured. */
+ val = dw_pcie_readl_dbi(dw, MSICAP0);
+ if (pci_msi_enabled())
+ val |= MSICAP0_MSIE;
+ else
+ val &= ~MSICAP0_MSIE;
+ dw_pcie_writel_dbi(dw, MSICAP0, val);
+
+ if (!pci_msi_enabled() || pp->use_imsi_rx) {
+ /* Clear AXIINTC mapping. */
+ writel(0, rcar->base + AXIINTCADDR);
+ writel(0, rcar->base + AXIINTCCONT);
+ } else {
+ ret = rcar_gen4_pcie_host_msi_addr(pp, &val);
+ if (ret)
+ goto err;
+
+ /* Point AXIINTC to GIC ITS and enable. */
+ writel(val, rcar->base + AXIINTCADDR);
+ writel(INTC_EN | INTC_MASK, rcar->base + AXIINTCCONT);
+ }
+
+ /* Configure MSI interrupt signal */
+ val = readl(rcar->base + PCIEINTSTS0EN);
+ if (pci_msi_enabled())
+ val |= MSI_CTRL_INT;
+ else
+ val &= ~MSI_CTRL_INT;
+ writel(val, rcar->base + PCIEINTSTS0EN);
+
+ return 0;
+
+err:
+ /* Deconfigure MSICAP0 MSIE. */
+ val = dw_pcie_readl_dbi(dw, MSICAP0);
+ val &= ~MSICAP0_MSIE;
+ dw_pcie_writel_dbi(dw, MSICAP0, val);
+
+ /* Clear AXIINTC mapping. */
+ writel(0, rcar->base + AXIINTCADDR);
+ writel(0, rcar->base + AXIINTCCONT);
+
+ /* Deconfigure MSI interrupt signal */
+ val = readl(rcar->base + PCIEINTSTS0EN);
+ val &= ~MSI_CTRL_INT;
+ writel(val, rcar->base + PCIEINTSTS0EN);
+
+ return ret;
+}
+
/* Host mode */
static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp)
{
struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
int ret;
- u32 val;
gpiod_set_value_cansleep(dw->pe_rst, 1);
@@ -328,16 +433,19 @@ static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp)
dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_0, 0x0);
dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_1, 0x0);
- /* Enable MSI interrupt signal */
- val = readl(rcar->base + PCIEINTSTS0EN);
- val |= MSI_CTRL_INT;
- writel(val, rcar->base + PCIEINTSTS0EN);
+ ret = rcar_gen4_pcie_host_msi_init(pp);
+ if (ret)
+ goto err;
msleep(PCIE_T_PVPERL_MS); /* pe_rst requires 100msec delay */
gpiod_set_value_cansleep(dw->pe_rst, 0);
return 0;
+
+err:
+ rcar_gen4_pcie_common_deinit(rcar);
+ return ret;
}
static void rcar_gen4_pcie_host_deinit(struct dw_pcie_rp *pp)
--
2.53.0
^ permalink raw reply related
* [PATCH v2 3/4] irqchip/gic-v3: Add Renesas R-Car Gen4 erratum workaround
From: Marek Vasut @ 2026-06-18 22:02 UTC (permalink / raw)
To: linux-pci
Cc: Marek Vasut, Yoshihiro Shimoda, Krzysztof Wilczyński,
Bjorn Helgaas, Catalin Marinas, Conor Dooley, Geert Uytterhoeven,
Krzysztof Kozlowski, Lorenzo Pieralisi, Manivannan Sadhasivam,
Marc Zyngier, Rob Herring, devicetree, linux-arm-kernel,
linux-doc, linux-kernel, linux-renesas-soc
In-Reply-To: <20260618220427.14325-1-marek.vasut+renesas@mailbox.org>
Renesas R-Car S4/V4H/V4M GIC600 integration has address width for AXI
or APB interface configured to 32 bit, it can therefore access only
the first 4 GiB of physical address space. This information comes from
R-Car V4H Interface Specification sheet, there is currently no technical
update number assigned to this limitation. Further input from hardware
engineer indicates that this limitation also applies to R-Car S4 and V4M.
Name the limitation GEN4GICITS1, and add a driver quirk to mitigate this
limitation.
The quirk is keyed on the combination of the GIC implementation
and the platform identification in the device tree.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
NOTE: This would not be possible without prior work from Shimoda-san
https://lore.kernel.org/all/20240214052050.1966439-1-yoshihiro.shimoda.uh@renesas.com/
---
Cc: "Krzysztof Wilczyński" <kwilczynski@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: Manivannan Sadhasivam <mani@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-doc@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
---
V2: Minimize the patch based on newly added patch in the series and
only add entries into dma_32bit_impaired_platforms array. Update
second paragraph of commit message slightly.
---
Documentation/arch/arm64/silicon-errata.rst | 1 +
arch/arm64/Kconfig | 9 +++++++++
drivers/irqchip/irq-gic-v3-its.c | 5 +++++
3 files changed, 15 insertions(+)
diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst
index 014aa1c215a16..b0c68b64f5ac2 100644
--- a/Documentation/arch/arm64/silicon-errata.rst
+++ b/Documentation/arch/arm64/silicon-errata.rst
@@ -352,6 +352,7 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| Qualcomm Tech. | Kryo4xx Gold | N/A | ARM64_ERRATUM_1286807 |
+----------------+-----------------+-----------------+-----------------------------+
+| Renesas | S4/V4H/V4M | N/A | RENESAS_ERRATUM_GEN4GICITS1 |
+----------------+-----------------+-----------------+-----------------------------+
| Rockchip | RK3588 | #3588001 | ROCKCHIP_ERRATUM_3588001 |
+----------------+-----------------+-----------------+-----------------------------+
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index b3afe0688919b..b9e17ce475e61 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -1382,6 +1382,15 @@ config NVIDIA_CARMEL_CNP_ERRATUM
If unsure, say Y.
+config RENESAS_ERRATUM_GEN4GICITS1
+ bool "Renesas R-Car Gen4: GIC600 can not access physical addresses above 4 GiB"
+ default y
+ help
+ The Renesas R-Car Gen4 S4/V4H/V4M GIC600 SoC integrations have AXI
+ addressing limited to the first 32-bit of physical address space.
+
+ If unsure, say Y.
+
config ROCKCHIP_ERRATUM_3568002
bool "Rockchip 3568002: GIC600 can not access physical addresses higher than 4GB"
default y
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 8ec2175b78288..96b26822e5bd2 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -4891,6 +4891,11 @@ static bool __maybe_unused its_enable_quirk_hip09_162100801(void *data)
}
static const char * const dma_32bit_impaired_platforms[] = {
+#ifdef CONFIG_RENESAS_ERRATUM_GEN4GICITS1
+ "renesas,r8a779f0",
+ "renesas,r8a779g0",
+ "renesas,r8a779h0",
+#endif
#ifdef CONFIG_ROCKCHIP_ERRATUM_3568002
"rockchip,rk3566",
"rockchip,rk3568",
--
2.53.0
^ permalink raw reply related
* [PATCH v2 4/4] arm64: dts: renesas: r8a779g0: Add GICv3 ITS and update PCIe nodes
From: Marek Vasut @ 2026-06-18 22:02 UTC (permalink / raw)
To: linux-pci
Cc: Marek Vasut, Yoshihiro Shimoda, Krzysztof Wilczyński,
Bjorn Helgaas, Catalin Marinas, Conor Dooley, Geert Uytterhoeven,
Krzysztof Kozlowski, Lorenzo Pieralisi, Manivannan Sadhasivam,
Marc Zyngier, Rob Herring, devicetree, linux-arm-kernel,
linux-doc, linux-kernel, linux-renesas-soc
In-Reply-To: <20260618220427.14325-1-marek.vasut+renesas@mailbox.org>
This SoC implements GIC600 with GICv3 ITS and PCIe host mode on this
SoC can use it. Add GIC ITS node into GIC node, update interrupt-map
and add msi-map into PCIe controller node.
The GIC ITS does have master interface to issue transactions to RAM.
The interface does support cacheable transactions, however, it does
not support shareable attribute, because the AXI port signals are tied
to inactive in this implementation. Therefore, add "dma-noncoherent"
DT property into the GIC ITS subnode.
The GIC redistributor does not have cacheable/shareable, therefore
add "dma-noncoherent" DT property into the GIC node.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
NOTE: This would not be possible without prior work from Shimoda-san
https://lore.kernel.org/all/20240214052144.1966569-1-yoshihiro.shimoda.uh@renesas.com/
---
Cc: "Krzysztof Wilczyński" <kwilczynski@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: Manivannan Sadhasivam <mani@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-doc@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
---
V2: No change
---
arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 31 ++++++++++++++++-------
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index 3a8af825bb253..82e864acf2601 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -792,6 +792,7 @@ pciec0: pcie@e65d0000 {
resets = <&cpg 624>;
reset-names = "pwr";
max-link-speed = <4>;
+ msi-parent = <&its>;
num-lanes = <2>;
#address-cells = <3>;
#size-cells = <2>;
@@ -802,10 +803,10 @@ pciec0: pcie@e65d0000 {
dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic 0 0 GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic 0 0 GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic 0 0 GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>;
snps,enable-cdm-check;
status = "disabled";
@@ -839,6 +840,7 @@ pciec1: pcie@e65d8000 {
resets = <&cpg 625>;
reset-names = "pwr";
max-link-speed = <4>;
+ msi-parent = <&its>;
num-lanes = <2>;
#address-cells = <3>;
#size-cells = <2>;
@@ -849,10 +851,10 @@ pciec1: pcie@e65d8000 {
dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic 0 0 GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic 0 0 GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic 0 0 GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
snps,enable-cdm-check;
status = "disabled";
@@ -2131,11 +2133,22 @@ ipmmu_mm: iommu@eefc0000 {
gic: interrupt-controller@f1000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
- #address-cells = <0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
interrupt-controller;
reg = <0x0 0xf1000000 0 0x20000>,
<0x0 0xf1060000 0 0x110000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ dma-noncoherent;
+
+ ranges = <0x0 0x0 0x0 0xf1000000 0x0 0x200000>;
+
+ its: msi-controller@40000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x40000 0x0 0x20000>;
+ dma-noncoherent;
+ msi-controller;
+ };
};
gpu: gpu@fd000000 {
--
2.53.0
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