* Re: [PATCH v4 1/3] dt-bindings: phy: nuvoton,ma35d1-usb2-phy: extend for dual-port and OTG
From: sashiko-bot @ 2026-07-20 10:28 UTC (permalink / raw)
To: Joey Lu
Cc: robh, neil.armstrong, conor+dt, vkoul, olteanv, linux-phy,
devicetree
In-Reply-To: <20260720102222.251179-2-a0987203069@gmail.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The `#phy-cells` property uses an `enum` constraint instead of a `const` constraint, violating Device Tree Bindings guidelines.
--
--- Patch [1]: [PATCH v4 1/3] dt-bindings: phy: nuvoton,ma35d1-usb2-phy: extend for dual-port and OTG ---
commit 676c30318df404b9fb25b710326b359f41a5cf10
Author: Joey Lu <a0987203069@gmail.com>
dt-bindings: phy: nuvoton,ma35d1-usb2-phy: extend for dual-port and OTG
This commit updates the Nuvoton MA35D1 USB2 PHY binding to support dual ports
managed by the same hardware block. It modifies the #phy-cells property to
allow values of 0 or 1 for port selection, while preserving backward
compatibility. It also introduces optional properties for resistor calibration
trim codes and over-current detect polarity.
> diff --git a/Documentation/devicetree/bindings/phy/nuvoton,ma35d1-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/nuvoton,ma35d1-usb2-phy.yaml
> index fff858c909a06..1bd22dd0e5fc5 100644
> --- a/Documentation/devicetree/bindings/phy/nuvoton,ma35d1-usb2-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/nuvoton,ma35d1-usb2-phy.yaml
[ ... ]
> @@ -15,7 +27,12 @@ properties:
> - nuvoton,ma35d1-usb2-phy
>
> "#phy-cells":
> - const: 0
> + enum: [0, 1]
[Severity: Low]
Does this violate the device tree binding subsystem rules for cell-count
properties? The guidelines specify that each cell-count property must have
a const constraint matching the hardware, rather than an enum constraint.
If the hardware requires different configurations depending on the variant
or backward compatibility, should this be enforced using conditional if-then
blocks instead of allowing either value unconditionally?
> + description:
> + When 0, the node exposes PHY0 only and consumers reference it
> + with no cell argument. When 1, the single cell selects the port,
> + with 0 for the OTG port (USB0, shared with DWC2 gadget controller)
> + and 1 for the host-only port (USB1).
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260720102222.251179-1-a0987203069@gmail.com?part=1
^ permalink raw reply
* Re: [PATCH v4 2/3] arm64: dts: nuvoton: ma35d1: add USB controllers and dual-port PHY node
From: sashiko-bot @ 2026-07-20 10:32 UTC (permalink / raw)
To: Joey Lu
Cc: olteanv, linux-phy, vkoul, robh, devicetree, neil.armstrong,
conor+dt
In-Reply-To: <20260720102222.251179-3-a0987203069@gmail.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The `usb_phy` node is placed inside a `simple-bus` without a `reg` property, triggering a `simple_bus_reg` dtc warning.
--
--- Patch [2]: [PATCH v4 2/3] arm64: dts: nuvoton: ma35d1: add USB controllers and dual-port PHY node ---
commit cf3aea78de55506203f48556a640406a6dccb9bc
Author: Joey Lu <a0987203069@gmail.com>
arm64: dts: nuvoton: ma35d1: add USB controllers and dual-port PHY node
This commit adds the USB subsystem nodes for the MA35D1 SoC, including the
DWC2 gadget, EHCI/OHCI hosts, and a dual-port PHY node. It also updates
the board files to configure pinctrl and enable the nodes.
> diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
> index 7228ad4735b5c..5a7a39b1b5143 100644
> --- a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
> +++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
> @@ -88,6 +88,14 @@ sys: system-management@40460000 {
> #reset-cells = <1>;
> };
>
> + usb_phy: usb-phy {
[Severity: Low]
Does placing this node inside the soc simple-bus without a reg property
trigger a simple_bus_reg dtc compiler warning?
The Device Tree specification states that children of a simple-bus must
represent memory-mapped devices, so nodes without a reg or ranges property
usually trigger a warning when placed directly under a simple-bus.
> + compatible = "nuvoton,ma35d1-usb2-phy";
> + clocks = <&clk HUSBH0_GATE>;
> + nuvoton,sys = <&sys>;
> + #phy-cells = <1>;
> + status = "disabled";
> + };
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260720102222.251179-1-a0987203069@gmail.com?part=2
^ permalink raw reply
* Re: [PATCH 3/4] ASoC: fsl_asrc: expose individual DAIs per conversion pair
From: sashiko-bot @ 2026-07-20 10:33 UTC (permalink / raw)
To: shengjiu.wang; +Cc: conor+dt, Frank.Li, imx, devicetree, robh
In-Reply-To: <20260720095450.1618747-4-shengjiu.wang@oss.nxp.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The newly registered DAIs (`paira`, `pairb`, `pairc`) share the exact same `dma_params_tx` and `dma_params_rx` structures, causing a data race and potential DMA misconfiguration when multiple streams are configured concurrently.
--
--- Patch [3]: [PATCH 3/4] ASoC: fsl_asrc: expose individual DAIs per conversion pair ---
commit 71178f6edf2667b8ee88b95ef47b739e170cca4b
Author: Shengjiu Wang <shengjiu.wang@nxp.com>
ASoC: fsl_asrc: expose individual DAIs per conversion pair
The i.MX ASRC hardware supports three independent conversion pairs
(A, B, C). This commit replaces the single fsl_asrc_dai instance
with an array of three DAI drivers, one per pair, allowing them
to be routed to separate audio paths simultaneously.
> diff --git a/sound/soc/fsl/fsl_asrc.c b/sound/soc/fsl/fsl_asrc.c
> index 0b28bcfa47fed..f83d6cdc6412d 100644
> --- a/sound/soc/fsl/fsl_asrc.c
> +++ b/sound/soc/fsl/fsl_asrc.c
[ ... ]
> @@ -1404,7 +1453,7 @@ static int fsl_asrc_probe(struct platform_device *pdev)
> goto err_pm_get_sync;
>
> ret = devm_snd_soc_register_component(&pdev->dev, &fsl_asrc_component,
> - &fsl_asrc_dai, 1);
> + fsl_asrc_dai, ARRAY_SIZE(fsl_asrc_dai));
[Severity: High]
Since this registers multiple DAIs to enable concurrent stream access, can this
cause a data race with the shared DMA parameters?
In fsl_asrc_dai_probe(), all three DAIs are assigned pointers to the exact same
shared DMA parameter structures:
snd_soc_dai_init_dma_data(dai, &asrc->dma_params_tx,
&asrc->dma_params_rx);
When multiple streams are configured concurrently, they will race to overwrite
these shared parameters without locking.
For example, in fsl_asrc_dma_hw_params():
dma_params_fe = snd_soc_dai_get_dma_data(snd_soc_rtd_to_cpu(rtd, 0), substream);
dma_params_fe->addr = asrc->paddr + asrc->get_fifo_addr(!dir, index);
dma_params_fe->maxburst = dma_params_be->maxburst;
Could this concurrent mutation cause DMA channels to be programmed with incorrect
FIFO addresses or maxburst values, resulting in audio cross-talk or DMA engine
errors?
> if (ret) {
> dev_err(&pdev->dev, "failed to register ASoC DAI\n");
> goto err_pm_get_sync;
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260720095450.1618747-1-shengjiu.wang@oss.nxp.com?part=3
^ permalink raw reply
* Re: [PATCH v5 01/17] spi: dt-bindings: add spi-max-post-config-frequency-hz property
From: Santhosh Kumar K @ 2026-07-20 10:34 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: broonie, robh, krzk+dt, conor+dt, miquel.raynal, richard,
vigneshr, pratyush, mwalle, takahiro.kuwano, linux-spi,
devicetree, linux-kernel, linux-mtd, praneeth, u-kumar1, a-dutta,
Conor Dooley, s-k6
In-Reply-To: <1a681388-5ffe-4df9-83bf-a7622ee489bf@kernel.org>
On 20/07/26 15:39, Krzysztof Kozlowski wrote:
> On 20/07/2026 10:48, Santhosh Kumar K wrote:
>>
>>
>> On 20/07/26 13:10, Krzysztof Kozlowski wrote:
>>> On 20/07/2026 09:38, Santhosh Kumar K wrote:
>>>>>> diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
>>>>>> index 880a9f624566..12211f8c9f7d 100644
>>>>>> --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
>>>>>> +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
>>>>>> @@ -45,6 +45,11 @@ properties:
>>>>>> description:
>>>>>> Maximum SPI clocking speed of the device in Hz.
>>>>>>
>>>>>> + spi-max-post-config-frequency-hz:
>>>>>> + description:
>>>>>> + Maximum SPI clock frequency in Hz achievable after controller-side
>>>>>> + configuration.
>>>>>
>>>>> How did you implement my feedback?
>>>>
>>>> Three points from your feedback:
>>>>
>>>> 1. -hz suffix: added
>>>>
>>>> 2. Array property: I still lean towards keeping this as a scalar for
>>>> now, as we don't have a concrete use case for multiple values today, and
>>>> supporting two frequencies should be sufficient for the foreseeable
>>>> future. I had responded to this in the v4 discussion as well, you may
>>>> have missed that response.
>>>>
>>>> 3. maxItems: Since the property remains a scalar, I have not added maxItems.
>>>
>>> So how did you make this property scalar?
>>
>> The -hz suffix constraints the property to a uint32 scalar through the
>> DT schema framework's property-units.yaml.
>
> Hm, where? I completely missed that, can you point me to the specific
> line? I see clearly that it is not a scalar.
>
>
>>
>> Adding an explicit $ref or maxItems for a unit-suffixed property is
>> rejected by dtbs_check with:
>> - "Standard unit suffix properties don't need a type $ref"
>
> This I did not propose - the type is fixed.
>
>> - "Scalar properties should not have array keywords"
>
> Cannot reproduce it.
I overlooked this. You are right, and I apologize for the incorrect
explanation.
The -hz suffix maps to uint32-matrix in property-units.yaml, not a
scalar. Without 'maxItems: 1', the property can accept multiple values.
I should have verified this before responding. Sorry again!
I'll add 'maxItems: 1' in the next version.
Thanks,
Santhosh.
>
> Best regards,
> Krzysztof
^ permalink raw reply
* Re: [PATCH v4 3/3] phy: nuvoton: phy-ma35d1-usb2: extend to dual-port with OTG support
From: sashiko-bot @ 2026-07-20 10:37 UTC (permalink / raw)
To: Joey Lu
Cc: olteanv, neil.armstrong, linux-phy, conor+dt, devicetree, robh,
vkoul
In-Reply-To: <20260720102222.251179-4-a0987203069@gmail.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] The driver fails to clear the MISCFCR0_UHOVRCURH hardware bit when the `nuvoton,oc-active-high` device tree property is absent, inheriting potentially incorrect bootloader state.
- [Medium] The driver ignores the return value of regmap_read(), potentially evaluating uninitialized stack memory if the read fails.
--
--- Patch [3]: [PATCH v4 3/3] phy: nuvoton: phy-ma35d1-usb2: extend to dual-port with OTG support ---
Note: The format of this review is altered due to strict recitation restrictions. Instead of inline patch quoting, a free-form summary of the findings is provided below.
Commit: 678e65678c8fb5e2363eb1d51e7a9a2159ca8dd9
Author: Joey Lu <a0987203069@gmail.com>
Subject: phy: nuvoton: phy-ma35d1-usb2: extend to dual-port with OTG support
This commit extends the driver to manage both USB ports and updates the init
polling logic to handle host-mode and device-mode clock stability. It also
registers a read-only USB role switch and adds support for the rcalcode and
oc-active-high device tree properties.
[Severity: Medium]
In ma35_usb_phy_init() and ma35_role_sw_get(), the return value of
regmap_read() is not checked before evaluating the 'val' stack variable. If
the register read fails, might the driver evaluate uninitialized memory,
causing it to return an unpredictable USB role or falsely bypass the PHY
initialization?
[Severity: High]
In ma35_usb_phy_probe(), the driver sets the MISCFCR0_UHOVRCURH bit if the
"nuvoton,oc-active-high" property is present, but lacks an else path to clear
it if the property is absent. Does this allow the hardware to incorrectly
inherit an inverted over-current polarity from the bootloader or a prior
kernel instance?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260720102222.251179-1-a0987203069@gmail.com?part=3
^ permalink raw reply
* [PATCH v5 1/2] of: kobj: export of_node_ktype for use by modules
From: Xu Yang @ 2026-07-20 10:47 UTC (permalink / raw)
To: gregkh, rafael, dakr, robh, saravanak, andriy.shevchenko
Cc: bartosz.golaszewski, driver-core, linux-kernel, devicetree, imx
From: Xu Yang <xu.yang_2@nxp.com>
of_node_init() is a static inline that references of_node_ktype when
CONFIG_OF_KOBJ=y. Any module that calls of_node_init() will therefore
have an unresolved reference to of_node_ktype at load time, because
the symbol is defined in drivers/of/kobj.c but was never exported.
This causes a modpost build error when CONFIG_OF_KOBJ=y and
CONFIG_DRIVER_PE_KUNIT_TEST=m:
ERROR: modpost: "of_node_ktype"
[drivers/base/test/property-entry-test.ko] undefined!
Add EXPORT_SYMBOL_GPL(of_node_ktype) so that GPL-licensed modules
such as the KUnit property-entry test can call of_node_init() without
hitting this linker error.
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202607181651.RnUuV8n6-lkp@intel.com/
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
Changes in v5:
- new one
---
drivers/of/kobj.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/of/kobj.c b/drivers/of/kobj.c
index 1bb61a2c3399..eacc53324d62 100644
--- a/drivers/of/kobj.c
+++ b/drivers/of/kobj.c
@@ -27,6 +27,7 @@ static void of_node_release(struct kobject *kobj)
const struct kobj_type of_node_ktype = {
.release = of_node_release,
};
+EXPORT_SYMBOL_GPL(of_node_ktype);
static ssize_t of_node_property_read(struct file *filp, struct kobject *kobj,
const struct bin_attribute *bin_attr, char *buf,
--
2.34.1
^ permalink raw reply related
* Re: [PATCH 4/4] ASoC: fsl_easrc: expose individual DAIs per conversion context
From: sashiko-bot @ 2026-07-20 10:43 UTC (permalink / raw)
To: shengjiu.wang; +Cc: imx, devicetree, Frank.Li, robh, conor+dt
In-Reply-To: <20260720095450.1618747-5-shengjiu.wang@oss.nxp.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Concurrent streams will cause a data race on the shared `dma_params_tx` and `dma_params_rx` structures, leading to incorrect DMA FIFO address configuration and state corruption.
--
--- Patch [4]: [PATCH 4/4] ASoC: fsl_easrc: expose individual DAIs per conversion context ---
commit 8f522766ccdfc101a1c60ab6f34e2623d03f39d0
Author: Shengjiu Wang <shengjiu.wang@nxp.com>
ASoC: fsl_easrc: expose individual DAIs per conversion context
The i.MX EASRC hardware supports four independent conversion contexts
(A, B, C, D). The driver previously registered a single DAI with generic
stream names "ASRC-Playback" and "ASRC-Capture", which prevents
individual contexts from being routed to separate audio paths
simultaneously. This commit replaces the single fsl_easrc_dai instance
with an array of four DAI drivers.
> diff --git a/sound/soc/fsl/fsl_easrc.c b/sound/soc/fsl/fsl_easrc.c
> index 15a3424967601..dd0c3046a0075 100644
> --- a/sound/soc/fsl/fsl_easrc.c
> +++ b/sound/soc/fsl/fsl_easrc.c
[ ... ]
> @@ -2245,7 +2317,7 @@ static int fsl_easrc_probe(struct platform_device *pdev)
> regcache_cache_only(easrc->regmap, true);
>
> ret = devm_snd_soc_register_component(dev, &fsl_easrc_component,
> - &fsl_easrc_dai, 1);
> + fsl_easrc_dai, ARRAY_SIZE(fsl_easrc_dai));
[Severity: High]
When multiple DAIs are registered and active concurrently, can this cause a
data race on the shared DMA parameters?
Since all four DAIs share the same operations, fsl_easrc_dai_probe()
initializes them all with the exact same pointers:
fsl_easrc_dai_probe() {
...
snd_soc_dai_init_dma_data(cpu_dai,
&easrc->dma_params_tx,
&easrc->dma_params_rx);
...
}
If an application opens multiple PCM devices simultaneously, won't their
concurrent hardware parameters operations modify the shared parameters
without locking?
fsl_asrc_dma_hw_params() {
...
dma_params_fe = snd_soc_dai_get_dma_data(snd_soc_rtd_to_cpu(rtd, 0), substream);
dma_params_fe->addr = asrc->paddr + asrc->get_fifo_addr(!dir, index);
dma_params_fe->maxburst = dma_params_be->maxburst;
...
}
Could this lead to incorrect DMA FIFO address configuration and state corruption
across the different DAI contexts?
> if (ret) {
> dev_err(dev, "failed to register ASoC DAI\n");
> goto err_pm_disable;
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260720095450.1618747-1-shengjiu.wang@oss.nxp.com?part=4
^ permalink raw reply
* [PATCH v5 2/2] device property: add test cases for fwnode_for_each_child_node()
From: Xu Yang @ 2026-07-20 10:47 UTC (permalink / raw)
To: gregkh, rafael, dakr, robh, saravanak, andriy.shevchenko
Cc: bartosz.golaszewski, driver-core, linux-kernel, devicetree, imx
In-Reply-To: <20260720104730.1285552-1-xu.yang_2@oss.nxp.com>
From: Xu Yang <xu.yang_2@nxp.com>
Add test cases for fwnode_for_each_child_node() API.
Test command:
$ ./tools/testing/kunit/kunit.py run property-entry
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
Changes in v5:
- add patch#1 to fix "of_node_ktype undefined error"
---
drivers/base/test/Kconfig | 1 +
drivers/base/test/property-entry-test.c | 136 ++++++++++++++++++++++++
2 files changed, 137 insertions(+)
diff --git a/drivers/base/test/Kconfig b/drivers/base/test/Kconfig
index 1ecf0791241a..542ce07530a1 100644
--- a/drivers/base/test/Kconfig
+++ b/drivers/base/test/Kconfig
@@ -17,6 +17,7 @@ config DM_KUNIT_TEST
config DRIVER_PE_KUNIT_TEST
tristate "KUnit Tests for property entry API" if !KUNIT_ALL_TESTS
depends on KUNIT
+ select OF
default KUNIT_ALL_TESTS
config DRIVER_SWNODE_KUNIT_TEST
diff --git a/drivers/base/test/property-entry-test.c b/drivers/base/test/property-entry-test.c
index a8657eb06f94..a3d1caf28cc7 100644
--- a/drivers/base/test/property-entry-test.c
+++ b/drivers/base/test/property-entry-test.c
@@ -4,6 +4,8 @@
// Copyright 2019 Google LLC.
#include <kunit/test.h>
+
+#include <linux/of.h>
#include <linux/property.h>
#include <linux/types.h>
@@ -489,6 +491,139 @@ static void pe_test_reference(struct kunit *test)
software_node_unregister_node_group(group);
}
+static struct fwnode_handle *create_device_node(struct kunit *test,
+ const char *name,
+ const char *full_name,
+ struct device_node *parent)
+{
+ struct device_node *node;
+
+ node = kunit_kzalloc(test, sizeof(*node), GFP_KERNEL);
+ KUNIT_ASSERT_NOT_ERR_OR_NULL(test, node);
+
+ node->name = kunit_kstrdup(test, name, GFP_KERNEL);
+ node->full_name = kunit_kstrdup(test, full_name, GFP_KERNEL);
+
+ if (parent) {
+ node->sibling = parent->child;
+ /* set the node as the first child of the parent */
+ parent->child = node;
+ node->parent = parent;
+ }
+
+ of_node_init(node);
+ return of_fwnode_handle(node);
+}
+
+/* Verifies that fwnode_for_each_child_node() can output correct children */
+static void pe_test_child_iteration(struct kunit *test)
+{
+ struct fwnode_handle *of_node, *of_node1;
+ struct fwnode_handle *sw_node, *sw_node1;
+ struct fwnode_handle *child;
+ int error, i, num;
+
+ static const struct software_node node = { .name = "sw" };
+ static const struct software_node node1 = { .name = "sw-1", .parent = &node};
+ static const struct software_node node2 = { .name = "sw-2", .parent = &node};
+ static const struct software_node node3 = { .name = "sw-3", .parent = &node};
+ static const struct software_node *group[] = { &node, &node1, &node2, &node3, NULL };
+
+ static const char * const of_child_array[] = { "of-1", "of-2", "of-3" };
+ static const char * const sw_child_array[] = { "sw-1", "sw-2", "sw-3" };
+ static const char * const of_sw_child_array[] = { "of-1", "of-2", "of-3",
+ "sw-1", "sw-2", "sw-3" };
+ static const char * const sw_of_child_array[] = { "sw-1", "sw-2", "sw-3",
+ "of-1", "of-2", "of-3" };
+
+ /* 1. Test OF node child iteration */
+
+ of_node = create_device_node(test, "of", "of", NULL);
+ create_device_node(test, "of", "of-3", to_of_node(of_node));
+ create_device_node(test, "of", "of-2", to_of_node(of_node));
+ of_node1 = create_device_node(test, "of", "of-1", to_of_node(of_node));
+
+ i = 0;
+ num = ARRAY_SIZE(of_child_array);
+ fwnode_for_each_child_node(of_node, child) {
+ KUNIT_ASSERT_LT(test, i, num);
+ KUNIT_EXPECT_STREQ(test, of_child_array[i++], fwnode_get_name(child));
+ }
+ KUNIT_EXPECT_PTR_EQ(test, child, NULL);
+
+ /* 2. Test SW node child iteration */
+
+ error = software_node_register_node_group(group);
+ KUNIT_ASSERT_EQ(test, error, 0);
+
+ sw_node = software_node_fwnode(&node);
+
+ i = 0;
+ num = ARRAY_SIZE(sw_child_array);
+ fwnode_for_each_child_node(sw_node, child) {
+ KUNIT_ASSERT_LT(test, i, num);
+ KUNIT_EXPECT_STREQ(test, sw_child_array[i++], fwnode_get_name(child));
+ }
+ KUNIT_EXPECT_PTR_EQ(test, child, NULL);
+
+ /* 3. Test OF (primary) + SW (secondary) node child iteration */
+
+ of_node->secondary = sw_node;
+ sw_node->secondary = ERR_PTR(-ENODEV);
+
+ i = 0;
+ num = ARRAY_SIZE(of_sw_child_array);
+ fwnode_for_each_child_node(of_node, child) {
+ KUNIT_ASSERT_LT(test, i, num);
+ KUNIT_EXPECT_STREQ(test, of_sw_child_array[i++], fwnode_get_name(child));
+ }
+ KUNIT_EXPECT_PTR_EQ(test, child, NULL);
+
+ /* 4. Test SW (primary) + OF (secondary) node child iteration */
+
+ sw_node->secondary = of_node;
+ of_node->secondary = ERR_PTR(-ENODEV);
+
+ i = 0;
+ num = ARRAY_SIZE(sw_of_child_array);
+ fwnode_for_each_child_node(sw_node, child) {
+ KUNIT_ASSERT_LT(test, i, num);
+ KUNIT_EXPECT_STREQ(test, sw_of_child_array[i++], fwnode_get_name(child));
+ }
+ KUNIT_EXPECT_PTR_EQ(test, child, NULL);
+
+ /* 5. Test OF (primary) + SW (secondary, but no children) node child iteration */
+
+ sw_node1 = software_node_fwnode(&node1);
+ of_node->secondary = sw_node1;
+ sw_node->secondary = ERR_PTR(-ENODEV);
+
+ i = 0;
+ num = ARRAY_SIZE(of_child_array);
+ fwnode_for_each_child_node(of_node, child) {
+ KUNIT_ASSERT_LT(test, i, num);
+ KUNIT_EXPECT_STREQ(test, of_child_array[i++], fwnode_get_name(child));
+ }
+ KUNIT_EXPECT_PTR_EQ(test, child, NULL);
+
+ /* 6. Test SW (primary) + OF (secondary, but no children) node child iteration */
+
+ sw_node->secondary = of_node1;
+ of_node->secondary = ERR_PTR(-ENODEV);
+
+ i = 0;
+ num = ARRAY_SIZE(sw_child_array);
+ fwnode_for_each_child_node(sw_node, child) {
+ KUNIT_ASSERT_LT(test, i, num);
+ KUNIT_EXPECT_STREQ(test, sw_child_array[i++], fwnode_get_name(child));
+ }
+ KUNIT_EXPECT_PTR_EQ(test, child, NULL);
+
+ of_node->secondary = NULL;
+ sw_node->secondary = NULL;
+ software_node_unregister_node_group(group);
+}
+
static struct kunit_case property_entry_test_cases[] = {
KUNIT_CASE(pe_test_uints),
KUNIT_CASE(pe_test_uint_arrays),
@@ -497,6 +632,7 @@ static struct kunit_case property_entry_test_cases[] = {
KUNIT_CASE(pe_test_move_inline_u8),
KUNIT_CASE(pe_test_move_inline_str),
KUNIT_CASE(pe_test_reference),
+ KUNIT_CASE(pe_test_child_iteration),
{ }
};
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v4 3/3] device property: add test cases for fwnode_for_each_child_node()
From: Xu Yang @ 2026-07-20 10:46 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Danilo Krummrich, Xu Yang, linux-acpi, driver-core, linux-kernel,
Daniel Scally, Heikki Krogerus, Sakari Ailus, Greg Kroah-Hartman,
Rafael J. Wysocki, Rob Herring, Saravana Kannan, devicetree
In-Reply-To: <alyMt-ya5skHmhtx@ashevche-desk.local>
Hi Danilo and Andy,
On Sun, Jul 19, 2026 at 11:37:49AM +0300, Andy Shevchenko wrote:
> On Sat, Jul 18, 2026 at 04:18:12PM +0200, Danilo Krummrich wrote:
> > On Thu Jun 11, 2026 at 10:31 PM CEST, Andy Shevchenko wrote:
> > >
> > > Add test cases for fwnode_for_each_child_node() API.
> > >
> > > Test command:
> > > $ ./tools/testing/kunit/kunit.py run property-entry
> > >
> > > Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> > > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> >
> > This patch broke the build [1], hence I dropped it from the queue (but kept the
> > first two patches of this series).
> >
> > of_node_init() can't be used from modules, either it needs EXPORT_SYMBOL_GPL()
> > itself, or of_node_ktype needs to be exported for this kunit test to work.
>
> Oh, thanks for pointing out.
Fix patches are sent:
https://lore.kernel.org/imx/20260720104730.1285552-1-xu.yang_2@oss.nxp.com/
Thanks,
Xu Yang
^ permalink raw reply
* Re: [PATCH v5 1/2] arm64: dts: qcom: sdm845-google: Add dual front IMX355 cameras
From: David Heidelberg @ 2026-07-20 10:49 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Petr Hodina, Richard Acayan, linux-arm-msm, devicetree,
linux-kernel, phone-devel
In-Reply-To: <d8e2c2fe-a504-4ba6-806d-f3923ea0249a@oss.qualcomm.com>
On 20/07/2026 10:24, Konrad Dybcio wrote:
> On 7/19/26 8:03 PM, David Heidelberg via B4 Relay wrote:
>> From: David Heidelberg <david@ixit.cz>
>>
>> The Pixel 3 features two front-facing Sony IMX355 sensors with
>> different focal lengths (standard and wide-angle).
>>
>> Sensors are connected via CSIPHY port 1 and 2 and controlled over CCI
>> I2C1, using MCLK2 as the clock source.
>>
>> This enables support for the dual front camera configuration.
>>
>> Signed-off-by: David Heidelberg <david@ixit.cz>
>> ---
[...]
> This addition fails dtbs_check
Oh... at least point I didn't realized I left there something which fails
dtbs_check. Fixed :)
Thanks
David
>
> Konrad
^ permalink raw reply
* [PATCH v7 00/10] arm64: dts: qcom: Extend Shikra device tree with peripheral and subsystem support
From: Komal Bajaj @ 2026-07-20 10:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Xueyao An, Dmitry Baryshkov, Sayantan Chakraborty,
Konrad Dybcio, Aastha Pandey, Imran Shaik, Raviteja Laggyshetty,
Vishnu Santhosh, Bibek Kumar Patro, Gaurav Kohli, Miaoqing Pan,
Yepuri Siddu, Anurag Pateriya
Extend Shikra DT with peripheral and subsystem support across all SoM
variants (CQ2390M, CQ2390S, IQ2390S) and their EVK boards.
The series adds:
- QUPv3 serial engine configuration
- cpufreq-hw node for hardware-assisted CPU frequency scaling
- DDR bandwidth monitor (BWMONv5) nodes with OPP tables for dynamic
DDR frequency scaling
- EPSS L3 interconnect provider node for L3 cache frequency scaling
- CPU OPP tables to drive DDR and L3 scaling per frequency domain
- SMP2P nodes for CDSP, modem and LMCU inter-processor signalling
- Remoteproc PAS nodes for CDSP, LPAICP and MPSS subsystems
- TSENS instance with 14 thermal sensors and thermal zone definitions
- Bluetooth (WCN3988) node with board-specific regulator supplies on
all three EVK variants
- WiFi node in the SoC DTSI with board-specific power supply and
calibration variant selection on all three EVK variants
- Gpio-reserved-ranges to tlmm to mark GPIOs used by the SoC
internally and not available for general use
This series depends on:
- https://lore.kernel.org/all/20260612-shikra-dt-v6-0-6b6cb58db477@oss.qualcomm.com/
- https://lore.kernel.org/all/20260524-shikra_epss_l3-v1-0-b1528a436134@oss.qualcomm.com/
- https://lore.kernel.org/linux-clk/20260608-shikra-gcc-rpmcc-clks-v5-0-94cefe092ee3@oss.qualcomm.com/
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
Changes in v7:
- Dropped cpu-bwmon DT binding accepted upstream
- Collected Reviewed-by tags from Konrad
- Minor nit picks from Konrad
- Link to v6: https://lore.kernel.org/r/20260714-s
Changes in v6:
- Collected Reviewed-by tags from Konrad
- Reworked WiFi/BT enablement into SoM dtsi files, including WCN3988
PMU/regulator supplies, Bluetooth and WiFi enablement
- Updated gpio-reserved-ranges to document reserved GPIO functions and
drop GPIO115/GPIO116 from the EVK reserved list
- Link to v5: https://lore.kernel.org/r/20260702-s
Changes in v5:
- Split the WiFi hardware description into a separate shikra.dtsi patch (Konrad)
- Moved common WCN3988 PMU, Bluetooth and WiFi properties into
shikra-evk.dtsi, leaving board files with board-specific supplies and
status updates (Konrad)
- Added missing CPU OPP entries for 768 MHz and 2208 MHz
- Added gpio-reserved-ranges for TLMM on CQM, CQS and IQS EVK boards
- Collected tags fron Dmitry and Konrad
- Link to v4: https://lore.kernel.org/r/20260608-shikra-dt-m1-v4-0-2114300594a6@oss.qualcomm.com
Changes in v4:
- Updated commit message for first commit of the series (Krzysztof)
- Collected tags from Dmitry and Krzysztof
- Updated wifi fimmware name (Dmitry)
- Link to v3: https://lore.kernel.org/r/20260601-shikra-dt-m1-v3-0-0fe3f8d9ec48@oss.qualcomm.com
Changes in v3:
- Add missing interrupt affinity cell (0) to GPI DMA interrupts
- Link to v2: https://lore.kernel.org/r/20260530-shikra-dt-m1-v2-0-6bb581035d13@oss.qualcomm.com
Changes in v2:
- Collected Reviewed-By tags from Dmitry and Konrad
- Squashed cpufreq_hw, EPSS and OPP tables into single commit (Dmitry)
- Removed labels from CPU OPP table entries (Dmitry)
- Squashed CQM, CQS and IQS remoteproc-enable patches into one commit (Dmitry)
- Added WCN3988 PMU support (Dmitry)
- Squashed Bluetooth and Wifi changes into one commit (Dmitry)
- Link to v1: https://lore.kernel.org/r/20260525-shikra-dt-m1-v1-0-f51a9838dbaa@oss.qualcomm.com
---
Bibek Kumar Patro (2):
arm64: dts: qcom: shikra: Add CDSP, LPAICP, MPSS remoteproc PAS nodes
arm64: dts: qcom: shikra: Enable CDSP, LPAICP and MPSS on EVK boards
Gaurav Kohli (1):
arm64: dts: qcom: shikra: Enable TSENS and thermal zones
Komal Bajaj (4):
arm64: dts: qcom: shikra: Add cpufreq-hw, EPSS L3 interconnect and OPP tables
arm64: dts: qcom: shikra: add WiFi node support
arm64: dts: qcom: shikra: Enable WiFi/BT on SoMs
arm64: dts: qcom: shikra: Add gpio-reserved-ranges to tlmm
Sayantan Chakraborty (1):
arm64: dts: qcom: shikra: Add DDR BWMON support
Vishnu Santhosh (1):
arm64: dts: qcom: shikra: Add SMP2P nodes
Xueyao An (1):
arm64: dts: qcom: Add QUPv3 configuration for Shikra
arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 19 +
arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi | 80 ++
arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 19 +
arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 19 +
arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi | 88 ++
arch/arm64/boot/dts/qcom/shikra.dtsi | 1682 +++++++++++++++++++++++++-
6 files changed, 1893 insertions(+), 14 deletions(-)
---
base-commit: 0718283ab28bc3907e10b61a6b4be6fefa1cbb2f
change-id: 20260525-shikra-dt-m1-082dec382e7f
Best regards,
--
Komal Bajaj <komal.bajaj@oss.qualcomm.com>
^ permalink raw reply
* [PATCH v7 01/10] arm64: dts: qcom: Add QUPv3 configuration for Shikra
From: Komal Bajaj @ 2026-07-20 10:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Xueyao An, Dmitry Baryshkov
In-Reply-To: <20260720-shikra-dt-m1-v7-0-7dc99100c6dd@oss.qualcomm.com>
From: Xueyao An <xueyao.an@oss.qualcomm.com>
Add device tree support for QUPv3 serial engine protocols on Shikra.
Shikra has 10 QUP serial engines under a single QUP wrapper, all with
support of GPI DMA engines.
Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 951 +++++++++++++++++++++++++++++++++++
1 file changed, 951 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 4e5bc9e17c8e..f0fb55b9deb9 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,shikra-gcc.h>
#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,rpm-icc.h>
#include <dt-bindings/interconnect/qcom,shikra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -348,6 +349,161 @@ tlmm: pinctrl@500000 {
gpio-ranges = <&tlmm 0 0 165>;
wakeup-parent = <&mpm>;
+ qup_i2c0_data_clk: qup-i2c0-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio2", "gpio3";
+ function = "qup0_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c1_data_clk: qup-i2c1-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio4", "gpio5";
+ function = "qup0_se1_01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c2_data_clk: qup-i2c2-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio6", "gpio7";
+ function = "qup0_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c3_data_clk: qup-i2c3-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio10", "gpio11";
+ function = "qup0_se3_01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c4_data_clk: qup-i2c4-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio12", "gpio13";
+ function = "qup0_se4_01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c5_data_clk: qup-i2c5-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio14", "gpio15";
+ function = "qup0_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c6_data_clk: qup-i2c6-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio18", "gpio19";
+ function = "qup0_se6";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c7_data_clk: qup-i2c7-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio20", "gpio21";
+ function = "qup0_se7_01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c8_data_clk: qup-i2c8-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio22", "gpio23";
+ function = "qup0_se8";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c9_data_clk: qup-i2c9-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio27", "gpio26";
+ function = "qup0_se9_01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi0_cs: qup-spi0-cs-state {
+ pins = "gpio1";
+ function = "qup0_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi0_data_clk: qup-spi0-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio2", "gpio3", "gpio0";
+ function = "qup0_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi2_cs: qup-spi2-cs-state {
+ pins = "gpio9";
+ function = "qup0_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi2_data_clk: qup-spi2-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio6", "gpio7", "gpio8";
+ function = "qup0_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi5_cs: qup-spi5-cs-state {
+ pins = "gpio17";
+ function = "qup0_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi5_data_clk: qup-spi5-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio14", "gpio15", "gpio16";
+ function = "qup0_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi6_cs: qup-spi6-cs-state {
+ pins = "gpio29";
+ function = "qup0_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi6_data_clk: qup-spi6-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio18", "gpio19", "gpio28";
+ function = "qup0_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi8_cs: qup-spi8-cs-state {
+ pins = "gpio25";
+ function = "qup0_se8";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi8_data_clk: qup-spi8-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio22", "gpio23", "gpio24";
+ function = "qup0_se8";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
qup_uart0_default: qup-uart0-default-state {
pins = "gpio0", "gpio1";
function = "qup0_se0";
@@ -355,6 +511,105 @@ qup_uart0_default: qup-uart0-default-state {
bias-disable;
};
+ qup_uart1_default: qup-uart1-default-state {
+ pins = "gpio4", "gpio5";
+ function = "qup0_se1_23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_uart2_default: qup-uart2-default-state {
+ /* TX, RX */
+ pins = "gpio8", "gpio9";
+ function = "qup0_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_uart2_cts_rts: qup-uart2-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio6", "gpio7";
+ function = "qup0_se2";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart3_default: qup-uart3-default-state {
+ pins = "gpio10", "gpio11";
+ function = "qup0_se3_23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_uart4_default: qup-uart4-default-state {
+ pins = "gpio12", "gpio13";
+ function = "qup0_se4_23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_uart5_default: qup-uart5-default-state {
+ /* TX, RX */
+ pins = "gpio16", "gpio17";
+ function = "qup0_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_uart5_cts_rts: qup-uart5-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio14", "gpio15";
+ function = "qup0_se5";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart6_default: qup-uart6-default-state {
+ /* TX, RX */
+ pins = "gpio28", "gpio29";
+ function = "qup0_se6";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_uart6_cts_rts: qup-uart6-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio18", "gpio19";
+ function = "qup0_se6";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart7_default: qup-uart7-default-state {
+ pins = "gpio20", "gpio21";
+ function = "qup0_se7_23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_uart8_default: qup-uart8-default-state {
+ /* TX, RX */
+ pins = "gpio24", "gpio25";
+ function = "qup0_se8";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_uart8_cts_rts: qup-uart8-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio22", "gpio23";
+ function = "qup0_se8";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart9_default: qup-uart9-default-state {
+ pins = "gpio26", "gpio27";
+ function = "qup0_se9_23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
sdc1_state_on: sdc1-on-state {
clk-pins {
pins = "sdc1_clk";
@@ -604,6 +859,34 @@ opp-384000000 {
};
};
+ gpi_dma0: dma-controller@4a00000 {
+ compatible = "qcom,shikra-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0x0 0x04a00000 0x0 0x60000>;
+
+ interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ dma-channels = <16>;
+ dma-channel-mask = <0xff>;
+ #dma-cells = <3>;
+
+ iommus = <&apps_smmu 0xf6 0x0>;
+ };
+
qupv3_0: geniqup@4ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x04ac0000 0x0 0x2000>;
@@ -613,10 +896,75 @@ qupv3_0: geniqup@4ac0000 {
clock-names = "m-ahb",
"s-ahb";
+ iommus = <&apps_smmu 0xe3 0x0>;
+
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ status = "disabled";
+
+ i2c0: i2c@4a80000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a80000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c0_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi0: spi@4a80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x4a80000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
uart0: serial@4a80000 {
compatible = "qcom,geni-debug-uart";
reg = <0x0 0x04a80000 0x0 0x4000>;
@@ -638,6 +986,609 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
status = "disabled";
};
+
+ i2c1: i2c@4a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a84000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c1_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart1: serial@4a84000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a84000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart1_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c2: i2c@4a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a88000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ pinctrl-0 = <&qup_i2c2_data_clk>;
+ pinctrl-names = "default";
+
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi2: spi@4a88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x4a88000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart2: serial@4a88000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a88000 0x0 0x4000>;
+
+ interrupts-extended = <&intc GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&tlmm 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart2_default>, <&qup_uart2_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c3: i2c@4a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a8c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c3_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart3: serial@4a8c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a8c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart3_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c4: i2c@4a90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a90000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c4_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart4: serial@4a90000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a90000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart4_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c5: i2c@4a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a94000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c5_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi5: spi@4a94000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x4a94000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart5: serial@4a94000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a94000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart5_default>, <&qup_uart5_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c6: i2c@4a98000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a98000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 6 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c6_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi6: spi@4a98000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x4a98000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 6 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart6: serial@4a98000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a98000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart6_default>, <&qup_uart6_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c7: i2c@4a9c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a9c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 7 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c7_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart7: serial@4a9c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a9c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart7_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c8: i2c@4aa0000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4aa0000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 8 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 8 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c8_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi8: spi@4aa0000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x4aa0000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma0 0 8 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 8 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart8: serial@4aa0000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04aa0000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart8_default>, <&qup_uart8_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c9: i2c@4aa4000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4aa4000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S9_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 9 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 9 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c9_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart9: serial@4aa4000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04aa4000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S9_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart9_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
};
sram@c11e000 {
--
2.34.1
^ permalink raw reply related
* [PATCH v7 02/10] arm64: dts: qcom: shikra: Add DDR BWMON support
From: Komal Bajaj @ 2026-07-20 10:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Sayantan Chakraborty, Konrad Dybcio,
Dmitry Baryshkov
In-Reply-To: <20260720-shikra-dt-m1-v7-0-7dc99100c6dd@oss.qualcomm.com>
From: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com>
Add CPU-to-DDR BWMON nodes and their corresponding opp tables for
Shikra SoC. This is necessary to enable power management and optimize
system performance from the perspective of dynamically changing DDR
frequencies.
Signed-off-by: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 40 ++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index f0fb55b9deb9..d66b97dea319 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -661,6 +661,46 @@ rclk-pins {
};
};
+ pmu@c91000 {
+ compatible = "qcom,shikra-cpu-bwmon", "qcom,sc7280-llcc-bwmon";
+ reg = <0x0 0x00c91000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>;
+
+ operating-points-v2 = <&cpu_bwmon_opp_table>;
+
+ cpu_bwmon_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-0 {
+ opp-peak-kBps = <1200000>;
+ };
+
+ opp-1 {
+ opp-peak-kBps = <2188000>;
+ };
+
+ opp-2 {
+ opp-peak-kBps = <3072000>;
+ };
+
+ opp-3 {
+ opp-peak-kBps = <4068000>;
+ };
+
+ opp-4 {
+ opp-peak-kBps = <6220000>;
+ };
+
+ opp-5 {
+ opp-peak-kBps = <7216000>;
+ };
+ };
+ };
+
mem_noc: interconnect@d00000 {
compatible = "qcom,shikra-mem-noc-core";
reg = <0x0 0x00d00000 0x0 0x43080>;
--
2.34.1
^ permalink raw reply related
* [PATCH v7 03/10] arm64: dts: qcom: shikra: Add cpufreq-hw, EPSS L3 interconnect and OPP tables
From: Komal Bajaj @ 2026-07-20 10:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Aastha Pandey, Imran Shaik, Raviteja Laggyshetty,
Sayantan Chakraborty, Konrad Dybcio, Dmitry Baryshkov
In-Reply-To: <20260720-shikra-dt-m1-v7-0-7dc99100c6dd@oss.qualcomm.com>
Add cpufreq-hw node to support cpufreq scaling on Qualcomm Shikra SoCs.
Also, add Epoch Subsystem (EPSS) L3 interconnect provider node and OPP
tables required to scale DDR and L3 per freq-domain on Shikra SoC.
Co-developed-by: Aastha Pandey <aastha.pandey@oss.qualcomm.com>
Signed-off-by: Aastha Pandey <aastha.pandey@oss.qualcomm.com>
Co-developed-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Co-developed-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Co-developed-by: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com>
Signed-off-by: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 140 +++++++++++++++++++++++++++++++++++
1 file changed, 140 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index d66b97dea319..26ae21d4c7e3 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,shikra-gcc.h>
#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,rpm-icc.h>
#include <dt-bindings/interconnect/qcom,shikra.h>
@@ -44,6 +45,14 @@ cpu0: cpu@0 {
next-level-cache = <&l3>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ clocks = <&cpufreq_hw 0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
};
cpu1: cpu@100 {
@@ -54,6 +63,14 @@ cpu1: cpu@100 {
next-level-cache = <&l3>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ clocks = <&cpufreq_hw 0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
};
cpu2: cpu@200 {
@@ -64,6 +81,14 @@ cpu2: cpu@200 {
next-level-cache = <&l3>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ clocks = <&cpufreq_hw 0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
};
cpu3: cpu@300 {
@@ -74,6 +99,14 @@ cpu3: cpu@300 {
next-level-cache = <&l2_3>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <489>;
+ clocks = <&cpufreq_hw 1>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cpu3_opp_table>;
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
l2_3: l2-cache {
compatible = "cache";
@@ -132,6 +165,86 @@ memory@80000000 {
reg = <0x0 0x80000000 0x0 0x0>;
};
+ cpu0_opp_table: opp-table-cpu0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-768000000 {
+ opp-hz = /bits/ 64 <768000000>;
+ opp-peak-kBps = <1200000 17817600>;
+ };
+
+ opp-1017600000 {
+ opp-hz = /bits/ 64 <1017600000>;
+ opp-peak-kBps = <2188000 25804800>;
+ };
+
+ opp-1094400000 {
+ opp-hz = /bits/ 64 <1094400000>;
+ opp-peak-kBps = <3072000 30105600>;
+ };
+
+ opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ opp-peak-kBps = <4068000 38707200>;
+ };
+
+ opp-1612800000 {
+ opp-hz = /bits/ 64 <1612800000>;
+ opp-peak-kBps = <6220000 43008000>;
+ };
+
+ opp-1804800000 {
+ opp-hz = /bits/ 64 <1804800000>;
+ opp-peak-kBps = <7216000 43622400>;
+ };
+
+ opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ opp-peak-kBps = <7216000 43622400>;
+ };
+ };
+
+ cpu3_opp_table: opp-table-cpu3 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-768000000 {
+ opp-hz = /bits/ 64 <768000000>;
+ opp-peak-kBps = <1200000 17817600>;
+ };
+
+ opp-1017600000 {
+ opp-hz = /bits/ 64 <1017600000>;
+ opp-peak-kBps = <2188000 25804800>;
+ };
+
+ opp-1190400000 {
+ opp-hz = /bits/ 64 <1190400000>;
+ opp-peak-kBps = <3072000 30105600>;
+ };
+
+ opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ opp-peak-kBps = <4068000 38707200>;
+ };
+
+ opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ opp-peak-kBps = <6220000 43008000>;
+ };
+
+ opp-1900800000 {
+ opp-hz = /bits/ 64 <1900800000>;
+ opp-peak-kBps = <7216000 43622400>;
+ };
+
+ opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ opp-peak-kBps = <7216000 43622400>;
+ };
+ };
+
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
@@ -1820,6 +1933,33 @@ frame@f42d000 {
status = "disabled";
};
};
+
+ epss_l3: interconnect@fd90000 {
+ compatible = "qcom,shikra-epss-l3";
+ reg = <0x0 0x0fd90000 0x0 0x1000>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+ #interconnect-cells = <1>;
+ };
+
+ cpufreq_hw: cpufreq@fd91000 {
+ compatible = "qcom,shikra-epss";
+ reg = <0x0 0x0fd91000 0x0 0x1000>,
+ <0x0 0x0fd92000 0x0 0x1000>;
+ reg-names = "freq-domain0",
+ "freq-domain1";
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "dcvsh-irq-0",
+ "dcvsh-irq-1";
+
+ #freq-domain-cells = <1>;
+ #clock-cells = <1>;
+ };
};
timer {
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v3 1/8] dt-bindings: clock: renesas: Split out RZ/T2H CPG binding
From: Lad, Prabhakar @ 2026-07-20 10:50 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, Brian Masney,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Wim Van Sebroeck,
Guenter Roeck, Magnus Damm, linux-renesas-soc, linux-clk,
devicetree, linux-kernel, linux-watchdog, Prabhakar, Biju Das,
Fabrizio Castro, Lad Prabhakar
In-Reply-To: <20260720-fractal-prodigious-spoonbill-86f534@quoll>
Hi Krzysztof,
On Mon, Jul 20, 2026 at 6:55 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On Thu, Jul 16, 2026 at 01:34:27PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Move the RZ/T2H and RZ/N2H clock controller bindings from the generic
> > renesas,cpg-mssr.yaml schema into a dedicated binding.
> >
> > Unlike the traditional Renesas CPG/MSSR block, the RZ/T2H and RZ/N2H
> > system controller integrates additional functionality beyond clock and
> > module-stop control, including reset control, clock monitor support,
> > write-protection registers and other system management features.
>
> Nothing of above differences got reflected in the code, so I do not
> understand this reasoning. Binding is exactly the same as the old one.
>
A syscon regmap is implemented [0] as part of the RZ/T2H CPG driver.
Since the RZ/T2H clock driver uses this syscon wrapper, a function
pointer is implemented to handle the RZ/T2H-specific configuration.
Also, as the initial implementation used separate device tree nodes,
Geert suggested splitting this binding schema off into a dedicated
file [1].
[0] https://lore.kernel.org/all/20260716123434.2576253-3-prabhakar.mahadev-lad.rj@bp.renesas.com/
[1] https://lore.kernel.org/all/CAMuHMdU62updtKeBBk-vO3YP+qaWTGqHQnzKvFJbrz4J5eEPMQ@mail.gmail.com/
Cheers, Prabhakar
Cheers,
Prabhakar
^ permalink raw reply
* [PATCH v7 04/10] arm64: dts: qcom: shikra: Add SMP2P nodes
From: Komal Bajaj @ 2026-07-20 10:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Vishnu Santhosh, Dmitry Baryshkov, Konrad Dybcio
In-Reply-To: <20260720-shikra-dt-m1-v7-0-7dc99100c6dd@oss.qualcomm.com>
From: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com>
Add SMP2P nodes for the cdsp, modem and lmcu subsystems to enable
inter-processor signalling for remoteproc state management.
Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 69 ++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 26ae21d4c7e3..53dddf35963e 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -428,6 +428,75 @@ lmcu_dtb_mem: lmcu-dtb@b4702000 {
};
};
+ smp2p-cdsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <94>, <432>;
+
+ interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING 0>;
+
+ mboxes = <&apcs_glb 6>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ cdsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ cdsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-lmcu {
+ compatible = "qcom,smp2p";
+ qcom,smem = <617>, <616>;
+
+ interrupts = <GIC_SPI 287 IRQ_TYPE_EDGE_RISING 0>;
+
+ mboxes = <&apcs_glb 10>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <26>;
+
+ lmcu_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ lmcu_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-mpss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+
+ interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING 0>;
+
+ mboxes = <&apcs_glb 14>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ modem_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ modem_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
soc: soc@0 {
compatible = "simple-bus";
--
2.34.1
^ permalink raw reply related
* [PATCH v7 05/10] arm64: dts: qcom: shikra: Add CDSP, LPAICP, MPSS remoteproc PAS nodes
From: Komal Bajaj @ 2026-07-20 10:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Bibek Kumar Patro, Konrad Dybcio, Dmitry Baryshkov
In-Reply-To: <20260720-shikra-dt-m1-v7-0-7dc99100c6dd@oss.qualcomm.com>
From: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Add nodes for remoteproc PAS loader for CDSP, LPAICP, MPSS subsystem.
Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 164 +++++++++++++++++++++++++++++++++++
1 file changed, 164 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 53dddf35963e..12e4281f7b35 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -1813,6 +1813,170 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
};
};
+ remoteproc_mpss: remoteproc@6080000 {
+ compatible = "qcom,shikra-mpss-pas";
+ reg = <0x0 0x06080000 0x0 0x100>;
+
+ interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING 0>,
+ <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "xo";
+
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+
+ power-domains = <&rpmpd RPMHPD_CX>;
+
+ memory-region = <&mpss_wlan_mem>;
+
+ qcom,smem-states = <&modem_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING 0>;
+ mboxes = <&apcs_glb 12>;
+ qcom,remote-pid = <1>;
+ label = "mpss";
+ };
+ };
+
+ remoteproc_cdsp: remoteproc@b300000 {
+ compatible = "qcom,shikra-cdsp-pas";
+ reg = <0x0 0x0b300000 0x0 0x100000>;
+
+ interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING 0>,
+ <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "xo";
+
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+
+ power-domains = <&rpmpd RPMHPD_CX>;
+
+ memory-region = <&cdsp_mem>;
+
+ qcom,smem-states = <&cdsp_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING 0>;
+ mboxes = <&apcs_glb 4>;
+ qcom,remote-pid = <5>;
+ label = "cdsp";
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ label = "cdsp";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+
+ compute-cb@1 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <1>;
+ iommus = <&apps_smmu 0x0201 0x0000>;
+ };
+
+ compute-cb@2 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <2>;
+ iommus = <&apps_smmu 0x0202 0x0000>;
+ };
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <&apps_smmu 0x0203 0x0000>;
+ };
+
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+ iommus = <&apps_smmu 0x0204 0x0000>;
+ };
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+ iommus = <&apps_smmu 0x0205 0x0000>;
+ };
+
+ compute-cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+ iommus = <&apps_smmu 0x0206 0x0000>;
+ };
+
+ compute-cb@9 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <9>;
+ iommus = <&apps_smmu 0x0209 0x0000>;
+ };
+ };
+ };
+ };
+
+ remoteproc_lpaicp: remoteproc@b800000 {
+ compatible = "qcom,shikra-lpaicp-pas";
+ reg = <0x0 0x0b800000 0x0 0x200000>;
+
+ interrupts-extended = <&intc GIC_SPI 257 IRQ_TYPE_EDGE_RISING 0>,
+ <&lmcu_smp2p_in 0 IRQ_TYPE_NONE>,
+ <&lmcu_smp2p_in 1 IRQ_TYPE_NONE>,
+ <&lmcu_smp2p_in 2 IRQ_TYPE_NONE>,
+ <&lmcu_smp2p_in 3 IRQ_TYPE_NONE>;
+
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "xo";
+
+ memory-region = <&lmcu_mem &lmcu_dtb_mem>;
+
+ qcom,smem-states = <&lmcu_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING 0>;
+ mboxes = <&apcs_glb 9>;
+ qcom,remote-pid = <26>;
+ label = "lpaicp";
+ };
+ };
+
sram@c11e000 {
compatible = "qcom,shikra-imem", "mmio-sram";
reg = <0x0 0x0c11e000 0x0 0x1000>;
--
2.34.1
^ permalink raw reply related
* [PATCH v7 06/10] arm64: dts: qcom: shikra: Enable CDSP, LPAICP and MPSS on EVK boards
From: Komal Bajaj @ 2026-07-20 10:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Bibek Kumar Patro, Konrad Dybcio, Dmitry Baryshkov
In-Reply-To: <20260720-shikra-dt-m1-v7-0-7dc99100c6dd@oss.qualcomm.com>
From: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Enable CDSP, LPAICP and MPSS for Qualcomm's Shikra CQM, CQS and
IQS EVK board.
Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 19 +++++++++++++++++++
arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 19 +++++++++++++++++++
arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 19 +++++++++++++++++++
3 files changed, 57 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
index 0a52ab9b7a4c..b112b21b1d79 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
@@ -23,6 +23,25 @@ chosen {
};
};
+&remoteproc_cdsp {
+ firmware-name = "qcom/shikra/cdsp.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_lpaicp {
+ firmware-name = "qcom/shikra/lpaicp.mbn",
+ "qcom/shikra/lpaicp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/shikra/cqm/qdsp6sw.mbn";
+
+ status = "okay";
+};
+
&sdhc_1 {
vmmc-supply = <&pm4125_l20>;
vqmmc-supply = <&pm4125_l14>;
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
index b3f19a64d7ae..e62ba5aef71f 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
@@ -23,6 +23,25 @@ chosen {
};
};
+&remoteproc_cdsp {
+ firmware-name = "qcom/shikra/cdsp.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_lpaicp {
+ firmware-name = "qcom/shikra/lpaicp.mbn",
+ "qcom/shikra/lpaicp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/shikra/cqs/qdsp6sw.mbn";
+
+ status = "okay";
+};
+
&sdhc_1 {
vmmc-supply = <&pm4125_l20>;
vqmmc-supply = <&pm4125_l14>;
diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
index 3003a47bd759..727809430fd1 100644
--- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
@@ -23,6 +23,25 @@ chosen {
};
};
+&remoteproc_cdsp {
+ firmware-name = "qcom/shikra/cdsp.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_lpaicp {
+ firmware-name = "qcom/shikra/lpaicp.mbn",
+ "qcom/shikra/lpaicp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/shikra/cqs/qdsp6sw.mbn";
+
+ status = "okay";
+};
+
&sdhc_1 {
vmmc-supply = <&pm8150_l17>;
vqmmc-supply = <&pm8150_s4>;
--
2.34.1
^ permalink raw reply related
* [PATCH v7 07/10] arm64: dts: qcom: shikra: Enable TSENS and thermal zones
From: Komal Bajaj @ 2026-07-20 10:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Gaurav Kohli, Dmitry Baryshkov, Konrad Dybcio
In-Reply-To: <20260720-shikra-dt-m1-v7-0-7dc99100c6dd@oss.qualcomm.com>
From: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>
The shikra includes one TSENS instance, with a total of 14 thermal
sensors distributed across various locations on the SoC.
The TSENS max/reset threshold is configured to 120°C in the hardware.
Enable all TSENS instances, and define the thermal zones with a hot trip
at 110°C and critical trip at 115°C.
Signed-off-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 267 +++++++++++++++++++++++++++++++++++
1 file changed, 267 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 12e4281f7b35..3abd0a686d0e 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -12,6 +12,7 @@
#include <dt-bindings/interconnect/qcom,shikra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
@@ -998,6 +999,18 @@ spmi_bus: spmi@1c40000 {
qcom,ee = <0>;
};
+ tsens0: thermal-sensor@4411000 {
+ compatible = "qcom,shikra-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x04411000 0x0 0x1000>,
+ <0x0 0x04410000 0x0 0x1000>;
+ interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "uplow",
+ "critical";
+ #qcom,sensors = <14>;
+ #thermal-sensor-cells = <1>;
+ };
+
rpm_msg_ram: sram@45f0000 {
compatible = "qcom,rpm-msg-ram", "mmio-sram";
reg = <0x0 0x045f0000 0x0 0x7000>;
@@ -2195,6 +2208,260 @@ cpufreq_hw: cpufreq@fd91000 {
};
};
+ thermal_zones: thermal-zones {
+ aoss0-thermal {
+ thermal-sensors = <&tsens0 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ aoss0-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-0-thermal {
+ thermal-sensors = <&tsens0 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu00-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-1-thermal {
+ thermal-sensors = <&tsens0 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu01-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-0-thermal {
+ thermal-sensors = <&tsens0 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu10-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-1-thermal {
+ thermal-sensors = <&tsens0 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu11-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss0-thermal {
+ thermal-sensors = <&tsens0 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpuss0-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-thermal {
+ thermal-sensors = <&tsens0 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpuss-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsp-thermal {
+ thermal-sensors = <&tsens0 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nsp-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss0-thermal {
+ thermal-sensors = <&tsens0 8>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ mdmss0-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss1-thermal {
+ thermal-sensors = <&tsens0 9>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ mdmss1-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ camera-thermal {
+ thermal-sensors = <&tsens0 10>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ camera-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ video-thermal {
+ thermal-sensors = <&tsens0 11>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ video-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-2-thermal {
+ thermal-sensors = <&tsens0 12>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu02-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss1-thermal {
+ thermal-sensors = <&tsens0 13>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpuss1-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
--
2.34.1
^ permalink raw reply related
* [PATCH v7 09/10] arm64: dts: qcom: shikra: Enable WiFi/BT on SoMs
From: Komal Bajaj @ 2026-07-20 10:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Yepuri Siddu, Miaoqing Pan, Dmitry Baryshkov,
Konrad Dybcio
In-Reply-To: <20260720-shikra-dt-m1-v7-0-7dc99100c6dd@oss.qualcomm.com>
Shikra SoM cards include WCN3988 WiFi/Bluetooth chip, with supplies
provided by on-card PMICs. Enable both interfaces and provide the
required supply and calibration data.
Co-developed-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
Signed-off-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
Co-developed-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
Signed-off-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi | 74 +++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi | 82 ++++++++++++++++++++++++++++
2 files changed, 156 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi
index dc3861489f64..2fff5fe9f6d2 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi
@@ -11,6 +11,10 @@
#include "pm8005.dtsi"
/ {
+ aliases {
+ serial1 = &uart8;
+ };
+
gpio-keys {
compatible = "gpio-keys";
label = "gpio-keys";
@@ -27,6 +31,42 @@ key-volume-up {
linux,can-disable;
};
};
+
+ wcn3988-pmu {
+ compatible = "qcom,wcn3988-pmu";
+
+ pinctrl-0 = <&sw_ctrl_default>;
+ pinctrl-names = "default";
+
+ swctrl-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>;
+
+ vddio-supply = <&pm4125_l7>;
+ vddxo-supply = <&pm4125_l13>;
+ vddrf-supply = <&pm4125_l10>;
+ vddch0-supply = <&pm4125_l22>;
+
+ regulators {
+ vreg_pmu_io: ldo0 {
+ regulator-name = "vreg_pmu_io";
+ };
+
+ vreg_pmu_xo: ldo1 {
+ regulator-name = "vreg_pmu_xo";
+ };
+
+ vreg_pmu_rf: ldo2 {
+ regulator-name = "vreg_pmu_rf";
+ };
+
+ vreg_pmu_ch0: ldo3 {
+ regulator-name = "vreg_pmu_ch0";
+ };
+
+ vreg_pmu_ch1: ldo4 {
+ regulator-name = "vreg_pmu_ch1";
+ };
+ };
+ };
};
&pm4125_gpios {
@@ -154,3 +194,37 @@ pm4125_l22: l22 {
};
};
};
+
+&tlmm {
+ sw_ctrl_default: sw-ctrl-default-state {
+ pins = "gpio88";
+ function = "gpio";
+ bias-pull-down;
+ };
+};
+
+&uart8 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,wcn3988-bt";
+ max-speed = <3200000>;
+
+ vddio-supply = <&vreg_pmu_io>;
+ vddxo-supply = <&vreg_pmu_xo>;
+ vddrf-supply = <&vreg_pmu_rf>;
+ vddch0-supply = <&vreg_pmu_ch0>;
+ };
+};
+
+&wifi {
+ vdd-0.8-cx-mx-supply = <&pm4125_l7>;
+ vdd-1.8-xo-supply = <&vreg_pmu_xo>;
+ vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
+ vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
+
+ qcom,calibration-variant = "Shikra_EVK";
+ firmware-name = "shikra";
+
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi
index 73945bf42112..657a14ca9606 100644
--- a/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi
@@ -10,6 +10,10 @@
#include "pm8150.dtsi"
/ {
+ aliases {
+ serial1 = &uart8;
+ };
+
gpio-key {
compatible = "gpio-keys";
label = "gpio-keys";
@@ -26,6 +30,50 @@ key-volume-up {
linux,can-disable;
};
};
+
+ vreg_wcn_3p3: regulator-wcn-3p3 {
+ compatible = "regulator-fixed";
+ regulator-name = "wcn_3p3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ wcn3988-pmu {
+ compatible = "qcom,wcn3988-pmu";
+
+ pinctrl-0 = <&sw_ctrl_default>;
+ pinctrl-names = "default";
+
+ swctrl-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>;
+
+ vddio-supply = <&pm8150_s4>;
+ vddxo-supply = <&pm8150_l12>;
+ vddrf-supply = <&pm8150_l8>;
+ vddch0-supply = <&vreg_wcn_3p3>;
+
+ regulators {
+ vreg_pmu_io: ldo0 {
+ regulator-name = "vreg_pmu_io";
+ };
+
+ vreg_pmu_xo: ldo1 {
+ regulator-name = "vreg_pmu_xo";
+ };
+
+ vreg_pmu_rf: ldo2 {
+ regulator-name = "vreg_pmu_rf";
+ };
+
+ vreg_pmu_ch0: ldo3 {
+ regulator-name = "vreg_pmu_ch0";
+ };
+
+ vreg_pmu_ch1: ldo4 {
+ regulator-name = "vreg_pmu_ch1";
+ };
+ };
+ };
};
&pm8150_gpios {
@@ -168,3 +216,37 @@ pm8150_l18: l18 {
};
};
};
+
+&tlmm {
+ sw_ctrl_default: sw-ctrl-default-state {
+ pins = "gpio88";
+ function = "gpio";
+ bias-pull-down;
+ };
+};
+
+&uart8 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,wcn3988-bt";
+ max-speed = <3200000>;
+
+ vddio-supply = <&vreg_pmu_io>;
+ vddxo-supply = <&vreg_pmu_xo>;
+ vddrf-supply = <&vreg_pmu_rf>;
+ vddch0-supply = <&vreg_pmu_ch0>;
+ };
+};
+
+&wifi {
+ vdd-0.8-cx-mx-supply = <&pm8150_s4>;
+ vdd-1.8-xo-supply = <&vreg_pmu_xo>;
+ vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
+ vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
+
+ qcom,calibration-variant = "Shikra_EVK";
+ firmware-name = "shikra";
+
+ status = "okay";
+};
--
2.34.1
^ permalink raw reply related
* [PATCH v7 08/10] arm64: dts: qcom: shikra: add WiFi node support
From: Komal Bajaj @ 2026-07-20 10:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Miaoqing Pan, Dmitry Baryshkov, Konrad Dybcio
In-Reply-To: <20260720-shikra-dt-m1-v7-0-7dc99100c6dd@oss.qualcomm.com>
Introduce the WiFi hardware description in shikra.dtsi, including
register space, interrupts, IOMMU configuration and reserved memory.
The node is kept disabled by default and is intended to be enabled
by board-specific device trees.
Signed-off-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 3abd0a686d0e..205814c4b349 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -2079,6 +2079,29 @@ apps_smmu: iommu@c600000 {
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
};
+ wifi: wifi@c800000 {
+ compatible = "qcom,wcn3990-wifi";
+ reg = <0x0 0x0c800000 0x0 0x800000>;
+ reg-names = "membase";
+ memory-region = <&wlan_mem>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&apps_smmu 0x1a0 0x1>;
+ qcom,msa-fixed-perm;
+
+ status = "disabled";
+ };
+
intc: interrupt-controller@f200000 {
compatible = "arm,gic-v3";
reg = <0x0 0xf200000 0x0 0x10000>,
--
2.34.1
^ permalink raw reply related
* [PATCH v7 10/10] arm64: dts: qcom: shikra: Add gpio-reserved-ranges to tlmm
From: Komal Bajaj @ 2026-07-20 10:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Anurag Pateriya
In-Reply-To: <20260720-shikra-dt-m1-v7-0-7dc99100c6dd@oss.qualcomm.com>
Add gpio-reserved-ranges property to the TLMM node for both Shikra
SoM variants (CQM and IQS). These reserved GPIOs are inaccessible
from the non-secure world and dedicated to fixed functions.
Signed-off-by: Anurag Pateriya <apateriy@qti.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi | 6 ++++++
arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi | 6 ++++++
2 files changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi
index 2fff5fe9f6d2..8ac42ff625a0 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi
@@ -196,6 +196,12 @@ pm4125_l22: l22 {
};
&tlmm {
+ gpio-reserved-ranges = <6 4>, /* Fingerprint SPI */
+ <14 4>, /* eSE SPI */
+ <30 2>, /* NFC SPI */
+ <138 1>, /* NFC Secure IO */
+ <155 11>; /* eMMC Boot */
+
sw_ctrl_default: sw-ctrl-default-state {
pins = "gpio88";
function = "gpio";
diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi
index 657a14ca9606..4ff97945274d 100644
--- a/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi
@@ -218,6 +218,12 @@ pm8150_l18: l18 {
};
&tlmm {
+ gpio-reserved-ranges = <6 4>, /* Fingerprint SPI */
+ <14 4>, /* eSE SPI */
+ <30 2>, /* NFC SPI */
+ <138 1>, /* NFC Secure IO */
+ <155 11>; /* eMMC Boot */
+
sw_ctrl_default: sw-ctrl-default-state {
pins = "gpio88";
function = "gpio";
--
2.34.1
^ permalink raw reply related
* [PATCH v6 1/2] arm64: dts: qcom: sdm845-google: Add dual front IMX355 cameras
From: David Heidelberg via B4 Relay @ 2026-07-20 10:53 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Konrad Dybcio, Petr Hodina, Richard Acayan, linux-arm-msm,
devicetree, linux-kernel, phone-devel, David Heidelberg
In-Reply-To: <20260720-pixel3-camera-v6-0-afe419bef476@ixit.cz>
From: David Heidelberg <david@ixit.cz>
The Pixel 3 features two front-facing Sony IMX355 sensors with
different focal lengths (standard and wide-angle).
Sensors are connected via CSIPHY port 1 and 2 and controlled over CCI
I2C1, using MCLK2 as the clock source.
This enables support for the dual front camera configuration.
Signed-off-by: David Heidelberg <david@ixit.cz>
---
arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 171 ++++++++++++++++++++-
1 file changed, 170 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi
index 9368fd6b87515..267dcd6eddaee 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi
@@ -1,16 +1,17 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include <dt-bindings/arm/qcom,ids.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/media/video-interfaces.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sdm845.dtsi"
#include "pm8998.dtsi"
#include "pmi8998.dtsi"
/delete-node/ &mpss_region;
/delete-node/ &venus_mem;
@@ -127,16 +128,48 @@ vreg_s4a_1p8: regulator-vreg-s4a-1p8 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vph_pwr>;
};
+ camera_front_avdd: regulator-front-cam-avdd {
+ compatible = "regulator-fixed";
+ regulator-name = "front_cam_avdd";
+
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&cam_front_avdd_default>;
+ pinctrl-names = "default";
+
+ vin-supply = <&vreg_bob>;
+ };
+
+ camera_front_aux_avdd: regulator-front-cam-aux-avdd {
+ compatible = "regulator-fixed";
+ regulator-name = "front_cam_aux_avdd";
+
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ gpios = <&tlmm 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&cam_front_aux_avdd_default>;
+ pinctrl-names = "default";
+
+ vin-supply = <&vreg_bob>;
+ };
+
wcn3990-pmu {
compatible = "qcom,wcn3990-pmu";
vddio-supply = <&vreg_s4a_1p8>;
vddxo-supply = <&vreg_l7a_1p8>;
vddrf-supply = <&vreg_l17a_1p3>;
vddch0-supply = <&vreg_l25a_3p3>;
@@ -314,16 +347,21 @@ vreg_l28a_3p0: ldo28 {
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
regulator-boot-on;
/*
* We can't properly bring the panel back if it gets turned off
* so keep it's regulators always on for now.
*/
regulator-always-on;
};
+
+ vreg_lvs1_1p8: lvs1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
};
regulators-1 {
compatible = "qcom,pmi8998-rpmh-regulators";
qcom,pmic-id = "b";
vdd-bob-supply = <&vph_pwr>;
@@ -346,24 +384,127 @@ regulators-2 {
vreg_s3c_0p6: smps3 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <600000>;
};
};
};
+&camss {
+ vdda-phy-supply = <&vreg_l1a_0p875>;
+ vdda-pll-supply = <&vreg_l26a_1p2>;
+
+ /*
+ * MCLK2 (GPIO15) is shared between both front camera sensors.
+ * The clock is generated by CAMCC, therefore the pin is
+ * configured here rather than in individual sensor nodes.
+ */
+ pinctrl-0 = <&cam_mclk2_default>;
+ pinctrl-1 = <&cam_mclk2_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ camss_endpoint1: endpoint {
+ bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&cam_aux_front_endpoint>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ camss_endpoint2: endpoint {
+ bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&cam_front_endpoint>;
+ };
+ };
+ };
+};
+
+&cci0_sleep {
+ /* bus has external pull-up */
+ /delete-property/ bias-pull-down;
+ bias-disable;
+};
+
&cci {
status = "okay";
};
&cci_i2c1 {
/* actuator @0c */
- /* front camera, imx355 @1a */
+ front_cam: camera@10 {
+ compatible = "sony,imx355";
+ reg = <0x10>;
+
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ assigned-clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ assigned-clock-rates = <24000000>;
+
+ reset-gpios = <&tlmm 21 GPIO_ACTIVE_LOW>;
+
+ avdd-supply = <&camera_front_avdd>;
+ dvdd-supply = <&vreg_s3a_1p35>;
+ dovdd-supply = <&vreg_lvs1_1p8>;
+
+ pinctrl-0 = <&cam_front_reset_default>;
+ pinctrl-names = "default";
+
+ rotation = <270>;
+ orientation = <0>;
+
+ port {
+ cam_front_endpoint: endpoint {
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <360000000>;
+ remote-endpoint = <&camss_endpoint2>;
+ };
+ };
+ };
+
+ front_aux_cam: camera@1a {
+ compatible = "sony,imx355";
+ reg = <0x1a>;
+
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ assigned-clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ assigned-clock-rates = <24000000>;
+
+ reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>;
+
+ avdd-supply = <&camera_front_aux_avdd>;
+ dvdd-supply = <&vreg_s3a_1p35>;
+ dovdd-supply = <&vreg_lvs1_1p8>;
+
+ pinctrl-0 = <&cam_front_aux_reset_default>;
+ pinctrl-names = "default";
+
+ rotation = <270>;
+ orientation = <0>;
+
+ port {
+ cam_aux_front_endpoint: endpoint {
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <360000000>;
+ remote-endpoint = <&camss_endpoint1>;
+ };
+ };
+ };
/* eeprom @50, at24 driver says 8K */
};
&cdsp_pas {
firmware-name = "qcom/sdm845/Google/blueline/cdsp.mbn";
status = "okay";
@@ -485,16 +626,44 @@ nfc_int_default: nfc-int-default-state {
nfc_enable_default: nfc-enable-default-state {
pins = "gpio25", "gpio79";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
+ cam_front_avdd_default: cam-avdd-default-state {
+ pins = "gpio8";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_front_aux_reset_default: cam-front-aux-reset-default-state {
+ pins = "gpio9";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_front_aux_avdd_default: cam-avdd-aux-default-state {
+ pins = "gpio14";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_front_reset_default: cam-front-reset-default-state {
+ pins = "gpio21";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
touchscreen_reset: ts-reset-state {
pins = "gpio99";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
touchscreen_pins: ts-pins-gpio-state {
--
2.53.0
^ permalink raw reply related
* [PATCH v6 0/2] Add initial dual front camera and rear flash support for Pixel 3 / 3 XL
From: David Heidelberg via B4 Relay @ 2026-07-20 10:53 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Konrad Dybcio, Petr Hodina, Richard Acayan, linux-arm-msm,
devicetree, linux-kernel, phone-devel, David Heidelberg
Describe the dual front-facing IMX355 sensors (standard and wide)
and enable the PMI8998 flash LED with hardware-accurate limits.
This brings up the basic camera topology and flash support in DT.
Signed-off-by: David Heidelberg <david@ixit.cz>
---
Changes in v6:
- Remove forgotten bias-pull-down property from cci0_sleep node.
(dtbs_check)
- ..-regulator -> regulator-.. (Konrad)
- Rename camera -pin to -state and remove _pin from the labes. (Konrad,
dtbs_check)
- Link to v5: https://lore.kernel.org/r/20260719-pixel3-camera-v5-0-99593f1bd8ec@ixit.cz
Changes in v5:
- Added function-enumarator to flash LEDs. (Sashiko)
- Dropped l22a regulator needed only for NFOV actuator. (Sashiko)
- Dropped vdda-csi[0-2]-supply, as it was unused. (Sashiko).
- Added previously omited cam_mclk2_sleep sleep state.
- Link to v4: https://lore.kernel.org/r/20260719-pixel3-camera-v4-0-48cab1236852@ixit.cz
Changes in v4:
- Use 24 MHz ext clock for the cameras, as the downstream does, since
the upstream driver can now support it.
- Added additional LED, as the phone contains two separately controlled
white LEDs flash (upper and bottom, in one module).
- Increase flash-max-microamp, as I took wrong "flash" from the
downstream sources and dropped Dmitry R-b.
- Address formatting issues. (Konrad)
- Link to v3: https://lore.kernel.org/r/20260412-pixel3-camera-v3-0-e26b090a6110@ixit.cz
Changes in v3:
- Dropped cam_vio label. (Dmitry)
- Move the MCLK2 pinctrl from cameras to common camss. (Dmitry)
- Link to v2: https://lore.kernel.org/r/20260411-pixel3-camera-v2-0-41b889abb14c@ixit.cz
Changes in v2:
- leds.h include escaped the initial submission. Fixed.
- Link to v1: https://lore.kernel.org/r/20260411-pixel3-camera-v1-0-2757606515b6@ixit.cz
---
David Heidelberg (2):
arm64: dts: qcom: sdm845-google: Add dual front IMX355 cameras
arm64: dts: qcom: sdm845-google: Enable PMI8998 camera flash LEDs
arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 198 ++++++++++++++++++++-
1 file changed, 197 insertions(+), 1 deletion(-)
---
base-commit: 0718283ab28bc3907e10b61a6b4be6fefa1cbb2f
change-id: 20260315-pixel3-camera-a9989bf589ee
Best regards,
--
David Heidelberg <david@ixit.cz>
^ permalink raw reply
* [PATCH v6 2/2] arm64: dts: qcom: sdm845-google: Enable PMI8998 camera flash LEDs
From: David Heidelberg via B4 Relay @ 2026-07-20 10:53 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Konrad Dybcio, Petr Hodina, Richard Acayan, linux-arm-msm,
devicetree, linux-kernel, phone-devel, David Heidelberg
In-Reply-To: <20260720-pixel3-camera-v6-0-afe419bef476@ixit.cz>
From: David Heidelberg <david@ixit.cz>
Enable the PMI8998 flash LED block and describe two white flash LEDs
used for the rear camera.
Configure the LED in flash mode with hardware limits matching the
original device configuration, including maximum current and timeout.
In contrary to downstream, we can control both LEDs separately.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 27 ++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi
index 267dcd6eddaee..c8699f72cfecf 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi
@@ -1,16 +1,17 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include <dt-bindings/arm/qcom,ids.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/media/video-interfaces.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sdm845.dtsi"
#include "pm8998.dtsi"
#include "pmi8998.dtsi"
/delete-node/ &mpss_region;
@@ -590,16 +591,42 @@ &pm8998_resin {
};
&pmi8998_charger {
monitored-battery = <&battery>;
status = "okay";
};
+&pmi8998_flash {
+ status = "okay";
+
+ /* upper flash module part */
+ led-0 {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_WHITE>;
+ led-sources = <1>;
+ led-max-microamp = <500000>;
+ flash-max-microamp = <1500000>;
+ flash-max-timeout-us = <1280000>;
+ function-enumerator = <0>;
+ };
+
+ /* lower flash module part */
+ led-1 {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_WHITE>;
+ led-sources = <2>;
+ led-max-microamp = <500000>;
+ flash-max-microamp = <1500000>;
+ flash-max-timeout-us = <1280000>;
+ function-enumerator = <1>;
+ };
+};
+
&qupv3_id_0 {
status = "okay";
};
&qupv3_id_1 {
status = "okay";
};
--
2.53.0
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