Re: [PATCH v6 10/11] arm64: dts: qcom: ipq5210: Add SPI node definitions

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] dts: incorrect reg cell count for spi0 node in ipq5210
- [Low] dts: missing #address-cells and #size-cells in ipq5210 spi nodes
--

commit 98b0e1a28d55f7b85bc8666419066bba608f1097
Author: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>

arm64: dts: qcom: ipq5210: Add SPI node definitions

This commit adds SPI node definitions for the QUP SPI blocks present in the
IPQ5210 SoC. It introduces spi0 and spi1 nodes with their basic configurations
including compatible strings, register addresses, clocks, and interrupts.

> diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi
> index 50ce79219fe23..23a2e27b70fa3 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi
> @@ -418,6 +418,17 @@ qupv3: geniqup@1ac0000 {
>  			#address-cells = <2>;
>  			#size-cells = <2>;
>  
> +			spi0: spi@1a80000 {
> +				compatible = "qcom,geni-spi";
> +				reg = <0x1a80000 0x4000>;

[Severity: Medium]
Will this reg property cause dtc warnings and runtime probing failures?

The parent node qupv3: geniqup@1ac0000 specifies #address-cells = <2>; and
#size-cells = <2>;. This requires all child nodes to specify their reg
properties with exactly 4 cells (2 for the 64-bit address, 2 for the 64-bit
size). The newly added spi0 node only provides 2 cells, whereas the sibling
spi1 node correctly uses 4 cells.

[Severity: Low]
Should #address-cells = <1>; and #size-cells = <0>; be added to this node?

SPI controller nodes typically define these properties in the SoC .dtsi so
that board files can cleanly instantiate SPI slave devices on the bus
without repeating them. Without these properties, when board-level device
trees attempt to attach child SPI devices, the device tree compiler will
emit warnings about missing #address-cells and #size-cells properties in
the parent node.

> +				clocks = <&gcc GCC_QUPV3_WRAP_SE0_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> +				assigned-clocks = <&gcc GCC_QUPV3_WRAP_SE0_CLK>;
> +				assigned-clock-rates = <50000000>;
> +				status = "disabled";
> +			};

[ ... ]

> +			spi1: spi@1a90000 {
> +				compatible = "qcom,geni-spi";
> +				reg = <0x0 0x01a90000 0x0 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP_SE4_CLK>;

[Severity: Low]
Similar to the spi0 node above, should this node also include
#address-cells = <1>; and #size-cells = <0>; to prevent dtc warnings when
board files attach child devices?

> +				clock-names = "se";
> +				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
> +				assigned-clocks = <&gcc GCC_QUPV3_WRAP_SE4_CLK>;
> +				assigned-clock-rates = <50000000>;
> +				status = "disabled";
> +			};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261008-08-dts-v6-0-f9c4ec8664d8@oss.qualcomm.com?part=10