* [PATCH v2 0/2] riscv: dts: spacemit: mark K1 boot nodes bootph-pre-ram
@ 2026-10-17 18:01 Hung-Chun Tseng
2026-10-17 18:01 ` [PATCH v2 1/2] riscv: dts: spacemit: k1: mark boot-critical SoC " Hung-Chun Tseng
2026-10-17 18:01 ` [PATCH v2 2/2] riscv: dts: spacemit: mark K1 board boot devices bootph-pre-ram Hung-Chun Tseng
0 siblings, 2 replies; 5+ messages in thread
From: Hung-Chun Tseng @ 2026-10-17 18:01 UTC (permalink / raw)
To: Yixun Lan, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
E Shattow, devicetree, linux-riscv, spacemit, linux-kernel
A bootloader SPL on the SpacemiT K1 runs from SRAM and needs a handful
of nodes before DRAM is up: the root clocks and clock controllers, the
console UART, the boot media (SD, eMMC, QSPI NOR), the board EEPROM
used to identify the board, and the PMIC rails it programs before DRAM
training. Today mainline U-Boot carries the bootph-pre-ram tags for
these in per-board -u-boot.dtsi files.
When I sent a U-Boot patch adding another such file for the Milk-V
Jupiter, E Shattow asked for the tags to go upstream first, so every
K1 board gets them and the U-Boot overlays can shrink [1]. Earlier
there was no working mainline SPL for K1 to justify them; there is now.
Patch 1 tags the SoC nodes in k1.dtsi, including i2c8, which every K1
board uses for the PMIC. Patch 2 tags the board-specific EEPROM and its
bus, the PMIC rails and the SPI NOR on the boards that have them. The
set of nodes matches what the mainline U-Boot SPL tags for the BPI-F3
and MusePi Pro. Pin control and regulator supplies are left untagged:
the K1 SPL does not enable SPL_PINCTRL, and neither the P1 PMIC driver
nor the SPI NOR and EEPROM drivers look up supplies there.
Testing: all K1 DTBs build, and dtbs_check is clean for them with and
without this series. I have not run an SPL built from these trees on
hardware. On a Milk-V Jupiter running Linux I checked that the EEPROM,
PMIC and SPI NOR answer at the addresses described.
Changes in v2:
- Tag i2c8 in k1.dtsi instead of in every board file (Yixun)
- Rebase onto the spacemit dt-for-next branch, where buck1 now carries
the buck1_0v9 label on musepi-pro and the OrangePi boards
- Link to v1: https://lore.kernel.org/all/20261012235624.77993-1-alan.tseng.cs@gmail.com/
[1] https://lore.kernel.org/u-boot/5d323a11-da4e-4071-bdeb-ab5c03e8f85e@freeshell.de/
Hung-Chun Tseng (2):
riscv: dts: spacemit: k1: mark boot-critical SoC nodes bootph-pre-ram
riscv: dts: spacemit: mark K1 board boot devices bootph-pre-ram
arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi | 6 ++++++
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 6 ++++++
arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 7 +++++++
arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts | 7 +++++++
arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts | 4 ++++
arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 5 +++++
arch/riscv/boot/dts/spacemit/k1.dtsi | 13 +++++++++++++
7 files changed, 48 insertions(+)
base-commit: d05c6236496071916e19012cda7149465f15e66e
--
2.43.0
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 1/2] riscv: dts: spacemit: k1: mark boot-critical SoC nodes bootph-pre-ram
2026-10-17 18:01 [PATCH v2 0/2] riscv: dts: spacemit: mark K1 boot nodes bootph-pre-ram Hung-Chun Tseng
@ 2026-10-17 18:01 ` Hung-Chun Tseng
2026-10-17 21:05 ` E Shattow
2026-10-17 18:01 ` [PATCH v2 2/2] riscv: dts: spacemit: mark K1 board boot devices bootph-pre-ram Hung-Chun Tseng
1 sibling, 1 reply; 5+ messages in thread
From: Hung-Chun Tseng @ 2026-10-17 18:01 UTC (permalink / raw)
To: Yixun Lan, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
E Shattow, devicetree, linux-riscv, spacemit, linux-kernel
A bootloader SPL that follows the K1 BootROM runs from SRAM before DRAM
is up. It needs the root clocks, the clock and reset controllers, the
console UART, the I2C bus of the PMIC (i2c8, which every K1 board
uses), and the boot media controllers: SD (sdhci0), eMMC and QSPI NOR.
Mark these nodes bootph-pre-ram so an SPL can use the upstream device
tree as is, instead of carrying the tags in per-board overlays.
These are the SoC nodes that the mainline U-Boot SPL for K1 currently
tags in its board -u-boot.dtsi files.
Assisted-by: claude-opus-5-5 dtbs_check
Signed-off-by: Hung-Chun Tseng <alan.tseng.cs@gmail.com>
---
arch/riscv/boot/dts/spacemit/k1.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index 3fabfd341..5d9550272 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -322,6 +322,7 @@ cluster1_l2_cache: l2-cache1 {
clocks {
vctcxo_1m: clock-1m {
compatible = "fixed-clock";
+ bootph-pre-ram;
clock-frequency = <1000000>;
clock-output-names = "vctcxo_1m";
#clock-cells = <0>;
@@ -329,6 +330,7 @@ vctcxo_1m: clock-1m {
vctcxo_24m: clock-24m {
compatible = "fixed-clock";
+ bootph-pre-ram;
clock-frequency = <24000000>;
clock-output-names = "vctcxo_24m";
#clock-cells = <0>;
@@ -336,6 +338,7 @@ vctcxo_24m: clock-24m {
vctcxo_3m: clock-3m {
compatible = "fixed-clock";
+ bootph-pre-ram;
clock-frequency = <3000000>;
clock-output-names = "vctcxo_3m";
#clock-cells = <0>;
@@ -343,6 +346,7 @@ vctcxo_3m: clock-3m {
osc_32k: clock-32k {
compatible = "fixed-clock";
+ bootph-pre-ram;
clock-frequency = <32768>;
clock-output-names = "osc_32k";
#clock-cells = <0>;
@@ -586,6 +590,7 @@ i2c5: i2c@d4013800 {
syscon_apbc: system-controller@d4015000 {
compatible = "spacemit,k1-syscon-apbc";
reg = <0x0 0xd4015000 0x0 0x1000>;
+ bootph-pre-ram;
clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
<&vctcxo_24m>;
clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
@@ -726,6 +731,7 @@ i2c7: i2c@d401d000 {
i2c8: i2c@d401d800 {
compatible = "spacemit,k1-i2c";
reg = <0x0 0xd401d800 0x0 0x38>;
+ bootph-pre-ram;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&syscon_apbc CLK_TWSI8>,
@@ -857,6 +863,7 @@ pwm19: pwm@d4022c00 {
syscon_mpmu: system-controller@d4050000 {
compatible = "spacemit,k1-syscon-mpmu";
reg = <0x0 0xd4050000 0x0 0x209c>;
+ bootph-pre-ram;
clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
<&vctcxo_24m>;
clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
@@ -869,6 +876,7 @@ syscon_mpmu: system-controller@d4050000 {
pll: clock-controller@d4090000 {
compatible = "spacemit,k1-pll";
reg = <0x0 0xd4090000 0x0 0x1000>;
+ bootph-pre-ram;
clocks = <&vctcxo_24m>;
spacemit,mpmu = <&syscon_mpmu>;
#clock-cells = <1>;
@@ -877,6 +885,7 @@ pll: clock-controller@d4090000 {
syscon_apmu: system-controller@d4282800 {
compatible = "spacemit,k1-syscon-apmu";
reg = <0x0 0xd4282800 0x0 0x400>;
+ bootph-pre-ram;
clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
<&vctcxo_24m>;
clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
@@ -956,6 +965,7 @@ uart0: serial@d4017000 {
compatible = "spacemit,k1-uart",
"intel,xscale-uart";
reg = <0x0 0xd4017000 0x0 0x100>;
+ bootph-pre-ram;
clocks = <&syscon_apbc CLK_UART0>,
<&syscon_apbc CLK_UART0_BUS>;
clock-names = "core", "bus";
@@ -1085,6 +1095,7 @@ qspi: spi@d420c000 {
reg = <0x0 0xd420c000 0x0 0x1000>,
<0x0 0xb8000000 0x0 0xc00000>;
reg-names = "QuadSPI", "QuadSPI-memory";
+ bootph-pre-ram;
clocks = <&syscon_apmu CLK_QSPI_BUS>,
<&syscon_apmu CLK_QSPI>;
clock-names = "qspi_en", "qspi";
@@ -1328,6 +1339,7 @@ usb_dwc3: usb@c0a00000 {
sdhci0: mmc@d4280000 {
compatible = "spacemit,k1-sdhci";
reg = <0x0 0xd4280000 0x0 0x200>;
+ bootph-pre-ram;
clocks = <&syscon_apmu CLK_SDH_AXI>,
<&syscon_apmu CLK_SDH0>;
clock-names = "core", "io";
@@ -1341,6 +1353,7 @@ sdhci0: mmc@d4280000 {
emmc: mmc@d4281000 {
compatible = "spacemit,k1-sdhci";
reg = <0x0 0xd4281000 0x0 0x200>;
+ bootph-pre-ram;
clocks = <&syscon_apmu CLK_SDH_AXI>,
<&syscon_apmu CLK_SDH2>;
clock-names = "core", "io";
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 2/2] riscv: dts: spacemit: mark K1 board boot devices bootph-pre-ram
2026-10-17 18:01 [PATCH v2 0/2] riscv: dts: spacemit: mark K1 boot nodes bootph-pre-ram Hung-Chun Tseng
2026-10-17 18:01 ` [PATCH v2 1/2] riscv: dts: spacemit: k1: mark boot-critical SoC " Hung-Chun Tseng
@ 2026-10-17 18:01 ` Hung-Chun Tseng
2026-10-17 18:07 ` sashiko-bot
1 sibling, 1 reply; 5+ messages in thread
From: Hung-Chun Tseng @ 2026-10-17 18:01 UTC (permalink / raw)
To: Yixun Lan, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
E Shattow, devicetree, linux-riscv, spacemit, linux-kernel
On K1 boards an SPL reads the board EEPROM (0x50 on i2c2) to identify
the board, and before DRAM training it programs the P1 PMIC (0x41 on
i2c8) rails buck1, buck3 and aldo1. Boards that boot from SPI NOR also
need the flash on QSPI.
Mark these board peripherals bootph-pre-ram on the boards that have
them, together with i2c2 where the EEPROM sits. i2c8 is tagged in
k1.dtsi, as every K1 board connects the PMIC there.
Assisted-by: claude-opus-5-5 dtbs_check
Signed-off-by: Hung-Chun Tseng <alan.tseng.cs@gmail.com>
---
arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi | 6 ++++++
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 6 ++++++
arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 7 +++++++
arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts | 7 +++++++
arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts | 4 ++++
arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 5 +++++
6 files changed, 35 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi b/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi
index 81c40df2a..acb8fa2e6 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi
@@ -64,6 +64,7 @@ &pdma {
};
&i2c2 {
+ bootph-pre-ram;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_0_cfg>;
status = "okay";
@@ -71,6 +72,7 @@ &i2c2 {
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
+ bootph-pre-ram;
vcc-supply = <&buck3_1v8>;
pagesize = <16>;
read-only;
@@ -100,6 +102,7 @@ &i2c8 {
pmic@41 {
compatible = "spacemit,p1";
reg = <0x41>;
+ bootph-pre-ram;
interrupts = <64>;
vin1-supply = <®_vcc_4v>;
vin2-supply = <®_vcc_4v>;
@@ -113,6 +116,7 @@ pmic@41 {
regulators {
buck1 {
+ bootph-pre-ram;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <5000>;
@@ -127,6 +131,7 @@ buck2 {
};
buck3_1v8: buck3 {
+ bootph-pre-ram;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1800000>;
regulator-ramp-delay = <5000>;
@@ -155,6 +160,7 @@ buck6 {
};
aldo1: aldo1 {
+ bootph-pre-ram;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index 58035d886..b91db3204 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -187,6 +187,7 @@ &qspi {
};
&i2c2 {
+ bootph-pre-ram;
pinctrl-0 = <&i2c2_0_cfg>;
pinctrl-names = "default";
status = "okay";
@@ -194,6 +195,7 @@ &i2c2 {
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
+ bootph-pre-ram;
vcc-supply = <&buck3_1v8>; /* EEPROM_VCC1V8 */
pagesize = <16>;
read-only;
@@ -223,6 +225,7 @@ &i2c8 {
pmic@41 {
compatible = "spacemit,p1";
reg = <0x41>;
+ bootph-pre-ram;
interrupts = <64>;
vin1-supply = <®_vcc_4v>;
vin2-supply = <®_vcc_4v>;
@@ -236,6 +239,7 @@ pmic@41 {
regulators {
buck1_0v9: buck1 {
+ bootph-pre-ram;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <5000>;
@@ -250,6 +254,7 @@ buck2 {
};
buck3_1v8: buck3 {
+ bootph-pre-ram;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1800000>;
regulator-ramp-delay = <5000>;
@@ -278,6 +283,7 @@ buck6 {
};
aldo1: aldo1 {
+ bootph-pre-ram;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts
index 635e95aad..d2a39cf55 100644
--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts
@@ -201,6 +201,7 @@ &pdma {
};
&i2c2 {
+ bootph-pre-ram;
pinctrl-0 = <&i2c2_0_cfg>;
pinctrl-names = "default";
status = "okay";
@@ -208,6 +209,7 @@ &i2c2 {
eeprom@50 {
compatible = "atmel,24c04";
reg = <0x50>;
+ bootph-pre-ram;
vcc-supply = <&buck3_1v8>; /* EEPROM_VCC18 */
pagesize = <16>;
read-only;
@@ -230,6 +232,7 @@ &i2c8 {
pmic@41 {
compatible = "spacemit,p1";
reg = <0x41>;
+ bootph-pre-ram;
interrupts = <64>;
vin1-supply = <®_vcc_4v>;
vin2-supply = <®_vcc_4v>;
@@ -243,6 +246,7 @@ pmic@41 {
regulators {
buck1_0v9: buck1 {
+ bootph-pre-ram;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <5000>;
@@ -257,6 +261,7 @@ buck2 {
};
buck3_1v8: buck3 {
+ bootph-pre-ram;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1800000>;
regulator-ramp-delay = <5000>;
@@ -285,6 +290,7 @@ buck6 {
};
aldo1: aldo1 {
+ bootph-pre-ram;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
@@ -386,6 +392,7 @@ &qspi {
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
+ bootph-pre-ram;
spi-max-frequency = <26500000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts
index 23f32a8a3..a3d0e38ac 100644
--- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts
@@ -160,6 +160,7 @@ &pdma {
};
&i2c2 {
+ bootph-pre-ram;
pinctrl-0 = <&i2c2_0_cfg>;
pinctrl-names = "default";
status = "okay";
@@ -167,6 +168,7 @@ &i2c2 {
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
+ bootph-pre-ram;
vcc-supply = <&buck3_1v8>; /* EEPROM_VCC1V8 */
pagesize = <8>;
read-only;
@@ -199,6 +201,7 @@ &i2c8 {
pmic@41 {
compatible = "spacemit,p1";
reg = <0x41>;
+ bootph-pre-ram;
interrupts = <64>;
vin1-supply = <®_vcc_4v>;
vin2-supply = <®_vcc_4v>;
@@ -212,6 +215,7 @@ pmic@41 {
regulators {
buck1_0v9: buck1 {
+ bootph-pre-ram;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <5000>;
@@ -226,6 +230,7 @@ buck2 {
};
buck3_1v8: buck3 {
+ bootph-pre-ram;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1800000>;
regulator-ramp-delay = <5000>;
@@ -254,6 +259,7 @@ buck6 {
};
aldo1: aldo1 {
+ bootph-pre-ram;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
@@ -353,6 +359,7 @@ &qspi {
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
+ bootph-pre-ram;
spi-max-frequency = <26500000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts
index eb77aae9d..5e2fde8be 100644
--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts
@@ -187,6 +187,7 @@ &i2c8 {
pmic@41 {
compatible = "spacemit,p1";
reg = <0x41>;
+ bootph-pre-ram;
interrupts = <64>;
vin1-supply = <&vcc4v0>;
vin2-supply = <&vcc4v0>;
@@ -200,6 +201,7 @@ pmic@41 {
regulators {
buck1_0v9: buck1 {
+ bootph-pre-ram;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <5000>;
@@ -214,6 +216,7 @@ buck2 {
};
buck3_1v8: buck3 {
+ bootph-pre-ram;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1800000>;
regulator-ramp-delay = <5000>;
@@ -242,6 +245,7 @@ buck6 {
};
aldo1_3v3: aldo1 {
+ bootph-pre-ram;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
index 790234f35..d4adfc5b7 100644
--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
@@ -214,6 +214,7 @@ &i2c8 {
pmic@41 {
compatible = "spacemit,p1";
reg = <0x41>;
+ bootph-pre-ram;
interrupts = <64>;
vin1-supply = <&vcc4v0>;
vin2-supply = <&vcc4v0>;
@@ -227,6 +228,7 @@ pmic@41 {
regulators {
buck1_0v9: buck1 {
+ bootph-pre-ram;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <5000>;
@@ -241,6 +243,7 @@ buck2 {
};
buck3_1v8: buck3 {
+ bootph-pre-ram;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1800000>;
regulator-ramp-delay = <5000>;
@@ -269,6 +272,7 @@ buck6 {
};
aldo1: aldo1 {
+ bootph-pre-ram;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
@@ -366,6 +370,7 @@ &qspi {
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
+ bootph-pre-ram;
spi-max-frequency = <26500000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 2/2] riscv: dts: spacemit: mark K1 board boot devices bootph-pre-ram
2026-10-17 18:01 ` [PATCH v2 2/2] riscv: dts: spacemit: mark K1 board boot devices bootph-pre-ram Hung-Chun Tseng
@ 2026-10-17 18:07 ` sashiko-bot
0 siblings, 0 replies; 5+ messages in thread
From: sashiko-bot @ 2026-10-17 18:07 UTC (permalink / raw)
To: Hung-Chun Tseng; +Cc: devicetree, robh, conor+dt
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] riscv: dts: spacemit: missing bootph-pre-ram on i2c2/eeprom@50 for OrangePi
--
commit 5b0574f2bdfb9fa217393dc3ab5d437d4cba162a
Author: Hung-Chun Tseng <alan.tseng.cs@gmail.com>
riscv: dts: spacemit: mark K1 board boot devices bootph-pre-ram
This commit marks the board EEPROM, i2c2, the P1 PMIC, and QSPI NOR flash
nodes with bootph-pre-ram across SpacemiT K1 board device trees so that
pre-RAM SPL can access them.
> diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts
> index eb77aae9d6008..5e2fde8be7692 100644
> --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts
> +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts
> @@ -187,6 +187,7 @@ &i2c8 {
> pmic@41 {
> compatible = "spacemit,p1";
> reg = <0x41>;
> + bootph-pre-ram;
> interrupts = <64>;
> vin1-supply = <&vcc4v0>;
> vin2-supply = <&vcc4v0>;
[ ... ]
> diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
> index 790234f3550a3..d4adfc5b74374 100644
> --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
> +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
> @@ -214,6 +214,7 @@ &i2c8 {
> pmic@41 {
> compatible = "spacemit,p1";
> reg = <0x41>;
> + bootph-pre-ram;
> interrupts = <64>;
> vin1-supply = <&vcc4v0>;
> vin2-supply = <&vcc4v0>;
[Severity: Medium]
Should &i2c2 and eeprom@50 also be marked with bootph-pre-ram in
arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts and
arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts?
The commit message notes that the SPL reads the board EEPROM at 0x50 on i2c2
to identify the board, and marks both i2c2 and eeprom@50 on the other K1
boards. Both k1-orangepi-r2s.dts and k1-orangepi-rv2.dts also enable &i2c2
and define the board identification EEPROM right above &i2c8:
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_0_cfg>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
...
};
};
Since i2c2 in arch/riscv/boot/dts/spacemit/k1.dtsi is not tagged with
bootph-pre-ram either, won't an SPL build that filters for bootph-pre-ram
strip both i2c2 and eeprom@50 on OrangePi R2S and OrangePi RV2?
(Alternatively, since every K1 board in the tree connects eeprom@50 on i2c2,
could i2c2 be tagged in k1.dtsi just like i2c8?)
[ ... ]
>
>
>
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261017180141.3477743-1-alan.tseng.cs@gmail.com?part=2
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/2] riscv: dts: spacemit: k1: mark boot-critical SoC nodes bootph-pre-ram
2026-10-17 18:01 ` [PATCH v2 1/2] riscv: dts: spacemit: k1: mark boot-critical SoC " Hung-Chun Tseng
@ 2026-10-17 21:05 ` E Shattow
0 siblings, 0 replies; 5+ messages in thread
From: E Shattow @ 2026-10-17 21:05 UTC (permalink / raw)
To: Hung-Chun Tseng, Yixun Lan, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
devicetree, linux-riscv, spacemit, linux-kernel
Hi Hung-Chun,
On 10/17/26 11:01, Hung-Chun Tseng wrote:
> A bootloader SPL that follows the K1 BootROM runs from SRAM before DRAM
> is up. It needs the root clocks, the clock and reset controllers, the
> console UART, the I2C bus of the PMIC (i2c8, which every K1 board
> uses), and the boot media controllers: SD (sdhci0), eMMC and QSPI NOR.
> Mark these nodes bootph-pre-ram so an SPL can use the upstream device
> tree as is, instead of carrying the tags in per-board overlays.
>
> These are the SoC nodes that the mainline U-Boot SPL for K1 currently
> tags in its board -u-boot.dtsi files.
Drop this last paragraph/sentence or place after scissors line, not for
the commit message itself.
Device tree in Linux describes hardware and not the arbitrary needs of
some other specific software project. Any SPL executed by hardware
BootROM SPL loader functionality in the SoC mask ROM will reasonably be
expected to need bootph-pre-ram tags on peripherals configured by that
same hardware workflow so boot can be successful in an initially
SRAM-constrained environment before DRAM setup. This is not the same as
stating that "U-Boot SPL for K1 currently tags..." which is a
description of arbitrary software and not any correct justification.
Examples illustrative how to reason about why bootph-pre-ram tags belong
upstream and not as recommendations for what to say in the commit message:
* Valid here upstream: BootROM serial UART SPL loader => U-Boot SPL UART
YMODEM U-Boot main app loader
* Valid here upstream: BootROM USB fastboot SPL loader => U-Boot SPL
fastboot U-Boot main app loader
* Valid downstream, not upstream here: BootROM USB fastboot SPL loader
=> U-Boot SPL UART YMODEM U-Boot main app loader; it is valid downstream
without additional effort as a side-effect of implementing all the valid
upstream bootph-pre-ram tags
* Valid downstream, not upstream here: BootROM serial UART SPL loader =>
serial UART-attached Bluetooth BLE VibeCodedBootLoader; When there is no
such Bluetooth BLE loader functionality in MaskROM BootROM code, any
bootloader project may implement such exotic interface and add
bootph-pre-ram tags in its own overrides downstream.
This is not so easy to review for lack of knowing the fact of what all
peripherals that BootROM may configure, and what tags might reasonably
be then extended to any SPL in any given BootROM SPL loader workflow.
Without knowledge of the BootROM code we then rely on vendor-employed
developer review and community testing for outcomes.
>
> Assisted-by: claude-opus-5-5 dtbs_check
> Signed-off-by: Hung-Chun Tseng <alan.tseng.cs@gmail.com>
> ---
> arch/riscv/boot/dts/spacemit/k1.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> index 3fabfd341..5d9550272 100644
> --- a/arch/riscv/boot/dts/spacemit/k1.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> @@ -322,6 +322,7 @@ cluster1_l2_cache: l2-cache1 {
> clocks {
> vctcxo_1m: clock-1m {
> compatible = "fixed-clock";
> + bootph-pre-ram;
> clock-frequency = <1000000>;
> clock-output-names = "vctcxo_1m";
> #clock-cells = <0>;
> @@ -329,6 +330,7 @@ vctcxo_1m: clock-1m {
>
> vctcxo_24m: clock-24m {
> compatible = "fixed-clock";
> + bootph-pre-ram;
> clock-frequency = <24000000>;
> clock-output-names = "vctcxo_24m";
> #clock-cells = <0>;
> @@ -336,6 +338,7 @@ vctcxo_24m: clock-24m {
>
> vctcxo_3m: clock-3m {
> compatible = "fixed-clock";
> + bootph-pre-ram;
> clock-frequency = <3000000>;
> clock-output-names = "vctcxo_3m";
> #clock-cells = <0>;
> @@ -343,6 +346,7 @@ vctcxo_3m: clock-3m {
>
> osc_32k: clock-32k {
> compatible = "fixed-clock";
> + bootph-pre-ram;
> clock-frequency = <32768>;
> clock-output-names = "osc_32k";
> #clock-cells = <0>;
> @@ -586,6 +590,7 @@ i2c5: i2c@d4013800 {
> syscon_apbc: system-controller@d4015000 {
> compatible = "spacemit,k1-syscon-apbc";
> reg = <0x0 0xd4015000 0x0 0x1000>;
> + bootph-pre-ram;
> clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
> <&vctcxo_24m>;
> clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
> @@ -726,6 +731,7 @@ i2c7: i2c@d401d000 {
> i2c8: i2c@d401d800 {
> compatible = "spacemit,k1-i2c";
> reg = <0x0 0xd401d800 0x0 0x38>;
> + bootph-pre-ram;
> #address-cells = <1>;
> #size-cells = <0>;
> clocks = <&syscon_apbc CLK_TWSI8>,
> @@ -857,6 +863,7 @@ pwm19: pwm@d4022c00 {
> syscon_mpmu: system-controller@d4050000 {
> compatible = "spacemit,k1-syscon-mpmu";
> reg = <0x0 0xd4050000 0x0 0x209c>;
> + bootph-pre-ram;
> clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
> <&vctcxo_24m>;
> clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
> @@ -869,6 +876,7 @@ syscon_mpmu: system-controller@d4050000 {
> pll: clock-controller@d4090000 {
> compatible = "spacemit,k1-pll";
> reg = <0x0 0xd4090000 0x0 0x1000>;
> + bootph-pre-ram;
> clocks = <&vctcxo_24m>;
> spacemit,mpmu = <&syscon_mpmu>;
> #clock-cells = <1>;
> @@ -877,6 +885,7 @@ pll: clock-controller@d4090000 {
> syscon_apmu: system-controller@d4282800 {
> compatible = "spacemit,k1-syscon-apmu";
> reg = <0x0 0xd4282800 0x0 0x400>;
> + bootph-pre-ram;
> clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
> <&vctcxo_24m>;
> clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
> @@ -956,6 +965,7 @@ uart0: serial@d4017000 {
> compatible = "spacemit,k1-uart",
> "intel,xscale-uart";
> reg = <0x0 0xd4017000 0x0 0x100>;
> + bootph-pre-ram;
> clocks = <&syscon_apbc CLK_UART0>,
> <&syscon_apbc CLK_UART0_BUS>;
> clock-names = "core", "bus";
> @@ -1085,6 +1095,7 @@ qspi: spi@d420c000 {
> reg = <0x0 0xd420c000 0x0 0x1000>,
> <0x0 0xb8000000 0x0 0xc00000>;
> reg-names = "QuadSPI", "QuadSPI-memory";
> + bootph-pre-ram;
> clocks = <&syscon_apmu CLK_QSPI_BUS>,
> <&syscon_apmu CLK_QSPI>;
> clock-names = "qspi_en", "qspi";
> @@ -1328,6 +1339,7 @@ usb_dwc3: usb@c0a00000 {
> sdhci0: mmc@d4280000 {
> compatible = "spacemit,k1-sdhci";
> reg = <0x0 0xd4280000 0x0 0x200>;
> + bootph-pre-ram;
> clocks = <&syscon_apmu CLK_SDH_AXI>,
> <&syscon_apmu CLK_SDH0>;
> clock-names = "core", "io";
> @@ -1341,6 +1353,7 @@ sdhci0: mmc@d4280000 {
> emmc: mmc@d4281000 {
> compatible = "spacemit,k1-sdhci";
> reg = <0x0 0xd4281000 0x0 0x200>;
> + bootph-pre-ram;
> clocks = <&syscon_apmu CLK_SDH_AXI>,
> <&syscon_apmu CLK_SDH2>;
> clock-names = "core", "io";
Presumably the BootROM does configure all of the above? If so, the shape
of this looks good to me, the device tree node sorting where
bootph-pre-ram is added appears correct. With that,
Reviewed-by: E Shattow <e@freeshell.de>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2026-10-17 21:06 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2026-10-17 18:01 [PATCH v2 0/2] riscv: dts: spacemit: mark K1 boot nodes bootph-pre-ram Hung-Chun Tseng
2026-10-17 18:01 ` [PATCH v2 1/2] riscv: dts: spacemit: k1: mark boot-critical SoC " Hung-Chun Tseng
2026-10-17 21:05 ` E Shattow
2026-10-17 18:01 ` [PATCH v2 2/2] riscv: dts: spacemit: mark K1 board boot devices bootph-pre-ram Hung-Chun Tseng
2026-10-17 18:07 ` sashiko-bot
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