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* [PATCH 0/2] Add ADLINK LEC-iMX95 board support
@ 2026-11-02  6:56 Dinesh kumar v
  2026-11-02  6:56 ` [PATCH 1/2] dt-bindings: arm: fsl: Add ADLINK LEC-iMX95 Dinesh kumar v
                   ` (2 more replies)
  0 siblings, 3 replies; 11+ messages in thread
From: Dinesh kumar v @ 2026-11-02  6:56 UTC (permalink / raw)
  To: Frank.Li, robh, krzk+dt, conor+dt, s.hauer
  Cc: imx, devicetree, linux-arm-kernel, kernel, festevam,
	Dinesh kumar v

This patch series adds device tree support for the ADLINK LEC-iMX95
module on the I-Pi SMARC Plus carrier board.

The series includes:

- Add the ADLINK LEC-iMX95 compatible strings to the Freescale i.MX
  device tree binding.

- Add the common device tree description for the LEC-iMX95 module.

- Add the I-Pi SMARC Plus carrier board device tree.

- Add the new board DTB to the Freescale device tree Makefile.

The module device tree describes the onboard peripherals and interfaces,
while the carrier board device tree describes the carrier-specific
hardware connections.

The device tree has been compiled and validated using DT schema checks.

Hardware: ADLINK LEC-iMX95
Carrier board: I-Pi SMARC Plus
SoC: NXP i.MX95

Signed-off-by: Dinesh kumar v <dinesh.v@adlinktech.com>

Dinesh kumar v (2):
  dt-bindings: arm: fsl: Add ADLINK LEC-iMX95
  arm64: dts: imx95: Add ADLINK LEC-iMX95 board support

 .../devicetree/bindings/arm/fsl.yaml          |   6 +
 arch/arm64/boot/dts/freescale/Makefile        |   1 +
 .../dts/freescale/imx95-lec-ipi-smarc.dts     | 237 ++++++++++
 arch/arm64/boot/dts/freescale/imx95-lec.dtsi  | 414 ++++++++++++++++++
 4 files changed, 658 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx95-lec-ipi-smarc.dts
 create mode 100644 arch/arm64/boot/dts/freescale/imx95-lec.dtsi

-- 
2.25.1


^ permalink raw reply	[flat|nested] 11+ messages in thread
* [PATCH 1/2] dt-bindings: arm: fsl: Add ADLINK LEC-iMX95
  2026-11-02  6:56 [PATCH 0/2] Add ADLINK LEC-iMX95 board support Dinesh kumar v
@ 2026-11-02  6:56 ` Dinesh kumar v
  2026-11-02  7:04   ` sashiko-bot
  2026-11-02  6:56 ` [PATCH 2/2] arm64: dts: imx95: Add ADLINK LEC-iMX95 board support Dinesh kumar v
  2026-11-02 10:26 ` [PATCH v2 0/3] " Dinesh kumar v
  2 siblings, 1 reply; 11+ messages in thread
From: Dinesh kumar v @ 2026-11-02  6:56 UTC (permalink / raw)
  To: Frank.Li, robh, krzk+dt, conor+dt, s.hauer
  Cc: imx, devicetree, linux-arm-kernel, kernel, festevam,
	Dinesh kumar v

Add compatible strings for the ADLINK LEC-iMX95 module and its
I-Pi SMARC Plus carrier board.

This allows the board to be identified using the following
compatible strings:
"adlink,lec-imx95-ipi-smarc",
"adlink,lec-imx95",
"fsl,imx95".

Signed-off-by: Dinesh kumar v <dinesh.v@adlinktech.com>
---
 Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index cb99fb74805b..1757ca4b0f44 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1636,6 +1636,12 @@ properties:
           - const: variscite,var-dart-mx95 # Variscite DART-MX95 SOM
           - const: fsl,imx95
 
+      - description: ADLINK LEC-iMX95 based Boards
+        items:
+          - const: adlink,lec-imx95-ipi-smarc
+          - const: adlink,lec-imx95
+          - const: fsl,imx95
+
       - description: i.MXRT1050 based Boards
         items:
           - enum:
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [PATCH 2/2] arm64: dts: imx95: Add ADLINK LEC-iMX95 board support
  2026-11-02  6:56 [PATCH 0/2] Add ADLINK LEC-iMX95 board support Dinesh kumar v
  2026-11-02  6:56 ` [PATCH 1/2] dt-bindings: arm: fsl: Add ADLINK LEC-iMX95 Dinesh kumar v
@ 2026-11-02  6:56 ` Dinesh kumar v
  2026-11-02  7:10   ` sashiko-bot
  2026-11-02 10:26 ` [PATCH v2 0/3] " Dinesh kumar v
  2 siblings, 1 reply; 11+ messages in thread
From: Dinesh kumar v @ 2026-11-02  6:56 UTC (permalink / raw)
  To: Frank.Li, robh, krzk+dt, conor+dt, s.hauer
  Cc: imx, devicetree, linux-arm-kernel, kernel, festevam,
	Dinesh kumar v

Add device tree support for the ADLINK LEC-iMX95 module on the
I-Pi SMARC Plus carrier board.

Add the common module device tree description and the carrier-specific
device tree describing the hardware interfaces and peripherals.

Also add the new board DTB to the Freescale device tree Makefile.

Signed-off-by: Dinesh kumar v <dinesh.v@adlinktech.com>
---
 arch/arm64/boot/dts/freescale/Makefile        |   1 +
 .../dts/freescale/imx95-lec-ipi-smarc.dts     | 237 ++++++++++
 arch/arm64/boot/dts/freescale/imx95-lec.dtsi  | 414 ++++++++++++++++++
 3 files changed, 652 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx95-lec-ipi-smarc.dts
 create mode 100644 arch/arm64/boot/dts/freescale/imx95-lec.dtsi

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index a80cccf34eb5..26b432127faa 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -983,6 +983,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-ivy.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-mallow.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-yavia.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-zinnia.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx95-lec-ipi-smarc.dtb
 
 imx95-15x15-evk-pcie-dtbs += imx95-15x15-evk.dtb imx-m2-pcie.dtbo
 dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx95-lec-ipi-smarc.dts b/arch/arm64/boot/dts/freescale/imx95-lec-ipi-smarc.dts
new file mode 100644
index 000000000000..9a77bff42b22
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-lec-ipi-smarc.dts
@@ -0,0 +1,237 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (C) 2026 ADLINK Technology Inc.
+ *
+ * https://www.adlinktech.com/products/Computer_on_Modules/SMARC/LEC-IMX95
+ * https://www.adlinktech.com/products/computer_on_modules/SMARCStarterKits/I-Pi_SMARC_IMX95
+ */
+
+/dts-v1/;
+
+#include "imx95-lec.dtsi"
+
+/ {
+	model = "ADLINK LEC-iMX95 on I-Pi SMARC Plus Carrier Board";
+	compatible = "adlink,lec-imx95-ipi-smarc",
+		     "adlink,lec-imx95",
+		     "fsl,imx95";
+};
+
+/* Ethernet SMARC GBE0 */
+&enetc_port0 {
+	pinctrl-0 = <&pinctrl_enetc0>;
+	phy-handle = <&ethphy0>;
+	pinctrl-names = "default";
+	phy-mode = "rgmii-id";
+
+	status = "okay";
+};
+
+/* Ethernet SMARC GBE1 */
+&enetc_port1 {
+	pinctrl-0 = <&pinctrl_enetc1>;
+	phy-handle = <&ethphy1>;
+	pinctrl-names = "default";
+	phy-mode = "rgmii-id";
+
+	status = "okay";
+};
+
+&lpi2c2 {
+	clock-frequency = <100000>;
+	pinctrl-0 = <&pinctrl_lpi2c2>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	/* U1000 SX1509BIULTRT_SEMTECH */
+	i2c2_gpio_expander_71: pinctrl@71 {
+		/*
+		 * GPIO Expander Mapping:
+		 * - 0: ENET1_RST_B_3V		=>		U2001
+		 * - 1: ENET2_RST_B_3V		=>		U2101
+		 * - 2: SERDES_RST#_3V		=>		SMARC S77 PCIE_C_RST
+		 * - 3: RC210_EN_3V		=>		U1300, RC21008B001GND
+		 * - 4: LT9611_RSTN_3V		=>		U1500
+		 * - 5: HDMI_INT_3V		<=		U1500
+		 * - 6: PCIEA_RST#_3V		=>		SMARC P75
+		 * - 7: PCIEB_RST#_3V		=>		SMARC S76
+		 * - 8: TPM_RST_N_1V8		=>		U2400
+		 * - 9: LID#_1V8		<=	R1005	SMARC S148
+		 * - 10: SLEEP#_1V8		<=	R1010	SMARC S149
+		 * - 11: CHARGING#_1V8		<=	R1007	SMARC S151
+		 * - 12: CHARGER_PRSNT#_1V8	<=	R1011	SMARC S152
+		 * - 13: BATLOW#_1V8		<=	R1014	SMARC S156
+		 * - 14: TEST#_1V8		<=	R1015	SMARC S157
+		 * - 15: DSI0_TE_1V8		<=	R1087	SMARC S144
+		 */
+		compatible = "semtech,sx1509q";
+		reg = <0x71>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		interrupt-parent = <&gpio4>;
+		interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-0 = <&pinctrl_sx1509q>;
+		pinctrl-names = "default";
+		semtech,probe-reset;
+
+		status = "okay";
+	};
+};
+
+&lpi2c3 {
+	pinctrl-0 = <&pinctrl_lpi2c3>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&lpi2c8 {
+	pinctrl-0 = <&pinctrl_lpi2c8>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+/* SMARC SPI0 */
+&lpspi6 {
+	cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>, <&gpio2 24 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&pinctrl_lpspi6>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+/* SMARC SER1, used as the Linux Console */
+&lpuart1 {
+	bootph-pre-ram;
+	pinctrl-0 = <&pinctrl_uart1>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&lpuart2 {
+	pinctrl-0 = <&pinctrl_uart2>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&lpuart5 {
+	pinctrl-0 = <&pinctrl_uart5>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+/* SMARC SER2 */
+&lpuart6 {
+	pinctrl-0 = <&pinctrl_uart6>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+/* SMARC SER0 */
+&lpuart7 {
+	pinctrl-0 = <&pinctrl_uart7>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&netc_blk_ctrl {
+	status = "okay";
+};
+
+&netc_emdio {
+	pinctrl-0 = <&pinctrl_emdio>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	ethphy0: ethernet-phy@1 {
+		compatible = "ethernet-phy-id001c.c916";
+		reg = <1>;
+		eee-broken-1000t;
+		realtek,clkout-disable;
+	};
+
+	ethphy1: ethernet-phy@4 {
+		compatible = "ethernet-phy-id001c.c916";
+		reg = <4>;
+		eee-broken-1000t;
+		realtek,clkout-disable;
+	};
+};
+
+&netc_timer {
+	status = "okay";
+};
+
+&netcmix_blk_ctrl {
+	status = "okay";
+};
+
+/* SMARC PCIE_A */
+&pcie0 {
+	pinctrl-0 = <&pinctrl_pcie0>;
+	pinctrl-names = "default";
+	supports-clkreq;
+
+	status = "okay";
+};
+
+&pcie0_port0 {
+	reset-gpios = <&i2c2_gpio_expander_71 6 GPIO_ACTIVE_LOW>; /* PCIEA_RST#_3V */
+};
+
+/* U1900 AW-CM276NF */
+&pcie1 {
+	pinctrl-0 = <&pinctrl_pcie1>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie1_port0 {
+	reset-gpios = <&i2c2_gpio_expander_71 7 GPIO_ACTIVE_LOW>; /* PCIEB_RST#_3V */
+};
+
+/* SMARC USB0 */
+&usb2 {
+	dr_mode = "host";
+	hnp-disable;
+	adp-disable;
+	srp-disable;
+	disable-over-current;
+
+	status = "okay";
+};
+
+&usb3 {
+	status = "okay";
+};
+
+&usb3_dwc3 {
+	dr_mode = "host";
+	snps,dis-u1-entry-quirk;
+	snps,dis-u2-entry-quirk;
+
+	status = "okay";
+};
+
+&usb3_phy {
+	status = "okay";
+};
+
+&usdhc1 {
+	status = "okay";
+};
+
+&usdhc2 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx95-lec.dtsi b/arch/arm64/boot/dts/freescale/imx95-lec.dtsi
new file mode 100644
index 000000000000..5402cb360888
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-lec.dtsi
@@ -0,0 +1,414 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (C) 2026 ADLINK Technology Inc.
+ * https://www.adlinktech.com/products/Computer_on_Modules/SMARC/LEC-IMX95
+ * https://www.adlinktech.com/products/computer_on_modules/SMARCStarterKits/I-Pi_SMARC_IMX95
+ */
+
+#include "imx95.dtsi"
+
+/ {
+	aliases {
+		ethernet0 = &enetc_port0;
+		ethernet1 = &enetc_port1;
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+		i2c1 = &lpi2c2;
+		i2c2 = &lpi2c3;
+		i2c7 = &lpi2c8;
+		mmc0 = &usdhc1;
+		mmc1 = &usdhc2;
+		serial0 = &lpuart1;
+		serial1 = &lpuart2;
+		serial4 = &lpuart5;
+		serial5 = &lpuart6;
+		serial6 = &lpuart7;
+		spi0 = &lpspi6;
+		usb0 = &usb3_dwc3;
+		usb1 = &usb2;
+	};
+
+	chosen {
+		stdout-path = &lpuart1;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x01 0x00>;
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2 {
+		compatible = "regulator-fixed";
+		bootph-pre-ram;
+		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+		enable-active-high;
+		pinctrl-names = "default";
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+		regulator-name = "VDD_SD2_3V3";
+		off-on-delay-us = <12000>;
+	};
+
+	reserved-memory {
+		ranges;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		linux_cma: linux,cma {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0 0x80000000 0 0x7f000000>;
+			reusable;
+			size = <0 0x3c000000>;
+			linux,cma-default;
+		};
+	};
+};
+
+&gpio2 {
+	gpio-line-names =
+		"SMARC_SPI0_CS0#",	/* 0 - GPIO_IO00 */
+		"SMARC_SPI0_DIN",	/* 1 - GPIO_IO01 */
+		"SMARC_SPI0_DO",	/* 2 - GPIO_IO02 */
+		"SMARC_SPI0_CK",	/* 3 - GPIO_IO03 */
+		"",			/* 4 - GPIO_IO04 */
+		"",			/* 5 - GPIO_IO05 */
+		"",			/* 6 - GPIO_IO06 */
+		"",			/* 7 - GPIO_IO07 */
+		"SMARC_UART0_TXD",	/* 8 - GPIO_IO08 */
+		"SMARC_UART0_RXD",	/* 9 - GPIO_IO09 */
+		"SMARC_UART0_CTS_B",	/* 10 - GPIO_IO10 */
+		"SMARC_UART0_RTS_B",	/* 11 - GPIO_IO11 */
+		"SMARC_I2C_GP_DAT",	/* 12 - GPIO_IO12 */
+		"SMARC_I2C_GP_CK",	/* 13 - GPIO_IO13 */
+		"UART3_TXD_1V8",	/* 14 - GPIO_IO14 */
+		"UART3_RXD_1V8",	/* 15 - GPIO_IO15 */
+		"SAI3_TXC_1V8",		/* 16 - GPIO_IO16 */
+		"SAI3_MCLK_1V8",	/* 17 - GPIO_IO17 */
+		"SMB_INT_B_1V8",	/* 18 - GPIO_IO18 */
+		"LVDS0_BKLT_PWM_1V8",	/* 19 - GPIO_IO19 */
+		"SAI3_RXD_1V8",		/* 20 - GPIO_IO20 */
+		"SAI3_TXD_1V8",		/* 21 - GPIO_IO21 */
+		"FAN_PWM_1V8",		/* 22 - GPIO_IO22 */
+		"LVDS1_BKLT_PWM_1V8",	/* 23 - GPIO_IO23 */
+		"SPI6_SS1_1V8",		/* 24 - GPIO_IO24 */
+		"",			/* 25 - GPIO_IO25 */
+		"SAI3_TXFS_1V8",	/* 26 - GPIO_IO26 */
+		"TPM_INT_N_1V8",	/* 27 - GPIO_IO27 */
+		"SMARC_I2C_PM_DAT",	/* 28 - GPIO_IO28 */
+		"SMARC_I2C_PM_CK",	/* 29 - GPIO_IO29 */
+		"SMARC_CAN1_TX",	/* 30 - GPIO_IO30 (SMARC CAN1_H via transceiver) */
+		"SMARC_CAN1_RX";	/* 31 - GPIO_IO31 (SMARC CAN1_L via transceiver) */
+};
+
+&gpio3 {
+	gpio-line-names =
+		"SD2_CD_B",
+		"SD2_CLK",
+		"SD2_CMD",
+		"SD2_DATA0",
+		"SD2_DATA1",
+		"SD2_DATA2",
+		"SD2_DATA3",
+		"SD2_RST_B_1V8A3V",
+		"SD1_CLK",
+		"SD1_CMD",
+		"SD1_DATA0",
+		"SD1_DATA1",
+		"SD1_DATA2",
+		"SD1_DATA3",
+		"SD1_DATA4",
+		"SD1_DATA5",
+		"SD1_DATA6",
+		"SD1_DATA7",
+		"SD1_STROBE",
+		"SD2_VSEL_1V8",
+		"SD3_CLK",
+		"SD3_CMD",
+		"SD3_DATA0",
+		"SD3_DATA1",
+		"SD3_DATA2",
+		"SD3_DATA3",
+		"CCM_CLKO1",
+		"CCM_CLKO2",
+		"DAP_TDI",
+		"DAP_TMS_SWDIO",
+		"DAP_TCLK_SWCLK",
+		"DAP_TDO_TRACESWO";
+};
+
+&gpio4 {
+	gpio-line-names =
+		"ENET1_MDC",
+		"ENET1_MDIO",
+		"ENET1_TD3",
+		"ENET1_TD2",
+		"ENET1_TD1",
+		"ENET1_TD0",
+		"ENET1_TX_CTL",
+		"ENET1_TXC",
+		"ENET1_RX_CTL",
+		"ENET1_RXC",
+		"ENET1_RD0",
+		"ENET1_RD1",
+		"ENET1_RD2",
+		"ENET1_RD3",
+		"RTC_INT#_1V8",
+		"IOEXP2_INT#_1V8",
+		"ENET2_TD3",
+		"ENET2_TD2",
+		"ENET2_TD1",
+		"ENET2_TD0",
+		"ENET2_TX_CTL",
+		"ENET2_TXC",
+		"ENET2_RX_CTL",
+		"ENET2_RXC",
+		"ENET2_RD0",
+		"ENET2_RD1",
+		"ENET2_RD2",
+		"ENET2_RD3",
+		"CCM_CLKO3",
+		"CCM_CLKO4";
+};
+
+&gpio5 {
+	gpio-line-names =
+		"QSPIA_DATA0",
+		"QSPIA_DATA1",
+		"QSPIA_DATA2",
+		"QSPIA_DATA3",
+		"SKU_CONFIG1_1V8",
+		"SKU_CONFIG2_1V8",
+		"SKU_CONFIG3_1V8",
+		"SYS_STATUS_1V8",
+		"SD2_WP_1V8",
+		"QSPIA_SCLK",
+		"QSPIA_nSS0",
+		"SYS_RST#_1V8",
+		"PCIE1_IMX_CLKREQ#_1V8",
+		"MCU_INTB1_1V8",
+		"MCU_INTB2_1V8",
+		"PCIE2_IMX_CLKREQ#_1V8",
+		"ENET1_INT_B_1V8",
+		"ENET2_INT_B_1V8";
+};
+
+&usdhc1 {
+	bootph-pre-ram;
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	pinctrl-3 = <&pinctrl_usdhc1>;
+	bus-width = <8>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+	no-sdio;
+	no-sd;
+	non-removable;
+};
+
+&usdhc2 {
+	bootph-pre-ram;
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+	bus-width = <4>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+};
+
+&scmi_iomuxc {
+	pinctrl_emdio: emdiogrp {
+		fsl,pins = <IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC		0x50e>,
+			   <IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO		0x90e>;
+	};
+
+	pinctrl_enetc0: enetc0grp {
+		fsl,pins = <IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3		0x50e>,
+			   <IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2		0x50e>,
+			   <IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1		0x50e>,
+			   <IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0		0x50e>,
+			   <IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL	0x57e>,
+			   <IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK	        0x58e>,
+			   <IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL	0x57e>,
+			   <IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK	        0x58e>,
+			   <IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0		0x57e>,
+			   <IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1		0x57e>,
+			   <IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2		0x57e>,
+			   <IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3		0x57e>;
+	};
+
+	pinctrl_enetc1: enetc1grp {
+		fsl,pins = <IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3		0x57e>,
+			   <IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2		0x57e>,
+			   <IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1		0x57e>,
+			   <IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0		0x57e>,
+			   <IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL	0x57e>,
+			   <IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK	        0x5fe>,
+			   <IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL	0x57e>,
+			   <IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK	        0x5fe>,
+			   <IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0		0x57e>,
+			   <IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1		0x57e>,
+			   <IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2		0x57e>,
+			   <IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3		0x57e>;
+	};
+
+	pinctrl_lpi2c2: lpi2c2grp {
+		fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL		0x40000b9e>,
+			   <IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA		0x40000b9e>;
+	};
+
+	pinctrl_lpi2c3: lpi2c3grp {
+		fsl,pins = <IMX95_PAD_GPIO_IO28__LPI2C3_SDA			0x40000b9e>,
+			   <IMX95_PAD_GPIO_IO29__LPI2C3_SCL			0x40000b9e>;
+	};
+
+	pinctrl_lpi2c8: lpi2c8grp {
+		fsl,pins = <IMX95_PAD_GPIO_IO13__LPI2C8_SCL		0x4000007e>,
+			   <IMX95_PAD_GPIO_IO12__LPI2C8_SDA		0x4000007e>;
+	};
+
+	pinctrl_lpspi6: lpspi6grp {
+		fsl,pins = <IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0		0x1fe>,
+			   <IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24		0x1fe>,
+			   <IMX95_PAD_GPIO_IO01__LPSPI6_SIN		0x3fe>,
+			   <IMX95_PAD_GPIO_IO02__LPSPI6_SOUT		0x3fe>,
+			   <IMX95_PAD_GPIO_IO03__LPSPI6_SCK		0x3fe>;
+	};
+
+	pinctrl_pcie0: pcie0grp {
+		fsl,pins = <IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B		0x4000031e>;
+	};
+
+	pinctrl_pcie1: pcie1grp {
+		fsl,pins = <IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B		0x4000031e>;
+	};
+
+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+		bootph-pre-ram;
+		fsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7		0x31e>;
+	};
+
+	pinctrl_sx1509q: sx1509qgrp {
+		fsl,pins = <IMX95_PAD_ENET2_MDIO__GPIO4_IO_BIT15		0x1fe>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		bootph-pre-ram;
+		fsl,pins = <IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX	0x31e>,
+			   <IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX	0x31e>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX	0x31e>,
+			   <IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX	0x31e>;
+	};
+
+	pinctrl_uart5: uart5grp {
+		fsl,pins = <IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX			0x31e>,
+			   <IMX95_PAD_DAP_TDI__LPUART5_RX				0x31e>,
+			   <IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B			0x31e>,
+			   <IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B			0x31e>;
+	};
+
+	pinctrl_uart6: uart6grp {
+		fsl,pins = <IMX95_PAD_GPIO_IO04__LPUART6_TX				0x31e>,
+			   <IMX95_PAD_GPIO_IO05__LPUART6_RX				0x31e>,
+			   <IMX95_PAD_GPIO_IO07__LPUART6_RTS_B				0x31e>,
+			   <IMX95_PAD_GPIO_IO06__LPUART6_CTS_B				0x31e>;
+	};
+
+	pinctrl_uart7: uart7grp {
+		fsl,pins = <IMX95_PAD_GPIO_IO08__LPUART7_TX				0x31e>,
+			   <IMX95_PAD_GPIO_IO09__LPUART7_RX				0x31e>,
+			   <IMX95_PAD_GPIO_IO11__LPUART7_RTS_B				0x31e>,
+			   <IMX95_PAD_GPIO_IO10__LPUART7_CTS_B				0x31e>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+		bootph-pre-ram;
+		fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK			0x158e>,
+			   <IMX95_PAD_SD1_CMD__USDHC1_CMD			0x138e>,
+			   <IMX95_PAD_SD1_DATA0__USDHC1_DATA0			0x138e>,
+			   <IMX95_PAD_SD1_DATA1__USDHC1_DATA1			0x138e>,
+			   <IMX95_PAD_SD1_DATA2__USDHC1_DATA2			0x138e>,
+			   <IMX95_PAD_SD1_DATA3__USDHC1_DATA3			0x138e>,
+			   <IMX95_PAD_SD1_DATA4__USDHC1_DATA4			0x138e>,
+			   <IMX95_PAD_SD1_DATA5__USDHC1_DATA5			0x138e>,
+			   <IMX95_PAD_SD1_DATA6__USDHC1_DATA6			0x138e>,
+			   <IMX95_PAD_SD1_DATA7__USDHC1_DATA7			0x138e>,
+			   <IMX95_PAD_SD1_STROBE__USDHC1_STROBE			0x158e>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+		bootph-pre-ram;
+		fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK			0x15fe>,
+			   <IMX95_PAD_SD1_CMD__USDHC1_CMD			0x13fe>,
+			   <IMX95_PAD_SD1_DATA0__USDHC1_DATA0			0x13fe>,
+			   <IMX95_PAD_SD1_DATA1__USDHC1_DATA1			0x13fe>,
+			   <IMX95_PAD_SD1_DATA2__USDHC1_DATA2			0x13fe>,
+			   <IMX95_PAD_SD1_DATA3__USDHC1_DATA3			0x13fe>,
+			   <IMX95_PAD_SD1_DATA4__USDHC1_DATA4			0x13fe>,
+			   <IMX95_PAD_SD1_DATA5__USDHC1_DATA5			0x13fe>,
+			   <IMX95_PAD_SD1_DATA6__USDHC1_DATA6			0x13fe>,
+			   <IMX95_PAD_SD1_DATA7__USDHC1_DATA7			0x13fe>,
+			   <IMX95_PAD_SD1_STROBE__USDHC1_STROBE			0x15fe>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		bootph-pre-ram;
+		fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK			0x158e>,
+			   <IMX95_PAD_SD1_CMD__USDHC1_CMD			0x138e>,
+			   <IMX95_PAD_SD1_DATA0__USDHC1_DATA0			0x138e>,
+			   <IMX95_PAD_SD1_DATA1__USDHC1_DATA1			0x138e>,
+			   <IMX95_PAD_SD1_DATA2__USDHC1_DATA2			0x138e>,
+			   <IMX95_PAD_SD1_DATA3__USDHC1_DATA3			0x138e>,
+			   <IMX95_PAD_SD1_DATA4__USDHC1_DATA4			0x138e>,
+			   <IMX95_PAD_SD1_DATA5__USDHC1_DATA5			0x138e>,
+			   <IMX95_PAD_SD1_DATA6__USDHC1_DATA6			0x138e>,
+			   <IMX95_PAD_SD1_DATA7__USDHC1_DATA7			0x138e>,
+			   <IMX95_PAD_SD1_STROBE__USDHC1_STROBE			0x158e>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+		bootph-pre-ram;
+		fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK			0x158e>,
+			   <IMX95_PAD_SD2_CMD__USDHC2_CMD			0x138e>,
+			   <IMX95_PAD_SD2_DATA0__USDHC2_DATA0			0x138e>,
+			   <IMX95_PAD_SD2_DATA1__USDHC2_DATA1			0x138e>,
+			   <IMX95_PAD_SD2_DATA2__USDHC2_DATA2			0x138e>,
+			   <IMX95_PAD_SD2_DATA3__USDHC2_DATA3			0x138e>,
+			   <IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+		bootph-pre-ram;
+		fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK			0x158e>,
+			   <IMX95_PAD_SD2_CMD__USDHC2_CMD			0x138e>,
+			   <IMX95_PAD_SD2_DATA0__USDHC2_DATA0			0x138e>,
+			   <IMX95_PAD_SD2_DATA1__USDHC2_DATA1			0x138e>,
+			   <IMX95_PAD_SD2_DATA2__USDHC2_DATA2			0x138e>,
+			   <IMX95_PAD_SD2_DATA3__USDHC2_DATA3			0x138e>,
+			   <IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+		bootph-pre-ram;
+		fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0		0x31e>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		bootph-pre-ram;
+		fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK			0x158e>,
+			   <IMX95_PAD_SD2_CMD__USDHC2_CMD			0x138e>,
+			   <IMX95_PAD_SD2_DATA0__USDHC2_DATA0			0x138e>,
+			   <IMX95_PAD_SD2_DATA1__USDHC2_DATA1			0x138e>,
+			   <IMX95_PAD_SD2_DATA2__USDHC2_DATA2			0x138e>,
+			   <IMX95_PAD_SD2_DATA3__USDHC2_DATA3			0x138e>,
+			   <IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e>;
+	};
+};
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 11+ messages in thread
* Re: [PATCH 1/2] dt-bindings: arm: fsl: Add ADLINK LEC-iMX95
  2026-11-02  6:56 ` [PATCH 1/2] dt-bindings: arm: fsl: Add ADLINK LEC-iMX95 Dinesh kumar v
@ 2026-11-02  7:04   ` sashiko-bot
  0 siblings, 0 replies; 11+ messages in thread
From: sashiko-bot @ 2026-11-02  7:04 UTC (permalink / raw)
  To: Dinesh kumar v; +Cc: imx, devicetree, robh, conor+dt, Frank.Li

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] dt-bindings: arm: fsl: undocumented adlink vendor prefix in fsl.yaml
--

commit adf2fbda79acf7e7bef8349bedcf40bfbb38f343
Author: Dinesh kumar v <dineshkumarv85@gmail.com>

dt-bindings: arm: fsl: Add ADLINK LEC-iMX95

This commit adds compatible strings to Documentation/devicetree/bindings/arm/fsl.yaml
for the ADLINK LEC-iMX95 module and its I-Pi SMARC Plus carrier board.

> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
> index 656f2596e1d53..c3f4c2814d6c0 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> @@ -1597,6 +1597,12 @@ properties:
>            - const: variscite,var-dart-mx95 # Variscite DART-MX95 SOM
>            - const: fsl,imx95
>  
> +      - description: ADLINK LEC-iMX95 based Boards
> +        items:
> +          - const: adlink,lec-imx95-ipi-smarc
> +          - const: adlink,lec-imx95
> +          - const: fsl,imx95

[Severity: Low]
Is the adlink vendor prefix documented in
Documentation/devicetree/bindings/vendor-prefixes.yaml?

Looking at patternProperties in
Documentation/devicetree/bindings/vendor-prefixes.yaml, the entries go
directly from adieng to admatec without an entry for adlink:

  "^adieng,.*":
    description: ADI Engineering, Inc.
  "^admatec,.*":
    description: admatec GmbH
  "^advantech,.*":
    description: Advantech Corporation

Without registering "^adlink,.*" in vendor-prefixes.yaml, running
dt_binding_check, dtbs_check, or scripts/checkpatch.pl reports an
undocumented vendor prefix for adlink,lec-imx95-ipi-smarc and
adlink,lec-imx95.

Also, in the i.MX95 section of properties.compatible.oneOf in
Documentation/devicetree/bindings/arm/fsl.yaml, the vendor board groups
(PHYTEC, Toradex, Variscite) are ordered alphabetically by vendor. Should the
ADLINK LEC-iMX95 based Boards entry be placed before PHYTEC i.MX 95 FPSC
based Boards instead of after Variscite DART-MX95 based Boards?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261102065645.121046-1-dinesh.v@adlinktech.com?part=1

^ permalink raw reply	[flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] arm64: dts: imx95: Add ADLINK LEC-iMX95 board support
  2026-11-02  6:56 ` [PATCH 2/2] arm64: dts: imx95: Add ADLINK LEC-iMX95 board support Dinesh kumar v
@ 2026-11-02  7:10   ` sashiko-bot
  0 siblings, 0 replies; 11+ messages in thread
From: sashiko-bot @ 2026-11-02  7:10 UTC (permalink / raw)
  To: Dinesh kumar v; +Cc: imx, devicetree, robh, conor+dt, Frank.Li

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] arm64: dts: imx95: missing open-drain bit in pinctrl_lpi2c8 pad config
- [Low] arm64: dts: imx95: undocumented adlink vendor prefix in compatible
--

commit 248f6e79db5b8ae0d4d8bd60d96acbf1ad1f767b
Author: Dinesh kumar v <dineshkumarv85@gmail.com>

arm64: dts: imx95: Add ADLINK LEC-iMX95 board support

This commit adds device tree descriptions for the ADLINK LEC-iMX95 System on
Module and the I-Pi SMARC Plus carrier board.

> diff --git a/arch/arm64/boot/dts/freescale/imx95-lec-ipi-smarc.dts b/arch/arm64/boot/dts/freescale/imx95-lec-ipi-smarc.dts
> new file mode 100644
> index 0000000000000..9a77bff42b225
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx95-lec-ipi-smarc.dts
> @@ -0,0 +1,237 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> +/*
> + * Copyright (C) 2026 ADLINK Technology Inc.
> + *
> + * https://www.adlinktech.com/products/Computer_on_Modules/SMARC/LEC-IMX95
> + * https://www.adlinktech.com/products/computer_on_modules/SMARCStarterKits/I-Pi_SMARC_IMX95
> + */
> +
> +/dts-v1/;
> +
> +#include "imx95-lec.dtsi"
> +
> +/ {
> +	model = "ADLINK LEC-iMX95 on I-Pi SMARC Plus Carrier Board";
> +	compatible = "adlink,lec-imx95-ipi-smarc",
> +		     "adlink,lec-imx95",
> +		     "fsl,imx95";
> +};

[Severity: Low]
The root node uses the "adlink" vendor prefix in its compatible property,
along with the new board and module compatible strings, but "adlink" does
not appear in Documentation/devicetree/bindings/vendor-prefixes.yaml and
the compatible strings are not documented in
Documentation/devicetree/bindings/arm/fsl.yaml.

Should the vendor prefix and board compatible bindings be documented so
dtbs_check and checkpatch.pl pass without undocumented DT string warnings?

> diff --git a/arch/arm64/boot/dts/freescale/imx95-lec.dtsi b/arch/arm64/boot/dts/freescale/imx95-lec.dtsi
> new file mode 100644
> index 0000000000000..5402cb360888a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx95-lec.dtsi

[ ... ]

> +&scmi_iomuxc {

[ ... ]

> +	pinctrl_lpi2c2: lpi2c2grp {
> +		fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL		0x40000b9e>,
> +			   <IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA		0x40000b9e>;
> +	};
> +
> +	pinctrl_lpi2c3: lpi2c3grp {
> +		fsl,pins = <IMX95_PAD_GPIO_IO28__LPI2C3_SDA			0x40000b9e>,
> +			   <IMX95_PAD_GPIO_IO29__LPI2C3_SCL			0x40000b9e>;
> +	};
> +
> +	pinctrl_lpi2c8: lpi2c8grp {
> +		fsl,pins = <IMX95_PAD_GPIO_IO13__LPI2C8_SCL		0x4000007e>,
> +			   <IMX95_PAD_GPIO_IO12__LPI2C8_SDA		0x4000007e>;
> +	};

[Severity: Medium]
In pinctrl_lpi2c8, IMX95_PAD_GPIO_IO13__LPI2C8_SCL and
IMX95_PAD_GPIO_IO12__LPI2C8_SDA are configured with 0x4000007e rather than
0x40000b9e as used in pinctrl_lpi2c2 and pinctrl_lpi2c3 above.

On i.MX95, bit 11 (0x800) of the IOMUXC pad control register enables
open-drain output and bit 9 (0x200) enables the internal pull-up. With
0x4000007e, both bits are cleared while lpi2c8 is enabled in
imx95-lec-ipi-smarc.dts, driving the I2C8 SCL and SDA lines as push-pull
outputs.

Should pinctrl_lpi2c8 use 0x40000b9e so that open-drain mode is enabled on
the I2C8 bus?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261102065645.121046-1-dinesh.v@adlinktech.com?part=2

^ permalink raw reply	[flat|nested] 11+ messages in thread
* [PATCH v2 0/3] Add ADLINK LEC-iMX95 board support
  2026-11-02  6:56 [PATCH 0/2] Add ADLINK LEC-iMX95 board support Dinesh kumar v
  2026-11-02  6:56 ` [PATCH 1/2] dt-bindings: arm: fsl: Add ADLINK LEC-iMX95 Dinesh kumar v
  2026-11-02  6:56 ` [PATCH 2/2] arm64: dts: imx95: Add ADLINK LEC-iMX95 board support Dinesh kumar v
@ 2026-11-02 10:26 ` Dinesh kumar v
  2026-11-02 10:26   ` [PATCH v2 1/3] dt-bindings: vendor-prefixes: Add ADLINK Dinesh kumar v
                     ` (2 more replies)
  2 siblings, 3 replies; 11+ messages in thread
From: Dinesh kumar v @ 2026-11-02 10:26 UTC (permalink / raw)
  To: Frank.Li, robh, krzk+dt, conor+dt, s.hauer
  Cc: imx, devicetree, linux-arm-kernel, kernel, festevam,
	Dinesh kumar v

This patch series adds device tree support for the ADLINK LEC-iMX95
module on the I-Pi SMARC Plus carrier board.

The series includes:

 - Add the ADLINK vendor prefix to vendor-prefixes.yaml.

 - Add the ADLINK LEC-iMX95 compatible strings to the Freescale
   i.MX device tree binding.

 - Add the common device tree description for the LEC-iMX95 module.

 - Add the I-Pi SMARC Plus carrier board device tree.

The module device tree describes the onboard peripherals and interfaces,
while the carrier board device tree describes the carrier-specific
hardware connections.

The device tree has been compiled and validated using DT schema checks.

Changes in v2:

 - Add the ADLINK vendor prefix to vendor-prefixes.yaml.

 - Move the ADLINK compatible entry before PHYTEC in alphabetical order.

 - Enable open-drain configuration for LPI2C8 SCL and SDA pins.

Hardware: ADLINK LEC-iMX95
Carrier board: I-Pi SMARC Plus
SoC: NXP i.MX95

Signed-off-by: Dinesh kumar v <dinesh.v@adlinktech.com>

Dinesh kumar v (3):
  dt-bindings: vendor-prefixes: Add ADLINK
  dt-bindings: arm: fsl: Add ADLINK LEC-iMX95
  arm64: dts: imx95: Add ADLINK LEC-iMX95 board support

 .../devicetree/bindings/arm/fsl.yaml          |   6 +
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 arch/arm64/boot/dts/freescale/Makefile        |   1 +
 .../dts/freescale/imx95-lec-ipi-smarc.dts     | 237 ++++++++++
 arch/arm64/boot/dts/freescale/imx95-lec.dtsi  | 414 ++++++++++++++++++
 5 files changed, 660 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx95-lec-ipi-smarc.dts
 create mode 100644 arch/arm64/boot/dts/freescale/imx95-lec.dtsi

-- 
2.25.1


^ permalink raw reply	[flat|nested] 11+ messages in thread
* [PATCH v2 1/3] dt-bindings: vendor-prefixes: Add ADLINK
  2026-11-02 10:26 ` [PATCH v2 0/3] " Dinesh kumar v
@ 2026-11-02 10:26   ` Dinesh kumar v
  2026-11-02 10:32     ` sashiko-bot
  2026-11-02 10:26   ` [PATCH v2 2/3] dt-bindings: arm: fsl: Add ADLINK LEC-iMX95 Dinesh kumar v
  2026-11-02 10:26   ` [PATCH v2 3/3] arm64: dts: imx95: Add ADLINK LEC-iMX95 board support Dinesh kumar v
  2 siblings, 1 reply; 11+ messages in thread
From: Dinesh kumar v @ 2026-11-02 10:26 UTC (permalink / raw)
  To: Frank.Li, robh, krzk+dt, conor+dt, s.hauer
  Cc: imx, devicetree, linux-arm-kernel, kernel, festevam,
	Dinesh kumar v

Add the ADLINK Technology Inc. vendor prefix for device tree
compatible strings used by ADLINK hardware.

Signed-off-by: Dinesh kumar v <dinesh.v@adlinktech.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index e467da45cd7a..6bbfa5619ee4 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -70,6 +70,8 @@ patternProperties:
     description: ADI Engineering, Inc.
   "^admatec,.*":
     description: admatec GmbH
+  "^adlink,.*":
+    description: ADLINK Technology Inc.
   "^advantech,.*":
     description: Advantech Corporation
   "^aeroflexgaisler,.*":
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [PATCH v2 2/3] dt-bindings: arm: fsl: Add ADLINK LEC-iMX95
  2026-11-02 10:26 ` [PATCH v2 0/3] " Dinesh kumar v
  2026-11-02 10:26   ` [PATCH v2 1/3] dt-bindings: vendor-prefixes: Add ADLINK Dinesh kumar v
@ 2026-11-02 10:26   ` Dinesh kumar v
  2026-11-02 10:26   ` [PATCH v2 3/3] arm64: dts: imx95: Add ADLINK LEC-iMX95 board support Dinesh kumar v
  2 siblings, 0 replies; 11+ messages in thread
From: Dinesh kumar v @ 2026-11-02 10:26 UTC (permalink / raw)
  To: Frank.Li, robh, krzk+dt, conor+dt, s.hauer
  Cc: imx, devicetree, linux-arm-kernel, kernel, festevam,
	Dinesh kumar v

Add compatible strings for the ADLINK LEC-iMX95 module and
its I-Pi SMARC Plus carrier board.

Signed-off-by: Dinesh kumar v <dinesh.v@adlinktech.com>
---
 Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index cb99fb74805b..baa96b004c52 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1577,6 +1577,12 @@ properties:
               - fsl,imx952-frdm           # i.MX952 FRDM Board
           - const: fsl,imx952
 
+      - description: ADLINK LEC-iMX95 based Boards
+        items:
+          - const: adlink,lec-imx95-ipi-smarc
+          - const: adlink,lec-imx95
+          - const: fsl,imx95
+
       - description: PHYTEC i.MX 95 FPSC based Boards
         items:
           - enum:
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [PATCH v2 3/3] arm64: dts: imx95: Add ADLINK LEC-iMX95 board support
  2026-11-02 10:26 ` [PATCH v2 0/3] " Dinesh kumar v
  2026-11-02 10:26   ` [PATCH v2 1/3] dt-bindings: vendor-prefixes: Add ADLINK Dinesh kumar v
  2026-11-02 10:26   ` [PATCH v2 2/3] dt-bindings: arm: fsl: Add ADLINK LEC-iMX95 Dinesh kumar v
@ 2026-11-02 10:26   ` Dinesh kumar v
  2026-11-02 10:45     ` sashiko-bot
  2 siblings, 1 reply; 11+ messages in thread
From: Dinesh kumar v @ 2026-11-02 10:26 UTC (permalink / raw)
  To: Frank.Li, robh, krzk+dt, conor+dt, s.hauer
  Cc: imx, devicetree, linux-arm-kernel, kernel, festevam,
	Dinesh kumar v

Add the common device tree description for the ADLINK LEC-iMX95
module and the I-Pi SMARC Plus carrier board.

Describe the onboard peripherals and carrier-specific hardware
connections.

Signed-off-by: Dinesh kumar v <dinesh.v@adlinktech.com>
---
 arch/arm64/boot/dts/freescale/Makefile        |   1 +
 .../dts/freescale/imx95-lec-ipi-smarc.dts     | 237 ++++++++++
 arch/arm64/boot/dts/freescale/imx95-lec.dtsi  | 414 ++++++++++++++++++
 3 files changed, 652 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx95-lec-ipi-smarc.dts
 create mode 100644 arch/arm64/boot/dts/freescale/imx95-lec.dtsi

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index a80cccf34eb5..26b432127faa 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -983,6 +983,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-ivy.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-mallow.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-yavia.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-zinnia.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx95-lec-ipi-smarc.dtb
 
 imx95-15x15-evk-pcie-dtbs += imx95-15x15-evk.dtb imx-m2-pcie.dtbo
 dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx95-lec-ipi-smarc.dts b/arch/arm64/boot/dts/freescale/imx95-lec-ipi-smarc.dts
new file mode 100644
index 000000000000..9a77bff42b22
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-lec-ipi-smarc.dts
@@ -0,0 +1,237 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (C) 2026 ADLINK Technology Inc.
+ *
+ * https://www.adlinktech.com/products/Computer_on_Modules/SMARC/LEC-IMX95
+ * https://www.adlinktech.com/products/computer_on_modules/SMARCStarterKits/I-Pi_SMARC_IMX95
+ */
+
+/dts-v1/;
+
+#include "imx95-lec.dtsi"
+
+/ {
+	model = "ADLINK LEC-iMX95 on I-Pi SMARC Plus Carrier Board";
+	compatible = "adlink,lec-imx95-ipi-smarc",
+		     "adlink,lec-imx95",
+		     "fsl,imx95";
+};
+
+/* Ethernet SMARC GBE0 */
+&enetc_port0 {
+	pinctrl-0 = <&pinctrl_enetc0>;
+	phy-handle = <&ethphy0>;
+	pinctrl-names = "default";
+	phy-mode = "rgmii-id";
+
+	status = "okay";
+};
+
+/* Ethernet SMARC GBE1 */
+&enetc_port1 {
+	pinctrl-0 = <&pinctrl_enetc1>;
+	phy-handle = <&ethphy1>;
+	pinctrl-names = "default";
+	phy-mode = "rgmii-id";
+
+	status = "okay";
+};
+
+&lpi2c2 {
+	clock-frequency = <100000>;
+	pinctrl-0 = <&pinctrl_lpi2c2>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	/* U1000 SX1509BIULTRT_SEMTECH */
+	i2c2_gpio_expander_71: pinctrl@71 {
+		/*
+		 * GPIO Expander Mapping:
+		 * - 0: ENET1_RST_B_3V		=>		U2001
+		 * - 1: ENET2_RST_B_3V		=>		U2101
+		 * - 2: SERDES_RST#_3V		=>		SMARC S77 PCIE_C_RST
+		 * - 3: RC210_EN_3V		=>		U1300, RC21008B001GND
+		 * - 4: LT9611_RSTN_3V		=>		U1500
+		 * - 5: HDMI_INT_3V		<=		U1500
+		 * - 6: PCIEA_RST#_3V		=>		SMARC P75
+		 * - 7: PCIEB_RST#_3V		=>		SMARC S76
+		 * - 8: TPM_RST_N_1V8		=>		U2400
+		 * - 9: LID#_1V8		<=	R1005	SMARC S148
+		 * - 10: SLEEP#_1V8		<=	R1010	SMARC S149
+		 * - 11: CHARGING#_1V8		<=	R1007	SMARC S151
+		 * - 12: CHARGER_PRSNT#_1V8	<=	R1011	SMARC S152
+		 * - 13: BATLOW#_1V8		<=	R1014	SMARC S156
+		 * - 14: TEST#_1V8		<=	R1015	SMARC S157
+		 * - 15: DSI0_TE_1V8		<=	R1087	SMARC S144
+		 */
+		compatible = "semtech,sx1509q";
+		reg = <0x71>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		interrupt-parent = <&gpio4>;
+		interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-0 = <&pinctrl_sx1509q>;
+		pinctrl-names = "default";
+		semtech,probe-reset;
+
+		status = "okay";
+	};
+};
+
+&lpi2c3 {
+	pinctrl-0 = <&pinctrl_lpi2c3>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&lpi2c8 {
+	pinctrl-0 = <&pinctrl_lpi2c8>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+/* SMARC SPI0 */
+&lpspi6 {
+	cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>, <&gpio2 24 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&pinctrl_lpspi6>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+/* SMARC SER1, used as the Linux Console */
+&lpuart1 {
+	bootph-pre-ram;
+	pinctrl-0 = <&pinctrl_uart1>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&lpuart2 {
+	pinctrl-0 = <&pinctrl_uart2>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&lpuart5 {
+	pinctrl-0 = <&pinctrl_uart5>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+/* SMARC SER2 */
+&lpuart6 {
+	pinctrl-0 = <&pinctrl_uart6>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+/* SMARC SER0 */
+&lpuart7 {
+	pinctrl-0 = <&pinctrl_uart7>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&netc_blk_ctrl {
+	status = "okay";
+};
+
+&netc_emdio {
+	pinctrl-0 = <&pinctrl_emdio>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	ethphy0: ethernet-phy@1 {
+		compatible = "ethernet-phy-id001c.c916";
+		reg = <1>;
+		eee-broken-1000t;
+		realtek,clkout-disable;
+	};
+
+	ethphy1: ethernet-phy@4 {
+		compatible = "ethernet-phy-id001c.c916";
+		reg = <4>;
+		eee-broken-1000t;
+		realtek,clkout-disable;
+	};
+};
+
+&netc_timer {
+	status = "okay";
+};
+
+&netcmix_blk_ctrl {
+	status = "okay";
+};
+
+/* SMARC PCIE_A */
+&pcie0 {
+	pinctrl-0 = <&pinctrl_pcie0>;
+	pinctrl-names = "default";
+	supports-clkreq;
+
+	status = "okay";
+};
+
+&pcie0_port0 {
+	reset-gpios = <&i2c2_gpio_expander_71 6 GPIO_ACTIVE_LOW>; /* PCIEA_RST#_3V */
+};
+
+/* U1900 AW-CM276NF */
+&pcie1 {
+	pinctrl-0 = <&pinctrl_pcie1>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie1_port0 {
+	reset-gpios = <&i2c2_gpio_expander_71 7 GPIO_ACTIVE_LOW>; /* PCIEB_RST#_3V */
+};
+
+/* SMARC USB0 */
+&usb2 {
+	dr_mode = "host";
+	hnp-disable;
+	adp-disable;
+	srp-disable;
+	disable-over-current;
+
+	status = "okay";
+};
+
+&usb3 {
+	status = "okay";
+};
+
+&usb3_dwc3 {
+	dr_mode = "host";
+	snps,dis-u1-entry-quirk;
+	snps,dis-u2-entry-quirk;
+
+	status = "okay";
+};
+
+&usb3_phy {
+	status = "okay";
+};
+
+&usdhc1 {
+	status = "okay";
+};
+
+&usdhc2 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx95-lec.dtsi b/arch/arm64/boot/dts/freescale/imx95-lec.dtsi
new file mode 100644
index 000000000000..60d68c146ae4
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-lec.dtsi
@@ -0,0 +1,414 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (C) 2026 ADLINK Technology Inc.
+ * https://www.adlinktech.com/products/Computer_on_Modules/SMARC/LEC-IMX95
+ * https://www.adlinktech.com/products/computer_on_modules/SMARCStarterKits/I-Pi_SMARC_IMX95
+ */
+
+#include "imx95.dtsi"
+
+/ {
+	aliases {
+		ethernet0 = &enetc_port0;
+		ethernet1 = &enetc_port1;
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+		i2c1 = &lpi2c2;
+		i2c2 = &lpi2c3;
+		i2c7 = &lpi2c8;
+		mmc0 = &usdhc1;
+		mmc1 = &usdhc2;
+		serial0 = &lpuart1;
+		serial1 = &lpuart2;
+		serial4 = &lpuart5;
+		serial5 = &lpuart6;
+		serial6 = &lpuart7;
+		spi0 = &lpspi6;
+		usb0 = &usb3_dwc3;
+		usb1 = &usb2;
+	};
+
+	chosen {
+		stdout-path = &lpuart1;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x01 0x00>;
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2 {
+		compatible = "regulator-fixed";
+		bootph-pre-ram;
+		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+		enable-active-high;
+		pinctrl-names = "default";
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+		regulator-name = "VDD_SD2_3V3";
+		off-on-delay-us = <12000>;
+	};
+
+	reserved-memory {
+		ranges;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		linux_cma: linux,cma {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0 0x80000000 0 0x7f000000>;
+			reusable;
+			size = <0 0x3c000000>;
+			linux,cma-default;
+		};
+	};
+};
+
+&gpio2 {
+	gpio-line-names =
+		"SMARC_SPI0_CS0#",	/* 0 - GPIO_IO00 */
+		"SMARC_SPI0_DIN",	/* 1 - GPIO_IO01 */
+		"SMARC_SPI0_DO",	/* 2 - GPIO_IO02 */
+		"SMARC_SPI0_CK",	/* 3 - GPIO_IO03 */
+		"",			/* 4 - GPIO_IO04 */
+		"",			/* 5 - GPIO_IO05 */
+		"",			/* 6 - GPIO_IO06 */
+		"",			/* 7 - GPIO_IO07 */
+		"SMARC_UART0_TXD",	/* 8 - GPIO_IO08 */
+		"SMARC_UART0_RXD",	/* 9 - GPIO_IO09 */
+		"SMARC_UART0_CTS_B",	/* 10 - GPIO_IO10 */
+		"SMARC_UART0_RTS_B",	/* 11 - GPIO_IO11 */
+		"SMARC_I2C_GP_DAT",	/* 12 - GPIO_IO12 */
+		"SMARC_I2C_GP_CK",	/* 13 - GPIO_IO13 */
+		"UART3_TXD_1V8",	/* 14 - GPIO_IO14 */
+		"UART3_RXD_1V8",	/* 15 - GPIO_IO15 */
+		"SAI3_TXC_1V8",		/* 16 - GPIO_IO16 */
+		"SAI3_MCLK_1V8",	/* 17 - GPIO_IO17 */
+		"SMB_INT_B_1V8",	/* 18 - GPIO_IO18 */
+		"LVDS0_BKLT_PWM_1V8",	/* 19 - GPIO_IO19 */
+		"SAI3_RXD_1V8",		/* 20 - GPIO_IO20 */
+		"SAI3_TXD_1V8",		/* 21 - GPIO_IO21 */
+		"FAN_PWM_1V8",		/* 22 - GPIO_IO22 */
+		"LVDS1_BKLT_PWM_1V8",	/* 23 - GPIO_IO23 */
+		"SPI6_SS1_1V8",		/* 24 - GPIO_IO24 */
+		"",			/* 25 - GPIO_IO25 */
+		"SAI3_TXFS_1V8",	/* 26 - GPIO_IO26 */
+		"TPM_INT_N_1V8",	/* 27 - GPIO_IO27 */
+		"SMARC_I2C_PM_DAT",	/* 28 - GPIO_IO28 */
+		"SMARC_I2C_PM_CK",	/* 29 - GPIO_IO29 */
+		"SMARC_CAN1_TX",	/* 30 - GPIO_IO30 (SMARC CAN1_H via transceiver) */
+		"SMARC_CAN1_RX";	/* 31 - GPIO_IO31 (SMARC CAN1_L via transceiver) */
+};
+
+&gpio3 {
+	gpio-line-names =
+		"SD2_CD_B",
+		"SD2_CLK",
+		"SD2_CMD",
+		"SD2_DATA0",
+		"SD2_DATA1",
+		"SD2_DATA2",
+		"SD2_DATA3",
+		"SD2_RST_B_1V8A3V",
+		"SD1_CLK",
+		"SD1_CMD",
+		"SD1_DATA0",
+		"SD1_DATA1",
+		"SD1_DATA2",
+		"SD1_DATA3",
+		"SD1_DATA4",
+		"SD1_DATA5",
+		"SD1_DATA6",
+		"SD1_DATA7",
+		"SD1_STROBE",
+		"SD2_VSEL_1V8",
+		"SD3_CLK",
+		"SD3_CMD",
+		"SD3_DATA0",
+		"SD3_DATA1",
+		"SD3_DATA2",
+		"SD3_DATA3",
+		"CCM_CLKO1",
+		"CCM_CLKO2",
+		"DAP_TDI",
+		"DAP_TMS_SWDIO",
+		"DAP_TCLK_SWCLK",
+		"DAP_TDO_TRACESWO";
+};
+
+&gpio4 {
+	gpio-line-names =
+		"ENET1_MDC",
+		"ENET1_MDIO",
+		"ENET1_TD3",
+		"ENET1_TD2",
+		"ENET1_TD1",
+		"ENET1_TD0",
+		"ENET1_TX_CTL",
+		"ENET1_TXC",
+		"ENET1_RX_CTL",
+		"ENET1_RXC",
+		"ENET1_RD0",
+		"ENET1_RD1",
+		"ENET1_RD2",
+		"ENET1_RD3",
+		"RTC_INT#_1V8",
+		"IOEXP2_INT#_1V8",
+		"ENET2_TD3",
+		"ENET2_TD2",
+		"ENET2_TD1",
+		"ENET2_TD0",
+		"ENET2_TX_CTL",
+		"ENET2_TXC",
+		"ENET2_RX_CTL",
+		"ENET2_RXC",
+		"ENET2_RD0",
+		"ENET2_RD1",
+		"ENET2_RD2",
+		"ENET2_RD3",
+		"CCM_CLKO3",
+		"CCM_CLKO4";
+};
+
+&gpio5 {
+	gpio-line-names =
+		"QSPIA_DATA0",
+		"QSPIA_DATA1",
+		"QSPIA_DATA2",
+		"QSPIA_DATA3",
+		"SKU_CONFIG1_1V8",
+		"SKU_CONFIG2_1V8",
+		"SKU_CONFIG3_1V8",
+		"SYS_STATUS_1V8",
+		"SD2_WP_1V8",
+		"QSPIA_SCLK",
+		"QSPIA_nSS0",
+		"SYS_RST#_1V8",
+		"PCIE1_IMX_CLKREQ#_1V8",
+		"MCU_INTB1_1V8",
+		"MCU_INTB2_1V8",
+		"PCIE2_IMX_CLKREQ#_1V8",
+		"ENET1_INT_B_1V8",
+		"ENET2_INT_B_1V8";
+};
+
+&usdhc1 {
+	bootph-pre-ram;
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	pinctrl-3 = <&pinctrl_usdhc1>;
+	bus-width = <8>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+	no-sdio;
+	no-sd;
+	non-removable;
+};
+
+&usdhc2 {
+	bootph-pre-ram;
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+	bus-width = <4>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+};
+
+&scmi_iomuxc {
+	pinctrl_emdio: emdiogrp {
+		fsl,pins = <IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC		0x50e>,
+			   <IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO		0x90e>;
+	};
+
+	pinctrl_enetc0: enetc0grp {
+		fsl,pins = <IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3		0x50e>,
+			   <IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2		0x50e>,
+			   <IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1		0x50e>,
+			   <IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0		0x50e>,
+			   <IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL	0x57e>,
+			   <IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK	        0x58e>,
+			   <IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL	0x57e>,
+			   <IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK	        0x58e>,
+			   <IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0		0x57e>,
+			   <IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1		0x57e>,
+			   <IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2		0x57e>,
+			   <IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3		0x57e>;
+	};
+
+	pinctrl_enetc1: enetc1grp {
+		fsl,pins = <IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3		0x57e>,
+			   <IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2		0x57e>,
+			   <IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1		0x57e>,
+			   <IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0		0x57e>,
+			   <IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL	0x57e>,
+			   <IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK	        0x5fe>,
+			   <IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL	0x57e>,
+			   <IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK	        0x5fe>,
+			   <IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0		0x57e>,
+			   <IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1		0x57e>,
+			   <IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2		0x57e>,
+			   <IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3		0x57e>;
+	};
+
+	pinctrl_lpi2c2: lpi2c2grp {
+		fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL		0x40000b9e>,
+			   <IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA		0x40000b9e>;
+	};
+
+	pinctrl_lpi2c3: lpi2c3grp {
+		fsl,pins = <IMX95_PAD_GPIO_IO28__LPI2C3_SDA			0x40000b9e>,
+			   <IMX95_PAD_GPIO_IO29__LPI2C3_SCL			0x40000b9e>;
+	};
+
+	pinctrl_lpi2c8: lpi2c8grp {
+		fsl,pins = <IMX95_PAD_GPIO_IO13__LPI2C8_SCL		0x40000b9e>,
+			   <IMX95_PAD_GPIO_IO12__LPI2C8_SDA		0x40000b9e>;
+	};
+
+	pinctrl_lpspi6: lpspi6grp {
+		fsl,pins = <IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0		0x1fe>,
+			   <IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24		0x1fe>,
+			   <IMX95_PAD_GPIO_IO01__LPSPI6_SIN		0x3fe>,
+			   <IMX95_PAD_GPIO_IO02__LPSPI6_SOUT		0x3fe>,
+			   <IMX95_PAD_GPIO_IO03__LPSPI6_SCK		0x3fe>;
+	};
+
+	pinctrl_pcie0: pcie0grp {
+		fsl,pins = <IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B		0x4000031e>;
+	};
+
+	pinctrl_pcie1: pcie1grp {
+		fsl,pins = <IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B		0x4000031e>;
+	};
+
+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+		bootph-pre-ram;
+		fsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7		0x31e>;
+	};
+
+	pinctrl_sx1509q: sx1509qgrp {
+		fsl,pins = <IMX95_PAD_ENET2_MDIO__GPIO4_IO_BIT15		0x1fe>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		bootph-pre-ram;
+		fsl,pins = <IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX	0x31e>,
+			   <IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX	0x31e>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX	0x31e>,
+			   <IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX	0x31e>;
+	};
+
+	pinctrl_uart5: uart5grp {
+		fsl,pins = <IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX			0x31e>,
+			   <IMX95_PAD_DAP_TDI__LPUART5_RX				0x31e>,
+			   <IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B			0x31e>,
+			   <IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B			0x31e>;
+	};
+
+	pinctrl_uart6: uart6grp {
+		fsl,pins = <IMX95_PAD_GPIO_IO04__LPUART6_TX				0x31e>,
+			   <IMX95_PAD_GPIO_IO05__LPUART6_RX				0x31e>,
+			   <IMX95_PAD_GPIO_IO07__LPUART6_RTS_B				0x31e>,
+			   <IMX95_PAD_GPIO_IO06__LPUART6_CTS_B				0x31e>;
+	};
+
+	pinctrl_uart7: uart7grp {
+		fsl,pins = <IMX95_PAD_GPIO_IO08__LPUART7_TX				0x31e>,
+			   <IMX95_PAD_GPIO_IO09__LPUART7_RX				0x31e>,
+			   <IMX95_PAD_GPIO_IO11__LPUART7_RTS_B				0x31e>,
+			   <IMX95_PAD_GPIO_IO10__LPUART7_CTS_B				0x31e>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+		bootph-pre-ram;
+		fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK			0x158e>,
+			   <IMX95_PAD_SD1_CMD__USDHC1_CMD			0x138e>,
+			   <IMX95_PAD_SD1_DATA0__USDHC1_DATA0			0x138e>,
+			   <IMX95_PAD_SD1_DATA1__USDHC1_DATA1			0x138e>,
+			   <IMX95_PAD_SD1_DATA2__USDHC1_DATA2			0x138e>,
+			   <IMX95_PAD_SD1_DATA3__USDHC1_DATA3			0x138e>,
+			   <IMX95_PAD_SD1_DATA4__USDHC1_DATA4			0x138e>,
+			   <IMX95_PAD_SD1_DATA5__USDHC1_DATA5			0x138e>,
+			   <IMX95_PAD_SD1_DATA6__USDHC1_DATA6			0x138e>,
+			   <IMX95_PAD_SD1_DATA7__USDHC1_DATA7			0x138e>,
+			   <IMX95_PAD_SD1_STROBE__USDHC1_STROBE			0x158e>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+		bootph-pre-ram;
+		fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK			0x15fe>,
+			   <IMX95_PAD_SD1_CMD__USDHC1_CMD			0x13fe>,
+			   <IMX95_PAD_SD1_DATA0__USDHC1_DATA0			0x13fe>,
+			   <IMX95_PAD_SD1_DATA1__USDHC1_DATA1			0x13fe>,
+			   <IMX95_PAD_SD1_DATA2__USDHC1_DATA2			0x13fe>,
+			   <IMX95_PAD_SD1_DATA3__USDHC1_DATA3			0x13fe>,
+			   <IMX95_PAD_SD1_DATA4__USDHC1_DATA4			0x13fe>,
+			   <IMX95_PAD_SD1_DATA5__USDHC1_DATA5			0x13fe>,
+			   <IMX95_PAD_SD1_DATA6__USDHC1_DATA6			0x13fe>,
+			   <IMX95_PAD_SD1_DATA7__USDHC1_DATA7			0x13fe>,
+			   <IMX95_PAD_SD1_STROBE__USDHC1_STROBE			0x15fe>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		bootph-pre-ram;
+		fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK			0x158e>,
+			   <IMX95_PAD_SD1_CMD__USDHC1_CMD			0x138e>,
+			   <IMX95_PAD_SD1_DATA0__USDHC1_DATA0			0x138e>,
+			   <IMX95_PAD_SD1_DATA1__USDHC1_DATA1			0x138e>,
+			   <IMX95_PAD_SD1_DATA2__USDHC1_DATA2			0x138e>,
+			   <IMX95_PAD_SD1_DATA3__USDHC1_DATA3			0x138e>,
+			   <IMX95_PAD_SD1_DATA4__USDHC1_DATA4			0x138e>,
+			   <IMX95_PAD_SD1_DATA5__USDHC1_DATA5			0x138e>,
+			   <IMX95_PAD_SD1_DATA6__USDHC1_DATA6			0x138e>,
+			   <IMX95_PAD_SD1_DATA7__USDHC1_DATA7			0x138e>,
+			   <IMX95_PAD_SD1_STROBE__USDHC1_STROBE			0x158e>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+		bootph-pre-ram;
+		fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK			0x158e>,
+			   <IMX95_PAD_SD2_CMD__USDHC2_CMD			0x138e>,
+			   <IMX95_PAD_SD2_DATA0__USDHC2_DATA0			0x138e>,
+			   <IMX95_PAD_SD2_DATA1__USDHC2_DATA1			0x138e>,
+			   <IMX95_PAD_SD2_DATA2__USDHC2_DATA2			0x138e>,
+			   <IMX95_PAD_SD2_DATA3__USDHC2_DATA3			0x138e>,
+			   <IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+		bootph-pre-ram;
+		fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK			0x158e>,
+			   <IMX95_PAD_SD2_CMD__USDHC2_CMD			0x138e>,
+			   <IMX95_PAD_SD2_DATA0__USDHC2_DATA0			0x138e>,
+			   <IMX95_PAD_SD2_DATA1__USDHC2_DATA1			0x138e>,
+			   <IMX95_PAD_SD2_DATA2__USDHC2_DATA2			0x138e>,
+			   <IMX95_PAD_SD2_DATA3__USDHC2_DATA3			0x138e>,
+			   <IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+		bootph-pre-ram;
+		fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0		0x31e>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		bootph-pre-ram;
+		fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK			0x158e>,
+			   <IMX95_PAD_SD2_CMD__USDHC2_CMD			0x138e>,
+			   <IMX95_PAD_SD2_DATA0__USDHC2_DATA0			0x138e>,
+			   <IMX95_PAD_SD2_DATA1__USDHC2_DATA1			0x138e>,
+			   <IMX95_PAD_SD2_DATA2__USDHC2_DATA2			0x138e>,
+			   <IMX95_PAD_SD2_DATA3__USDHC2_DATA3			0x138e>,
+			   <IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e>;
+	};
+};
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: vendor-prefixes: Add ADLINK
  2026-11-02 10:26   ` [PATCH v2 1/3] dt-bindings: vendor-prefixes: Add ADLINK Dinesh kumar v
@ 2026-11-02 10:32     ` sashiko-bot
  0 siblings, 0 replies; 11+ messages in thread
From: sashiko-bot @ 2026-11-02 10:32 UTC (permalink / raw)
  To: Dinesh kumar v; +Cc: imx, devicetree, robh, conor+dt, Frank.Li

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] dt-bindings: vendor-prefixes: adlink entry added out of alphabetical order
- [Low] dt-bindings: vendor-prefixes: Author and Signed-off-by email mismatch
--

commit dba9f5e74cdb4e9777b31ecece91c151c0904cf4
Author: Dinesh kumar v <dineshkumarv85@gmail.com>

dt-bindings: vendor-prefixes: Add ADLINK

This commit adds the adlink vendor prefix for ADLINK Technology Inc. to the
device tree vendor-prefixes schema.

>     dt-bindings: vendor-prefixes: Add ADLINK
>     
>     Add the ADLINK Technology Inc. vendor prefix for device tree
>     compatible strings used by ADLINK hardware.
>     
>     Signed-off-by: Dinesh kumar v <dinesh.v@adlinktech.com>

[Severity: Low]
The commit Author email address (dineshkumarv85@gmail.com) does not match the
Signed-off-by email address (dinesh.v@adlinktech.com), which triggers a
checkpatch FROM_SIGN_OFF_MISMATCH warning. Should the Author and Signed-off-by
addresses be aligned?

> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index c981a133753e9..eee3764fab51e 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -70,6 +70,8 @@ patternProperties:
>      description: ADI Engineering, Inc.
>    "^admatec,.*":
>      description: admatec GmbH
> +  "^adlink,.*":
> +    description: ADLINK Technology Inc.

[Severity: Low]
The patternProperties list in
Documentation/devicetree/bindings/vendor-prefixes.yaml specifies:

  # Keep list in alphabetical order.

Should the "^adlink,.*" entry be placed before "^admatec,.*" rather than after
it to maintain alphabetical ordering?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261102102653.272056-1-dinesh.v@adlinktech.com?part=1

^ permalink raw reply	[flat|nested] 11+ messages in thread
* Re: [PATCH v2 3/3] arm64: dts: imx95: Add ADLINK LEC-iMX95 board support
  2026-11-02 10:26   ` [PATCH v2 3/3] arm64: dts: imx95: Add ADLINK LEC-iMX95 board support Dinesh kumar v
@ 2026-11-02 10:45     ` sashiko-bot
  0 siblings, 0 replies; 11+ messages in thread
From: sashiko-bot @ 2026-11-02 10:45 UTC (permalink / raw)
  To: Dinesh kumar v; +Cc: imx, devicetree, robh, conor+dt, Frank.Li

Thank you for your contribution! Sashiko AI review found 5 potential issue(s) to consider:
- [Low] arm64: dts: imx95: on-module LEC-iMX95 components placed in carrier board DTS
- [Low] arm64: dts: imx95: duplicate usb@4c100000 reference via usb3 and usb3_dwc3
- [Low] arm64: dts: imx95: imx95-lec-ipi-smarc.dtb not sorted alphabetically in Makefile
- [Low] arm64: dts: imx95: Author email does not match Signed-off-by email
- [Low] arm64: dts: imx95: duplicate USDHC pinctrl groups and 200MHz pad settings
--

commit 15a8ff538ba6c35961382a83a0abb8e1fea067e2
Author: Dinesh kumar v <dineshkumarv85@gmail.com>

arm64: dts: imx95: Add ADLINK LEC-iMX95 board support

This commit adds the device tree description for the ADLINK LEC-iMX95 system
on module and the I-Pi SMARC Plus carrier board, along with the corresponding
Makefile entry.

>     arm64: dts: imx95: Add ADLINK LEC-iMX95 board support
>     
>     Add the common device tree description for the ADLINK LEC-iMX95
>     module and the I-Pi SMARC Plus carrier board.
>     
>     Describe the onboard peripherals and carrier-specific hardware
>     connections.
>     
>     Signed-off-by: Dinesh kumar v <dinesh.v@adlinktech.com>

[Severity: Low]
This isn't a bug, but the Author email address (dineshkumarv85@gmail.com) does
not match the Signed-off-by email address (dinesh.v@adlinktech.com). Should
these two addresses match?

> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index a80cccf34eb56..26b432127faa6 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -983,6 +983,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-ivy.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-mallow.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-yavia.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-zinnia.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx95-lec-ipi-smarc.dtb

[Severity: Low]
This isn't a bug, but the imx95 targets in arch/arm64/boot/dts/freescale/Makefile
are sorted alphabetically. Should imx95-lec-ipi-smarc.dtb be placed between
imx95-aquila-dev.dtb and imx95-navq.dtb instead of at the end of the list?

[ ... ]

> diff --git a/arch/arm64/boot/dts/freescale/imx95-lec-ipi-smarc.dts b/arch/arm64/boot/dts/freescale/imx95-lec-ipi-smarc.dts
> new file mode 100644
> index 0000000000000..9a77bff42b225
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx95-lec-ipi-smarc.dts

[ ... ]

> +/* Ethernet SMARC GBE0 */
> +&enetc_port0 {
> +	pinctrl-0 = <&pinctrl_enetc0>;
> +	phy-handle = <&ethphy0>;
> +	pinctrl-names = "default";
> +	phy-mode = "rgmii-id";
> +
> +	status = "okay";
> +};
> +
> +/* Ethernet SMARC GBE1 */
> +&enetc_port1 {
> +	pinctrl-0 = <&pinctrl_enetc1>;
> +	phy-handle = <&ethphy1>;
> +	pinctrl-names = "default";
> +	phy-mode = "rgmii-id";
> +
> +	status = "okay";
> +};
> +
> +&lpi2c2 {
> +	clock-frequency = <100000>;
> +	pinctrl-0 = <&pinctrl_lpi2c2>;
> +	pinctrl-names = "default";
> +
> +	status = "okay";
> +
> +	/* U1000 SX1509BIULTRT_SEMTECH */
> +	i2c2_gpio_expander_71: pinctrl@71 {
> +		/*
> +		 * GPIO Expander Mapping:
> +		 * - 0: ENET1_RST_B_3V		=>		U2001
> +		 * - 1: ENET2_RST_B_3V		=>		U2101
> +		 * - 2: SERDES_RST#_3V		=>		SMARC S77 PCIE_C_RST
> +		 * - 3: RC210_EN_3V		=>		U1300, RC21008B001GND
> +		 * - 4: LT9611_RSTN_3V		=>		U1500
> +		 * - 5: HDMI_INT_3V		<=		U1500
> +		 * - 6: PCIEA_RST#_3V		=>		SMARC P75
> +		 * - 7: PCIEB_RST#_3V		=>		SMARC S76
> +		 * - 8: TPM_RST_N_1V8		=>		U2400
> +		 * - 9: LID#_1V8		<=	R1005	SMARC S148
> +		 * - 10: SLEEP#_1V8		<=	R1010	SMARC S149
> +		 * - 11: CHARGING#_1V8		<=	R1007	SMARC S151
> +		 * - 12: CHARGER_PRSNT#_1V8	<=	R1011	SMARC S152
> +		 * - 13: BATLOW#_1V8		<=	R1014	SMARC S156
> +		 * - 14: TEST#_1V8		<=	R1015	SMARC S157
> +		 * - 15: DSI0_TE_1V8		<=	R1087	SMARC S144
> +		 */
> +		compatible = "semtech,sx1509q";
> +		reg = <0x71>;
> +		#gpio-cells = <2>;
> +		gpio-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-controller;
> +		interrupt-parent = <&gpio4>;
> +		interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
> +		pinctrl-0 = <&pinctrl_sx1509q>;
> +		pinctrl-names = "default";
> +		semtech,probe-reset;
> +
> +		status = "okay";
> +	};
> +};

[ ... ]

> +&netc_emdio {
> +	pinctrl-0 = <&pinctrl_emdio>;
> +	pinctrl-names = "default";
> +
> +	status = "okay";
> +
> +	ethphy0: ethernet-phy@1 {
> +		compatible = "ethernet-phy-id001c.c916";
> +		reg = <1>;
> +		eee-broken-1000t;
> +		realtek,clkout-disable;
> +	};
> +
> +	ethphy1: ethernet-phy@4 {
> +		compatible = "ethernet-phy-id001c.c916";
> +		reg = <4>;
> +		eee-broken-1000t;
> +		realtek,clkout-disable;
> +	};
> +};

[ ... ]

> +&usb3 {
> +	status = "okay";
> +};
> +
> +&usb3_dwc3 {
> +	dr_mode = "host";
> +	snps,dis-u1-entry-quirk;
> +	snps,dis-u2-entry-quirk;
> +
> +	status = "okay";
> +};

[Severity: Low]
In arch/arm64/boot/dts/freescale/imx95.dtsi, usb3 and usb3_dwc3 are labels on
the same flattened usb@4c100000 node:

    usb3: usb3_dwc3: usb@4c100000 {

Should &usb3 and &usb3_dwc3 in arch/arm64/boot/dts/freescale/imx95-lec-ipi-smarc.dts
be merged into a single node reference so status = "okay" is not set twice on
the same node?

> +
> +&usb3_phy {
> +	status = "okay";
> +};
> +
> +&usdhc1 {
> +	status = "okay";
> +};

[Severity: Low]
Several on-module components and module pinmux bindings are placed here in
arch/arm64/boot/dts/freescale/imx95-lec-ipi-smarc.dts rather than in
arch/arm64/boot/dts/freescale/imx95-lec.dtsi:

- i2c2_gpio_expander_71 under lpi2c2 is on the module (its interrupt pin is
  named and muxed via pinctrl_sx1509q in imx95-lec.dtsi, and its pins control
  on-module devices as well as SMARC signals).
- ethphy0 and ethphy1 under netc_emdio, along with the RGMII/MDIO pinctrl-0
  and phy-mode properties on enetc_port0, enetc_port1, and netc_emdio, are part
  of the SMARC module's GBE0/GBE1 implementation.
- usdhc1 is configured as the non-removable on-module storage in
  imx95-lec.dtsi, but status = "okay" is only set in the carrier board file.
- The pinctrl-0 and pinctrl-names properties referencing the pinctrl_* groups
  defined in imx95-lec.dtsi are only attached to the peripheral nodes in
  imx95-lec-ipi-smarc.dts.

Should these on-module definitions and pinctrl properties be moved into
imx95-lec.dtsi so that other carrier board device trees including
imx95-lec.dtsi do not have to duplicate them?

[ ... ]

> diff --git a/arch/arm64/boot/dts/freescale/imx95-lec.dtsi b/arch/arm64/boot/dts/freescale/imx95-lec.dtsi
> new file mode 100644
> index 0000000000000..60d68c146ae46
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx95-lec.dtsi

[ ... ]

> +	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
> +		bootph-pre-ram;
> +		fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK			0x158e>,
> +			   <IMX95_PAD_SD1_CMD__USDHC1_CMD			0x138e>,
> +			   <IMX95_PAD_SD1_DATA0__USDHC1_DATA0			0x138e>,
> +			   <IMX95_PAD_SD1_DATA1__USDHC1_DATA1			0x138e>,
> +			   <IMX95_PAD_SD1_DATA2__USDHC1_DATA2			0x138e>,
> +			   <IMX95_PAD_SD1_DATA3__USDHC1_DATA3			0x138e>,
> +			   <IMX95_PAD_SD1_DATA4__USDHC1_DATA4			0x138e>,
> +			   <IMX95_PAD_SD1_DATA5__USDHC1_DATA5			0x138e>,
> +			   <IMX95_PAD_SD1_DATA6__USDHC1_DATA6			0x138e>,
> +			   <IMX95_PAD_SD1_DATA7__USDHC1_DATA7			0x138e>,
> +			   <IMX95_PAD_SD1_STROBE__USDHC1_STROBE			0x158e>;
> +	};
> +
> +	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
> +		bootph-pre-ram;
> +		fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK			0x15fe>,
> +			   <IMX95_PAD_SD1_CMD__USDHC1_CMD			0x13fe>,
> +			   <IMX95_PAD_SD1_DATA0__USDHC1_DATA0			0x13fe>,
> +			   <IMX95_PAD_SD1_DATA1__USDHC1_DATA1			0x13fe>,
> +			   <IMX95_PAD_SD1_DATA2__USDHC1_DATA2			0x13fe>,
> +			   <IMX95_PAD_SD1_DATA3__USDHC1_DATA3			0x13fe>,
> +			   <IMX95_PAD_SD1_DATA4__USDHC1_DATA4			0x13fe>,
> +			   <IMX95_PAD_SD1_DATA5__USDHC1_DATA5			0x13fe>,
> +			   <IMX95_PAD_SD1_DATA6__USDHC1_DATA6			0x13fe>,
> +			   <IMX95_PAD_SD1_DATA7__USDHC1_DATA7			0x13fe>,
> +			   <IMX95_PAD_SD1_STROBE__USDHC1_STROBE			0x15fe>;
> +	};
> +
> +	pinctrl_usdhc1: usdhc1grp {
> +		bootph-pre-ram;
> +		fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK			0x158e>,
> +			   <IMX95_PAD_SD1_CMD__USDHC1_CMD			0x138e>,
> +			   <IMX95_PAD_SD1_DATA0__USDHC1_DATA0			0x138e>,
> +			   <IMX95_PAD_SD1_DATA1__USDHC1_DATA1			0x138e>,
> +			   <IMX95_PAD_SD1_DATA2__USDHC1_DATA2			0x138e>,
> +			   <IMX95_PAD_SD1_DATA3__USDHC1_DATA3			0x138e>,
> +			   <IMX95_PAD_SD1_DATA4__USDHC1_DATA4			0x138e>,
> +			   <IMX95_PAD_SD1_DATA5__USDHC1_DATA5			0x138e>,
> +			   <IMX95_PAD_SD1_DATA6__USDHC1_DATA6			0x138e>,
> +			   <IMX95_PAD_SD1_DATA7__USDHC1_DATA7			0x138e>,
> +			   <IMX95_PAD_SD1_STROBE__USDHC1_STROBE			0x158e>;
> +	};
> +
> +	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
> +		bootph-pre-ram;
> +		fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK			0x158e>,
> +			   <IMX95_PAD_SD2_CMD__USDHC2_CMD			0x138e>,
> +			   <IMX95_PAD_SD2_DATA0__USDHC2_DATA0			0x138e>,
> +			   <IMX95_PAD_SD2_DATA1__USDHC2_DATA1			0x138e>,
> +			   <IMX95_PAD_SD2_DATA2__USDHC2_DATA2			0x138e>,
> +			   <IMX95_PAD_SD2_DATA3__USDHC2_DATA3			0x138e>,
> +			   <IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e>;
> +	};
> +
> +	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
> +		bootph-pre-ram;
> +		fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK			0x158e>,
> +			   <IMX95_PAD_SD2_CMD__USDHC2_CMD			0x138e>,
> +			   <IMX95_PAD_SD2_DATA0__USDHC2_DATA0			0x138e>,
> +			   <IMX95_PAD_SD2_DATA1__USDHC2_DATA1			0x138e>,
> +			   <IMX95_PAD_SD2_DATA2__USDHC2_DATA2			0x138e>,
> +			   <IMX95_PAD_SD2_DATA3__USDHC2_DATA3			0x138e>,
> +			   <IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e>;
> +	};
> +
> +	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
> +		bootph-pre-ram;
> +		fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0		0x31e>;
> +	};
> +
> +	pinctrl_usdhc2: usdhc2grp {
> +		bootph-pre-ram;
> +		fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK			0x158e>,
> +			   <IMX95_PAD_SD2_CMD__USDHC2_CMD			0x138e>,
> +			   <IMX95_PAD_SD2_DATA0__USDHC2_DATA0			0x138e>,
> +			   <IMX95_PAD_SD2_DATA1__USDHC2_DATA1			0x138e>,
> +			   <IMX95_PAD_SD2_DATA2__USDHC2_DATA2			0x138e>,
> +			   <IMX95_PAD_SD2_DATA3__USDHC2_DATA3			0x138e>,
> +			   <IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e>;
> +	};

[Severity: Low]
In scmi_iomuxc in arch/arm64/boot/dts/freescale/imx95-lec.dtsi,
pinctrl_usdhc2_200mhz uses the same 0x158e and 0x138e pad configuration values
as pinctrl_usdhc2_100mhz and pinctrl_usdhc2, whereas pinctrl_usdhc1_200mhz uses
0x15fe and 0x13fe. In addition, pinctrl_usdhc1_100mhz is identical to
pinctrl_usdhc1, and pinctrl_usdhc2_100mhz is identical to pinctrl_usdhc2.

Should pinctrl_usdhc2_200mhz use 0x15fe/0x13fe for 200MHz operation, or if all
states intentionally use the same pad settings, can the duplicate pinctrl
groups be dropped in favor of reusing pinctrl_usdhc1 and pinctrl_usdhc2?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261102102653.272056-1-dinesh.v@adlinktech.com?part=3

^ permalink raw reply	[flat|nested] 11+ messages in thread
end of thread, other threads:[~2026-11-02 10:45 UTC | newest]

Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-11-02  6:56 [PATCH 0/2] Add ADLINK LEC-iMX95 board support Dinesh kumar v
2026-11-02  6:56 ` [PATCH 1/2] dt-bindings: arm: fsl: Add ADLINK LEC-iMX95 Dinesh kumar v
2026-11-02  7:04   ` sashiko-bot
2026-11-02  6:56 ` [PATCH 2/2] arm64: dts: imx95: Add ADLINK LEC-iMX95 board support Dinesh kumar v
2026-11-02  7:10   ` sashiko-bot
2026-11-02 10:26 ` [PATCH v2 0/3] " Dinesh kumar v
2026-11-02 10:26   ` [PATCH v2 1/3] dt-bindings: vendor-prefixes: Add ADLINK Dinesh kumar v
2026-11-02 10:32     ` sashiko-bot
2026-11-02 10:26   ` [PATCH v2 2/3] dt-bindings: arm: fsl: Add ADLINK LEC-iMX95 Dinesh kumar v
2026-11-02 10:26   ` [PATCH v2 3/3] arm64: dts: imx95: Add ADLINK LEC-iMX95 board support Dinesh kumar v
2026-11-02 10:45     ` sashiko-bot

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