[PATCH 0/2] ASoC: tegra: Add Tegra268 ADMAIF support

[PATCH 0/2] ASoC: tegra: Add Tegra268 ADMAIF support

[Sheetal]

Tegra268 reuses the Tegra264 ADMAIF register layout but provides only
five RX and five TX interfaces. Add its binding, SoC data, DAI and
control tables, and FIFO defaults to match this configuration.

Anupama Kunkulagunta (2):
  dt-bindings: sound: Add Tegra268 ADMAIF support
  ASoC: tegra: ADMAIF: Add Tegra268 support

 .../sound/nvidia,tegra210-admaif.yaml         | 22 +++++++
 sound/soc/tegra/tegra210_admaif.c             | 66 +++++++++++++++++++
 sound/soc/tegra/tegra210_admaif.h             | 20 ++++++
 3 files changed, 108 insertions(+)

-- 
2.43.0

[PATCH 1/2] dt-bindings: sound: Add Tegra268 ADMAIF support

[Sheetal]

From: Anupama Kunkulagunta <akunkulagunt@nvidia.com>

Add the Tegra268 ADMAIF compatible. Tegra268 ADMAIF supports five
RX and five TX channels.

Signed-off-by: Anupama Kunkulagunta <akunkulagunt@nvidia.com>
Signed-off-by: Sheetal <sheetal@nvidia.com>
---
 .../sound/nvidia,tegra210-admaif.yaml         | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif.yaml
index 2ce4049f94ac..054bacf60234 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif.yaml
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif.yaml
@@ -27,6 +27,7 @@ properties:
           - nvidia,tegra210-admaif
           - nvidia,tegra186-admaif
           - nvidia,tegra264-admaif
+          - nvidia,tegra268-admaif
       - items:
           - enum:
               - nvidia,tegra234-admaif
@@ -134,6 +135,27 @@ allOf:
           minItems: 1
           maxItems: 64
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nvidia,tegra268-admaif
+    then:
+      properties:
+        dmas:
+          description:
+            DMA channel specifiers, equally divided for Tx and Rx.
+          minItems: 1
+          maxItems: 10
+        dma-names:
+          items:
+            pattern: "^[rt]x[1-5]$"
+          description:
+            Should be "rx1", "rx2" ... "rx5" for DMA Rx channel
+            Should be "tx1", "tx2" ... "tx5" for DMA Tx channel
+          minItems: 1
+          maxItems: 10
+
 required:
   - compatible
   - reg
-- 
2.43.0

[PATCH 2/2] ASoC: tegra: ADMAIF: Add Tegra268 support

[Sheetal]

From: Anupama Kunkulagunta <akunkulagunt@nvidia.com>

Tegra268 reuses the Tegra264 ADMAIF register layout but provides only
five RX and five TX interfaces. Add the compatible and SoC data for
this configuration.

Add register defaults and five-entry DAI and control tables. Retain
the Tegra264 32-channel per-stream limit and use Tegra268 FIFO defaults.

Set the register bound one stride past the final global TX enable
status register so the access callbacks mark it readable and volatile.

Signed-off-by: Anupama Kunkulagunta <akunkulagunt@nvidia.com>
Signed-off-by: Sheetal <sheetal@nvidia.com>
---
 sound/soc/tegra/tegra210_admaif.c | 66 +++++++++++++++++++++++++++++++
 sound/soc/tegra/tegra210_admaif.h | 20 ++++++++++
 2 files changed, 86 insertions(+)

diff --git a/sound/soc/tegra/tegra210_admaif.c b/sound/soc/tegra/tegra210_admaif.c
index 87e898cc35e4..72a245ced209 100644
--- a/sound/soc/tegra/tegra210_admaif.c
+++ b/sound/soc/tegra/tegra210_admaif.c
@@ -184,6 +184,20 @@ static const struct reg_default tegra264_admaif_reg_defaults[] = {
 	{(TEGRA_ADMAIF_GLOBAL_CG_0 + TEGRA264_ADMAIF_GLOBAL_BASE), 0x00000003}
 };
 
+static const struct reg_default tegra268_admaif_reg_defaults[] = {
+	ADMAIF_RX_REG_DEFAULTS(1, TEGRA268),
+	ADMAIF_RX_REG_DEFAULTS(2, TEGRA268),
+	ADMAIF_RX_REG_DEFAULTS(3, TEGRA268),
+	ADMAIF_RX_REG_DEFAULTS(4, TEGRA268),
+	ADMAIF_RX_REG_DEFAULTS(5, TEGRA268),
+	ADMAIF_TX_REG_DEFAULTS(1, TEGRA268),
+	ADMAIF_TX_REG_DEFAULTS(2, TEGRA268),
+	ADMAIF_TX_REG_DEFAULTS(3, TEGRA268),
+	ADMAIF_TX_REG_DEFAULTS(4, TEGRA268),
+	ADMAIF_TX_REG_DEFAULTS(5, TEGRA268),
+	{(TEGRA_ADMAIF_GLOBAL_CG_0 + TEGRA268_ADMAIF_GLOBAL_BASE), 0x00000003}
+};
+
 static bool tegra_admaif_wr_reg(struct device *dev, unsigned int reg)
 {
 	struct tegra_admaif *admaif = dev_get_drvdata(dev);
@@ -342,6 +356,20 @@ static const struct regmap_config tegra264_admaif_regmap_config = {
 	.cache_type		= REGCACHE_FLAT,
 };
 
+static const struct regmap_config tegra268_admaif_regmap_config = {
+	.reg_bits		= 32,
+	.reg_stride		= 4,
+	.val_bits		= 32,
+	.max_register		= TEGRA268_ADMAIF_LAST_REG,
+	.writeable_reg		= tegra_admaif_wr_reg,
+	.readable_reg		= tegra_admaif_rd_reg,
+	.volatile_reg		= tegra_admaif_volatile_reg,
+	.reg_defaults		= tegra268_admaif_reg_defaults,
+	.num_reg_defaults	= TEGRA268_ADMAIF_CHANNEL_COUNT * 6 + 1,
+	.reg_default_cb		= regmap_default_zero_cb,
+	.cache_type		= REGCACHE_FLAT,
+};
+
 static int tegra_admaif_runtime_suspend(struct device *dev)
 {
 	struct tegra_admaif *admaif = dev_get_drvdata(dev);
@@ -796,6 +824,14 @@ static struct snd_soc_dai_driver tegra264_admaif_cmpnt_dais[] = {
 	DAI("ADMAIF32", TEGRA264_ADMAIF_MAX_CHANNEL),
 };
 
+static struct snd_soc_dai_driver tegra268_admaif_cmpnt_dais[] = {
+	DAI("ADMAIF1", TEGRA268_ADMAIF_MAX_CHANNEL),
+	DAI("ADMAIF2", TEGRA268_ADMAIF_MAX_CHANNEL),
+	DAI("ADMAIF3", TEGRA268_ADMAIF_MAX_CHANNEL),
+	DAI("ADMAIF4", TEGRA268_ADMAIF_MAX_CHANNEL),
+	DAI("ADMAIF5", TEGRA268_ADMAIF_MAX_CHANNEL),
+};
+
 static const char * const tegra_admaif_stereo_conv_text[] = {
 	"CH0", "CH1", "AVG",
 };
@@ -908,6 +944,14 @@ static struct snd_kcontrol_new tegra264_admaif_controls[] = {
 	TEGRA_ADMAIF_CIF_CTRL(32),
 };
 
+static struct snd_kcontrol_new tegra268_admaif_controls[] = {
+	TEGRA_ADMAIF_CIF_CTRL(1),
+	TEGRA_ADMAIF_CIF_CTRL(2),
+	TEGRA_ADMAIF_CIF_CTRL(3),
+	TEGRA_ADMAIF_CIF_CTRL(4),
+	TEGRA_ADMAIF_CIF_CTRL(5),
+};
+
 static const struct snd_soc_component_driver tegra210_admaif_cmpnt = {
 	.controls		= tegra210_admaif_controls,
 	.num_controls		= ARRAY_SIZE(tegra210_admaif_controls),
@@ -938,6 +982,16 @@ static const struct snd_soc_component_driver tegra264_admaif_cmpnt = {
 	.pointer		= tegra_pcm_pointer,
 };
 
+static const struct snd_soc_component_driver tegra268_admaif_cmpnt = {
+	.controls		= tegra268_admaif_controls,
+	.num_controls		= ARRAY_SIZE(tegra268_admaif_controls),
+	.pcm_new		= tegra_pcm_new,
+	.open			= tegra_pcm_open,
+	.close			= tegra_pcm_close,
+	.hw_params		= tegra_pcm_hw_params,
+	.pointer		= tegra_pcm_pointer,
+};
+
 static const struct tegra_admaif_soc_data soc_data_tegra210 = {
 	.num_ch		= TEGRA210_ADMAIF_CHANNEL_COUNT,
 	.max_stream_ch	= TEGRA210_ADMAIF_MAX_CHANNEL,
@@ -971,10 +1025,22 @@ static const struct tegra_admaif_soc_data soc_data_tegra264 = {
 	.rx_base	= TEGRA264_ADMAIF_RX_BASE,
 };
 
+static const struct tegra_admaif_soc_data soc_data_tegra268 = {
+	.num_ch		= TEGRA268_ADMAIF_CHANNEL_COUNT,
+	.max_stream_ch	= TEGRA268_ADMAIF_MAX_CHANNEL,
+	.cmpnt		= &tegra268_admaif_cmpnt,
+	.dais		= tegra268_admaif_cmpnt_dais,
+	.regmap_conf	= &tegra268_admaif_regmap_config,
+	.global_base	= TEGRA268_ADMAIF_GLOBAL_BASE,
+	.tx_base	= TEGRA268_ADMAIF_TX_BASE,
+	.rx_base	= TEGRA268_ADMAIF_RX_BASE,
+};
+
 static const struct of_device_id tegra_admaif_of_match[] = {
 	{ .compatible = "nvidia,tegra210-admaif", .data = &soc_data_tegra210 },
 	{ .compatible = "nvidia,tegra186-admaif", .data = &soc_data_tegra186 },
 	{ .compatible = "nvidia,tegra264-admaif", .data = &soc_data_tegra264 },
+	{ .compatible = "nvidia,tegra268-admaif", .data = &soc_data_tegra268 },
 	{},
 };
 MODULE_DEVICE_TABLE(of, tegra_admaif_of_match);
diff --git a/sound/soc/tegra/tegra210_admaif.h b/sound/soc/tegra/tegra210_admaif.h
index fd9877aa95d3..4a7fff91f8bb 100644
--- a/sound/soc/tegra/tegra210_admaif.h
+++ b/sound/soc/tegra/tegra210_admaif.h
@@ -31,6 +31,14 @@
 #define TEGRA264_ADMAIF_TX_BASE				0x1000
 #define TEGRA264_ADMAIF_GLOBAL_BASE			0x2000
 #define TEGRA264_ADMAIF_MAX_CHANNEL			32
+/* Tegra268 specific */
+#define TEGRA268_ADMAIF_CHANNEL_COUNT			5
+#define TEGRA268_ADMAIF_RX_BASE				TEGRA264_ADMAIF_RX_BASE
+#define TEGRA268_ADMAIF_TX_BASE				TEGRA264_ADMAIF_TX_BASE
+#define TEGRA268_ADMAIF_GLOBAL_BASE			TEGRA264_ADMAIF_GLOBAL_BASE
+#define TEGRA268_ADMAIF_LAST_REG			(TEGRA268_ADMAIF_GLOBAL_BASE + \
+							 TEGRA_ADMAIF_GLOBAL_TX_ENABLE_STATUS + 4)
+#define TEGRA268_ADMAIF_MAX_CHANNEL			TEGRA264_ADMAIF_MAX_CHANNEL
 /* Global registers */
 #define TEGRA_ADMAIF_GLOBAL_ENABLE			0x0
 #define TEGRA_ADMAIF_GLOBAL_CG_0			0x8
@@ -204,6 +212,18 @@
 #define TEGRA264_ADMAIF_TX30_FIFO_CTRL_REG_DEFAULT	0x01800257
 #define TEGRA264_ADMAIF_TX31_FIFO_CTRL_REG_DEFAULT	0x0180025a
 #define TEGRA264_ADMAIF_TX32_FIFO_CTRL_REG_DEFAULT	0x0180025d
+/* Default values - Tegra268 */
+#define TEGRA268_ADMAIF_CIF_REG_DEFAULT			0x00003f00
+#define TEGRA268_ADMAIF_RX1_FIFO_CTRL_REG_DEFAULT	0x00000500
+#define TEGRA268_ADMAIF_RX2_FIFO_CTRL_REG_DEFAULT	0x00000507
+#define TEGRA268_ADMAIF_RX3_FIFO_CTRL_REG_DEFAULT	0x0000050e
+#define TEGRA268_ADMAIF_RX4_FIFO_CTRL_REG_DEFAULT	0x00000514
+#define TEGRA268_ADMAIF_RX5_FIFO_CTRL_REG_DEFAULT	0x0000051a
+#define TEGRA268_ADMAIF_TX1_FIFO_CTRL_REG_DEFAULT	0x03000500
+#define TEGRA268_ADMAIF_TX2_FIFO_CTRL_REG_DEFAULT	0x03000507
+#define TEGRA268_ADMAIF_TX3_FIFO_CTRL_REG_DEFAULT	0x0300050e
+#define TEGRA268_ADMAIF_TX4_FIFO_CTRL_REG_DEFAULT	0x03000514
+#define TEGRA268_ADMAIF_TX5_FIFO_CTRL_REG_DEFAULT	0x0300051a
 
 enum {
 	DATA_8BIT,
-- 
2.43.0

Re: [PATCH 1/2] dt-bindings: sound: Add Tegra268 ADMAIF support

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] dt-bindings: sound: unwieldy per-compatible conditionals in tegra210-admaif
--

commit 8b302b26b4687658ab926b6d8c1160f749d509a9
Author: Anupama Kunkulagunta <akunkulagunt@nvidia.com>

dt-bindings: sound: Add Tegra268 ADMAIF support

This commit adds the nvidia,tegra268-admaif compatible string and its
per-compatible DMA channel constraints for five RX and five TX channels to
the Tegra210 ADMAIF device tree binding schema.

> diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif.yaml
> index 2ce4049f94acc..054bacf602349 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif.yaml
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif.yaml

[ ... ]

> @@ -134,6 +135,27 @@ allOf:
>            minItems: 1
>            maxItems: 64
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: nvidia,tegra268-admaif
> +    then:
> +      properties:
> +        dmas:
> +          description:
> +            DMA channel specifiers, equally divided for Tx and Rx.
> +          minItems: 1
> +          maxItems: 10
> +        dma-names:
> +          items:
> +            pattern: "^[rt]x[1-5]$"
> +          description:
> +            Should be "rx1", "rx2" ... "rx5" for DMA Rx channel
> +            Should be "tx1", "tx2" ... "tx5" for DMA Tx channel
> +          minItems: 1
> +          maxItems: 10

[Severity: Low]
This isn't a bug, but in Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif.yaml,
the top-level properties section leaves dmas and dma-names as bare true
booleans:

  dmas: true

  dma-names: true

while the allOf section already contains three per-compatible if-then blocks
for nvidia,tegra210-admaif, nvidia,tegra186-admaif, and
nvidia,tegra264-admaif. Adding a fourth per-compatible if-then block here for
nvidia,tegra268-admaif duplicates the dmas and dma-names descriptions,
minItems/maxItems bounds, and dma-names pattern structure again.

Since the per-compatible conditionals in this schema are becoming unwieldy
due to variant differences, would it be cleaner to split the variants into
separate schema documents or factor the shared dmas and dma-names definitions
into the top-level properties section instead of piling on another
conditional block?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261104111836.1100527-1-sheetal@nvidia.com?part=1