[PATCH 0/7] arm64: dts: qcom: sm8350: Add SoundWire and LPASS

[PATCH 0/7] arm64: dts: qcom: sm8350: Add SoundWire and LPASS

[Demeter Barna via B4 Relay]

SM8350 has the ADSP audio services in its dtsi but none of the LPASS
codec macros or SoundWire controllers, so boards can't describe their
codecs and DMICs yet. This series adds the RX, TX and VA macros with
their SoundWire controllers, and the SM8350 sound card compatible.

Patches 1-2 go through clk, 3-5 and 7 through ASoC, 6 through qcom
arm64. The macros use the data the drivers already have: RX that of
SM8250, TX that of SM8450, VA that of SC7280.

Tested on the Razer Edge 5G: both DMICs record through the VA macro and
the WCD9380 enumerates on the RX and TX buses. Capture from the
WCD9380's ADCs through the TX macro is silent with the SM8450 data, and
headphone playback isn't tested. The WSA macro is left out: this board
has no WSA amplifiers to test it with.

Prepared with the help of an AI coding assistant, reviewed and tested
by me.

---
Demeter Barna (7):
      dt-bindings: clock: qcom,sc8280xp-lpasscc: Add SM8350 LPASS audio CSR
      clk: qcom: lpassaudiocc-sc7280: Add SM8350 audio CSR resets
      ASoC: dt-bindings: qcom,lpass-rx-macro: Add SM8350 LPASS RX
      ASoC: dt-bindings: qcom,lpass-tx-macro: Add SM8350 LPASS TX
      ASoC: dt-bindings: qcom,lpass-va-macro: Add SM8350 LPASS VA
      arm64: dts: qcom: sm8350: Add SoundWire and LPASS
      ASoC: dt-bindings: qcom,sm8250: Add SM8350 sound card

 .../bindings/clock/qcom,sc8280xp-lpasscc.yaml      |   1 +
 .../bindings/sound/qcom,lpass-rx-macro.yaml        |  12 +-
 .../bindings/sound/qcom,lpass-tx-macro.yaml        |  12 +-
 .../bindings/sound/qcom,lpass-va-macro.yaml        |   3 +
 .../devicetree/bindings/sound/qcom,sm8250.yaml     |   3 +
 arch/arm64/boot/dts/qcom/sm8350.dtsi               | 196 +++++++++++++++++++++
 drivers/clk/qcom/lpassaudiocc-sc7280.c             |   4 +
 7 files changed, 223 insertions(+), 8 deletions(-)
---
base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4
change-id: 20261104-b4-sm8350-sound-eab29042cf89

Best regards,
--  
Demeter Barna <me@fromdisposition.org>

[PATCH 1/7] dt-bindings: clock: qcom,sc8280xp-lpasscc: Add SM8350 LPASS audio CSR

[Demeter Barna via B4 Relay]

From: Demeter Barna <me@fromdisposition.org>

As on SC8280XP, the SM8350 LPASS audio CSR is controlled by the ADSP and
only provides resets to the OS, so it takes no clocks. Its resets are the
RX, TX and WSA SoundWire ones of SC7280 (at 0xa0, 0xa8 and 0xb0);
SC8280XP has no TX reset in this block, so there is no SC8280XP fallback
and the SC7280 reset IDs are used.

Signed-off-by: Demeter Barna <me@fromdisposition.org>
---
 Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml
index f235b4e24..3d4a794ab 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml
@@ -22,6 +22,7 @@ properties:
       - enum:
           - qcom,sc8280xp-lpassaudiocc
           - qcom,sc8280xp-lpasscc
+          - qcom,sm8350-lpassaudiocc
       - items:
           - const: qcom,x1e80100-lpassaudiocc
           - const: qcom,sc8280xp-lpassaudiocc

-- 
2.53.0

Re: [PATCH 1/7] dt-bindings: clock: qcom,sc8280xp-lpasscc: Add SM8350 LPASS audio CSR

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] dt-bindings: clock: missing sc7280 header in qcom,sc8280xp-lpasscc See also
--

commit dee8eaeed95bbc7385e8c1208d78c9a4483b6760
Author: Demeter Barna <me@fromdisposition.org>

dt-bindings: clock: qcom,sc8280xp-lpasscc: Add SM8350 LPASS audio CSR

This commit adds the qcom,sm8350-lpassaudiocc compatible to the
qcom,sc8280xp-lpasscc binding schema for the SM8350 LPASS audio CSR block,
which only provides resets to the OS and uses the SC7280 reset IDs.

> diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml
> index f235b4e24cc70..3d4a794abf134 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml
> @@ -22,6 +22,7 @@ properties:
>        - enum:
>            - qcom,sc8280xp-lpassaudiocc
>            - qcom,sc8280xp-lpasscc
> +          - qcom,sm8350-lpassaudiocc

[Severity: Low]
As noted in the commit message and implemented in
drivers/clk/qcom/lpassaudiocc-sc7280.c, qcom,sm8350-lpassaudiocc binds to
lpass_audio_cc_reset_sc7280_desc and uses the reset IDs from
include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h:

  LPASS_AUDIO_SWR_RX_CGCR  0
  LPASS_AUDIO_SWR_TX_CGCR  1
  LPASS_AUDIO_SWR_WSA_CGCR 2

However, the description property in
Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml only
lists the SC8280XP header:

  description: |
    Qualcomm LPASS core and audio clock control module provides the clocks,
    and reset on SC8280XP.

    See also:
      include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h

In include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h, the same macro names
have different numeric values (with LPASS_AUDIO_SWR_WSA_CGCR defined as 1
and LPASS_AUDIO_SWR_TX_CGCR defined as 0 for the LPASS TCSR block).

Should include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h also be listed
under "See also:" in description so that users of this binding know where
the SM8350 reset IDs are defined?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261104-b4-sm8350-sound-v1-0-4c872df294fa@fromdisposition.org?part=1

[PATCH 2/7] clk: qcom: lpassaudiocc-sc7280: Add SM8350 audio CSR resets

[Demeter Barna via B4 Relay]

From: Demeter Barna <me@fromdisposition.org>

Without these resets the codecs on the SoundWire buses fail to
initialize. The offsets match the QCM6490 reset-only descriptor, but
the SM8350 node only has the CSR region, so probe it from index 0.

Signed-off-by: Demeter Barna <me@fromdisposition.org>
---
 drivers/clk/qcom/lpassaudiocc-sc7280.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpassaudiocc-sc7280.c
index 7e2172969..11332f9f0 100644
--- a/drivers/clk/qcom/lpassaudiocc-sc7280.c
+++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c
@@ -732,6 +732,7 @@ static const struct qcom_cc_desc lpass_audio_cc_reset_sc7280_desc = {
 static const struct of_device_id lpass_audio_cc_sc7280_match_table[] = {
 	{ .compatible = "qcom,qcm6490-lpassaudiocc", .data = &lpass_audio_cc_reset_sc7280_desc },
 	{ .compatible = "qcom,sc7280-lpassaudiocc", .data = &lpass_audio_cc_sc7280_desc },
+	{ .compatible = "qcom,sm8350-lpassaudiocc", .data = &lpass_audio_cc_reset_sc7280_desc },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, lpass_audio_cc_sc7280_match_table);
@@ -768,6 +769,9 @@ static int lpass_audio_cc_sc7280_probe(struct platform_device *pdev)
 	if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcm6490-lpassaudiocc"))
 		return qcom_cc_probe_by_index(pdev, 1, desc);
 
+	if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-lpassaudiocc"))
+		return qcom_cc_probe_by_index(pdev, 0, desc);
+
 	ret = lpass_audio_setup_runtime_pm(pdev);
 	if (ret)
 		return ret;

-- 
2.53.0

[PATCH 3/7] ASoC: dt-bindings: qcom,lpass-rx-macro: Add SM8350 LPASS RX

[Demeter Barna via B4 Relay]

From: Demeter Barna <me@fromdisposition.org>

The SM8350 RX macro takes the clocks of SM8250, and the driver handles
it with the same data as SM8250 and SM8450, so add it with SM8250 as
the fallback. Use "contains" in the clocks condition so that it covers
the fallback form.

Signed-off-by: Demeter Barna <me@fromdisposition.org>
---
 .../devicetree/bindings/sound/qcom,lpass-rx-macro.yaml       | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml
index 4988e7ed6..67a4a9536 100644
--- a/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml
+++ b/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml
@@ -19,6 +19,9 @@ properties:
           - qcom,sm8450-lpass-rx-macro
           - qcom,sm8550-lpass-rx-macro
           - qcom,sc8280xp-lpass-rx-macro
+      - items:
+          - const: qcom,sm8350-lpass-rx-macro
+          - const: qcom,sm8250-lpass-rx-macro
       - items:
           - enum:
               - qcom,eliza-lpass-rx-macro
@@ -103,10 +106,11 @@ allOf:
   - if:
       properties:
         compatible:
-          enum:
-            - qcom,sc8280xp-lpass-rx-macro
-            - qcom,sm8250-lpass-rx-macro
-            - qcom,sm8450-lpass-rx-macro
+          contains:
+            enum:
+              - qcom,sc8280xp-lpass-rx-macro
+              - qcom,sm8250-lpass-rx-macro
+              - qcom,sm8450-lpass-rx-macro
     then:
       properties:
         clocks:

-- 
2.53.0

[PATCH 4/7] ASoC: dt-bindings: qcom,lpass-tx-macro: Add SM8350 LPASS TX

[Demeter Barna via B4 Relay]

From: Demeter Barna <me@fromdisposition.org>

The SM8350 TX macro is LPASS v9.2 as on SM8450 and takes the same
clocks, so add it with SM8450 as the fallback. Use "contains" in the
clocks condition so that it also covers the fallback form.

Signed-off-by: Demeter Barna <me@fromdisposition.org>
---
 .../devicetree/bindings/sound/qcom,lpass-tx-macro.yaml       | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml
index d8682ff2e..f9702a11e 100644
--- a/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml
+++ b/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml
@@ -19,6 +19,9 @@ properties:
           - qcom,sm8450-lpass-tx-macro
           - qcom,sm8550-lpass-tx-macro
           - qcom,sc8280xp-lpass-tx-macro
+      - items:
+          - const: qcom,sm8350-lpass-tx-macro
+          - const: qcom,sm8450-lpass-tx-macro
       - items:
           - enum:
               - qcom,eliza-lpass-tx-macro
@@ -90,10 +93,11 @@ allOf:
   - if:
       properties:
         compatible:
-          enum:
-            - qcom,sc8280xp-lpass-tx-macro
-            - qcom,sm8250-lpass-tx-macro
-            - qcom,sm8450-lpass-tx-macro
+          contains:
+            enum:
+              - qcom,sc8280xp-lpass-tx-macro
+              - qcom,sm8250-lpass-tx-macro
+              - qcom,sm8450-lpass-tx-macro
     then:
       properties:
         clocks:

-- 
2.53.0

[PATCH 5/7] ASoC: dt-bindings: qcom,lpass-va-macro: Add SM8350 LPASS VA

[Demeter Barna via B4 Relay]

From: Demeter Barna <me@fromdisposition.org>

The SM8350 VA macro takes the mclk, macro and dcodec clocks, as SC7280
does without power-domains, and reports LPASS codec version 2.0 in its
core ID registers. The SC7280 driver data reads the version from there,
while the SM8250 data sets 1.0, so use SC7280 as the fallback.

Signed-off-by: Demeter Barna <me@fromdisposition.org>
---
 Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml
index aea31fbda..a5466e61b 100644
--- a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml
+++ b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml
@@ -19,6 +19,9 @@ properties:
           - qcom,sm8450-lpass-va-macro
           - qcom,sm8550-lpass-va-macro
           - qcom,sc8280xp-lpass-va-macro
+      - items:
+          - const: qcom,sm8350-lpass-va-macro
+          - const: qcom,sc7280-lpass-va-macro
       - items:
           - enum:
               - qcom,eliza-lpass-va-macro

-- 
2.53.0

[PATCH 6/7] arm64: dts: qcom: sm8350: Add SoundWire and LPASS

[Demeter Barna via B4 Relay]

From: Demeter Barna <me@fromdisposition.org>

Add the LPASS RX, TX and VA macros, the RX and TX SoundWire controllers
with their audio CSR resets, and the LPI pin states for SoundWire and
the DMICs.

The port tables have an entry for each port the controllers report in
SWRM_COMP_PARAMS (RX: 6 out, 1 in; TX: 4 in). The RX parameters are
those of the downstream SM8350 table (lahaina-port-config.h), which match
SM8250 for the WCD938x ports and SM8450 for the PCM output port; the TX
ones are those of SM8450, which has the same TX macro and three TX data
lanes. As on SM8250, the macros are clocked from the TX core clock.

As on SM8450 and later, the SoundWire pin states are on the SoundWire
controllers; the pin settings are those of SM8550 and of the downstream
SM8350 boards.

Signed-off-by: Demeter Barna <me@fromdisposition.org>
---
 arch/arm64/boot/dts/qcom/sm8350.dtsi | 196 +++++++++++++++++++++++++++++++++++
 1 file changed, 196 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 55b32050c..85476a04e 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
 #include <dt-bindings/clock/qcom,gpucc-sm8350.h>
+#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/clock/qcom,sm8350-videocc.h>
 #include <dt-bindings/dma/qcom-gpi.h>
@@ -2022,6 +2023,133 @@ compute-cb@5 {
 			};
 		};
 
+		rxmacro: codec@3200000 {
+			compatible = "qcom,sm8350-lpass-rx-macro",
+				     "qcom,sm8250-lpass-rx-macro";
+			reg = <0 0x03200000 0 0x1000>;
+
+			clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&vamacro>;
+			clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
+
+			#clock-cells = <0>;
+			clock-output-names = "mclk";
+			#sound-dai-cells = <1>;
+
+			status = "disabled";
+		};
+
+		swr1: soundwire@3210000 {
+			compatible = "qcom,soundwire-v1.6.0";
+			reg = <0 0x03210000 0 0x2000>;
+			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "core";
+
+			clocks = <&rxmacro>;
+			clock-names = "iface";
+			resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
+			reset-names = "swr_audio_cgcr";
+			label = "RX";
+
+			pinctrl-0 = <&rx_swr_active>;
+			pinctrl-names = "default";
+
+			qcom,ports-sinterval =		/bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0x18f 0xff>;
+			qcom,ports-offset1 =		/bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff>;
+			qcom,ports-offset2 =		/bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff>;
+			qcom,ports-hstart =		/bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff>;
+			qcom,ports-hstop =		/bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff>;
+			qcom,ports-word-length =	/bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff>;
+			qcom,ports-block-pack-mode =	/bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff>;
+			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff>;
+			qcom,ports-lane-control =	/bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff>;
+
+			#address-cells = <2>;
+			#size-cells = <0>;
+			#sound-dai-cells = <1>;
+
+			status = "disabled";
+		};
+
+		txmacro: codec@3220000 {
+			compatible = "qcom,sm8350-lpass-tx-macro",
+				     "qcom,sm8450-lpass-tx-macro";
+			reg = <0 0x03220000 0 0x1000>;
+
+			clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&vamacro>;
+			clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
+
+			#clock-cells = <0>;
+			clock-output-names = "mclk";
+			#sound-dai-cells = <1>;
+
+			status = "disabled";
+		};
+
+		swr2: soundwire@3230000 {
+			compatible = "qcom,soundwire-v1.6.0";
+			reg = <0 0x03230000 0 0x2000>;
+			interrupts-extended = <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+					      <&pdc 130 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "core", "wakeup";
+
+			clocks = <&txmacro>;
+			clock-names = "iface";
+			resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>;
+			reset-names = "swr_audio_cgcr";
+			label = "TX";
+
+			pinctrl-0 = <&tx_swr_active>;
+			pinctrl-names = "default";
+
+			qcom,ports-sinterval-low =	/bits/ 8 <0x01 0x01 0x03 0x03>;
+			qcom,ports-offset1 =		/bits/ 8 <0x00 0x00 0x01 0x01>;
+			qcom,ports-offset2 =		/bits/ 8 <0x00 0x00 0x00 0x00>;
+			qcom,ports-hstart =		/bits/ 8 <0xff 0xff 0xff 0xff>;
+			qcom,ports-hstop =		/bits/ 8 <0xff 0xff 0xff 0xff>;
+			qcom,ports-word-length =	/bits/ 8 <0xff 0xff 0xff 0xff>;
+			qcom,ports-block-pack-mode =	/bits/ 8 <0xff 0xff 0xff 0xff>;
+			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff>;
+			qcom,ports-lane-control =	/bits/ 8 <0x01 0x02 0x00 0x00>;
+
+			#address-cells = <2>;
+			#size-cells = <0>;
+			#sound-dai-cells = <1>;
+
+			status = "disabled";
+		};
+
+		lpass_audiocc: clock-controller@32a9000 {
+			compatible = "qcom,sm8350-lpassaudiocc";
+			reg = <0 0x032a9000 0 0x1000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		vamacro: codec@3370000 {
+			compatible = "qcom,sm8350-lpass-va-macro",
+				     "qcom,sc7280-lpass-va-macro";
+			reg = <0 0x03370000 0 0x1000>;
+
+			clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+			clock-names = "mclk", "macro", "dcodec";
+
+			#clock-cells = <0>;
+			clock-output-names = "fsgen";
+			#sound-dai-cells = <1>;
+
+			status = "disabled";
+		};
+
 		lpass_tlmm: pinctrl@33c0000 {
 			compatible = "qcom,sm8350-lpass-lpi-pinctrl";
 			reg = <0 0x033c0000 0 0x20000>,
@@ -2034,6 +2162,74 @@ lpass_tlmm: pinctrl@33c0000 {
 			gpio-controller;
 			#gpio-cells = <2>;
 			gpio-ranges = <&lpass_tlmm 0 0 15>;
+
+			dmic01_default: dmic01-default-state {
+				clk-pins {
+					pins = "gpio6";
+					function = "dmic1_clk";
+					drive-strength = <8>;
+					output-high;
+				};
+
+				data-pins {
+					pins = "gpio7";
+					function = "dmic1_data";
+					drive-strength = <8>;
+					input-enable;
+				};
+			};
+
+			dmic23_default: dmic23-default-state {
+				clk-pins {
+					pins = "gpio8";
+					function = "dmic2_clk";
+					drive-strength = <8>;
+					output-high;
+				};
+
+				data-pins {
+					pins = "gpio9";
+					function = "dmic2_data";
+					drive-strength = <8>;
+					input-enable;
+				};
+			};
+
+			rx_swr_active: rx-swr-active-state {
+				clk-pins {
+					pins = "gpio3";
+					function = "swr_rx_clk";
+					drive-strength = <2>;
+					slew-rate = <1>;
+					bias-disable;
+				};
+
+				data-pins {
+					pins = "gpio4", "gpio5";
+					function = "swr_rx_data";
+					drive-strength = <2>;
+					slew-rate = <1>;
+					bias-bus-hold;
+				};
+			};
+
+			tx_swr_active: tx-swr-active-state {
+				clk-pins {
+					pins = "gpio0";
+					function = "swr_tx_clk";
+					drive-strength = <2>;
+					slew-rate = <1>;
+					bias-disable;
+				};
+
+				data-pins {
+					pins = "gpio1", "gpio2", "gpio14";
+					function = "swr_tx_data";
+					drive-strength = <2>;
+					slew-rate = <1>;
+					bias-bus-hold;
+				};
+			};
 		};
 
 		gpu: gpu@3d00000 {

-- 
2.53.0

Re: [PATCH 6/7] arm64: dts: qcom: sm8350: Add SoundWire and LPASS

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] arm64: dts: qcom: sm8350: wrong PDC wakeup interrupt on swr2 node
--

commit e0bc0fd5876d3b09082c8770bf88a52e98e61a79
Author: Demeter Barna <me@fromdisposition.org>

arm64: dts: qcom: sm8350: Add SoundWire and LPASS

This commit adds the LPASS RX, TX, and VA macro nodes, the RX and TX
SoundWire controller nodes along with the LPASS audio clock controller,
and the LPI pin configuration states for SoundWire and DMICs on SM8350.

> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index 55b32050ce9c8..85476a04ea3fd 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
[ ... ]
> @@ -2022,6 +2023,133 @@ compute-cb@5 {
[ ... ]
> +		swr2: soundwire@3230000 {
> +			compatible = "qcom,soundwire-v1.6.0";
> +			reg = <0 0x03230000 0 0x2000>;
> +			interrupts-extended = <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
> +					      <&pdc 130 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "core", "wakeup";

[Severity: Medium]
Should the wakeup interrupt on swr2 use PDC pin 70 instead of 130 on
SM8350?

When swr2 enters runtime suspend via swrm_runtime_suspend() in
drivers/soundwire/qcom.c, it stops the bus clock and enables
ctrl->wake_irq so that a peripheral pulling TX data lane 0
(WCD_SWR_TX_DATA0, LPI gpio1 / TLMM gpio169 on SM8350) high can wake the
controller.

In drivers/pinctrl/qcom/pinctrl-sm8350.c, sm8350_pdc_map routes TLMM
gpio169 to PDC pin 70 (which pdc maps to GIC_SPI 520 via
qcom,pdc-ranges), whereas PDC pin 130 is the SC7280 mapping and is not
mapped to any GPIO on SM8350:

drivers/pinctrl/qcom/pinctrl-sm8350.c:sm8350_pdc_map[] = {
	...
	{ 169, 70 }, { 172, 132 }, { 174, 87 }, { 175, 88 }, { 177, 89 },
	...
};

With <&pdc 130 IRQ_TYPE_LEVEL_HIGH>, peripheral wakeup events on the TX
SoundWire bus will not fire during runtime suspend.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261104-b4-sm8350-sound-v1-0-4c872df294fa@fromdisposition.org?part=6

[PATCH 7/7] ASoC: dt-bindings: qcom,sm8250: Add SM8350 sound card

[Demeter Barna via B4 Relay]

From: Demeter Barna <me@fromdisposition.org>

The SM8350 sound card is the SM8250 one: the same DSP services (APR with
q6afe, q6asm, q6adm), LPASS codec macros and back ends, handled by the
sm8250 machine driver. Add its compatible with the SM8250 one as a
fallback.

Signed-off-by: Demeter Barna <me@fromdisposition.org>
---
 Documentation/devicetree/bindings/sound/qcom,sm8250.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
index e2e3fc99e..ccf553f38 100644
--- a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
+++ b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
@@ -21,6 +21,9 @@ properties:
               - lenovo,yoga-c630-sndcard
               - qcom,db845c-sndcard
           - const: qcom,sdm845-sndcard
+      - items:
+          - const: qcom,sm8350-sndcard
+          - const: qcom,sm8250-sndcard
       - items:
           - enum:
               - qcom,eliza-sndcard

-- 
2.53.0