From: <shiju.jose@huawei.com>
To: <linux-edac@vger.kernel.org>, <linux-cxl@vger.kernel.org>,
<mchehab@kernel.org>, <dave.jiang@intel.com>,
<dan.j.williams@intel.com>, <jonathan.cameron@huawei.com>,
<alison.schofield@intel.com>, <nifan.cxl@gmail.com>,
<vishal.l.verma@intel.com>, <ira.weiny@intel.com>,
<dave@stgolabs.net>
Cc: <linux-kernel@vger.kernel.org>, <linuxarm@huawei.com>,
<tanxiaofei@huawei.com>, <prime.zeng@hisilicon.com>,
<shiju.jose@huawei.com>
Subject: [PATCH v2 10/14] rasdaemon: ras-mc-ctl: Fix logging of memory event type in CXL DRAM error table
Date: Fri, 10 Jan 2025 12:26:36 +0000 [thread overview]
Message-ID: <20250110122641.1668-11-shiju.jose@huawei.com> (raw)
In-Reply-To: <20250110122641.1668-1-shiju.jose@huawei.com>
From: Shiju Jose <shiju.jose@huawei.com>
CXL spec rev 3.0 section 8.2.9.2.1.2 defines the DRAM Event Record.
Fix decoding of memory event type in the CXL DRAM error table in RAS
SQLite database.
For e.g. if value is 0x1 it will be logged as an Invalid Address
(General Media Event Record - Memory Event Type) instead of Scrub Media
ECC Error (DRAM Event Record - Memory Event Type) and so on.
Fixes: c38c14afc5d7 ("rasdaemon: ras-mc-ctl: Add support for CXL DRAM trace events")
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
---
util/ras-mc-ctl.in | 22 +++++++++++++++++++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/util/ras-mc-ctl.in b/util/ras-mc-ctl.in
index c24941f..3f9bad0 100755
--- a/util/ras-mc-ctl.in
+++ b/util/ras-mc-ctl.in
@@ -1339,7 +1339,7 @@ sub get_cxl_descriptor_flags_text
return join (", ", @out);
}
-sub get_cxl_mem_event_type
+sub get_cxl_gmer_mem_event_type
{
my @types;
@@ -1354,6 +1354,22 @@ sub get_cxl_mem_event_type
return $types[$_[0]];
}
+sub get_cxl_der_mem_event_type
+{
+ my @types;
+
+ if ($_[0] < 0 || $_[0] > 3) {
+ return "unknown-type";
+ }
+
+ @types = ("Media ECC Error",
+ "Scrub Media ECC Error",
+ "Invalid Address",
+ "Data Path Error");
+
+ return $types[$_[0]];
+}
+
sub get_cxl_transaction_type
{
my @types;
@@ -1978,7 +1994,7 @@ sub errors
$out .= sprintf "dpa=0x%llx, ", $dpa if (defined $dpa && length $dpa);
$out .= sprintf "dpa_flags: %s, ", get_cxl_dpa_flags_text($dpa_flags) if (defined $dpa_flags && length $dpa_flags);
$out .= sprintf "descriptor_flags: %s, ", get_cxl_descriptor_flags_text($descriptor) if (defined $descriptor && length $descriptor);
- $out .= sprintf "memory event type: %s, ", get_cxl_mem_event_type($mem_event_type) if (defined $mem_event_type && length $mem_event_type);
+ $out .= sprintf "memory event type: %s, ", get_cxl_gmer_mem_event_type($mem_event_type) if (defined $mem_event_type && length $mem_event_type);
$out .= sprintf "transaction_type: %s, ", get_cxl_transaction_type($transaction_type) if (defined $transaction_type && length $transaction_type);
$out .= sprintf "channel=%u, ", $channel if (defined $channel && length $channel);
$out .= sprintf "rank=%u, ", $rank if (defined $rank && length $rank);
@@ -2024,7 +2040,7 @@ sub errors
$out .= sprintf "dpa=0x%llx, ", $dpa if (defined $dpa && length $dpa);
$out .= sprintf "dpa_flags: %s, ", get_cxl_dpa_flags_text($dpa_flags) if (defined $dpa_flags && length $dpa_flags);
$out .= sprintf "descriptor_flags: %s, ", get_cxl_descriptor_flags_text($descriptor) if (defined $descriptor && length $descriptor);
- $out .= sprintf "memory event type: %s, ", get_cxl_mem_event_type($type) if (defined $type && length $type);
+ $out .= sprintf "memory event type: %s, ", get_cxl_der_mem_event_type($type) if (defined $type && length $type);
$out .= sprintf "transaction_type: %s, ", get_cxl_transaction_type($transaction_type) if (defined $transaction_type && length $transaction_type);
$out .= sprintf "channel=%u, ", $channel if (defined $channel && length $channel);
$out .= sprintf "rank=%u, ", $rank if (defined $rank && length $rank);
--
2.43.0
next prev parent reply other threads:[~2025-01-10 12:27 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-10 12:26 [PATCH v2 00/14] rasdaemon: cxl: Update CXL event logging and recording to CXL spec rev 3.1 shiju.jose
2025-01-10 12:26 ` [PATCH v2 01/14] rasdaemon: Fix for parsing error when trace event's format file is larger than PAGE_SIZE shiju.jose
2025-01-10 16:02 ` Jonathan Cameron
2025-01-10 16:11 ` Shiju Jose
2025-01-10 12:26 ` [PATCH v2 02/14] rasdaemon: cxl: Fix logging of memory event type of DRAM trace event shiju.jose
2025-01-10 12:26 ` [PATCH v2 03/14] rasdaemon: cxl: Fix mismatch in region field's name with kernel " shiju.jose
2025-01-10 12:26 ` [PATCH v2 04/14] rasdaemon: cxl: Add automatic indexing for storing CXL fields in SQLite database shiju.jose
2025-01-10 12:26 ` [PATCH v2 05/14] rasdaemon: cxl: Update common event to CXL spec rev 3.1 shiju.jose
2025-01-10 12:26 ` [PATCH v2 06/14] rasdaemon: cxl: Add Component Identifier formatting for " shiju.jose
2025-01-10 12:26 ` [PATCH v2 07/14] rasdaemon: cxl: Update CXL general media event to " shiju.jose
2025-01-10 12:26 ` [PATCH v2 08/14] rasdaemon: cxl: Update CXL DRAM " shiju.jose
2025-01-10 12:26 ` [PATCH v2 09/14] rasdaemon: cxl: Update memory module " shiju.jose
2025-01-10 12:26 ` shiju.jose [this message]
2025-01-10 12:26 ` [PATCH v2 11/14] rasdaemon: ras-mc-ctl: Update logging of common event data to align with " shiju.jose
2025-01-10 12:26 ` [PATCH v2 12/14] rasdaemon: ras-mc-ctl: Update logging of CXL general media " shiju.jose
2025-01-10 12:26 ` [PATCH v2 13/14] rasdaemon: ras-mc-ctl: Update logging of CXL DRAM " shiju.jose
2025-01-10 12:26 ` [PATCH v2 14/14] rasdaemon: ras-mc-ctl: Update logging of CXL memory module " shiju.jose
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