From: <shiju.jose@huawei.com>
To: <linux-edac@vger.kernel.org>, <linux-cxl@vger.kernel.org>,
<mchehab@kernel.org>, <dave.jiang@intel.com>,
<dan.j.williams@intel.com>, <jonathan.cameron@huawei.com>,
<alison.schofield@intel.com>, <nifan.cxl@gmail.com>,
<vishal.l.verma@intel.com>, <ira.weiny@intel.com>,
<dave@stgolabs.net>
Cc: <linux-kernel@vger.kernel.org>, <linuxarm@huawei.com>,
<tanxiaofei@huawei.com>, <prime.zeng@hisilicon.com>,
<shiju.jose@huawei.com>
Subject: [PATCH v2 06/14] rasdaemon: cxl: Add Component Identifier formatting for CXL spec rev 3.1
Date: Fri, 10 Jan 2025 12:26:32 +0000 [thread overview]
Message-ID: <20250110122641.1668-7-shiju.jose@huawei.com> (raw)
In-Reply-To: <20250110122641.1668-1-shiju.jose@huawei.com>
From: Shiju Jose <shiju.jose@huawei.com>
Add Component Identifier formatting for CXL spec rev 3.1, Section
8.2.9.2.1, Table 8-44.
Add helper function to print component ID, parse and log PLDM entity ID
and resource ID.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
---
ras-cxl-handler.c | 41 +++++++++++++++++++++++++++++++++++++++++
ras-record.h | 3 +++
2 files changed, 44 insertions(+)
diff --git a/ras-cxl-handler.c b/ras-cxl-handler.c
index d16eaef..80afa9f 100644
--- a/ras-cxl-handler.c
+++ b/ras-cxl-handler.c
@@ -573,6 +573,47 @@ int ras_cxl_overflow_event_handler(struct trace_seq *s,
return 0;
}
+/*
+ * Component ID Format
+ * CXL 3.1 section 8.2.9.2.1; Table 8-44
+ */
+#define CXL_PLDM_COMPONENT_ID_ENTITY_VALID BIT(0)
+#define CXL_PLDM_COMPONENT_ID_RES_VALID BIT(1)
+static const struct cxl_event_flags cxl_pldm_comp_id_flags[] = {
+ { .bit = CXL_PLDM_COMPONENT_ID_ENTITY_VALID, .flag = "PLDM Entity ID" },
+ { .bit = CXL_PLDM_COMPONENT_ID_RES_VALID, .flag = "Resource ID" },
+};
+
+static int ras_cxl_print_component_id(struct trace_seq *s, uint8_t *comp_id,
+ uint8_t *entity_id, uint8_t *res_id)
+{
+ int i;
+
+ if (comp_id[0] & CXL_PLDM_COMPONENT_ID_ENTITY_VALID) {
+ if (trace_seq_printf(s, "PLDM Entity ID:") <= 0)
+ return -1;
+ for (i = 1; i < 7; i++) {
+ if (trace_seq_printf(s, "%02x ", comp_id[i]) <= 0)
+ return -1;
+ }
+ if (entity_id)
+ memcpy(entity_id, &comp_id[1], CXL_PLDM_ENTITY_ID_LEN);
+ }
+
+ if (comp_id[0] & CXL_PLDM_COMPONENT_ID_RES_VALID) {
+ if (trace_seq_printf(s, "Resource ID:") <= 0)
+ return -1;
+ for (i = 7; i < 11; i++) {
+ if (trace_seq_printf(s, "%02x ", comp_id[i]) <= 0)
+ return -1;
+ }
+ if (res_id)
+ memcpy(res_id, &comp_id[7], CXL_PLDM_RES_ID_LEN);
+ }
+
+ return 0;
+}
+
/*
* Common Event Record Format
* CXL 3.1 section 8.2.9.2.1; Table 8-43
diff --git a/ras-record.h b/ras-record.h
index 2a0124a..a3a88eb 100644
--- a/ras-record.h
+++ b/ras-record.h
@@ -137,6 +137,9 @@ struct ras_cxl_poison_event {
#define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10
#define CXL_EVENT_DER_CORRECTION_MASK_SIZE 0x20
+#define CXL_PLDM_ENTITY_ID_LEN 6
+#define CXL_PLDM_RES_ID_LEN 4
+
struct ras_cxl_aer_ue_event {
char timestamp[64];
const char *memdev;
--
2.43.0
next prev parent reply other threads:[~2025-01-10 12:27 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-10 12:26 [PATCH v2 00/14] rasdaemon: cxl: Update CXL event logging and recording to CXL spec rev 3.1 shiju.jose
2025-01-10 12:26 ` [PATCH v2 01/14] rasdaemon: Fix for parsing error when trace event's format file is larger than PAGE_SIZE shiju.jose
2025-01-10 16:02 ` Jonathan Cameron
2025-01-10 16:11 ` Shiju Jose
2025-01-10 12:26 ` [PATCH v2 02/14] rasdaemon: cxl: Fix logging of memory event type of DRAM trace event shiju.jose
2025-01-10 12:26 ` [PATCH v2 03/14] rasdaemon: cxl: Fix mismatch in region field's name with kernel " shiju.jose
2025-01-10 12:26 ` [PATCH v2 04/14] rasdaemon: cxl: Add automatic indexing for storing CXL fields in SQLite database shiju.jose
2025-01-10 12:26 ` [PATCH v2 05/14] rasdaemon: cxl: Update common event to CXL spec rev 3.1 shiju.jose
2025-01-10 12:26 ` shiju.jose [this message]
2025-01-10 12:26 ` [PATCH v2 07/14] rasdaemon: cxl: Update CXL general media " shiju.jose
2025-01-10 12:26 ` [PATCH v2 08/14] rasdaemon: cxl: Update CXL DRAM " shiju.jose
2025-01-10 12:26 ` [PATCH v2 09/14] rasdaemon: cxl: Update memory module " shiju.jose
2025-01-10 12:26 ` [PATCH v2 10/14] rasdaemon: ras-mc-ctl: Fix logging of memory event type in CXL DRAM error table shiju.jose
2025-01-10 12:26 ` [PATCH v2 11/14] rasdaemon: ras-mc-ctl: Update logging of common event data to align with CXL spec rev 3.1 shiju.jose
2025-01-10 12:26 ` [PATCH v2 12/14] rasdaemon: ras-mc-ctl: Update logging of CXL general media " shiju.jose
2025-01-10 12:26 ` [PATCH v2 13/14] rasdaemon: ras-mc-ctl: Update logging of CXL DRAM " shiju.jose
2025-01-10 12:26 ` [PATCH v2 14/14] rasdaemon: ras-mc-ctl: Update logging of CXL memory module " shiju.jose
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