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From: <shiju.jose@huawei.com>
To: <linux-edac@vger.kernel.org>, <linux-cxl@vger.kernel.org>,
	<mchehab@kernel.org>, <dave.jiang@intel.com>,
	<dan.j.williams@intel.com>, <jonathan.cameron@huawei.com>,
	<alison.schofield@intel.com>, <nifan.cxl@gmail.com>,
	<vishal.l.verma@intel.com>, <ira.weiny@intel.com>,
	<dave@stgolabs.net>
Cc: <linux-kernel@vger.kernel.org>, <linuxarm@huawei.com>,
	<tanxiaofei@huawei.com>, <prime.zeng@hisilicon.com>,
	<shiju.jose@huawei.com>
Subject: [PATCH v2 05/14] rasdaemon: cxl: Update common event to CXL spec rev 3.1
Date: Fri, 10 Jan 2025 12:26:31 +0000	[thread overview]
Message-ID: <20250110122641.1668-6-shiju.jose@huawei.com> (raw)
In-Reply-To: <20250110122641.1668-1-shiju.jose@huawei.com>

From: Shiju Jose <shiju.jose@huawei.com>

CXL spec 3.1 section 8.2.9.2.1 Table 8-42, Common Event Record format has
updated with Maintenance Operation Subclass information.

Add updates in rasdaemon CXL event handler for the above spec change
and for the corresponding changes in kernel CXL common trace event
implementation.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
---
 ras-cxl-handler.c | 10 +++++++++-
 ras-record.c      |  5 +++++
 ras-record.h      |  1 +
 ras-report.c      |  6 ++++--
 4 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/ras-cxl-handler.c b/ras-cxl-handler.c
index 7d4fc9f..d16eaef 100644
--- a/ras-cxl-handler.c
+++ b/ras-cxl-handler.c
@@ -575,18 +575,20 @@ int ras_cxl_overflow_event_handler(struct trace_seq *s,
 
 /*
  * Common Event Record Format
- * CXL 3.0 section 8.2.9.2.1; Table 8-42
+ * CXL 3.1 section 8.2.9.2.1; Table 8-43
  */
 #define CXL_EVENT_RECORD_FLAG_PERMANENT		BIT(2)
 #define CXL_EVENT_RECORD_FLAG_MAINT_NEEDED	BIT(3)
 #define CXL_EVENT_RECORD_FLAG_PERF_DEGRADED	BIT(4)
 #define CXL_EVENT_RECORD_FLAG_HW_REPLACE	BIT(5)
+#define CXL_EVENT_RECORD_FLAG_MAINT_OP_SUB_CLASS_VALID	BIT(6)
 
 static const struct  cxl_event_flags cxl_hdr_flags[] = {
 	{ .bit = CXL_EVENT_RECORD_FLAG_PERMANENT, .flag = "PERMANENT_CONDITION" },
 	{ .bit = CXL_EVENT_RECORD_FLAG_MAINT_NEEDED, .flag = "MAINTENANCE_NEEDED" },
 	{ .bit = CXL_EVENT_RECORD_FLAG_PERF_DEGRADED, .flag = "PERFORMANCE_DEGRADED" },
 	{ .bit = CXL_EVENT_RECORD_FLAG_HW_REPLACE, .flag = "HARDWARE_REPLACEMENT_NEEDED" },
+	{ .bit = CXL_EVENT_RECORD_FLAG_MAINT_OP_SUB_CLASS_VALID, .flag = "MAINT_OP_SUB_CLASS_VALID" },
 };
 
 static int handle_ras_cxl_common_hdr(struct trace_seq *s,
@@ -670,6 +672,12 @@ static int handle_ras_cxl_common_hdr(struct trace_seq *s,
 	if (trace_seq_printf(s, "hdr_maint_op_class:%u ", hdr->hdr_maint_op_class) <= 0)
 		return -1;
 
+	if (tep_get_field_val(s,  event, "hdr_maint_op_sub_class", record, &val, 1) < 0)
+		return -1;
+	hdr->hdr_maint_op_sub_class = val;
+	if (trace_seq_printf(s, "hdr_maint_op_sub_class:%u ", hdr->hdr_maint_op_sub_class) <= 0)
+		return -1;
+
 	return 0;
 }
 
diff --git a/ras-record.c b/ras-record.c
index 3d95f97..f680ebe 100644
--- a/ras-record.c
+++ b/ras-record.c
@@ -797,6 +797,7 @@ static int ras_store_cxl_common_hdr(sqlite3_stmt *stmt, struct ras_cxl_event_com
 	sqlite3_bind_text(stmt, idx++, hdr->hdr_timestamp, -1, NULL);
 	sqlite3_bind_int(stmt, idx++, hdr->hdr_length);
 	sqlite3_bind_int(stmt, idx++, hdr->hdr_maint_op_class);
+	sqlite3_bind_int(stmt, idx++, hdr->hdr_maint_op_sub_class);
 
 	return idx;
 }
@@ -818,6 +819,7 @@ static const struct db_fields cxl_generic_event_fields[] = {
 	{ .name = "hdr_ts",		.type = "TEXT" },
 	{ .name = "hdr_length",		.type = "INTEGER" },
 	{ .name = "hdr_maint_op_class",	.type = "INTEGER" },
+	{ .name = "hdr_maint_op_sub_class",	.type = "INTEGER" },
 	{ .name = "data",		.type = "BLOB" },
 };
 
@@ -874,6 +876,7 @@ static const struct db_fields cxl_general_media_event_fields[] = {
 	{ .name = "hdr_ts",		.type = "TEXT" },
 	{ .name = "hdr_length",		.type = "INTEGER" },
 	{ .name = "hdr_maint_op_class",	.type = "INTEGER" },
+	{ .name = "hdr_maint_op_sub_class",	.type = "INTEGER" },
 	{ .name = "dpa",		.type = "INTEGER" },
 	{ .name = "dpa_flags",		.type = "INTEGER" },
 	{ .name = "descriptor",		.type = "INTEGER" },
@@ -953,6 +956,7 @@ static const struct db_fields cxl_dram_event_fields[] = {
 	{ .name = "hdr_ts",		.type = "TEXT" },
 	{ .name = "hdr_length",		.type = "INTEGER" },
 	{ .name = "hdr_maint_op_class",	.type = "INTEGER" },
+	{ .name = "hdr_maint_op_sub_class",	.type = "INTEGER" },
 	{ .name = "dpa",		.type = "INTEGER" },
 	{ .name = "dpa_flags",		.type = "INTEGER" },
 	{ .name = "descriptor",		.type = "INTEGER" },
@@ -1039,6 +1043,7 @@ static const struct db_fields cxl_memory_module_event_fields[] = {
 	{ .name = "hdr_ts",		.type = "TEXT" },
 	{ .name = "hdr_length",		.type = "INTEGER" },
 	{ .name = "hdr_maint_op_class",	.type = "INTEGER" },
+	{ .name = "hdr_maint_op_sub_class",	.type = "INTEGER" },
 	{ .name = "event_type",		.type = "INTEGER" },
 	{ .name = "health_status",	.type = "INTEGER" },
 	{ .name = "media_status",	.type = "INTEGER" },
diff --git a/ras-record.h b/ras-record.h
index cd549a1..2a0124a 100644
--- a/ras-record.h
+++ b/ras-record.h
@@ -179,6 +179,7 @@ struct ras_cxl_event_common_hdr {
 	char hdr_timestamp[64];
 	uint8_t hdr_length;
 	uint8_t hdr_maint_op_class;
+	uint8_t hdr_maint_op_sub_class;
 };
 
 struct ras_cxl_generic_event {
diff --git a/ras-report.c b/ras-report.c
index bc77d04..7e974b9 100644
--- a/ras-report.c
+++ b/ras-report.c
@@ -507,7 +507,8 @@ static int set_cxl_generic_event_backtrace(char *buf, struct ras_cxl_generic_eve
 		"hdr_related_handle=0x%x\n"
 		"hdr_timestamp=%s\n"
 		"hdr_length=%u\n"
-		"hdr_maint_op_class=%u\n",
+		"hdr_maint_op_class=%u\n"
+		"hdr_maint_op_sub_class=%u\n",
 		ev->hdr.timestamp,
 		ev->hdr.memdev,
 		ev->hdr.host,
@@ -519,7 +520,8 @@ static int set_cxl_generic_event_backtrace(char *buf, struct ras_cxl_generic_eve
 		ev->hdr.hdr_related_handle,
 		ev->hdr.hdr_timestamp,
 		ev->hdr.hdr_length,
-		ev->hdr.hdr_maint_op_class);
+		ev->hdr.hdr_maint_op_class,
+		ev->hdr.hdr_maint_op_sub_class);
 
 	return 0;
 }
-- 
2.43.0


  parent reply	other threads:[~2025-01-10 12:27 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-10 12:26 [PATCH v2 00/14] rasdaemon: cxl: Update CXL event logging and recording to CXL spec rev 3.1 shiju.jose
2025-01-10 12:26 ` [PATCH v2 01/14] rasdaemon: Fix for parsing error when trace event's format file is larger than PAGE_SIZE shiju.jose
2025-01-10 16:02   ` Jonathan Cameron
2025-01-10 16:11     ` Shiju Jose
2025-01-10 12:26 ` [PATCH v2 02/14] rasdaemon: cxl: Fix logging of memory event type of DRAM trace event shiju.jose
2025-01-10 12:26 ` [PATCH v2 03/14] rasdaemon: cxl: Fix mismatch in region field's name with kernel " shiju.jose
2025-01-10 12:26 ` [PATCH v2 04/14] rasdaemon: cxl: Add automatic indexing for storing CXL fields in SQLite database shiju.jose
2025-01-10 12:26 ` shiju.jose [this message]
2025-01-10 12:26 ` [PATCH v2 06/14] rasdaemon: cxl: Add Component Identifier formatting for CXL spec rev 3.1 shiju.jose
2025-01-10 12:26 ` [PATCH v2 07/14] rasdaemon: cxl: Update CXL general media event to " shiju.jose
2025-01-10 12:26 ` [PATCH v2 08/14] rasdaemon: cxl: Update CXL DRAM " shiju.jose
2025-01-10 12:26 ` [PATCH v2 09/14] rasdaemon: cxl: Update memory module " shiju.jose
2025-01-10 12:26 ` [PATCH v2 10/14] rasdaemon: ras-mc-ctl: Fix logging of memory event type in CXL DRAM error table shiju.jose
2025-01-10 12:26 ` [PATCH v2 11/14] rasdaemon: ras-mc-ctl: Update logging of common event data to align with CXL spec rev 3.1 shiju.jose
2025-01-10 12:26 ` [PATCH v2 12/14] rasdaemon: ras-mc-ctl: Update logging of CXL general media " shiju.jose
2025-01-10 12:26 ` [PATCH v2 13/14] rasdaemon: ras-mc-ctl: Update logging of CXL DRAM " shiju.jose
2025-01-10 12:26 ` [PATCH v2 14/14] rasdaemon: ras-mc-ctl: Update logging of CXL memory module " shiju.jose

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