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From: Yazen Ghannam <yazen.ghannam@amd.com>
To: Borislav Petkov <bp@alien8.de>
Cc: x86@kernel.org, Tony Luck <tony.luck@intel.com>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	Len Brown <lenb@kernel.org>,
	linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org,
	Smita.KoralahalliChannabasappa@amd.com,
	Qiuxu Zhuo <qiuxu.zhuo@intel.com>,
	Nikolay Borisov <nik.borisov@suse.com>,
	Bert Karwatzki <spasswolf@web.de>,
	linux-acpi@vger.kernel.org
Subject: Re: [PATCH v7 2/8] x86/mce: Unify AMD DFR handler with MCA Polling
Date: Mon, 27 Oct 2025 10:11:39 -0400	[thread overview]
Message-ID: <20251027141139.GA51741@yaz-khff2.amd.com> (raw)
In-Reply-To: <20251027133542.GA8279@yaz-khff2.amd.com>

On Mon, Oct 27, 2025 at 09:35:42AM -0400, Yazen Ghannam wrote:
> On Sat, Oct 25, 2025 at 05:03:04PM +0200, Borislav Petkov wrote:
> > On Fri, Oct 24, 2025 at 11:27:23PM +0200, Borislav Petkov wrote:
> > > On Fri, Oct 24, 2025 at 04:30:12PM -0400, Yazen Ghannam wrote:
> > > > Should I send another revision?
> > > 
> > > Nah, I'm not done simplifying this yet. :-P
> > 
> > Yeah, no, looks ok now:
> > 

Here's another fixup. I also simplified the function parameters and
tweaked the code comments.

Thanks,
Yazen

---
 arch/x86/kernel/cpu/mce/core.c | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 7be062429ce3..eaee48b8b339 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -726,21 +726,18 @@ DEFINE_PER_CPU(unsigned, mce_poll_count);
  * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and
  *    log it.
  */
-static bool smca_should_log_poll_error(enum mcp_flags flags, struct mce_hw_err *err)
+static bool smca_should_log_poll_error(struct mce *m)
 {
-	struct mce *m = &err->m;
-
 	/*
-	 * If the MCA_STATUS register has a deferred error, then continue using it as
-	 * the status register.
-	 *
-	 * MCA_DESTAT will be cleared at the end of the handler.
+	 * If MCA_STATUS happens to have a deferred error, then MCA_DESTAT will
+	 * be cleared at the end of the handler.
 	 */
-	if ((m->status & MCI_STATUS_VAL) && (m->status & MCI_STATUS_DEFERRED))
+	if (m->status & MCI_STATUS_VAL)
 		return true;
 
 	/*
-	 * If the MCA_DESTAT register has a deferred error, then use it instead.
+	 * Use the MCA_DESTAT register if it has a deferred error. The redundant
+	 * status bit check is to filter out any bogus errors.
 	 *
 	 * MCA_STATUS will not be cleared at the end of the handler.
 	 */
@@ -780,7 +777,7 @@ static bool should_log_poll_error(enum mcp_flags flags, struct mce_hw_err *err)
 	struct mce *m = &err->m;
 
 	if (mce_flags.smca)
-		return smca_should_log_poll_error(flags, err);
+		return smca_should_log_poll_error(m);
 
 	/* If this entry is not valid, ignore it. */
 	if (!(m->status & MCI_STATUS_VAL))
-- 
2.51.1


  reply	other threads:[~2025-10-27 14:11 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-16 16:37 [PATCH v7 0/8] AMD MCA interrupts rework Yazen Ghannam
2025-10-16 16:37 ` [PATCH v7 1/8] x86/mce: Unify AMD THR handler with MCA Polling Yazen Ghannam
2025-10-16 16:37 ` [PATCH v7 2/8] x86/mce: Unify AMD DFR " Yazen Ghannam
2025-10-24 15:03   ` Borislav Petkov
2025-10-24 20:30     ` Yazen Ghannam
2025-10-24 21:27       ` Borislav Petkov
2025-10-25 15:03         ` Borislav Petkov
2025-10-27 13:35           ` Yazen Ghannam
2025-10-27 14:11             ` Yazen Ghannam [this message]
2025-10-28 15:22               ` Borislav Petkov
2025-10-28 15:42                 ` Yazen Ghannam
2025-10-28 17:46                   ` Borislav Petkov
2025-10-28 20:37                     ` Yazen Ghannam
2025-10-28 23:18                       ` Borislav Petkov
2025-10-29 15:09                         ` Yazen Ghannam
2025-10-29 16:02                           ` Borislav Petkov
2025-10-16 16:37 ` [PATCH v7 3/8] x86/mce/amd: Enable interrupt vectors once per-CPU on SMCA systems Yazen Ghannam
2025-10-16 16:37 ` [PATCH v7 4/8] x86/mce/amd: Support SMCA Corrected Error Interrupt Yazen Ghannam
2025-10-16 16:37 ` [PATCH v7 5/8] x86/mce/amd: Remove redundant reset_block() Yazen Ghannam
2025-10-16 16:37 ` [PATCH v7 6/8] x86/mce/amd: Define threshold restart function for banks Yazen Ghannam
2025-10-16 16:37 ` [PATCH v7 7/8] x86/mce: Handle AMD threshold interrupt storms Yazen Ghannam
2025-10-16 16:37 ` [PATCH v7 8/8] x86/mce: Save and use APEI corrected threshold limit Yazen Ghannam
2025-11-02 12:32   ` Borislav Petkov

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