Re: [PATCH v7 2/8] x86/mce: Unify AMD DFR handler with MCA Polling

[Yazen Ghannam <yazen.ghannam@amd.com>]

On Tue, Oct 28, 2025 at 04:22:31PM +0100, Borislav Petkov wrote:
> On Mon, Oct 27, 2025 at 10:11:39AM -0400, Yazen Ghannam wrote:
> >  	/*
> > -	 * If the MCA_STATUS register has a deferred error, then continue using it as
> > -	 * the status register.
> > -	 *
> > -	 * MCA_DESTAT will be cleared at the end of the handler.
> > +	 * If MCA_STATUS happens to have a deferred error, then MCA_DESTAT will
> > +	 * be cleared at the end of the handler.
> >  	 */
> > -	if ((m->status & MCI_STATUS_VAL) && (m->status & MCI_STATUS_DEFERRED))
> > +	if (m->status & MCI_STATUS_VAL)
> >  		return true;
> 
> I'm still confused by those comments - we check VAL but we talk about
> deferred...

Yes, fair point. How about this?

	/*
	 * If MCA_STATUS has a valid error of any type, then use it.
	 *
	 * If the error happens to be a deferred error, then the copy
	 * saved in MCA_DESTAT will be cleared at the end of the
	 * handler.
	 *
	 * If MCA_STATUS does not have a valid error, then check
	 * MCA_DESTAT for a valid deferred error.
	 */
> 
> >  
> >  	/*
> > -	 * If the MCA_DESTAT register has a deferred error, then use it instead.
> > +	 * Use the MCA_DESTAT register if it has a deferred error.
> 
> This one...
> 
> > The redundant
> > +	 * status bit check is to filter out any bogus errors.
> 
> ... probably only confuses. No need to mention it.
> 

Okay, agreed. I think this entire second comment can be removed.

Thanks,
Yazen