From: Mario Limonciello <mario.limonciello@amd.com>
To: <linux-firmware@kernel.org>, Josh Boyer <jwboyer@kernel.org>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Subject: [PATCH 09/20] cxgb4: correct typographical errors caught by codespell
Date: Tue, 15 Aug 2023 13:00:07 -0500 [thread overview]
Message-ID: <20230815180018.25554-10-mario.limonciello@amd.com> (raw)
In-Reply-To: <20230815180018.25554-1-mario.limonciello@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
cxgb4/configs/t4-config-default.txt | 6 +++---
cxgb4/configs/t5-config-default.txt | 6 +++---
cxgb4/configs/t5-config-hashfilter.txt | 6 +++---
cxgb4/configs/t6-config-default.txt | 6 +++---
cxgb4/configs/t6-config-hashfilter.txt | 8 ++++----
5 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/cxgb4/configs/t4-config-default.txt b/cxgb4/configs/t4-config-default.txt
index 1774b4d9..b758fc5e 100644
--- a/cxgb4/configs/t4-config-default.txt
+++ b/cxgb4/configs/t4-config-default.txt
@@ -17,7 +17,7 @@
# finite. This requires balancing the configuration/operation needs of
# device drivers across OSes and a large number of customer application.
#
-# Some of the more important resources to allocate and their constaints are:
+# Some of the more important resources to allocate and their constraints are:
# 1. Virtual Interfaces: 128.
# 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions
# must use a power of 2 Ingress Queues.
@@ -275,7 +275,7 @@
# to directly select the type of Physical Function to which they wish to be
# attached.
#
-# Note that the actual values used for the PCI-E Intelectual Property will be
+# Note that the actual values used for the PCI-E Intellectual Property will be
# 1 less than those below since that's the way it "counts" things. For
# readability, we use the number we actually mean ...
#
@@ -491,7 +491,7 @@
# MPS features a 196608 bytes ingress buffer that is used for ingress buffering
# for packets from the wire as well as the loopback path of the L2 switch. The
-# folling params control how the buffer memory is distributed and the L2 flow
+# following params control how the buffer memory is distributed and the L2 flow
# control settings:
#
# bg_mem: %-age of mem to use for port/buffer group
diff --git a/cxgb4/configs/t5-config-default.txt b/cxgb4/configs/t5-config-default.txt
index 44fdfad7..352af3c0 100644
--- a/cxgb4/configs/t5-config-default.txt
+++ b/cxgb4/configs/t5-config-default.txt
@@ -18,7 +18,7 @@
# are finite. This requires balancing the configuration/operation needs of
# device drivers across OSes and a large number of customer application.
#
-# Some of the more important resources to allocate and their constaints are:
+# Some of the more important resources to allocate and their constraints are:
# 1. Virtual Interfaces: 256.
# 2. Ingress Queues with Free Lists: 1024.
# 3. Egress Queues: 128K.
@@ -310,7 +310,7 @@
# to directly select the type of Physical Function to which they wish to be
# attached.
#
-# Note that the actual values used for the PCI-E Intelectual Property will be
+# Note that the actual values used for the PCI-E Intellectual Property will be
# 1 less than those below since that's the way it "counts" things. For
# readability, we use the number we actually mean ...
#
@@ -540,7 +540,7 @@
# MPS features a 196608 bytes ingress buffer that is used for ingress buffering
# for packets from the wire as well as the loopback path of the L2 switch. The
-# folling params control how the buffer memory is distributed and the L2 flow
+# following params control how the buffer memory is distributed and the L2 flow
# control settings:
#
# bg_mem: %-age of mem to use for port/buffer group
diff --git a/cxgb4/configs/t5-config-hashfilter.txt b/cxgb4/configs/t5-config-hashfilter.txt
index e106f24b..38e8ef4b 100644
--- a/cxgb4/configs/t5-config-hashfilter.txt
+++ b/cxgb4/configs/t5-config-hashfilter.txt
@@ -18,7 +18,7 @@
# are finite. This requires balancing the configuration/operation needs of
# device drivers across OSes and a large number of customer application.
#
-# Some of the more important resources to allocate and their constaints are:
+# Some of the more important resources to allocate and their constraints are:
# 1. Virtual Interfaces: 256.
# 2. Ingress Queues with Free Lists: 1024.
# 3. Egress Queues: 128K.
@@ -316,7 +316,7 @@
# to directly select the type of Physical Function to which they wish to be
# attached.
#
-# Note that the actual values used for the PCI-E Intelectual Property will be
+# Note that the actual values used for the PCI-E Intellectual Property will be
# 1 less than those below since that's the way it "counts" things. For
# readability, we use the number we actually mean ...
#
@@ -408,7 +408,7 @@
# MPS features a 196608 bytes ingress buffer that is used for ingress buffering
# for packets from the wire as well as the loopback path of the L2 switch. The
-# folling params control how the buffer memory is distributed and the L2 flow
+# following params control how the buffer memory is distributed and the L2 flow
# control settings:
#
# bg_mem: %-age of mem to use for port/buffer group
diff --git a/cxgb4/configs/t6-config-default.txt b/cxgb4/configs/t6-config-default.txt
index b0145ab2..bc000316 100644
--- a/cxgb4/configs/t6-config-default.txt
+++ b/cxgb4/configs/t6-config-default.txt
@@ -18,7 +18,7 @@
# are finite. This requires balancing the configuration/operation needs of
# device drivers across OSes and a large number of customer application.
#
-# Some of the more important resources to allocate and their constaints are:
+# Some of the more important resources to allocate and their constraints are:
# 1. Virtual Interfaces: 256.
# 2. Ingress Queues with Free Lists: 1024.
# 3. Egress Queues: 128K.
@@ -327,7 +327,7 @@
# to directly select the type of Physical Function to which they wish to be
# attached.
#
-# Note that the actual values used for the PCI-E Intelectual Property will be
+# Note that the actual values used for the PCI-E Intellectual Property will be
# 1 less than those below since that's the way it "counts" things. For
# readability, we use the number we actually mean ...
#
@@ -556,7 +556,7 @@
# MPS features a 196608 bytes ingress buffer that is used for ingress buffering
# for packets from the wire as well as the loopback path of the L2 switch. The
-# folling params control how the buffer memory is distributed and the L2 flow
+# following params control how the buffer memory is distributed and the L2 flow
# control settings:
#
# bg_mem: %-age of mem to use for port/buffer group
diff --git a/cxgb4/configs/t6-config-hashfilter.txt b/cxgb4/configs/t6-config-hashfilter.txt
index f8c78210..921a30d2 100644
--- a/cxgb4/configs/t6-config-hashfilter.txt
+++ b/cxgb4/configs/t6-config-hashfilter.txt
@@ -18,7 +18,7 @@
# are finite. This requires balancing the configuration/operation needs of
# device drivers across OSes and a large number of customer application.
#
-# Some of the more important resources to allocate and their constaints are:
+# Some of the more important resources to allocate and their constraints are:
# 1. Virtual Interfaces: 256.
# 2. Ingress Queues with Free Lists: 1024.
# 3. Egress Queues: 128K.
@@ -167,7 +167,7 @@
# LE_DB_CONFIG
reg[0x19c04] = 0x00000000/0x02040000 # LE IPv4 compression disabled
- # EXTN_HASH_IPV4 Diable
+ # EXTN_HASH_IPV4 Disable
#LE_DB_RSP_CODE_0
reg[0x19c74] = 0x00000004/0x0000000f # TCAM_ACTV_HIT = 4
@@ -304,7 +304,7 @@
# to directly select the type of Physical Function to which they wish to be
# attached.
#
-# Note that the actual values used for the PCI-E Intelectual Property will be
+# Note that the actual values used for the PCI-E Intellectual Property will be
# 1 less than those below since that's the way it "counts" things. For
# readability, we use the number we actually mean ...
#
@@ -393,7 +393,7 @@
# MPS features a 196608 bytes ingress buffer that is used for ingress buffering
# for packets from the wire as well as the loopback path of the L2 switch. The
-# folling params control how the buffer memory is distributed and the L2 flow
+# following params control how the buffer memory is distributed and the L2 flow
# control settings:
#
# bg_mem: %-age of mem to use for port/buffer group
--
2.25.1
next prev parent reply other threads:[~2023-08-15 18:00 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-15 17:59 [PATCH 00/20] Add preparations to be able to run in a CI/CD system Mario Limonciello
2023-08-15 17:59 ` [PATCH 01/20] ath11k: update typographical errors in the Notice.txt files Mario Limonciello
2023-08-15 18:00 ` [PATCH 02/20] ath10k: correct " Mario Limonciello
2023-08-15 18:00 ` [PATCH 03/20] i915: correct typographical errors caught by codespell Mario Limonciello
2023-08-15 18:00 ` [PATCH 04/20] adsp_sst: " Mario Limonciello
2023-08-15 18:00 ` [PATCH 05/20] agere: correct typographical errors in LICENSE " Mario Limonciello
2023-08-15 18:00 ` [PATCH 06/20] qca: correct typographical errors in NOTICE.txt " Mario Limonciello
2023-08-15 18:00 ` [PATCH 07/20] usbdux: correct typographical errors " Mario Limonciello
2023-08-15 18:00 ` [PATCH 08/20] dsp56k: correct typographical error " Mario Limonciello
2023-08-15 18:00 ` Mario Limonciello [this message]
2023-08-15 18:00 ` [PATCH 10/20] cavium_liquidio: fix typographical errors " Mario Limonciello
2023-08-15 18:00 ` [PATCH 11/20] kaweth: correct " Mario Limonciello
2023-08-15 18:00 ` [PATCH 12/20] xc5000c: " Mario Limonciello
2023-08-15 18:00 ` [PATCH 13/20] qcom: " Mario Limonciello
2023-08-15 18:00 ` [PATCH 14/20] keyspan_pda: " Mario Limonciello
2023-08-15 18:00 ` [PATCH 15/20] carl9170fw: " Mario Limonciello
2023-08-15 18:00 ` [PATCH 16/20] WHENCE: " Mario Limonciello
2023-08-15 18:00 ` [PATCH 17/20] check_whence: reformat using python black Mario Limonciello
2023-08-15 18:00 ` [PATCH 18/20] Add CI/CD with ci-fairy Mario Limonciello
2023-08-15 18:00 ` [PATCH 19/20] Wire up pre-commit to `make check` Mario Limonciello
2023-08-15 18:00 ` [PATCH 20/20] Rewrite README in markdown Mario Limonciello
2023-08-25 17:22 ` [PATCH 00/20] Add preparations to be able to run in a CI/CD system Dmitry Baryshkov
2023-08-28 11:15 ` Josh Boyer
2023-08-30 15:51 ` Mario Limonciello
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