[PATCH v4 0/2] upboard pinctrl support for device id INTC1055

[PATCH v4 0/2] upboard pinctrl support for device id INTC1055

[Gary Wang]

Add missing groups and functions in Tigerlake's pinctrl driver for INTC1055.
Add support "UP Xtreme i12" board.

The pinctrl-upboard is provide additional driving power & pin mux function
through native SOC pins->FPGA/CPLD->hat pins for flexable board level
applications. it's probe from ACPI device id AANT0F01 & AANT0F04.

Signed-off-by: Gary Wang <is0124@gmail.com>
---
Changes in v4:
- Update commit author name.
- Fixes respective tags.
- Fixes the indentation and wrapping in commit message.
- Link to v3: https://lore.kernel.org/r/20260702-upboard-pinctrl-add-upboard-intc1055-support-v3-0-e6bda3032914@gmail.com

Changes in v3:
- Correction pwm & uart pin mode in INTC1055.
- Remove unsupport up boards.
- Update cover letter.
- Link to v2: https://lore.kernel.org/r/20260612-upboard-pinctrl-add-upboard-intc1055-support-v2-0-4111b256c840@gmail.com

Changes in v2:
- Add brief introduction pinctrl-upboard architecture in cover content.
- Add more detail explaining for pinctrl-tigerlake commit message.
- Link to v1: https://lore.kernel.org/r/20260610-upboard-pinctrl-add-upboard-intc1055-support-v1-0-8185d2abbfb1@gmail.com

---
Gary Wang (2):
      pinctrl: tigerlake: add some pin groups and functions for INTC1055
      pinctrl: upboard: add device id INTC1055 based UP boards support

 drivers/pinctrl/intel/pinctrl-tigerlake.c | 32 +++++++++++++++++++++++++++++++
 drivers/pinctrl/pinctrl-upboard.c         | 21 ++++++++++++++++++++
 2 files changed, 53 insertions(+)
---
base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482
change-id: 20260609-upboard-pinctrl-add-upboard-intc1055-support-bd1d81311b7a

Best regards,
-- 
Gary Wang <is0124@gmail.com>

[PATCH v4 1/2] pinctrl: tigerlake: add some pin groups and functions for INTC1055

[Gary Wang]

Add i2c0, i2c1, pwm0, uart1, ssp2 pin groups & functions in tgllp_soc_data
for device id INTC1055. The pinctrl-upboard driver set the correct pin
function corresponding to these data.

Signed-off-by: Gary Wang <is0124@gmail.com>
Acked-by: Linus Walleij <linusw@kernel.org>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
---
 drivers/pinctrl/intel/pinctrl-tigerlake.c | 32 +++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/drivers/pinctrl/intel/pinctrl-tigerlake.c b/drivers/pinctrl/intel/pinctrl-tigerlake.c
index ae231f7fba49..0a11b9dac3dd 100644
--- a/drivers/pinctrl/intel/pinctrl-tigerlake.c
+++ b/drivers/pinctrl/intel/pinctrl-tigerlake.c
@@ -330,6 +330,34 @@ static const struct pinctrl_pin_desc tgllp_pins[] = {
 	PINCTRL_PIN(276, "SPI0_CLK_LOOPBK"),
 };
 
+static const unsigned int tgllp_i2c0_pins[] = { 5, 6 };
+static const unsigned int tgllp_i2c1_pins[] = { 7, 8 };
+static const unsigned int tgllp_pwm0_pins[] = { 99 };
+static const unsigned int tgllp_uart1_pins[] = { 85, 86, 87, 88 };
+static const unsigned int tgllp_ssp2_pins[] = { 108, 109, 110, 111 };
+
+static const struct intel_pingroup tgllp_groups[] = {
+	PIN_GROUP("i2c0_grp", tgllp_i2c0_pins, 2),
+	PIN_GROUP("i2c1_grp", tgllp_i2c1_pins, 2),
+	PIN_GROUP("pwm0_grp", tgllp_pwm0_pins, 2),
+	PIN_GROUP("uart1_grp", tgllp_uart1_pins, 2),
+	PIN_GROUP("ssp2_grp", tgllp_ssp2_pins, 7),
+};
+
+static const char * const tgllp_i2c0_groups[] = { "i2c0_grp" };
+static const char * const tgllp_i2c1_groups[] = { "i2c1_grp" };
+static const char * const tgllp_pwm0_groups[] = { "pwm0_grp" };
+static const char * const tgllp_uart1_groups[] = { "uart1_grp" };
+static const char * const tgllp_ssp2_groups[] = { "ssp2_grp" };
+
+static const struct intel_function tgllp_functions[] = {
+	FUNCTION("i2c0", tgllp_i2c0_groups),
+	FUNCTION("i2c1", tgllp_i2c1_groups),
+	FUNCTION("pwm0", tgllp_pwm0_groups),
+	FUNCTION("uart1", tgllp_uart1_groups),
+	FUNCTION("ssp2", tgllp_ssp2_groups),
+};
+
 static const struct intel_padgroup tgllp_community0_gpps[] = {
 	INTEL_GPP(0, 0, 25, 0),				/* GPP_B */
 	INTEL_GPP(1, 26, 41, 32),			/* GPP_T */
@@ -367,6 +395,10 @@ static const struct intel_community tgllp_communities[] = {
 static const struct intel_pinctrl_soc_data tgllp_soc_data = {
 	.pins = tgllp_pins,
 	.npins = ARRAY_SIZE(tgllp_pins),
+	.groups = tgllp_groups,
+	.ngroups = ARRAY_SIZE(tgllp_groups),
+	.functions = tgllp_functions,
+	.nfunctions = ARRAY_SIZE(tgllp_functions),
 	.communities = tgllp_communities,
 	.ncommunities = ARRAY_SIZE(tgllp_communities),
 };

-- 
2.43.0

[PATCH v4 2/2] pinctrl: upboard: add device id INTC1055 based UP boards support

[Gary Wang]

Add support "UP Xtreme i12" and I2C/PWM/UART/SPI pins mapping data.

Signed-off-by: Gary Wang <is0124@gmail.com>
Reviewed-by: Thomas Richard <thomas.richard@bootlin.com>
Acked-by: Linus Walleij <linusw@kernel.org>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
---
 drivers/pinctrl/pinctrl-upboard.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-upboard.c b/drivers/pinctrl/pinctrl-upboard.c
index f8c8b9d84990..de1920a3387d 100644
--- a/drivers/pinctrl/pinctrl-upboard.c
+++ b/drivers/pinctrl/pinctrl-upboard.c
@@ -912,6 +912,19 @@ static const struct upboard_pinctrl_map upboard_pinctrl_map_apl01 = {
 	.nmaps = ARRAY_SIZE(pinctrl_map_apl01),
 };
 
+static const struct pinctrl_map pinctrl_map_adl[] = {
+	PIN_MAP_MUX_GROUP_DEFAULT("upboard-pinctrl", "INTC1055:00", "i2c0_grp", "i2c0"),
+	PIN_MAP_MUX_GROUP_DEFAULT("upboard-pinctrl", "INTC1055:00", "i2c1_grp", "i2c1"),
+	PIN_MAP_MUX_GROUP_DEFAULT("upboard-pinctrl", "INTC1055:00", "pwm0_grp", "pwm0"),
+	PIN_MAP_MUX_GROUP_DEFAULT("upboard-pinctrl", "INTC1055:00", "uart1_grp", "uart1"),
+	PIN_MAP_MUX_GROUP_DEFAULT("upboard-pinctrl", "INTC1055:00", "ssp2_grp", "ssp2"),
+};
+
+static const struct upboard_pinctrl_map upboard_pinctrl_map_adl = {
+	.maps = &pinctrl_map_adl[0],
+	.nmaps = ARRAY_SIZE(pinctrl_map_adl),
+};
+
 static const struct dmi_system_id dmi_platform_info[] = {
 	{
 		/* UP Squared */
@@ -921,6 +934,14 @@ static const struct dmi_system_id dmi_platform_info[] = {
 		},
 		.driver_data = (void *)&upboard_pinctrl_map_apl01,
 	},
+	{
+		/* UP Xtreme i12 */
+		.matches = {
+			DMI_EXACT_MATCH(DMI_SYS_VENDOR, "AAEON"),
+			DMI_EXACT_MATCH(DMI_BOARD_NAME, "UPX-ADLP01"),
+		},
+		.driver_data = (void *)&upboard_pinctrl_map_adl,
+	},
 	{ }
 };
 

-- 
2.43.0

Re: [PATCH v4 2/2] pinctrl: upboard: add device id INTC1055 based UP boards support

[Thomas Richard]

Hello Gary,

On 7/6/26 12:36 PM, Gary Wang wrote:
> Add support "UP Xtreme i12" and I2C/PWM/UART/SPI pins mapping data.

Driver probes successfully on UP Xtreme i12.

I tested the IOs:
- pwm0 does not work.
- uart1 partially works: TX is okay, but loopback doesn't work. Signal
is bad when I add a loopback. Looks like pinctrl misconfig on SoC side.
- i2c busses are okay.
- for SPI, MOSI and CLK are okay, but not CS.
- all GPIOs are okay.

Could you have a look please.

Best Regards,
Thomas

Re: [PATCH v4 2/2] pinctrl: upboard: add device id INTC1055 based UP boards support

[GaryWang]

On Tue, Jul 7, 2026 at 7:50 PM Thomas Richard
<thomas.richard@bootlin.com> wrote:
>
> Hello Gary,
>
> On 7/6/26 12:36 PM, Gary Wang wrote:
> > Add support "UP Xtreme i12" and I2C/PWM/UART/SPI pins mapping data.
>
> Driver probes successfully on UP Xtreme i12.
>
> I tested the IOs:
> - pwm0 does not work.
you have to use our pwm kernel module for pwm test, I'll provide later.
> - uart1 partially works: TX is okay, but loopback doesn't work. Signal
> is bad when I add a loopback. Looks like pinctrl misconfig on SoC side.
uart1 tested ok on our side, if you loop TX/RX do not forget to turn off
hardware flow control. and we have executed cmd as below to make sure
direction is set all right.
echo "uart1_grp uart1" >
/sys/kernel/debug/pinctrl/upboard-pinctrl/pinmux-select
> - i2c busses are okay.
> - for SPI, MOSI and CLK are okay, but not CS.
Do you have enabled spi in BIOS HAT configuration?
CS0 should be ok, it's SOC defined, CS1 is optional, users can activate low by
himself before read/write, actually all gpio can be manually used as CS pin.
> - all GPIOs are okay.
>
> Could you have a look please.
>
> Best Regards,
> Thomas
>

Re: [PATCH v4 2/2] pinctrl: upboard: add device id INTC1055 based UP boards support

[Thomas Richard]

Hello Gary,

On 7/7/26 5:55 PM, GaryWang wrote:
> On Tue, Jul 7, 2026 at 7:50 PM Thomas Richard
> <thomas.richard@bootlin.com> wrote:
>>
>> Hello Gary,
>>
>> On 7/6/26 12:36 PM, Gary Wang wrote:
>>> Add support "UP Xtreme i12" and I2C/PWM/UART/SPI pins mapping data.
>>
>> Driver probes successfully on UP Xtreme i12.
>>
>> I tested the IOs:
>> - pwm0 does not work.
> you have to use our pwm kernel module for pwm test, I'll provide later.

Ack

>> - uart1 partially works: TX is okay, but loopback doesn't work. Signal
>> is bad when I add a loopback. Looks like pinctrl misconfig on SoC side.
> uart1 tested ok on our side, if you loop TX/RX do not forget to turn off
> hardware flow control. and we have executed cmd as below to make sure
> direction is set all right.
> echo "uart1_grp uart1" >
> /sys/kernel/debug/pinctrl/upboard-pinctrl/pinmux-select

I did some tests with/without flow control using linux-serial-test tool.

>> - i2c busses are okay.
>> - for SPI, MOSI and CLK are okay, but not CS.
> Do you have enabled spi in BIOS HAT configuration?
> CS0 should be ok, it's SOC defined, CS1 is optional, users can activate low by
> himself before read/write, actually all gpio can be manually used as CS pin.

I applied an ACPI overlay. I'll test it again.

>> - all GPIOs are okay.
>>
>> Could you have a look please.

Anyway these are not related to this patch series.
Thanks for the clarification.

Tested-by: Thomas Richard <thomas.richard@bootlin.com>

Best Regards,
Thomas

Re: [PATCH v4 2/2] pinctrl: upboard: add device id INTC1055 based UP boards support

[Andy Shevchenko]

On Wed, Jul 8, 2026 at 10:49 AM Thomas Richard
<thomas.richard@bootlin.com> wrote:
> On 7/7/26 5:55 PM, GaryWang wrote:
> > On Tue, Jul 7, 2026 at 7:50 PM Thomas Richard
> > <thomas.richard@bootlin.com> wrote:
> >> On 7/6/26 12:36 PM, Gary Wang wrote:

...

> >> I tested the IOs:
> >> - pwm0 does not work.
> > you have to use our pwm kernel module for pwm test, I'll provide later.
>
> Ack

Can you, folks, elaborate why this is a requirement and what exactly
is not working?

> >> - uart1 partially works: TX is okay, but loopback doesn't work. Signal
> >> is bad when I add a loopback. Looks like pinctrl misconfig on SoC side.
> > uart1 tested ok on our side, if you loop TX/RX do not forget to turn off
> > hardware flow control. and we have executed cmd as below to make sure
> > direction is set all right.
> > echo "uart1_grp uart1" >
> > /sys/kernel/debug/pinctrl/upboard-pinctrl/pinmux-select
>
> I did some tests with/without flow control using linux-serial-test tool.

I'm sorry it's not so clear to me, does it mean the serial interface
is (still) not properly working or you have done that pinmux
configuration and everything becomes fine (as Tested-by tag suggests)?

...

> >> - for SPI, MOSI and CLK are okay, but not CS.
> > Do you have enabled spi in BIOS HAT configuration?
> > CS0 should be ok, it's SOC defined, CS1 is optional, users can activate low by
> > himself before read/write, actually all gpio can be manually used as CS pin.
>
> I applied an ACPI overlay. I'll test it again.

I suppose this part is not as critical and I just wonder what the test
results are.

...

> Anyway these are not related to this patch series.
> Thanks for the clarification.
>
> Tested-by: Thomas Richard <thomas.richard@bootlin.com>

So, after all, are they all good to go?

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v4 2/2] pinctrl: upboard: add device id INTC1055 based UP boards support

[GaryWang]

On Wed, Jul 8, 2026 at 5:21 PM Andy Shevchenko
<andy.shevchenko@gmail.com> wrote:
>
> On Wed, Jul 8, 2026 at 10:49 AM Thomas Richard
> <thomas.richard@bootlin.com> wrote:
> > On 7/7/26 5:55 PM, GaryWang wrote:
> > > On Tue, Jul 7, 2026 at 7:50 PM Thomas Richard
> > > <thomas.richard@bootlin.com> wrote:
> > >> On 7/6/26 12:36 PM, Gary Wang wrote:
>
> ...
>
> > >> I tested the IOs:
> > >> - pwm0 does not work.
> > > you have to use our pwm kernel module for pwm test, I'll provide later.
> >
> > Ack
>
> Can you, folks, elaborate why this is a requirement and what exactly
> is not working?
>
pwm resource IO address is not reported correctly, I fixed it in pwm
kernel modules
for testing, we set the pin mode to the correct function in this patch.

> > >> - uart1 partially works: TX is okay, but loopback doesn't work. Signal
> > >> is bad when I add a loopback. Looks like pinctrl misconfig on SoC side.
> > > uart1 tested ok on our side, if you loop TX/RX do not forget to turn off
> > > hardware flow control. and we have executed cmd as below to make sure
> > > direction is set all right.
> > > echo "uart1_grp uart1" >
> > > /sys/kernel/debug/pinctrl/upboard-pinctrl/pinmux-select
> >
> > I did some tests with/without flow control using linux-serial-test tool.
>
> I'm sorry it's not so clear to me, does it mean the serial interface
> is (still) not properly working or you have done that pinmux
> configuration and everything becomes fine (as Tested-by tag suggests)?
>
checking with Thomas, but testing ok on our side.
> ...
>
> > >> - for SPI, MOSI and CLK are okay, but not CS.
> > > Do you have enabled spi in BIOS HAT configuration?
> > > CS0 should be ok, it's SOC defined, CS1 is optional, users can activate low by
> > > himself before read/write, actually all gpio can be manually used as CS pin.
> >
> > I applied an ACPI overlay. I'll test it again.
>
> I suppose this part is not as critical and I just wonder what the test
> results are.
>
testing ok on our side, waiting for Thomas to clarify.
> ...
>
> > Anyway these are not related to this patch series.
> > Thanks for the clarification.
> >
> > Tested-by: Thomas Richard <thomas.richard@bootlin.com>
>
> So, after all, are they all good to go?
need Thomas verify, I thought only uart has problem in his testing.
>
> --
> With Best Regards,
> Andy Shevchenko

Re: [PATCH v4 2/2] pinctrl: upboard: add device id INTC1055 based UP boards support

[Thomas Richard]

On 7/8/26 11:21 AM, Andy Shevchenko wrote:
> On Wed, Jul 8, 2026 at 10:49 AM Thomas Richard
> <thomas.richard@bootlin.com> wrote:
>> On 7/7/26 5:55 PM, GaryWang wrote:
>>> On Tue, Jul 7, 2026 at 7:50 PM Thomas Richard
>>> <thomas.richard@bootlin.com> wrote:
>>>> On 7/6/26 12:36 PM, Gary Wang wrote:
> 
> ...
> 
>>>> I tested the IOs:
>>>> - pwm0 does not work.
>>> you have to use our pwm kernel module for pwm test, I'll provide later.
>>
>> Ack
> 
> Can you, folks, elaborate why this is a requirement and what exactly
> is not working?
> 
>>>> - uart1 partially works: TX is okay, but loopback doesn't work. Signal
>>>> is bad when I add a loopback. Looks like pinctrl misconfig on SoC side.
>>> uart1 tested ok on our side, if you loop TX/RX do not forget to turn off
>>> hardware flow control. and we have executed cmd as below to make sure
>>> direction is set all right.
>>> echo "uart1_grp uart1" >
>>> /sys/kernel/debug/pinctrl/upboard-pinctrl/pinmux-select
>>
>> I did some tests with/without flow control using linux-serial-test tool.
> 
> I'm sorry it's not so clear to me, does it mean the serial interface
> is (still) not properly working or you have done that pinmux
> configuration and everything becomes fine (as Tested-by tag suggests)?
> 
> ...
> 
>>>> - for SPI, MOSI and CLK are okay, but not CS.
>>> Do you have enabled spi in BIOS HAT configuration?
>>> CS0 should be ok, it's SOC defined, CS1 is optional, users can activate low by
>>> himself before read/write, actually all gpio can be manually used as CS pin.
>>
>> I applied an ACPI overlay. I'll test it again.
> 
> I suppose this part is not as critical and I just wonder what the test
> results are.
> 
> ...
> 
>> Anyway these are not related to this patch series.
>> Thanks for the clarification.
>>
>> Tested-by: Thomas Richard <thomas.richard@bootlin.com>
> 
> So, after all, are they all good to go?

Yes,

I tested all functions and it is okay.

It was my fault, my test script did not select pingroup and function
correctly, so FPGA pins were misconfigured.

You can pick my TB tag.

Best Regards,
Thomas

Re: [PATCH v4 0/2] upboard pinctrl support for device id INTC1055

[Andy Shevchenko]

On Mon, Jul 06, 2026 at 06:36:33PM +0800, Gary Wang wrote:
> Add missing groups and functions in Tigerlake's pinctrl driver for INTC1055.
> Add support "UP Xtreme i12" board.
> 
> The pinctrl-upboard is provide additional driving power & pin mux function
> through native SOC pins->FPGA/CPLD->hat pins for flexable board level
> applications. it's probe from ACPI device id AANT0F01 & AANT0F04.

Pushed to my review and testing queue, thanks!

-- 
With Best Regards,
Andy Shevchenko