Re: [PATCH v3] i2c: cadence: Add standard bus recovery support

[Michal Simek <michal.simek@amd.com>]

Hi Wolfram,

On 7/29/22 13:17, Michal Simek wrote:
> 
> 
> On 7/29/22 13:05, Datta, Shubhrajyoti wrote:
>> [AMD Official Use Only - General]
>>
>>
>>
>>> -----Original Message-----
>>> From: Simek, Michal <michal.simek@amd.com>
>>> Sent: Friday, July 29, 2022 4:26 PM
>>> To: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>; linux-
>>> i2c@vger.kernel.org
>>> Cc: michal.simek@xilinx.com; git-dev (AMD-Xilinx) <git-dev@amd.com>;
>>> Chirag Parekh <chiragp@xilinx.com>; Robert Hancock
>>> <robert.hancock@calian.com>
>>> Subject: Re: [PATCH v3] i2c: cadence: Add standard bus recovery support
>>>
>>>
>>>
>>> On 7/28/22 07:51, Shubhrajyoti Datta wrote:
>>>> Hook up the standard GPIO/pinctrl-based recovery support.
>>>> We are doing the recovery at the beginning on a timeout.
>>>>
>>>> Multiple people have contributed to the series.
>>>> Original patch from Cirag and another one from Robert.
>>>>
>>>> Cc: Chirag Parekh <chiragp@xilinx.com>
>>>> Cc: Robert Hancock <robert.hancock@calian.com>
>>>> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
>>>> ---
>>>>    v2:
>>>> Updated the busbusy check on a timeout
>>>> v3:
>>>> Added pinctrl_get
>>>>
>>>> Did unit testing and probed the scl to see the clock pulses.
>>>
>>> Can you please describe testing procedure? What board did you use?
>>> What was the hardware configuration?
>>
>>
>> Tested on zcu102 .  and then I called the recovery in send  setup .
>> Also I had added the prints in the
>> To confirm that the core was calling the zynqmp pinctrl to set pin mux.
>>
>> The scl  line was Probed. I could see the clock cycles in the scl line.
>>
>> [   84.286340] zynqmp-pinctrl firmware:zynqmp-firmware:pinctrl: set mux  for 
>> pin 14
>> [   84.293779] zynqmp-pinctrl firmware:zynqmp-firmware:pinctrl: set mux  for 
>> pin 15
>> [   84.301266] i2c-core: set_scl_gpio_value 164 1
>> [   84.305807] i2c i2c-0: SCL is set_scl 1 i ia 1
>> [   84.310331] i2c-core: get_scl_gpio_value 158
>> [   84.314681] i2c-core: set_scl_gpio_value 164 0
>> [   84.322519] i2c i2c-0: SCL is set_scl 0
>> [   84.326439] i2c i2c-0: SCL is set_scl 0 i ia 2
>> [   84.330965] i2c-core: set_scl_gpio_value 164 1
>> [   84.335496] i2c i2c-0: SCL is set_scl 1
>> [   84.339418] i2c i2c-0: SCL is set_scl 1 i ia 3
>> [   84.343947] i2c-core: get_scl_gpio_value 158
>> [   84.348302] i2c-core: set_scl_gpio_value 164 0
>> [   84.356135] i2c i2c-0: SCL is set_scl 0
>> [   84.360059] i2c i2c-0: SCL is set_scl 0 i ia 4
>> [   84.364586] i2c-core: set_scl_gpio_value 164 1
>> [   84.369117] i2c i2c-0: SCL is set_scl 1
>> [   84.373037] i2c i2c-0: SCL is set_scl 1 i ia 5
>> [   84.377564] i2c-core: get_scl_gpio_value 158
>> [   84.381914] i2c-core: set_scl_gpio_value 164 0
> 
> ok. Thanks.
> 
> Acked-by: Michal Simek <michal.simek@amd.com>
> 

Do you see any issue with this version?

Thanks,
Michal