[PATCH 0/4] Add CCI support for Milos, enable on Fairphone (Gen. 6)

[PATCH 0/4] Add CCI support for Milos, enable on Fairphone (Gen. 6)

[Luca Weiss]

Add the compatible strings for the CCI busses on Milos, and the EEPROMs
found on the Fairphone (Gen. 6) camera modules, and add them to the
milos dtsi and device dts.

This series soft-depends on https://lore.kernel.org/linux-arm-msm/20260116-milos-camcc-icc-v1-0-400b7fcd156a@fairphone.com/T/

The patches can be applied without the dependency, but the final dts
patches should probably only land once the other series has been fully
applied, otherwise the CCI busses cannot actually be used (unless some
other component turns on the mmss_noc) and you get a kernel warning like
the following:

[  291.055839] ------------[ cut here ]------------
[  291.055860] cam_cc_camss_top_gdsc status stuck at 'off'
[  291.055878] WARNING: drivers/clk/qcom/gdsc.c:178 at gdsc_toggle_logic+0x138/0x144, CPU#4: hexdump/1995

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Luca Weiss (4):
      dt-bindings: eeprom: at24: Add compatible for Puya P24C128F
      dt-bindings: i2c: qcom-cci: Document Milos compatible
      arm64: dts: qcom: milos: Add CCI busses
      arm64: dts: qcom: milos-fairphone-fp6: Add camera EEPROMs on CCI busses

 Documentation/devicetree/bindings/eeprom/at24.yaml |   1 +
 .../devicetree/bindings/i2c/qcom,i2c-cci.yaml      |  18 ++
 arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts   |  50 ++++++
 arch/arm64/boot/dts/qcom/milos.dtsi                | 194 +++++++++++++++++++++
 4 files changed, 263 insertions(+)
---
base-commit: ef1c7b875741bef0ff37ae8ab8a9aaf407dc141c
change-id: 20260106-milos-cci-f7f4d8821e87
prerequisite-change-id: 20260116-milos-camcc-icc-d41bdff31ef8:v1
prerequisite-patch-id: fc79344d381fea48318bbf62ce7c16b5687df074
prerequisite-patch-id: 323271b304b98b6ac0e98032f355de26c8e4fa6b
prerequisite-patch-id: ba8a70f210c54a14c69a60c26eea22d384b0397f
prerequisite-patch-id: de6e7d9f90ce4d8b37342e5198f042edee4b81a4
prerequisite-patch-id: aa3dc6c12366d6574b7e85808fcb107deddb8435

Best regards,
-- 
Luca Weiss <luca.weiss@fairphone.com>

[PATCH 1/4] dt-bindings: eeprom: at24: Add compatible for Puya P24C128F

[Luca Weiss]

Add the compatible for an 128Kb EEPROM from Puya.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
 Documentation/devicetree/bindings/eeprom/at24.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/eeprom/at24.yaml b/Documentation/devicetree/bindings/eeprom/at24.yaml
index 95ac2f15f601..ef88f46928a4 100644
--- a/Documentation/devicetree/bindings/eeprom/at24.yaml
+++ b/Documentation/devicetree/bindings/eeprom/at24.yaml
@@ -142,6 +142,7 @@ properties:
           - enum:
               - giantec,gt24p128e
               - giantec,gt24p128f
+              - puya,p24c128f
               - renesas,r1ex24128
               - samsung,s524ad0xd1
           - const: atmel,24c128

-- 
2.52.0

Re: [PATCH 1/4] dt-bindings: eeprom: at24: Add compatible for Puya P24C128F

[Konrad Dybcio]

On 1/16/26 2:38 PM, Luca Weiss wrote:
> Add the compatible for an 128Kb EEPROM from Puya.
> 
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: (subset) [PATCH 1/4] dt-bindings: eeprom: at24: Add compatible for Puya P24C128F

[Bartosz Golaszewski]

On Fri, 16 Jan 2026 14:38:55 +0100, Luca Weiss wrote:
> Add the compatible for an 128Kb EEPROM from Puya.
> 
> 

Applied, thanks!

[1/4] dt-bindings: eeprom: at24: Add compatible for Puya P24C128F
      commit: c6e79d34bf80c008e5f5fba2c8cce3df81a84335

Best regards,
-- 
Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>

[PATCH 2/4] dt-bindings: i2c: qcom-cci: Document Milos compatible

[Luca Weiss]

Add Milos compatible for the CAMSS CCI interfaces.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
 .../devicetree/bindings/i2c/qcom,i2c-cci.yaml          | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
index a3fe1eea6aec..c57d81258fba 100644
--- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
+++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
@@ -27,6 +27,7 @@ properties:
       - items:
           - enum:
               - qcom,kaanapali-cci
+              - qcom,milos-cci
               - qcom,qcm2290-cci
               - qcom,sa8775p-cci
               - qcom,sc7280-cci
@@ -263,6 +264,23 @@ allOf:
             - const: cpas_ahb
             - const: cci
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,milos-cci
+    then:
+      properties:
+        clocks:
+          minItems: 3
+          maxItems: 3
+        clock-names:
+          items:
+            - const: soc_ahb
+            - const: cpas_ahb
+            - const: cci
+
 additionalProperties: false
 
 examples:

-- 
2.52.0

Re: [PATCH 2/4] dt-bindings: i2c: qcom-cci: Document Milos compatible

[Krzysztof Kozlowski]

On Fri, Jan 16, 2026 at 02:38:56PM +0100, Luca Weiss wrote:
> Add Milos compatible for the CAMSS CCI interfaces.
> 
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
>  .../devicetree/bindings/i2c/qcom,i2c-cci.yaml          | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
> index a3fe1eea6aec..c57d81258fba 100644
> --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
> +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
> @@ -27,6 +27,7 @@ properties:
>        - items:
>            - enum:
>                - qcom,kaanapali-cci
> +              - qcom,milos-cci
>                - qcom,qcm2290-cci
>                - qcom,sa8775p-cci
>                - qcom,sc7280-cci
> @@ -263,6 +264,23 @@ allOf:
>              - const: cpas_ahb
>              - const: cci
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,milos-cci
> +    then:
> +      properties:
> +        clocks:
> +          minItems: 3
> +          maxItems: 3
> +        clock-names:
> +          items:
> +            - const: soc_ahb
> +            - const: cpas_ahb
> +            - const: cci

Same comments as other discussion these days - I guess that soc_ahb
serves the same purpose as camnoc_axi, so this is just last entri in the
if:then: blocks.

I really find this binding terrible - around six names for AHB - so I do
not want another combination...

Best regards,
Krzysztof

Re: [PATCH 2/4] dt-bindings: i2c: qcom-cci: Document Milos compatible

[Konrad Dybcio]

On 1/17/26 12:54 PM, Krzysztof Kozlowski wrote:
> On Fri, Jan 16, 2026 at 02:38:56PM +0100, Luca Weiss wrote:
>> Add Milos compatible for the CAMSS CCI interfaces.
>>
>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>> ---
>>  .../devicetree/bindings/i2c/qcom,i2c-cci.yaml          | 18 ++++++++++++++++++
>>  1 file changed, 18 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
>> index a3fe1eea6aec..c57d81258fba 100644
>> --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
>> +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
>> @@ -27,6 +27,7 @@ properties:
>>        - items:
>>            - enum:
>>                - qcom,kaanapali-cci
>> +              - qcom,milos-cci
>>                - qcom,qcm2290-cci
>>                - qcom,sa8775p-cci
>>                - qcom,sc7280-cci
>> @@ -263,6 +264,23 @@ allOf:
>>              - const: cpas_ahb
>>              - const: cci
>>  
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            enum:
>> +              - qcom,milos-cci
>> +    then:
>> +      properties:
>> +        clocks:
>> +          minItems: 3
>> +          maxItems: 3
>> +        clock-names:
>> +          items:
>> +            - const: soc_ahb
>> +            - const: cpas_ahb
>> +            - const: cci
> 
> Same comments as other discussion these days - I guess that soc_ahb
> serves the same purpose as camnoc_axi, so this is just last entri in the
> if:then: blocks.
> 
> I really find this binding terrible - around six names for AHB - so I do
> not want another combination...

I dug up the CCI doc, it talks about the CCI having a CC_CCI_CLK clock ("cci"
here) and a CC_PBUS_CLK (AHB interface to the rest of the SoC).

The CAMSS TOP doc (for Milos specifically, but I would assume there's a
pattern) says that for access to CCI_0, I need to enable CAM_CC_CPAS_AHB_CLK
and CAM_CC_CCI_0_CLK. CPAS is a wrapper inside CAMSS that contains most of
the programmable IPs on there (notably not the CSIPHYs, at least not on this
platform)

It further mentions that GCC_SOC_AHB_CLK is required for *any* register
access within CAMSS. Perhaps it sits right in front of the xNoC-to-CAMNoC
interface.

This only enforces my imagination of CAMSS being a fully contained "bus"
(perhaps somewhat like AxNOC on 8996 represented with a simple-pm-bus)..

+Dmitry, myself and a number of our colleagues were deliberating how to
best represent the hardware going forward and I think we at some point waved
the idea of putting every camera subdevice under a "camss: bus@ {}"-type node,
which would hold the reference to the TITAN_TOP_GDSC. This seems fitting for
housing the SOC_AHB clock as well and therefore concluding this discussion.

Konrad

Re: [PATCH 2/4] dt-bindings: i2c: qcom-cci: Document Milos compatible

[Luca Weiss]

Hi all,

On Tue Jan 20, 2026 at 2:18 PM CET, Konrad Dybcio wrote:
> On 1/17/26 12:54 PM, Krzysztof Kozlowski wrote:
>> On Fri, Jan 16, 2026 at 02:38:56PM +0100, Luca Weiss wrote:
>>> Add Milos compatible for the CAMSS CCI interfaces.
>>>
>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>>> ---
>>>  .../devicetree/bindings/i2c/qcom,i2c-cci.yaml          | 18 ++++++++++++++++++
>>>  1 file changed, 18 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
>>> index a3fe1eea6aec..c57d81258fba 100644
>>> --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
>>> +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
>>> @@ -27,6 +27,7 @@ properties:
>>>        - items:
>>>            - enum:
>>>                - qcom,kaanapali-cci
>>> +              - qcom,milos-cci
>>>                - qcom,qcm2290-cci
>>>                - qcom,sa8775p-cci
>>>                - qcom,sc7280-cci
>>> @@ -263,6 +264,23 @@ allOf:
>>>              - const: cpas_ahb
>>>              - const: cci
>>>  
>>> +  - if:
>>> +      properties:
>>> +        compatible:
>>> +          contains:
>>> +            enum:
>>> +              - qcom,milos-cci
>>> +    then:
>>> +      properties:
>>> +        clocks:
>>> +          minItems: 3
>>> +          maxItems: 3
>>> +        clock-names:
>>> +          items:
>>> +            - const: soc_ahb
>>> +            - const: cpas_ahb
>>> +            - const: cci
>> 
>> Same comments as other discussion these days - I guess that soc_ahb
>> serves the same purpose as camnoc_axi, so this is just last entri in the
>> if:then: blocks.
>> 
>> I really find this binding terrible - around six names for AHB - so I do
>> not want another combination...
>
> I dug up the CCI doc, it talks about the CCI having a CC_CCI_CLK clock ("cci"
> here) and a CC_PBUS_CLK (AHB interface to the rest of the SoC).
>
> The CAMSS TOP doc (for Milos specifically, but I would assume there's a
> pattern) says that for access to CCI_0, I need to enable CAM_CC_CPAS_AHB_CLK
> and CAM_CC_CCI_0_CLK. CPAS is a wrapper inside CAMSS that contains most of
> the programmable IPs on there (notably not the CSIPHYs, at least not on this
> platform)
>
> It further mentions that GCC_SOC_AHB_CLK is required for *any* register
> access within CAMSS. Perhaps it sits right in front of the xNoC-to-CAMNoC
> interface.
>
> This only enforces my imagination of CAMSS being a fully contained "bus"
> (perhaps somewhat like AxNOC on 8996 represented with a simple-pm-bus)..
>
> +Dmitry, myself and a number of our colleagues were deliberating how to
> best represent the hardware going forward and I think we at some point waved
> the idea of putting every camera subdevice under a "camss: bus@ {}"-type node,
> which would hold the reference to the TITAN_TOP_GDSC. This seems fitting for
> housing the SOC_AHB clock as well and therefore concluding this discussion.

How can we continue here? What change can I do to unblock this? I can't
tell whether soc_ahb == camnoc_axi for this platform so I need some help
here.

Regards
Luca

Re: [PATCH 2/4] dt-bindings: i2c: qcom-cci: Document Milos compatible

[Luca Weiss]

On Fri Feb 13, 2026 at 2:16 PM CET, Luca Weiss wrote:
> Hi all,
>
> On Tue Jan 20, 2026 at 2:18 PM CET, Konrad Dybcio wrote:
>> On 1/17/26 12:54 PM, Krzysztof Kozlowski wrote:
>>> On Fri, Jan 16, 2026 at 02:38:56PM +0100, Luca Weiss wrote:
>>>> Add Milos compatible for the CAMSS CCI interfaces.
>>>>
>>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>>>> ---
>>>>  .../devicetree/bindings/i2c/qcom,i2c-cci.yaml          | 18 ++++++++++++++++++
>>>>  1 file changed, 18 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
>>>> index a3fe1eea6aec..c57d81258fba 100644
>>>> --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
>>>> +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
>>>> @@ -27,6 +27,7 @@ properties:
>>>>        - items:
>>>>            - enum:
>>>>                - qcom,kaanapali-cci
>>>> +              - qcom,milos-cci
>>>>                - qcom,qcm2290-cci
>>>>                - qcom,sa8775p-cci
>>>>                - qcom,sc7280-cci
>>>> @@ -263,6 +264,23 @@ allOf:
>>>>              - const: cpas_ahb
>>>>              - const: cci
>>>>  
>>>> +  - if:
>>>> +      properties:
>>>> +        compatible:
>>>> +          contains:
>>>> +            enum:
>>>> +              - qcom,milos-cci
>>>> +    then:
>>>> +      properties:
>>>> +        clocks:
>>>> +          minItems: 3
>>>> +          maxItems: 3
>>>> +        clock-names:
>>>> +          items:
>>>> +            - const: soc_ahb
>>>> +            - const: cpas_ahb
>>>> +            - const: cci
>>> 
>>> Same comments as other discussion these days - I guess that soc_ahb
>>> serves the same purpose as camnoc_axi, so this is just last entri in the
>>> if:then: blocks.
>>> 
>>> I really find this binding terrible - around six names for AHB - so I do
>>> not want another combination...
>>
>> I dug up the CCI doc, it talks about the CCI having a CC_CCI_CLK clock ("cci"
>> here) and a CC_PBUS_CLK (AHB interface to the rest of the SoC).
>>
>> The CAMSS TOP doc (for Milos specifically, but I would assume there's a
>> pattern) says that for access to CCI_0, I need to enable CAM_CC_CPAS_AHB_CLK
>> and CAM_CC_CCI_0_CLK. CPAS is a wrapper inside CAMSS that contains most of
>> the programmable IPs on there (notably not the CSIPHYs, at least not on this
>> platform)
>>
>> It further mentions that GCC_SOC_AHB_CLK is required for *any* register
>> access within CAMSS. Perhaps it sits right in front of the xNoC-to-CAMNoC
>> interface.
>>
>> This only enforces my imagination of CAMSS being a fully contained "bus"
>> (perhaps somewhat like AxNOC on 8996 represented with a simple-pm-bus)..
>>
>> +Dmitry, myself and a number of our colleagues were deliberating how to
>> best represent the hardware going forward and I think we at some point waved
>> the idea of putting every camera subdevice under a "camss: bus@ {}"-type node,
>> which would hold the reference to the TITAN_TOP_GDSC. This seems fitting for
>> housing the SOC_AHB clock as well and therefore concluding this discussion.
>
> How can we continue here? What change can I do to unblock this? I can't
> tell whether soc_ahb == camnoc_axi for this platform so I need some help
> here.

Any feedback on this?

Regards
Luca

Re: [PATCH 2/4] dt-bindings: i2c: qcom-cci: Document Milos compatible

[Dmitry Baryshkov]

On Fri, Mar 13, 2026 at 11:43:07AM +0100, Luca Weiss wrote:
> On Fri Feb 13, 2026 at 2:16 PM CET, Luca Weiss wrote:
> > Hi all,
> >
> > On Tue Jan 20, 2026 at 2:18 PM CET, Konrad Dybcio wrote:
> >> On 1/17/26 12:54 PM, Krzysztof Kozlowski wrote:
> >>> On Fri, Jan 16, 2026 at 02:38:56PM +0100, Luca Weiss wrote:
> >>>> Add Milos compatible for the CAMSS CCI interfaces.
> >>>>
> >>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> >>>> ---
> >>>>  .../devicetree/bindings/i2c/qcom,i2c-cci.yaml          | 18 ++++++++++++++++++
> >>>>  1 file changed, 18 insertions(+)
> >>>>
> >>>> diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
> >>>> index a3fe1eea6aec..c57d81258fba 100644
> >>>> --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
> >>>> +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
> >>>> @@ -27,6 +27,7 @@ properties:
> >>>>        - items:
> >>>>            - enum:
> >>>>                - qcom,kaanapali-cci
> >>>> +              - qcom,milos-cci
> >>>>                - qcom,qcm2290-cci
> >>>>                - qcom,sa8775p-cci
> >>>>                - qcom,sc7280-cci
> >>>> @@ -263,6 +264,23 @@ allOf:
> >>>>              - const: cpas_ahb
> >>>>              - const: cci
> >>>>  
> >>>> +  - if:
> >>>> +      properties:
> >>>> +        compatible:
> >>>> +          contains:
> >>>> +            enum:
> >>>> +              - qcom,milos-cci
> >>>> +    then:
> >>>> +      properties:
> >>>> +        clocks:
> >>>> +          minItems: 3
> >>>> +          maxItems: 3
> >>>> +        clock-names:
> >>>> +          items:
> >>>> +            - const: soc_ahb
> >>>> +            - const: cpas_ahb
> >>>> +            - const: cci
> >>> 
> >>> Same comments as other discussion these days - I guess that soc_ahb
> >>> serves the same purpose as camnoc_axi, so this is just last entri in the
> >>> if:then: blocks.
> >>> 
> >>> I really find this binding terrible - around six names for AHB - so I do
> >>> not want another combination...
> >>
> >> I dug up the CCI doc, it talks about the CCI having a CC_CCI_CLK clock ("cci"
> >> here) and a CC_PBUS_CLK (AHB interface to the rest of the SoC).
> >>
> >> The CAMSS TOP doc (for Milos specifically, but I would assume there's a
> >> pattern) says that for access to CCI_0, I need to enable CAM_CC_CPAS_AHB_CLK
> >> and CAM_CC_CCI_0_CLK. CPAS is a wrapper inside CAMSS that contains most of
> >> the programmable IPs on there (notably not the CSIPHYs, at least not on this
> >> platform)
> >>
> >> It further mentions that GCC_SOC_AHB_CLK is required for *any* register
> >> access within CAMSS. Perhaps it sits right in front of the xNoC-to-CAMNoC
> >> interface.
> >>
> >> This only enforces my imagination of CAMSS being a fully contained "bus"
> >> (perhaps somewhat like AxNOC on 8996 represented with a simple-pm-bus)..
> >>
> >> +Dmitry, myself and a number of our colleagues were deliberating how to
> >> best represent the hardware going forward and I think we at some point waved
> >> the idea of putting every camera subdevice under a "camss: bus@ {}"-type node,
> >> which would hold the reference to the TITAN_TOP_GDSC. This seems fitting for
> >> housing the SOC_AHB clock as well and therefore concluding this discussion.
> >
> > How can we continue here? What change can I do to unblock this? I can't
> > tell whether soc_ahb == camnoc_axi for this platform so I need some help
> > here.
> 
> Any feedback on this?

I went on and checked. No Milos's soc_ahb != camnoc_axi. They serve
different purposes.

-- 
With best wishes
Dmitry

Re: [PATCH 2/4] dt-bindings: i2c: qcom-cci: Document Milos compatible

[Luca Weiss]

On Fri Mar 13, 2026 at 5:18 PM CET, Dmitry Baryshkov wrote:
> On Fri, Mar 13, 2026 at 11:43:07AM +0100, Luca Weiss wrote:
>> On Fri Feb 13, 2026 at 2:16 PM CET, Luca Weiss wrote:
>> > Hi all,
>> >
>> > On Tue Jan 20, 2026 at 2:18 PM CET, Konrad Dybcio wrote:
>> >> On 1/17/26 12:54 PM, Krzysztof Kozlowski wrote:
>> >>> On Fri, Jan 16, 2026 at 02:38:56PM +0100, Luca Weiss wrote:
>> >>>> Add Milos compatible for the CAMSS CCI interfaces.
>> >>>>
>> >>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>> >>>> ---
>> >>>>  .../devicetree/bindings/i2c/qcom,i2c-cci.yaml          | 18 ++++++++++++++++++
>> >>>>  1 file changed, 18 insertions(+)
>> >>>>
>> >>>> diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
>> >>>> index a3fe1eea6aec..c57d81258fba 100644
>> >>>> --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
>> >>>> +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
>> >>>> @@ -27,6 +27,7 @@ properties:
>> >>>>        - items:
>> >>>>            - enum:
>> >>>>                - qcom,kaanapali-cci
>> >>>> +              - qcom,milos-cci
>> >>>>                - qcom,qcm2290-cci
>> >>>>                - qcom,sa8775p-cci
>> >>>>                - qcom,sc7280-cci
>> >>>> @@ -263,6 +264,23 @@ allOf:
>> >>>>              - const: cpas_ahb
>> >>>>              - const: cci
>> >>>>  
>> >>>> +  - if:
>> >>>> +      properties:
>> >>>> +        compatible:
>> >>>> +          contains:
>> >>>> +            enum:
>> >>>> +              - qcom,milos-cci
>> >>>> +    then:
>> >>>> +      properties:
>> >>>> +        clocks:
>> >>>> +          minItems: 3
>> >>>> +          maxItems: 3
>> >>>> +        clock-names:
>> >>>> +          items:
>> >>>> +            - const: soc_ahb
>> >>>> +            - const: cpas_ahb
>> >>>> +            - const: cci
>> >>> 
>> >>> Same comments as other discussion these days - I guess that soc_ahb
>> >>> serves the same purpose as camnoc_axi, so this is just last entri in the
>> >>> if:then: blocks.
>> >>> 
>> >>> I really find this binding terrible - around six names for AHB - so I do
>> >>> not want another combination...
>> >>
>> >> I dug up the CCI doc, it talks about the CCI having a CC_CCI_CLK clock ("cci"
>> >> here) and a CC_PBUS_CLK (AHB interface to the rest of the SoC).
>> >>
>> >> The CAMSS TOP doc (for Milos specifically, but I would assume there's a
>> >> pattern) says that for access to CCI_0, I need to enable CAM_CC_CPAS_AHB_CLK
>> >> and CAM_CC_CCI_0_CLK. CPAS is a wrapper inside CAMSS that contains most of
>> >> the programmable IPs on there (notably not the CSIPHYs, at least not on this
>> >> platform)
>> >>
>> >> It further mentions that GCC_SOC_AHB_CLK is required for *any* register
>> >> access within CAMSS. Perhaps it sits right in front of the xNoC-to-CAMNoC
>> >> interface.
>> >>
>> >> This only enforces my imagination of CAMSS being a fully contained "bus"
>> >> (perhaps somewhat like AxNOC on 8996 represented with a simple-pm-bus)..
>> >>
>> >> +Dmitry, myself and a number of our colleagues were deliberating how to
>> >> best represent the hardware going forward and I think we at some point waved
>> >> the idea of putting every camera subdevice under a "camss: bus@ {}"-type node,
>> >> which would hold the reference to the TITAN_TOP_GDSC. This seems fitting for
>> >> housing the SOC_AHB clock as well and therefore concluding this discussion.
>> >
>> > How can we continue here? What change can I do to unblock this? I can't
>> > tell whether soc_ahb == camnoc_axi for this platform so I need some help
>> > here.
>> 
>> Any feedback on this?
>
> I went on and checked. No Milos's soc_ahb != camnoc_axi. They serve
> different purposes.

Thanks Dmitry, appreciate it!

@Krzysztof: Could you take another look at the binding then please?

Regards
Luca

Re: [PATCH 2/4] dt-bindings: i2c: qcom-cci: Document Milos compatible

[Krzysztof Kozlowski]

On 16/03/2026 09:03, Luca Weiss wrote:
>>
>> I went on and checked. No Milos's soc_ahb != camnoc_axi. They serve
>> different purposes.
> 
> Thanks Dmitry, appreciate it!
> 
> @Krzysztof: Could you take another look at the binding then please?

It is two months old patch, so for sure you need to resend it, but I
gave my tag now.

Best regards,
Krzysztof

Re: [PATCH 2/4] dt-bindings: i2c: qcom-cci: Document Milos compatible

[Luca Weiss]

On Thu Mar 19, 2026 at 5:58 PM CET, Krzysztof Kozlowski wrote:
> On 16/03/2026 09:03, Luca Weiss wrote:
>>>
>>> I went on and checked. No Milos's soc_ahb != camnoc_axi. They serve
>>> different purposes.
>> 
>> Thanks Dmitry, appreciate it!
>> 
>> @Krzysztof: Could you take another look at the binding then please?
>
> It is two months old patch, so for sure you need to resend it, but I
> gave my tag now.

Your concern was addressed in a reply in this thread, so I thought I'd
ask for your R-b here, instead of sending another revision where you may
not feel like your concerns have been addressed.

Neither option feels perfect.

Regards
Luca

>
> Best regards,
> Krzysztof

Re: [PATCH 2/4] dt-bindings: i2c: qcom-cci: Document Milos compatible

[Krzysztof Kozlowski]

On 16/01/2026 14:38, Luca Weiss wrote:
> Add Milos compatible for the CAMSS CCI interfaces.
> 
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
>  .../devicetree/bindings/i2c/qcom,i2c-cci.yaml          | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

[PATCH 3/4] arm64: dts: qcom: milos: Add CCI busses

[Luca Weiss]

Add the nodes and the pinctrl for the CCI I2C busses on the Milos SoC.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
 arch/arm64/boot/dts/qcom/milos.dtsi | 194 ++++++++++++++++++++++++++++++++++++
 1 file changed, 194 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
index 58b4c2966df1..c8771beffa9b 100644
--- a/arch/arm64/boot/dts/qcom/milos.dtsi
+++ b/arch/arm64/boot/dts/qcom/milos.dtsi
@@ -1652,6 +1652,72 @@ videocc: clock-controller@aaf0000 {
 			#power-domain-cells = <1>;
 		};
 
+		cci0: cci@ac15000 {
+			compatible = "qcom,milos-cci", "qcom,msm8996-cci";
+			reg = <0x0 0x0ac15000 0x0 0x1000>;
+			interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING 0>;
+			power-domains = <&camcc CAM_CC_CAMSS_TOP_GDSC>;
+			clocks = <&camcc CAM_CC_SOC_AHB_CLK>,
+				 <&camcc CAM_CC_CPAS_AHB_CLK>,
+				 <&camcc CAM_CC_CCI_0_CLK>;
+			clock-names = "soc_ahb",
+				      "cpas_ahb",
+				      "cci";
+			pinctrl-0 = <&cci0_0_default &cci0_1_default>;
+			pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
+			pinctrl-names = "default", "sleep";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			cci0_i2c0: i2c-bus@0 {
+				reg = <0>;
+				clock-frequency = <1000000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			cci0_i2c1: i2c-bus@1 {
+				reg = <1>;
+				clock-frequency = <1000000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
+		cci1: cci@ac16000 {
+			compatible = "qcom,milos-cci", "qcom,msm8996-cci";
+			reg = <0x0 0x0ac16000 0x0 0x1000>;
+			interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING 0>;
+			power-domains = <&camcc CAM_CC_CAMSS_TOP_GDSC>;
+			clocks = <&camcc CAM_CC_SOC_AHB_CLK>,
+				 <&camcc CAM_CC_CPAS_AHB_CLK>,
+				 <&camcc CAM_CC_CCI_1_CLK>;
+			clock-names = "soc_ahb",
+				      "cpas_ahb",
+				      "cci";
+			pinctrl-0 = <&cci1_0_default &cci1_1_default>;
+			pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
+			pinctrl-names = "default", "sleep";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			cci1_i2c0: i2c-bus@0 {
+				reg = <0>;
+				clock-frequency = <1000000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			cci1_i2c1: i2c-bus@1 {
+				reg = <1>;
+				clock-frequency = <1000000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
 		camcc: clock-controller@adb0000 {
 			compatible = "qcom,milos-camcc";
 			reg = <0x0 0x0adb0000 0x0 0x40000>;
@@ -1791,6 +1857,134 @@ tlmm: pinctrl@f100000 {
 
 			wakeup-parent = <&pdc>;
 
+			cci0_0_default: cci0-0-default-state {
+				sda-pins {
+					pins = "gpio88";
+					function = "cci_i2c_sda";
+					drive-strength = <2>;
+					bias-pull-up = <2200>;
+				};
+
+				scl-pins {
+					pins = "gpio89";
+					function = "cci_i2c_scl";
+					drive-strength = <2>;
+					bias-pull-up = <2200>;
+				};
+			};
+
+			cci0_0_sleep: cci0-0-sleep-state {
+				sda-pins {
+					pins = "gpio88";
+					function = "cci_i2c_sda";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+
+				scl-pins {
+					pins = "gpio89";
+					function = "cci_i2c_scl";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+
+			cci0_1_default: cci0-1-default-state {
+				sda-pins {
+					pins = "gpio90";
+					function = "cci_i2c_sda";
+					drive-strength = <2>;
+					bias-pull-up = <2200>;
+				};
+
+				scl-pins {
+					pins = "gpio91";
+					function = "cci_i2c_scl";
+					drive-strength = <2>;
+					bias-pull-up = <2200>;
+				};
+			};
+
+			cci0_1_sleep: cci0-1-sleep-state {
+				sda-pins {
+					pins = "gpio90";
+					function = "cci_i2c_sda";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+
+				scl-pins {
+					pins = "gpio91";
+					function = "cci_i2c_scl";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+
+			cci1_0_default: cci1-0-default-state {
+				sda-pins {
+					pins = "gpio92";
+					function = "cci_i2c_sda";
+					drive-strength = <2>;
+					bias-pull-up = <2200>;
+				};
+
+				scl-pins {
+					pins = "gpio93";
+					function = "cci_i2c_scl";
+					drive-strength = <2>;
+					bias-pull-up = <2200>;
+				};
+			};
+
+			cci1_0_sleep: cci1-0-sleep-state {
+				sda-pins {
+					pins = "gpio92";
+					function = "cci_i2c_sda";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+
+				scl-pins {
+					pins = "gpio93";
+					function = "cci_i2c_scl";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+
+			cci1_1_default: cci1-1-default-state {
+				sda-pins {
+					pins = "gpio94";
+					function = "cci_i2c_sda";
+					drive-strength = <2>;
+					bias-pull-up = <2200>;
+				};
+
+				scl-pins {
+					pins = "gpio95";
+					function = "cci_i2c_scl";
+					drive-strength = <2>;
+					bias-pull-up = <2200>;
+				};
+			};
+
+			cci1_1_sleep: cci1-1-sleep-state {
+				sda-pins {
+					pins = "gpio94";
+					function = "cci_i2c_sda";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+
+				scl-pins {
+					pins = "gpio95";
+					function = "cci_i2c_scl";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+
 			qup_i2c1_data_clk: qup-i2c1-data-clk-state {
 				/* SDA, SCL */
 				pins = "gpio4", "gpio5";

-- 
2.52.0

Re: [PATCH 3/4] arm64: dts: qcom: milos: Add CCI busses

[Konrad Dybcio]

On 1/16/26 2:38 PM, Luca Weiss wrote:
> Add the nodes and the pinctrl for the CCI I2C busses on the Milos SoC.
> 
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
>  arch/arm64/boot/dts/qcom/milos.dtsi | 194 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 194 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
> index 58b4c2966df1..c8771beffa9b 100644
> --- a/arch/arm64/boot/dts/qcom/milos.dtsi
> +++ b/arch/arm64/boot/dts/qcom/milos.dtsi
> @@ -1652,6 +1652,72 @@ videocc: clock-controller@aaf0000 {
>  			#power-domain-cells = <1>;
>  		};
>  
> +		cci0: cci@ac15000 {
> +			compatible = "qcom,milos-cci", "qcom,msm8996-cci";
> +			reg = <0x0 0x0ac15000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING 0>;
> +			power-domains = <&camcc CAM_CC_CAMSS_TOP_GDSC>;
> +			clocks = <&camcc CAM_CC_SOC_AHB_CLK>,
> +				 <&camcc CAM_CC_CPAS_AHB_CLK>,
> +				 <&camcc CAM_CC_CCI_0_CLK>;
> +			clock-names = "soc_ahb",
> +				      "cpas_ahb",
> +				      "cci";
> +			pinctrl-0 = <&cci0_0_default &cci0_1_default>;
> +			pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
> +			pinctrl-names = "default", "sleep";
> +			status = "disabled";

With the pins moving to the child nodes, we may as well move the
disablement there, peeking at the code, I think it should handle it
well

[...]

>  		camcc: clock-controller@adb0000 {
>  			compatible = "qcom,milos-camcc";
>  			reg = <0x0 0x0adb0000 0x0 0x40000>;
> @@ -1791,6 +1857,134 @@ tlmm: pinctrl@f100000 {
>  
>  			wakeup-parent = <&pdc>;
>  
> +			cci0_0_default: cci0-0-default-state {
> +				sda-pins {
> +					pins = "gpio88";
> +					function = "cci_i2c_sda";
> +					drive-strength = <2>;
> +					bias-pull-up = <2200>;
> +				};

It would be fantastic if the GPIOs remained sorted by the GPIO num

Konrad

[PATCH 4/4] arm64: dts: qcom: milos-fairphone-fp6: Add camera EEPROMs on CCI busses

[Luca Weiss]

Enable the CCI I2C busses and add nodes for the EEPROMs found on the
camera that are connected there.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
 arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 50 ++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
index 7629ceddde2a..c4a706e945ba 100644
--- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
+++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
@@ -529,6 +529,56 @@ vreg_l11f: ldo11 {
 	};
 };
 
+&cci0 {
+	status = "okay";
+};
+
+&cci0_i2c0 {
+	/* Main cam: Sony IMX896 @ 0x1a */
+
+	eeprom@50 {
+		compatible = "puya,p24c128f", "atmel,24c128";
+		reg = <0x50>;
+		vcc-supply = <&vreg_l6p>;
+		read-only;
+	};
+
+	/* Dongwoon DW9784 VCM/OIS @ 0x72 */
+};
+
+
+&cci0_i2c1 {
+	/* Awinic AW86017 VCM @ 0x0c */
+	/* UW cam: OmniVision OV13B10 @ 0x36 */
+
+	eeprom@52 {
+		compatible = "puya,p24c128f", "atmel,24c128";
+		reg = <0x52>;
+		vcc-supply = <&vreg_l6p>;
+		read-only;
+	};
+};
+
+&cci1 {
+	/* cci1_i2c0 is not used for CCI */
+	pinctrl-0 = <&cci1_1_default>;
+	pinctrl-1 = <&cci1_1_sleep>;
+
+	status = "okay";
+};
+
+&cci1_i2c1 {
+	/* Awinic AW86016 VCM @ 0x0c */
+	/* Front cam: Samsung S5KKD1 @ 0x3d */
+
+	eeprom@51 {
+		compatible = "puya,p24c128f", "atmel,24c128";
+		reg = <0x51>;
+		vcc-supply = <&vreg_l6p>;
+		read-only;
+	};
+};
+
 &gcc {
 	protected-clocks = <GCC_PCIE_1_AUX_CLK>, <GCC_PCIE_1_AUX_CLK_SRC>,
 			   <GCC_PCIE_1_CFG_AHB_CLK>, <GCC_PCIE_1_MSTR_AXI_CLK>,

-- 
2.52.0

Re: [PATCH 4/4] arm64: dts: qcom: milos-fairphone-fp6: Add camera EEPROMs on CCI busses

[Konrad Dybcio]

On 1/16/26 2:38 PM, Luca Weiss wrote:
> Enable the CCI I2C busses and add nodes for the EEPROMs found on the
> camera that are connected there.
> 
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
>  arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 50 ++++++++++++++++++++++++
>  1 file changed, 50 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
> index 7629ceddde2a..c4a706e945ba 100644
> --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
> +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
> @@ -529,6 +529,56 @@ vreg_l11f: ldo11 {
>  	};
>  };
>  
> +&cci0 {
> +	status = "okay";
> +};
> +
> +&cci0_i2c0 {
> +	/* Main cam: Sony IMX896 @ 0x1a */
> +
> +	eeprom@50 {
> +		compatible = "puya,p24c128f", "atmel,24c128";
> +		reg = <0x50>;
> +		vcc-supply = <&vreg_l6p>;
> +		read-only;
> +	};
> +
> +	/* Dongwoon DW9784 VCM/OIS @ 0x72 */
> +};
> +
> +
> +&cci0_i2c1 {
> +	/* Awinic AW86017 VCM @ 0x0c */
> +	/* UW cam: OmniVision OV13B10 @ 0x36 */

There's a driver for this one!

> +
> +	eeprom@52 {
> +		compatible = "puya,p24c128f", "atmel,24c128";
> +		reg = <0x52>;
> +		vcc-supply = <&vreg_l6p>;
> +		read-only;
> +	};
> +};
> +
> +&cci1 {
> +	/* cci1_i2c0 is not used for CCI */
> +	pinctrl-0 = <&cci1_1_default>;
> +	pinctrl-1 = <&cci1_1_sleep>;

Let's keep them per-bus-subnode so we don't have to override it

otherwise

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 4/4] arm64: dts: qcom: milos-fairphone-fp6: Add camera EEPROMs on CCI busses

[Luca Weiss]

On Fri Jan 16, 2026 at 2:59 PM CET, Konrad Dybcio wrote:
> On 1/16/26 2:38 PM, Luca Weiss wrote:
>> Enable the CCI I2C busses and add nodes for the EEPROMs found on the
>> camera that are connected there.
>> 
>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>> ---
>>  arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 50 ++++++++++++++++++++++++
>>  1 file changed, 50 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>> index 7629ceddde2a..c4a706e945ba 100644
>> --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>> +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>> @@ -529,6 +529,56 @@ vreg_l11f: ldo11 {
>>  	};
>>  };
>>  
>> +&cci0 {
>> +	status = "okay";
>> +};
>> +
>> +&cci0_i2c0 {
>> +	/* Main cam: Sony IMX896 @ 0x1a */
>> +
>> +	eeprom@50 {
>> +		compatible = "puya,p24c128f", "atmel,24c128";
>> +		reg = <0x50>;
>> +		vcc-supply = <&vreg_l6p>;
>> +		read-only;
>> +	};
>> +
>> +	/* Dongwoon DW9784 VCM/OIS @ 0x72 */
>> +};
>> +
>> +
>> +&cci0_i2c1 {
>> +	/* Awinic AW86017 VCM @ 0x0c */
>> +	/* UW cam: OmniVision OV13B10 @ 0x36 */
>
> There's a driver for this one!

Yep! Already got patches to add the required regulators & devicetree
support to the driver, but since I've got zero on CAMSS so far, I
couldn't test it more than reading chip ID.

>
>> +
>> +	eeprom@52 {
>> +		compatible = "puya,p24c128f", "atmel,24c128";
>> +		reg = <0x52>;
>> +		vcc-supply = <&vreg_l6p>;
>> +		read-only;
>> +	};
>> +};
>> +
>> +&cci1 {
>> +	/* cci1_i2c0 is not used for CCI */
>> +	pinctrl-0 = <&cci1_1_default>;
>> +	pinctrl-1 = <&cci1_1_sleep>;
>
> Let's keep them per-bus-subnode so we don't have to override it

I don't see any upstream example of that, would the pinctrl work
correctly with that?

While this isn't necessarily pretty like that, it does work :)

>
> otherwise
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Thanks!

Regards
Luca

>
> Konrad

Re: [PATCH 4/4] arm64: dts: qcom: milos-fairphone-fp6: Add camera EEPROMs on CCI busses

[Konrad Dybcio]

On 1/16/26 3:54 PM, Luca Weiss wrote:
> On Fri Jan 16, 2026 at 2:59 PM CET, Konrad Dybcio wrote:
>> On 1/16/26 2:38 PM, Luca Weiss wrote:
>>> Enable the CCI I2C busses and add nodes for the EEPROMs found on the
>>> camera that are connected there.
>>>
>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>>> ---
>>>  arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 50 ++++++++++++++++++++++++
>>>  1 file changed, 50 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>>> index 7629ceddde2a..c4a706e945ba 100644
>>> --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>>> +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>>> @@ -529,6 +529,56 @@ vreg_l11f: ldo11 {
>>>  	};
>>>  };
>>>  
>>> +&cci0 {
>>> +	status = "okay";
>>> +};
>>> +
>>> +&cci0_i2c0 {
>>> +	/* Main cam: Sony IMX896 @ 0x1a */
>>> +
>>> +	eeprom@50 {
>>> +		compatible = "puya,p24c128f", "atmel,24c128";
>>> +		reg = <0x50>;
>>> +		vcc-supply = <&vreg_l6p>;
>>> +		read-only;
>>> +	};
>>> +
>>> +	/* Dongwoon DW9784 VCM/OIS @ 0x72 */
>>> +};
>>> +
>>> +
>>> +&cci0_i2c1 {
>>> +	/* Awinic AW86017 VCM @ 0x0c */
>>> +	/* UW cam: OmniVision OV13B10 @ 0x36 */
>>
>> There's a driver for this one!
> 
> Yep! Already got patches to add the required regulators & devicetree
> support to the driver, but since I've got zero on CAMSS so far, I
> couldn't test it more than reading chip ID.

That means the digital part works.. I'd say it's a good enough
indicator

>>> +
>>> +	eeprom@52 {
>>> +		compatible = "puya,p24c128f", "atmel,24c128";
>>> +		reg = <0x52>;
>>> +		vcc-supply = <&vreg_l6p>;
>>> +		read-only;
>>> +	};
>>> +};
>>> +
>>> +&cci1 {
>>> +	/* cci1_i2c0 is not used for CCI */
>>> +	pinctrl-0 = <&cci1_1_default>;
>>> +	pinctrl-1 = <&cci1_1_sleep>;
>>
>> Let's keep them per-bus-subnode so we don't have to override it
> 
> I don't see any upstream example of that, would the pinctrl work
> correctly with that?

Hmm.. I assumed it would.. and I assumed we do have examples but
ma-a-aybe they got stuck somewhere in the review purgatory?

If you'd be inclined to test that, you can add a pr_err() to e.g.
msm_pinmux_set_mux() and observe whether that changes as you
interact with the sensor over i2c

> While this isn't necessarily pretty like that, it does work :)

It's the right thing from the hw description standpoint.. we have
a huuuge amount of peripherals that fight for the same sets of pins
(which is part of the reason why you can't turn on all 30-some QUPs
by default, and depending on the function+QUPindex combo the pin
requirements differ)

Konrad

Re: [PATCH 4/4] arm64: dts: qcom: milos-fairphone-fp6: Add camera EEPROMs on CCI busses

[Luca Weiss]

On Mon Jan 19, 2026 at 11:42 AM CET, Konrad Dybcio wrote:
> On 1/16/26 3:54 PM, Luca Weiss wrote:
>> On Fri Jan 16, 2026 at 2:59 PM CET, Konrad Dybcio wrote:
>>> On 1/16/26 2:38 PM, Luca Weiss wrote:
>>>> Enable the CCI I2C busses and add nodes for the EEPROMs found on the
>>>> camera that are connected there.
>>>>
>>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>>>> ---
>>>>  arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 50 ++++++++++++++++++++++++
>>>>  1 file changed, 50 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>>>> index 7629ceddde2a..c4a706e945ba 100644
>>>> --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>>>> +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>>>> @@ -529,6 +529,56 @@ vreg_l11f: ldo11 {
>>>>  	};
>>>>  };
>>>>  
>>>> +&cci0 {
>>>> +	status = "okay";
>>>> +};
>>>> +
>>>> +&cci0_i2c0 {
>>>> +	/* Main cam: Sony IMX896 @ 0x1a */
>>>> +
>>>> +	eeprom@50 {
>>>> +		compatible = "puya,p24c128f", "atmel,24c128";
>>>> +		reg = <0x50>;
>>>> +		vcc-supply = <&vreg_l6p>;
>>>> +		read-only;
>>>> +	};
>>>> +
>>>> +	/* Dongwoon DW9784 VCM/OIS @ 0x72 */
>>>> +};
>>>> +
>>>> +
>>>> +&cci0_i2c1 {
>>>> +	/* Awinic AW86017 VCM @ 0x0c */
>>>> +	/* UW cam: OmniVision OV13B10 @ 0x36 */
>>>
>>> There's a driver for this one!
>> 
>> Yep! Already got patches to add the required regulators & devicetree
>> support to the driver, but since I've got zero on CAMSS so far, I
>> couldn't test it more than reading chip ID.
>
> That means the digital part works.. I'd say it's a good enough
> indicator
>
>>>> +
>>>> +	eeprom@52 {
>>>> +		compatible = "puya,p24c128f", "atmel,24c128";
>>>> +		reg = <0x52>;
>>>> +		vcc-supply = <&vreg_l6p>;
>>>> +		read-only;
>>>> +	};
>>>> +};
>>>> +
>>>> +&cci1 {
>>>> +	/* cci1_i2c0 is not used for CCI */
>>>> +	pinctrl-0 = <&cci1_1_default>;
>>>> +	pinctrl-1 = <&cci1_1_sleep>;
>>>
>>> Let's keep them per-bus-subnode so we don't have to override it
>> 
>> I don't see any upstream example of that, would the pinctrl work
>> correctly with that?
>
> Hmm.. I assumed it would.. and I assumed we do have examples but
> ma-a-aybe they got stuck somewhere in the review purgatory?
>
> If you'd be inclined to test that, you can add a pr_err() to e.g.
> msm_pinmux_set_mux() and observe whether that changes as you
> interact with the sensor over i2c

Yeah that doesn't work. With the following diff I just get some CCI
timeouts and at24 driver doesn't probe correctly. I'd prefer not to do
some yak shaving to get this patch upstream.

Regards
Luca

diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
index b6cd95fc294e..9f9410615aea 100644
--- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
+++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
@@ -671,10 +671,6 @@ eeprom@52 {
 };
 
 &cci1 {
-	/* cci1_i2c0 is not used for CCI */
-	pinctrl-0 = <&cci1_1_default>;
-	pinctrl-1 = <&cci1_1_sleep>;
-
 	status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
index adf050600a4e..a2438cf60271 100644
--- a/arch/arm64/boot/dts/qcom/milos.dtsi
+++ b/arch/arm64/boot/dts/qcom/milos.dtsi
@@ -1755,9 +1755,6 @@ cci0: cci@ac15000 {
 			clock-names = "soc_ahb",
 				      "cpas_ahb",
 				      "cci";
-			pinctrl-0 = <&cci0_0_default &cci0_1_default>;
-			pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
-			pinctrl-names = "default", "sleep";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -1765,6 +1762,9 @@ cci0: cci@ac15000 {
 			cci0_i2c0: i2c-bus@0 {
 				reg = <0>;
 				clock-frequency = <1000000>;
+				pinctrl-0 = <&cci0_0_default>;
+				pinctrl-1 = <&cci0_0_sleep>;
+				pinctrl-names = "default", "sleep";
 				#address-cells = <1>;
 				#size-cells = <0>;
 			};
@@ -1772,6 +1772,9 @@ cci0_i2c0: i2c-bus@0 {
 			cci0_i2c1: i2c-bus@1 {
 				reg = <1>;
 				clock-frequency = <1000000>;
+				pinctrl-0 = <&cci0_1_default>;
+				pinctrl-1 = <&cci0_1_sleep>;
+				pinctrl-names = "default", "sleep";
 				#address-cells = <1>;
 				#size-cells = <0>;
 			};
@@ -1788,9 +1791,6 @@ cci1: cci@ac16000 {
 			clock-names = "soc_ahb",
 				      "cpas_ahb",
 				      "cci";
-			pinctrl-0 = <&cci1_0_default &cci1_1_default>;
-			pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
-			pinctrl-names = "default", "sleep";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -1798,6 +1798,9 @@ cci1: cci@ac16000 {
 			cci1_i2c0: i2c-bus@0 {
 				reg = <0>;
 				clock-frequency = <1000000>;
+				pinctrl-0 = <&cci1_0_default>;
+				pinctrl-1 = <&cci1_0_sleep>;
+				pinctrl-names = "default", "sleep";
 				#address-cells = <1>;
 				#size-cells = <0>;
 			};
@@ -1805,6 +1808,9 @@ cci1_i2c0: i2c-bus@0 {
 			cci1_i2c1: i2c-bus@1 {
 				reg = <1>;
 				clock-frequency = <1000000>;
+				pinctrl-0 = <&cci1_1_default>;
+				pinctrl-1 = <&cci1_1_sleep>;
+				pinctrl-names = "default", "sleep";
 				#address-cells = <1>;
 				#size-cells = <0>;
 			};

Re: [PATCH 4/4] arm64: dts: qcom: milos-fairphone-fp6: Add camera EEPROMs on CCI busses

[Konrad Dybcio]

On 2/13/26 2:39 PM, Luca Weiss wrote:
> On Mon Jan 19, 2026 at 11:42 AM CET, Konrad Dybcio wrote:
>> On 1/16/26 3:54 PM, Luca Weiss wrote:
>>> On Fri Jan 16, 2026 at 2:59 PM CET, Konrad Dybcio wrote:
>>>> On 1/16/26 2:38 PM, Luca Weiss wrote:
>>>>> Enable the CCI I2C busses and add nodes for the EEPROMs found on the
>>>>> camera that are connected there.
>>>>>
>>>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>>>>> ---
>>>>>  arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 50 ++++++++++++++++++++++++
>>>>>  1 file changed, 50 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>>>>> index 7629ceddde2a..c4a706e945ba 100644
>>>>> --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>>>>> +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>>>>> @@ -529,6 +529,56 @@ vreg_l11f: ldo11 {
>>>>>  	};
>>>>>  };
>>>>>  
>>>>> +&cci0 {
>>>>> +	status = "okay";
>>>>> +};
>>>>> +
>>>>> +&cci0_i2c0 {
>>>>> +	/* Main cam: Sony IMX896 @ 0x1a */
>>>>> +
>>>>> +	eeprom@50 {
>>>>> +		compatible = "puya,p24c128f", "atmel,24c128";
>>>>> +		reg = <0x50>;
>>>>> +		vcc-supply = <&vreg_l6p>;
>>>>> +		read-only;
>>>>> +	};
>>>>> +
>>>>> +	/* Dongwoon DW9784 VCM/OIS @ 0x72 */
>>>>> +};
>>>>> +
>>>>> +
>>>>> +&cci0_i2c1 {
>>>>> +	/* Awinic AW86017 VCM @ 0x0c */
>>>>> +	/* UW cam: OmniVision OV13B10 @ 0x36 */
>>>>
>>>> There's a driver for this one!
>>>
>>> Yep! Already got patches to add the required regulators & devicetree
>>> support to the driver, but since I've got zero on CAMSS so far, I
>>> couldn't test it more than reading chip ID.
>>
>> That means the digital part works.. I'd say it's a good enough
>> indicator
>>
>>>>> +
>>>>> +	eeprom@52 {
>>>>> +		compatible = "puya,p24c128f", "atmel,24c128";
>>>>> +		reg = <0x52>;
>>>>> +		vcc-supply = <&vreg_l6p>;
>>>>> +		read-only;
>>>>> +	};
>>>>> +};
>>>>> +
>>>>> +&cci1 {
>>>>> +	/* cci1_i2c0 is not used for CCI */
>>>>> +	pinctrl-0 = <&cci1_1_default>;
>>>>> +	pinctrl-1 = <&cci1_1_sleep>;
>>>>
>>>> Let's keep them per-bus-subnode so we don't have to override it
>>>
>>> I don't see any upstream example of that, would the pinctrl work
>>> correctly with that?
>>
>> Hmm.. I assumed it would.. and I assumed we do have examples but
>> ma-a-aybe they got stuck somewhere in the review purgatory?
>>
>> If you'd be inclined to test that, you can add a pr_err() to e.g.
>> msm_pinmux_set_mux() and observe whether that changes as you
>> interact with the sensor over i2c
> 
> Yeah that doesn't work. With the following diff I just get some CCI
> timeouts and at24 driver doesn't probe correctly. I'd prefer not to do
> some yak shaving to get this patch upstream.

I think the setting happens somewhere near

drivers/base/dd.c : really_probe() : pinctrl_bind_pins()

which implies there would be a driver in play, which there isn't for the
CCI subnodes.. But let's kick that can down the road

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad