Re: [PATCH v4 11/14] iommu/amd: Introduce iommu_dev_data.ppr

[Vasant Hegde <vasant.hegde@amd.com>]

Jason,


On 8/16/2023 12:03 AM, Jason Gunthorpe wrote:
> On Tue, Aug 15, 2023 at 10:21:59AM +0000, Vasant Hegde wrote:
>> From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
>>
>> For AMD IOMMU, the PPR feature is needed to support IO page fault (IOPF).
>> PPR is enabled per PCI end-point device, and is configured by the PPR bit
>> in the IOMMU device table entry (i.e DTE[PPR]).
>>
>> Introducing struct iommu_dev_data.ppr track PPR setting for each device.
>>
>> Also iommu_dev_data.ppr will be set only when IOMMU supports PPR. Hence
>> remove redundant feature support check in set_dte_entry().
>>
>> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
>> Co-developed-by: Vasant Hegde <vasant.hegde@amd.com>
>> Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
>> ---
>>  drivers/iommu/amd/amd_iommu_types.h |  1 +
>>  drivers/iommu/amd/iommu.c           | 10 ++++------
>>  2 files changed, 5 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
>> index 1c61dca63824..c9027119ab35 100644
>> --- a/drivers/iommu/amd/amd_iommu_types.h
>> +++ b/drivers/iommu/amd/amd_iommu_types.h
>> @@ -816,6 +816,7 @@ struct iommu_dev_data {
>>  	u8 ats_enabled  :1;		  /* ATS state */
>>  	u8 pri_tlp      :1;		  /* PASID TLB required for
>>  					     PPR completions */
>> +	bool ppr;			  /* Enable device PPR support */
>>  	bool use_vapic;			  /* Enable device to use vapic mode */
>>  	bool defer_attach;
> 
> Linus would not like this if he saw it, continue using the u8 :1
> bitfield..

Sure. Will fix it.

> 
> Otherwise looks fine
> 
> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>

Thanks
-Vasant