From: Vasant Hegde via iommu <iommu@lists.linux-foundation.org>
To: <iommu@lists.linux-foundation.org>
Cc: Vasant Hegde <vasant.hegde@amd.com>
Subject: [PATCH v2 33/37] iommu/amd: Specify PCI segment ID when getting pci device
Date: Mon, 25 Apr 2022 17:04:11 +0530 [thread overview]
Message-ID: <20220425113415.24087-34-vasant.hegde@amd.com> (raw)
In-Reply-To: <20220425113415.24087-1-vasant.hegde@amd.com>
From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Upcoming AMD systems can have multiple PCI segments. Hence pass PCI
segment ID to pci_get_domain_bus_and_slot() instead of '0'.
Co-developed-by: Vasant Hegde <vasant.hegde@amd.com>
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
drivers/iommu/amd/init.c | 6 ++++--
drivers/iommu/amd/iommu.c | 19 ++++++++++---------
2 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index 4a9f424eb4b4..ccc0208d4b69 100644
--- a/drivers/iommu/amd/init.c
+++ b/drivers/iommu/amd/init.c
@@ -1961,7 +1961,8 @@ static int __init iommu_init_pci(struct amd_iommu *iommu)
int cap_ptr = iommu->cap_ptr;
int ret;
- iommu->dev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(iommu->devid),
+ iommu->dev = pci_get_domain_bus_and_slot(iommu->pci_seg->id,
+ PCI_BUS_NUM(iommu->devid),
iommu->devid & 0xff);
if (!iommu->dev)
return -ENODEV;
@@ -2024,7 +2025,8 @@ static int __init iommu_init_pci(struct amd_iommu *iommu)
int i, j;
iommu->root_pdev =
- pci_get_domain_bus_and_slot(0, iommu->dev->bus->number,
+ pci_get_domain_bus_and_slot(iommu->pci_seg->id,
+ iommu->dev->bus->number,
PCI_DEVFN(0, 0));
/*
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index 1e375d469280..46236fb05a1f 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -473,7 +473,7 @@ static void dump_command(unsigned long phys_addr)
pr_err("CMD[%d]: %08x\n", i, cmd->data[i]);
}
-static void amd_iommu_report_rmp_hw_error(volatile u32 *event)
+static void amd_iommu_report_rmp_hw_error(struct amd_iommu *iommu, volatile u32 *event)
{
struct iommu_dev_data *dev_data = NULL;
int devid, vmg_tag, flags;
@@ -485,7 +485,7 @@ static void amd_iommu_report_rmp_hw_error(volatile u32 *event)
flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
spa = ((u64)event[3] << 32) | (event[2] & 0xFFFFFFF8);
- pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
+ pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, PCI_BUS_NUM(devid),
devid & 0xff);
if (pdev)
dev_data = dev_iommu_priv_get(&pdev->dev);
@@ -505,7 +505,7 @@ static void amd_iommu_report_rmp_hw_error(volatile u32 *event)
pci_dev_put(pdev);
}
-static void amd_iommu_report_rmp_fault(volatile u32 *event)
+static void amd_iommu_report_rmp_fault(struct amd_iommu *iommu, volatile u32 *event)
{
struct iommu_dev_data *dev_data = NULL;
int devid, flags_rmp, vmg_tag, flags;
@@ -518,7 +518,7 @@ static void amd_iommu_report_rmp_fault(volatile u32 *event)
flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
gpa = ((u64)event[3] << 32) | event[2];
- pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
+ pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, PCI_BUS_NUM(devid),
devid & 0xff);
if (pdev)
dev_data = dev_iommu_priv_get(&pdev->dev);
@@ -544,13 +544,14 @@ static void amd_iommu_report_rmp_fault(volatile u32 *event)
#define IS_WRITE_REQUEST(flags) \
((flags) & EVENT_FLAG_RW)
-static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
+static void amd_iommu_report_page_fault(struct amd_iommu *iommu,
+ u16 devid, u16 domain_id,
u64 address, int flags)
{
struct iommu_dev_data *dev_data = NULL;
struct pci_dev *pdev;
- pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
+ pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, PCI_BUS_NUM(devid),
devid & 0xff);
if (pdev)
dev_data = dev_iommu_priv_get(&pdev->dev);
@@ -613,7 +614,7 @@ static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
}
if (type == EVENT_TYPE_IO_FAULT) {
- amd_iommu_report_page_fault(devid, pasid, address, flags);
+ amd_iommu_report_page_fault(iommu, devid, pasid, address, flags);
return;
}
@@ -654,10 +655,10 @@ static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
pasid, address, flags);
break;
case EVENT_TYPE_RMP_FAULT:
- amd_iommu_report_rmp_fault(event);
+ amd_iommu_report_rmp_fault(iommu, event);
break;
case EVENT_TYPE_RMP_HW_ERR:
- amd_iommu_report_rmp_hw_error(event);
+ amd_iommu_report_rmp_hw_error(iommu, event);
break;
case EVENT_TYPE_INV_PPR_REQ:
pasid = PPR_PASID(*((u64 *)__evt));
--
2.27.0
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
next prev parent reply other threads:[~2022-04-25 11:43 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-25 11:33 [PATCH v2 00/37] iommu/amd: Add multiple PCI segments support Vasant Hegde via iommu
2022-04-25 11:33 ` [PATCH v2 01/37] iommu/amd: Update struct iommu_dev_data defination Vasant Hegde via iommu
2022-04-28 9:55 ` Joerg Roedel
2022-04-29 14:34 ` Vasant Hegde via iommu
2022-04-25 11:33 ` [PATCH v2 02/37] iommu/amd: Introduce pci segment structure Vasant Hegde via iommu
2022-04-28 9:54 ` Joerg Roedel
2022-04-29 14:41 ` Vasant Hegde via iommu
2022-04-25 11:33 ` [PATCH v2 03/37] iommu/amd: Introduce per PCI segment device table Vasant Hegde via iommu
2022-04-25 11:33 ` [PATCH v2 04/37] iommu/amd: Introduce per PCI segment rlookup table Vasant Hegde via iommu
2022-04-25 11:33 ` [PATCH v2 05/37] iommu/amd: Introduce per PCI segment irq_lookup_table Vasant Hegde via iommu
2022-04-25 11:33 ` [PATCH v2 06/37] iommu/amd: Introduce per PCI segment dev_data_list Vasant Hegde via iommu
2022-04-25 11:33 ` [PATCH v2 07/37] iommu/amd: Introduce per PCI segment old_dev_tbl_cpy Vasant Hegde via iommu
2022-04-25 11:33 ` [PATCH v2 08/37] iommu/amd: Introduce per PCI segment alias_table Vasant Hegde via iommu
2022-04-25 11:33 ` [PATCH v2 09/37] iommu/amd: Introduce per PCI segment unity map list Vasant Hegde via iommu
2022-04-25 11:33 ` [PATCH v2 10/37] iommu/amd: Introduce per PCI segment last_bdf Vasant Hegde via iommu
2022-04-28 10:10 ` Joerg Roedel
2022-04-29 14:45 ` Vasant Hegde via iommu
2022-05-02 10:54 ` Joerg Roedel
2022-05-05 9:09 ` Vasant Hegde via iommu
2022-04-25 11:33 ` [PATCH v2 11/37] iommu/amd: Introduce per PCI segment device table size Vasant Hegde via iommu
2022-04-28 10:14 ` Joerg Roedel
2022-04-25 11:33 ` [PATCH v2 12/37] iommu/amd: Introduce per PCI segment alias " Vasant Hegde via iommu
2022-04-25 11:33 ` [PATCH v2 13/37] iommu/amd: Introduce per PCI segment rlookup " Vasant Hegde via iommu
2022-04-25 11:33 ` [PATCH v2 14/37] iommu/amd: Convert to use per PCI segment irq_lookup_table Vasant Hegde via iommu
2022-04-25 11:33 ` [PATCH v2 15/37] iommu/amd: Convert to use rlookup_amd_iommu helper function Vasant Hegde via iommu
2022-04-25 11:33 ` [PATCH v2 16/37] iommu/amd: Update irq_remapping_alloc to use IOMMU lookup " Vasant Hegde via iommu
2022-04-25 11:33 ` [PATCH v2 17/37] iommu/amd: Introduce struct amd_ir_data.iommu Vasant Hegde via iommu
2022-04-25 11:33 ` [PATCH v2 18/37] iommu/amd: Update amd_irte_ops functions Vasant Hegde via iommu
2022-04-25 11:33 ` [PATCH v2 19/37] iommu/amd: Update alloc_irq_table and alloc_irq_index Vasant Hegde via iommu
2022-04-25 11:33 ` [PATCH v2 20/37] iommu/amd: Convert to use per PCI segment rlookup_table Vasant Hegde via iommu
2022-04-25 11:33 ` [PATCH v2 21/37] iommu/amd: Update set_dte_entry and clear_dte_entry Vasant Hegde via iommu
2022-04-25 11:34 ` [PATCH v2 22/37] iommu/amd: Update iommu_ignore_device Vasant Hegde via iommu
2022-04-25 11:34 ` [PATCH v2 23/37] iommu/amd: Update dump_dte_entry Vasant Hegde via iommu
2022-04-25 11:34 ` [PATCH v2 24/37] iommu/amd: Update set_dte_irq_entry Vasant Hegde via iommu
2022-04-25 11:34 ` [PATCH v2 25/37] iommu/amd: Update (un)init_device_table_dma() Vasant Hegde via iommu
2022-04-25 11:34 ` [PATCH v2 26/37] iommu/amd: Update set_dev_entry_bit() and get_dev_entry_bit() Vasant Hegde via iommu
2022-04-25 11:34 ` [PATCH v2 27/37] iommu/amd: Remove global amd_iommu_dev_table Vasant Hegde via iommu
2022-04-28 10:15 ` Joerg Roedel
2022-04-29 14:39 ` Vasant Hegde via iommu
2022-04-25 11:34 ` [PATCH v2 28/37] iommu/amd: Remove global amd_iommu_alias_table Vasant Hegde via iommu
2022-04-25 11:34 ` [PATCH v2 29/37] iommu/amd: Remove global amd_iommu_last_bdf Vasant Hegde via iommu
2022-04-25 11:34 ` [PATCH v2 30/37] iommu/amd: Flush upto last_bdf only Vasant Hegde via iommu
2022-04-25 11:34 ` [PATCH v2 31/37] iommu/amd: Introduce get_device_sbdf_id() helper function Vasant Hegde via iommu
2022-04-25 11:34 ` [PATCH v2 32/37] iommu/amd: Include PCI segment ID when initialize IOMMU Vasant Hegde via iommu
2022-04-25 11:34 ` Vasant Hegde via iommu [this message]
2022-04-25 11:34 ` [PATCH v2 34/37] iommu/amd: Add PCI segment support for ivrs_ioapic, ivrs_hpet, ivrs_acpihid commands Vasant Hegde via iommu
2022-04-25 11:34 ` [PATCH v2 35/37] iommu/amd: Print PCI segment ID in error log messages Vasant Hegde via iommu
2022-04-25 11:34 ` [PATCH v2 36/37] iommu/amd: Update device_state structure to include PCI seg ID Vasant Hegde via iommu
2022-04-25 11:34 ` [PATCH v2 37/37] iommu/amd: Update amd_iommu_fault " Vasant Hegde via iommu
2022-04-28 10:19 ` Joerg Roedel
2022-04-29 14:37 ` Vasant Hegde via iommu
2022-04-28 10:22 ` [PATCH v2 00/37] iommu/amd: Add multiple PCI segments support Joerg Roedel
2022-04-29 14:35 ` Vasant Hegde via iommu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220425113415.24087-34-vasant.hegde@amd.com \
--to=iommu@lists.linux-foundation.org \
--cc=vasant.hegde@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox