From: Jason Gunthorpe <jgg@nvidia.com>
To: Vasant Hegde <vasant.hegde@amd.com>
Cc: Baolu Lu <baolu.lu@linux.intel.com>,
"Deucher, Alexander" <Alexander.Deucher@amd.com>,
"iommu@lists.linux.dev" <iommu@lists.linux.dev>,
"joro@8bytes.org" <joro@8bytes.org>,
"Suthikulpanit, Suravee" <Suravee.Suthikulpanit@amd.com>,
"Huang2, Wei" <Wei.Huang2@amd.com>,
"jsnitsel@redhat.com" <jsnitsel@redhat.com>,
"Kuehling, Felix" <Felix.Kuehling@amd.com>
Subject: Re: [PATCH v3 1/5] iommu/amd: Remove iommu_v2 module
Date: Mon, 25 Sep 2023 12:57:09 -0300 [thread overview]
Message-ID: <20230925155709.GG13733@nvidia.com> (raw)
In-Reply-To: <c7014abb-2c8e-fc3f-5cae-75060c8dcaf5@amd.com>
On Mon, Sep 25, 2023 at 08:41:41PM +0530, Vasant Hegde wrote:
> Jason,
>
> On 9/22/2023 5:30 PM, Jason Gunthorpe wrote:
> > On Fri, Sep 22, 2023 at 02:22:11PM +0530, Vasant Hegde wrote:
> >>> 2) PCI device supports ATS and PASID
> >>> In this case, ATS is required for PRI, so we should enable it even if
> >>> the default domain has been configured to PASSTHROUGH mode.
> >>
> >> IMO we should enable ATS along with enable_feature(PRI).
> >
> > Definately not. ATS is valuable and importnat without PRI.
>
> I get that. But I am not sure whether I understood the usecase when domain is in
> passthrough mode. Do you have any usecase to enable ATS when device is in pass
> through mode?
Yes, we can have the main device functionality running in passthrough
and still support SVA on a PASID. This requires ATS to be globally on
for the function.
Jason
next prev parent reply other threads:[~2023-09-25 15:57 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-21 9:31 [PATCH v3 0/5] iommu/amd: SVA Support (part 2) - deprecate iommu_v2 module Vasant Hegde
2023-09-21 9:31 ` [PATCH v3 1/5] iommu/amd: Remove " Vasant Hegde
2023-09-21 14:05 ` Deucher, Alexander
2023-09-21 14:14 ` Jason Gunthorpe
2023-09-21 15:15 ` Deucher, Alexander
2023-09-21 16:31 ` Jason Gunthorpe
2023-09-22 2:23 ` Baolu Lu
2023-09-22 8:52 ` Vasant Hegde
2023-09-22 12:00 ` Jason Gunthorpe
2023-09-25 15:11 ` Vasant Hegde
2023-09-25 15:57 ` Jason Gunthorpe [this message]
2023-09-25 16:31 ` Deucher, Alexander
2023-09-25 16:37 ` Jason Gunthorpe
2023-09-22 11:59 ` Jason Gunthorpe
2023-09-22 12:13 ` Baolu Lu
2023-09-22 12:18 ` Jason Gunthorpe
2023-09-22 12:42 ` Baolu Lu
2023-09-22 12:43 ` Jason Gunthorpe
2023-09-25 9:04 ` joro
2023-09-25 15:40 ` Vasant Hegde
2023-09-28 14:52 ` Deucher, Alexander
2023-10-05 11:29 ` Vasant Hegde
2023-10-06 15:19 ` Deucher, Alexander
2023-09-22 18:08 ` Deucher, Alexander
2023-09-22 18:15 ` Deucher, Alexander
2023-09-22 6:45 ` Vasant Hegde
2023-09-22 18:13 ` Deucher, Alexander
2023-09-25 15:30 ` Vasant Hegde
2023-09-21 9:31 ` [PATCH v3 2/5] iommu/amd: Remove PPR support Vasant Hegde
2023-09-21 9:31 ` [PATCH v3 3/5] iommu/amd: Remove amd_iommu_device_info() Vasant Hegde
2023-09-21 9:31 ` [PATCH v3 4/5] iommu/amd: Remove unused EXPORT_SYMBOLS Vasant Hegde
2023-09-21 9:31 ` [PATCH v3 5/5] Revert "iommu: Fix false ownership failure on AMD systems with PASID activated" Vasant Hegde
2023-10-02 6:32 ` [PATCH v3 0/5] iommu/amd: SVA Support (part 2) - deprecate iommu_v2 module Joerg Roedel
2023-10-05 11:30 ` Vasant Hegde
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