Re: [PATCH v3 1/5] iommu/amd: Remove iommu_v2 module

[Jason Gunthorpe <jgg@nvidia.com>]

On Mon, Sep 25, 2023 at 04:31:50PM +0000, Deucher, Alexander wrote:

> > On 9/22/2023 5:30 PM, Jason Gunthorpe wrote:
> > > On Fri, Sep 22, 2023 at 02:22:11PM +0530, Vasant Hegde wrote:
> > >>> 2) PCI device supports ATS and PASID
> > >>>    In this case, ATS is required for PRI, so we should enable it
> > >>> even if
> > >>>    the default domain has been configured to PASSTHROUGH mode.
> > >>
> > >> IMO we should enable ATS along with enable_feature(PRI).
> > >
> > > Definately not. ATS is valuable and importnat without PRI.
> >
> > I get that. But I am not sure whether I understood the usecase when domain is
> > in passthrough mode. Do you have any usecase to enable ATS when device is
> > in pass through mode?
> 
> It should still reduce latency.  Even in 1:1 mode, there is still an
> address lookup that can be cached.

Oh, on a lot of devices the ATS bits just enable device's PCI to issue
ATS, it doesn't mean that *every* operation has to be ATS.

So the non-SVA transactions can freely run in non-ATS mode with 1:1
while only SVA operations use ATS.

IIRC most IOMMU still have a lookup for a translated request to
validate that the RID is authorized to use them. So there is no
savings, just overhead.

Jason