From: Jason Gunthorpe <jgg@ziepe.ca>
To: Vasant Hegde <vasant.hegde@amd.com>
Cc: iommu@lists.linux.dev, joro@8bytes.org,
suravee.suthikulpanit@amd.com, wei.huang2@amd.com,
jsnitsel@redhat.com
Subject: Re: [PATCH v5 12/14] iommu/amd: Initial SVA support for AMD IOMMU
Date: Fri, 2 Feb 2024 11:25:24 -0400 [thread overview]
Message-ID: <20240202152524.GA2606743@ziepe.ca> (raw)
In-Reply-To: <20240118073339.6978-13-vasant.hegde@amd.com>
On Thu, Jan 18, 2024 at 07:33:37AM +0000, Vasant Hegde wrote:
> +static int iommu_pasid_enable(struct iommu_dev_data *dev_data)
> +{
> + struct device *dev = dev_data->dev;
> + int ret = 0;
> +
> + spin_lock(&dev_data->lock);
> +
> + if (is_pasid_enabled(dev_data))
> + goto out;
> +
> + if (!amd_iommu_pasid_supported()) {
> + ret = -ENODEV;
> + goto out;
> + }
> +
> + /* attach_device path enables device PASID feature */
> + if (!dev_data->pasid_enabled) {
How many times are we testing for this? Just check if the gcr3 table
is installed once
> + ret = -EINVAL;
> + goto out;
> + }
> +
> + ret = amd_iommu_gcr3_init(dev_data, dev->iommu->max_pasids);
> +
> +out:
> + spin_unlock(&dev_data->lock);
> + return ret;
> +}
This seems like too much, and it doesn't need to be in a function..
1) Check directly if the gcr3 table is installed otherwise try to
install it. That might be a usefull function
2) Precompute the max pasids during device probe and store it in
iommu_dev_data. Just check if PASID >= max_pasid and fail
> +static void iommu_pasid_disable(struct iommu_dev_data *dev_data)
> +{
> + spin_lock(&dev_data->lock);
> +
> + if (!is_gcr3_table_empty(dev_data))
> + goto out;
Caller already checked this
> +
> + if (dev_data->gcr3_info.gcr3_tbl == NULL)
> + goto out;
Can't happen, right?
> +
> + amd_iommu_gcr3_uninit(dev_data);
Just write it out clearly in remove dev pasid
if (is_gcr3_table_empty(dev_data))
amd_iommu_gcr3_uninit(dev_data);
> +static int iommu_setup_pasid_pri(struct iommu_dev_data *dev_data)
> +{
> + struct pci_dev *pdev;
> + int ret;
> +
> + if (is_pasid_enabled(dev_data))
> + return 0;
> +
> + ret = iommu_pasid_enable(dev_data);
> + if (ret)
> + return ret;
> +
> + pdev = dev_is_pci(dev_data->dev) ? to_pci_dev(dev_data->dev) : NULL;
> + if (!pdev || !amd_iommu_pdev_pri_supported(pdev))
> + return 0;
> +
> + if (!dev_data->pri_enabled)
> + return -EINVAL;
> +
> + ret = amd_iommu_iopf_enable_device(dev_data->dev);
> +
> + return ret;
> +}
> +
> +static void remove_dev_pasid(struct pdom_dev_data *pdom_dev_data)
> +{
> + /* Update GCR3 table and flush IOTLB */
> + amd_iommu_clear_gcr3(pdom_dev_data->dev_data, pdom_dev_data->pasid);
This is in the wrong place, there is only one DTE/GCR3 remove_dev is
touching. The list iteration below is just to clean up the tracking
list it should not touch HW. Move this up into
amd_iommu_remove_dev_pasid.
And these functions related to the tracking list should be more
general and called in more places. Just the tracking list itself
should have a few patches to create it and situate it generically in
the driver. Even the RID should be using the same mechanism.
> +int iommu_sva_set_dev_pasid(struct iommu_domain *domain,
> + struct device *dev, ioasid_t pasid)
> +{
> + struct pdom_dev_data *pdom_dev_data;
> + struct protection_domain *sva_pdom = to_pdomain(domain);
> + struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev);
> + unsigned long flags;
> + int ret = -EINVAL;
> +
> + /* PASID zero is used for requests from the I/O device without PASID */
> + if (pasid == 0 || pasid >= dev->iommu->max_pasids)
> + return ret;
> +
> + /* Make sure PASID/PRI is enabled */
> + ret = iommu_setup_pasid_pri(dev_data);
> + if (ret)
> + return ret;
> +
> + /* Add PASID to protection domain pasid list */
> + pdom_dev_data = kzalloc(sizeof(*pdom_dev_data), GFP_KERNEL);
> + if (pdom_dev_data == NULL)
> + return ret;
> +
> + pdom_dev_data->pasid = pasid;
> + pdom_dev_data->dev_data = dev_data;
> +
> + /* Setup GCR3 table */
> + ret = amd_iommu_set_gcr3(dev_data, pasid,
> + iommu_virt_to_phys(domain->mm->pgd));
> + if (ret) {
> + kfree(pdom_dev_data);
> + return ret;
> + }
> +
> + spin_lock_irqsave(&sva_pdom->lock, flags);
> + list_add(&pdom_dev_data->list, &sva_pdom->dev_data_list);
> + spin_unlock_irqrestore(&sva_pdom->lock, flags);
This doesn't seem right? The tracking list should be loaded before any
change is made visible to the HW, or at least under the same lock.
Jason
next prev parent reply other threads:[~2024-02-02 15:25 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-18 7:33 [PATCH v5 00/14] iommu/amd: SVA Support (Part 4) - SVA and IOPF Vasant Hegde
2024-01-18 7:33 ` [PATCH v5 01/14] iommu/amd: Rename amd_iommu_v2_supported() as amd_iommu_pasid_supported() Vasant Hegde
2024-01-18 7:33 ` [PATCH v5 02/14] iommu/amd: Introduce per device DTE update function Vasant Hegde
2024-02-02 15:29 ` Jason Gunthorpe
2024-01-18 7:33 ` [PATCH v5 03/14] iommu/amd: Add support for enabling/disabling IOMMU features Vasant Hegde
2024-01-18 7:33 ` [PATCH v5 04/14] iommu/amd: Move PPR-related functions into ppr.c Vasant Hegde
2024-02-02 15:29 ` Jason Gunthorpe
2024-01-18 7:33 ` [PATCH v5 05/14] iommu/amd: Fix PPR interrupt processing logic Vasant Hegde
2024-02-02 15:30 ` Jason Gunthorpe
2024-01-18 7:33 ` [PATCH v5 06/14] iommu/amd: Define per-IOMMU iopf_queue Vasant Hegde
2024-02-02 15:30 ` Jason Gunthorpe
2024-01-18 7:33 ` [PATCH v5 07/14] iommu/amd: Add support for page response Vasant Hegde
2024-02-01 20:20 ` Jason Gunthorpe
2024-02-06 15:39 ` Vasant Hegde
2024-01-18 7:33 ` [PATCH v5 08/14] iommu/amd: Add support for add/remove device for IOPF Vasant Hegde
2024-02-01 21:46 ` Jason Gunthorpe
2024-02-06 16:02 ` Vasant Hegde
2024-01-18 7:33 ` [PATCH v5 09/14] iommu/amd: Add IO page fault notifier handler Vasant Hegde
2024-01-18 7:33 ` [PATCH v5 10/14] iommu/amd: Introduce logic to enable/disable IOPF Vasant Hegde
2024-02-01 21:49 ` Jason Gunthorpe
2024-02-06 16:19 ` Vasant Hegde
2024-02-06 16:36 ` Jason Gunthorpe
2024-02-06 17:29 ` Vasant Hegde
2024-02-06 17:58 ` Jason Gunthorpe
2024-02-07 8:58 ` Vasant Hegde
2024-02-07 12:36 ` Baolu Lu
2024-02-07 18:00 ` Vasant Hegde
2024-02-08 17:31 ` Jason Gunthorpe
2024-02-08 18:37 ` Vasant Hegde
2024-02-08 19:03 ` Jason Gunthorpe
2024-01-18 7:33 ` [PATCH v5 11/14] iommu/amd: Add GCR3 [un]initialization function Vasant Hegde
2024-02-02 15:17 ` Jason Gunthorpe
2024-02-06 17:00 ` Vasant Hegde
2024-01-18 7:33 ` [PATCH v5 12/14] iommu/amd: Initial SVA support for AMD IOMMU Vasant Hegde
2024-02-02 15:25 ` Jason Gunthorpe [this message]
2024-02-06 17:16 ` Vasant Hegde
2024-02-06 17:34 ` Jason Gunthorpe
2024-02-07 9:31 ` Vasant Hegde
2024-02-08 17:41 ` Jason Gunthorpe
2024-02-08 18:23 ` Vasant Hegde
2024-02-08 18:48 ` Jason Gunthorpe
2024-01-18 7:33 ` [PATCH v5 13/14] iommu: Add ops->domain_alloc_sva() Vasant Hegde
2024-01-18 7:33 ` [PATCH v5 14/14] iommu/amd: Add SVA domain support Vasant Hegde
2024-02-02 15:28 ` Jason Gunthorpe
2024-01-18 7:40 ` [PATCH v5 00/14] iommu/amd: SVA Support (Part 4) - SVA and IOPF Vasant Hegde
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