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From: Jason Gunthorpe <jgg@ziepe.ca>
To: Vasant Hegde <vasant.hegde@amd.com>
Cc: iommu@lists.linux.dev, joro@8bytes.org,
	suravee.suthikulpanit@amd.com, wei.huang2@amd.com,
	jsnitsel@redhat.com
Subject: Re: [PATCH v5 10/14] iommu/amd: Introduce logic to enable/disable IOPF
Date: Thu, 8 Feb 2024 15:03:33 -0400	[thread overview]
Message-ID: <20240208190333.GY31743@ziepe.ca> (raw)
In-Reply-To: <beee7947-9c1a-95b6-66d7-88e130fd2956@amd.com>

On Fri, Feb 09, 2024 at 12:07:16AM +0530, Vasant Hegde wrote:
> On 2/8/2024 11:01 PM, Jason Gunthorpe wrote:
> > On Wed, Feb 07, 2024 at 02:28:08PM +0530, Vasant Hegde wrote:
> > 
> >>> You already know what is going to happen at the very start of attach,
> >>> you don't need to "enable it after" just do it right the first time
> >>> through.
> >>
> >> First time we will not know whether device will actually use fault handler or
> >> not. All we will know is whether IOMMU and device is capable of PRI or not.
> > 
> > I don't understand this, you should know all of this before you get to
> > setting the DTE. What is missing?
> 
> In attach path we will know the device capabilities (like PRI) but we will not
> know whether device is going to use it or not. Its like device has capability,
> let us enable it without assuming device may use it.

I don't understand "device may use it"

At domain pasid attach time you have the domain being attached and
information the device capabilities.

The decision is simple, if the domain is using PRI and the device
supports PRI you enable PRI.

This means you enable PRI when you attach the first PRI domain to the
GCR3, which will require rewriting the DTE during set_dev_pasid.

This is part of the same logical flow where you'd rewrite the DTE
during set_dev_pasid to do things like IDENTITY and BLOCKING RID
support.

> >> If I have to enable PRI in attach path then I don't need to track number of
> >> domain stuff. I can simply do something like
> >> 	if (pdom_is_sva_capable(pdom))
> >> 		// enable PRI in IOMMU
> >> 		// enable device PRI
> >>
> >> and in detach path,
> >> 	if (PRI is enabled)
> >> 		// disable IOMMU/device PRI stuff
> > 
> > Each PASID can have PRI on or not, so you need to keep track of how
> > many PASIDs are using PRI at any moment and keep things in sync that
> > way.
> > 
> > If there are no PRI handlers installed then the PCI config space
> > should disable PRI and all the PRI bits flushed and disabled.
> 
> If we don't have handler then PRI is disabled in attach device path only.
>
> So in detach path, if number of PASIDs are zero then we are good to disable PRI
> (at least for the current usage model).

So this is why you are having the problem above, the PRI logic should
not be in the attach_dev path because that does not take in a PRI
capable domaine (currently only SVA)

It should be triggered in set_dev_pasid and remove_dev_pasid.

I'm trying to get you to organize things so they are ready for the
next steps and things are not in the wrong spot.

Jason

  reply	other threads:[~2024-02-08 19:03 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-18  7:33 [PATCH v5 00/14] iommu/amd: SVA Support (Part 4) - SVA and IOPF Vasant Hegde
2024-01-18  7:33 ` [PATCH v5 01/14] iommu/amd: Rename amd_iommu_v2_supported() as amd_iommu_pasid_supported() Vasant Hegde
2024-01-18  7:33 ` [PATCH v5 02/14] iommu/amd: Introduce per device DTE update function Vasant Hegde
2024-02-02 15:29   ` Jason Gunthorpe
2024-01-18  7:33 ` [PATCH v5 03/14] iommu/amd: Add support for enabling/disabling IOMMU features Vasant Hegde
2024-01-18  7:33 ` [PATCH v5 04/14] iommu/amd: Move PPR-related functions into ppr.c Vasant Hegde
2024-02-02 15:29   ` Jason Gunthorpe
2024-01-18  7:33 ` [PATCH v5 05/14] iommu/amd: Fix PPR interrupt processing logic Vasant Hegde
2024-02-02 15:30   ` Jason Gunthorpe
2024-01-18  7:33 ` [PATCH v5 06/14] iommu/amd: Define per-IOMMU iopf_queue Vasant Hegde
2024-02-02 15:30   ` Jason Gunthorpe
2024-01-18  7:33 ` [PATCH v5 07/14] iommu/amd: Add support for page response Vasant Hegde
2024-02-01 20:20   ` Jason Gunthorpe
2024-02-06 15:39     ` Vasant Hegde
2024-01-18  7:33 ` [PATCH v5 08/14] iommu/amd: Add support for add/remove device for IOPF Vasant Hegde
2024-02-01 21:46   ` Jason Gunthorpe
2024-02-06 16:02     ` Vasant Hegde
2024-01-18  7:33 ` [PATCH v5 09/14] iommu/amd: Add IO page fault notifier handler Vasant Hegde
2024-01-18  7:33 ` [PATCH v5 10/14] iommu/amd: Introduce logic to enable/disable IOPF Vasant Hegde
2024-02-01 21:49   ` Jason Gunthorpe
2024-02-06 16:19     ` Vasant Hegde
2024-02-06 16:36       ` Jason Gunthorpe
2024-02-06 17:29         ` Vasant Hegde
2024-02-06 17:58           ` Jason Gunthorpe
2024-02-07  8:58             ` Vasant Hegde
2024-02-07 12:36               ` Baolu Lu
2024-02-07 18:00                 ` Vasant Hegde
2024-02-08 17:31               ` Jason Gunthorpe
2024-02-08 18:37                 ` Vasant Hegde
2024-02-08 19:03                   ` Jason Gunthorpe [this message]
2024-01-18  7:33 ` [PATCH v5 11/14] iommu/amd: Add GCR3 [un]initialization function Vasant Hegde
2024-02-02 15:17   ` Jason Gunthorpe
2024-02-06 17:00     ` Vasant Hegde
2024-01-18  7:33 ` [PATCH v5 12/14] iommu/amd: Initial SVA support for AMD IOMMU Vasant Hegde
2024-02-02 15:25   ` Jason Gunthorpe
2024-02-06 17:16     ` Vasant Hegde
2024-02-06 17:34       ` Jason Gunthorpe
2024-02-07  9:31         ` Vasant Hegde
2024-02-08 17:41           ` Jason Gunthorpe
2024-02-08 18:23             ` Vasant Hegde
2024-02-08 18:48               ` Jason Gunthorpe
2024-01-18  7:33 ` [PATCH v5 13/14] iommu: Add ops->domain_alloc_sva() Vasant Hegde
2024-01-18  7:33 ` [PATCH v5 14/14] iommu/amd: Add SVA domain support Vasant Hegde
2024-02-02 15:28   ` Jason Gunthorpe
2024-01-18  7:40 ` [PATCH v5 00/14] iommu/amd: SVA Support (Part 4) - SVA and IOPF Vasant Hegde

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