From: Vasant Hegde <vasant.hegde@amd.com>
To: Jason Gunthorpe <jgg@ziepe.ca>
Cc: iommu@lists.linux.dev, joro@8bytes.org,
suravee.suthikulpanit@amd.com, wei.huang2@amd.com,
jsnitsel@redhat.com
Subject: Re: [PATCH v5 10/14] iommu/amd: Introduce logic to enable/disable IOPF
Date: Tue, 6 Feb 2024 22:59:03 +0530 [thread overview]
Message-ID: <873201d4-57d1-e856-87c8-08e2ca71f0a2@amd.com> (raw)
In-Reply-To: <20240206163657.GG31743@ziepe.ca>
Jason,
On 2/6/2024 10:06 PM, Jason Gunthorpe wrote:
> On Tue, Feb 06, 2024 at 09:49:36PM +0530, Vasant Hegde wrote:
>
>>> This dte change is in the wrong place. When the domain is first
>>> attached we know if it requires PRI or not. At that moment the DTE
>>> should be set properly, it should not be set wrong and then changed
>>> later.
>>
>> We want to enable PPR support only after setting up the handler.
>
> That's backwards. It means error handling can't really be sane..
Why do you think enabling feature only when we are really going to use it backwards?
>
>>> (and again the whole dte setting flow needs cleaning, I think you
>>> should do that before trying to build more complex stuff on top)
>>
>> Yeah. I want to fix few things in that path. But that's outside this series.
>
> I was looking at it and there are many security bugs in here now that
> iommufd can change the DTE at any time. The current design assumes DMA
> will be stopped and ignores the spec guidance on how to do a safe DTE
> update :(
What security issues are you referring? Can you elaborate?
>
> I'm really not comfortable with adding more stuff here until the
> security issue is solved. Especially if the more stuff is drifting
> further from being correct. If you can keep the updates in set_dte
> then maybe with some reluctance. But not like this with random touches
> to the DTE all over the place.
Currently all DTE update is happening inside set_dte only (dirty bit enable is
an exception that may need to moved inside set_dte). This patch just invokes
that set_dte and invalidates cache.
-Vasant
>
> I was looking at what it would take and got part way through. It is a
> very similar problem to ARM and I drafted a similar solution.
>
> Jason
next prev parent reply other threads:[~2024-02-06 17:29 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-18 7:33 [PATCH v5 00/14] iommu/amd: SVA Support (Part 4) - SVA and IOPF Vasant Hegde
2024-01-18 7:33 ` [PATCH v5 01/14] iommu/amd: Rename amd_iommu_v2_supported() as amd_iommu_pasid_supported() Vasant Hegde
2024-01-18 7:33 ` [PATCH v5 02/14] iommu/amd: Introduce per device DTE update function Vasant Hegde
2024-02-02 15:29 ` Jason Gunthorpe
2024-01-18 7:33 ` [PATCH v5 03/14] iommu/amd: Add support for enabling/disabling IOMMU features Vasant Hegde
2024-01-18 7:33 ` [PATCH v5 04/14] iommu/amd: Move PPR-related functions into ppr.c Vasant Hegde
2024-02-02 15:29 ` Jason Gunthorpe
2024-01-18 7:33 ` [PATCH v5 05/14] iommu/amd: Fix PPR interrupt processing logic Vasant Hegde
2024-02-02 15:30 ` Jason Gunthorpe
2024-01-18 7:33 ` [PATCH v5 06/14] iommu/amd: Define per-IOMMU iopf_queue Vasant Hegde
2024-02-02 15:30 ` Jason Gunthorpe
2024-01-18 7:33 ` [PATCH v5 07/14] iommu/amd: Add support for page response Vasant Hegde
2024-02-01 20:20 ` Jason Gunthorpe
2024-02-06 15:39 ` Vasant Hegde
2024-01-18 7:33 ` [PATCH v5 08/14] iommu/amd: Add support for add/remove device for IOPF Vasant Hegde
2024-02-01 21:46 ` Jason Gunthorpe
2024-02-06 16:02 ` Vasant Hegde
2024-01-18 7:33 ` [PATCH v5 09/14] iommu/amd: Add IO page fault notifier handler Vasant Hegde
2024-01-18 7:33 ` [PATCH v5 10/14] iommu/amd: Introduce logic to enable/disable IOPF Vasant Hegde
2024-02-01 21:49 ` Jason Gunthorpe
2024-02-06 16:19 ` Vasant Hegde
2024-02-06 16:36 ` Jason Gunthorpe
2024-02-06 17:29 ` Vasant Hegde [this message]
2024-02-06 17:58 ` Jason Gunthorpe
2024-02-07 8:58 ` Vasant Hegde
2024-02-07 12:36 ` Baolu Lu
2024-02-07 18:00 ` Vasant Hegde
2024-02-08 17:31 ` Jason Gunthorpe
2024-02-08 18:37 ` Vasant Hegde
2024-02-08 19:03 ` Jason Gunthorpe
2024-01-18 7:33 ` [PATCH v5 11/14] iommu/amd: Add GCR3 [un]initialization function Vasant Hegde
2024-02-02 15:17 ` Jason Gunthorpe
2024-02-06 17:00 ` Vasant Hegde
2024-01-18 7:33 ` [PATCH v5 12/14] iommu/amd: Initial SVA support for AMD IOMMU Vasant Hegde
2024-02-02 15:25 ` Jason Gunthorpe
2024-02-06 17:16 ` Vasant Hegde
2024-02-06 17:34 ` Jason Gunthorpe
2024-02-07 9:31 ` Vasant Hegde
2024-02-08 17:41 ` Jason Gunthorpe
2024-02-08 18:23 ` Vasant Hegde
2024-02-08 18:48 ` Jason Gunthorpe
2024-01-18 7:33 ` [PATCH v5 13/14] iommu: Add ops->domain_alloc_sva() Vasant Hegde
2024-01-18 7:33 ` [PATCH v5 14/14] iommu/amd: Add SVA domain support Vasant Hegde
2024-02-02 15:28 ` Jason Gunthorpe
2024-01-18 7:40 ` [PATCH v5 00/14] iommu/amd: SVA Support (Part 4) - SVA and IOPF Vasant Hegde
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=873201d4-57d1-e856-87c8-08e2ca71f0a2@amd.com \
--to=vasant.hegde@amd.com \
--cc=iommu@lists.linux.dev \
--cc=jgg@ziepe.ca \
--cc=joro@8bytes.org \
--cc=jsnitsel@redhat.com \
--cc=suravee.suthikulpanit@amd.com \
--cc=wei.huang2@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox