From: Jason Gunthorpe <jgg@nvidia.com>
To: "Tian, Kevin" <kevin.tian@intel.com>
Cc: Lu Baolu <baolu.lu@linux.intel.com>,
David Woodhouse <dwmw2@infradead.org>,
"iommu@lists.linux.dev" <iommu@lists.linux.dev>,
Joerg Roedel <joro@8bytes.org>,
Robin Murphy <robin.murphy@arm.com>,
Will Deacon <will@kernel.org>,
"patches@lists.linux.dev" <patches@lists.linux.dev>,
Tina Zhang <tina.zhang@intel.com>,
"Wang, Wei W" <wei.w.wang@intel.com>
Subject: Re: [PATCH 7/9] iommupt/x86: Support SW bits and permit PT_FEAT_DMA_INCOHERENT
Date: Fri, 22 Aug 2025 11:55:10 -0300 [thread overview]
Message-ID: <20250822145510.GB1405994@nvidia.com> (raw)
In-Reply-To: <BN9PR11MB5276C6E52E069F5E2D608CEE8C3DA@BN9PR11MB5276.namprd11.prod.outlook.com>
On Fri, Aug 22, 2025 at 09:17:32AM +0000, Tian, Kevin wrote:
> > From: Jason Gunthorpe <jgg@nvidia.com>
> > Sent: Thursday, July 17, 2025 3:58 AM
> > +static inline u64 x86_64_pt_sw_bit(unsigned int bitnr)
> > +{
> > + /* Bits marked Ignored/AVL in the specification */
> > + switch (bitnr) {
> > + case 0:
> > + return BIT(9);
> > + case 1:
> > + return BIT(11);
> > + case 2 ... 12:
> > + return BIT_ULL((bitnr - 2) + 52);
> > + /* Remaing bits 9-8,6,4,3 are only available in some entries */
>
> s/Remaing/Remaining/
>
> bit9 is available bit in all entries. As commented in last patch, I'd probably
> just remove this line.
How about:
/* Some bits in 8,6,4,3 are available in some entries */
Jason
next prev parent reply other threads:[~2025-08-22 14:55 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-16 19:57 [PATCH 0/9] Convert Intel VT-D to use the generic iommu page table Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 1/9] iommu/pages: Add support for a incoherent IOMMU page walker Jason Gunthorpe
2025-07-21 8:41 ` Baolu Lu
2025-07-29 22:32 ` Jason Gunthorpe
2025-07-30 1:49 ` Baolu Lu
2025-08-11 21:21 ` Jason Gunthorpe
2025-08-15 11:28 ` Tian, Kevin
2025-08-22 21:13 ` Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 2/9] iommupt: Add basic support for SW bits in the page table Jason Gunthorpe
2025-08-15 11:29 ` Tian, Kevin
2025-08-18 23:35 ` Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 3/9] iommupt: Use the incoherent start/stop functions for PT_FEAT_DMA_INCOHERENT Jason Gunthorpe
2025-08-15 11:35 ` Tian, Kevin
2025-08-22 20:45 ` Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 4/9] iommupt: Flush the CPU cache after any writes to the page table Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 5/9] iommupt: Add the Intel VT-D second stage page table format Jason Gunthorpe
2025-07-22 3:11 ` Baolu Lu
2025-07-29 23:05 ` Jason Gunthorpe
2025-07-30 2:00 ` Baolu Lu
2025-08-22 9:14 ` Tian, Kevin
2025-08-22 14:53 ` Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 6/9] iommupt/x86: Set the dirty bit only for writable PTEs Jason Gunthorpe
2025-07-21 10:02 ` Baolu Lu
2025-07-16 19:57 ` [PATCH 7/9] iommupt/x86: Support SW bits and permit PT_FEAT_DMA_INCOHERENT Jason Gunthorpe
2025-07-22 5:17 ` Baolu Lu
2025-07-29 23:13 ` Jason Gunthorpe
2025-07-30 2:35 ` Baolu Lu
2025-08-22 9:17 ` Tian, Kevin
2025-08-22 14:55 ` Jason Gunthorpe [this message]
2025-07-16 19:57 ` [PATCH 8/9] iommu/vt-d: Use the generic iommu page table Jason Gunthorpe
2025-07-22 6:44 ` Baolu Lu
2025-07-29 23:39 ` Jason Gunthorpe
2025-08-22 9:35 ` Tian, Kevin
2025-08-22 20:43 ` Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 9/9] iommupt: Add a kunit test for the SW bits Jason Gunthorpe
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