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From: Baolu Lu <baolu.lu@linux.intel.com>
To: Jason Gunthorpe <jgg@nvidia.com>
Cc: David Woodhouse <dwmw2@infradead.org>,
	iommu@lists.linux.dev, Joerg Roedel <joro@8bytes.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Will Deacon <will@kernel.org>, Kevin Tian <kevin.tian@intel.com>,
	patches@lists.linux.dev, Tina Zhang <tina.zhang@intel.com>,
	Wei Wang <wei.w.wang@intel.com>
Subject: Re: [PATCH 7/9] iommupt/x86: Support SW bits and permit PT_FEAT_DMA_INCOHERENT
Date: Wed, 30 Jul 2025 10:35:38 +0800	[thread overview]
Message-ID: <f15dc6cb-f936-4f3c-9282-184f37e472cc@linux.intel.com> (raw)
In-Reply-To: <20250729231314.GE82395@nvidia.com>

On 7/30/25 07:13, Jason Gunthorpe wrote:
> On Tue, Jul 22, 2025 at 01:17:59PM +0800, Baolu Lu wrote:
>>> +static inline u64 x86_64_pt_sw_bit(unsigned int bitnr)
>>> +{
>>> +	/* Bits marked Ignored/AVL in the specification */
>>> +	switch (bitnr) {
>>> +	case 0:
>>> +		return BIT(9);
>>> +	case 1:
>>> +		return BIT(11);
>>> +	case 2 ... 12:
>>> +		return BIT_ULL((bitnr - 2) + 52);
>>
>> Just out of curiosity, why bit 63 can't be used as the sw bit?
> 
> It is not ignored, but used for XD/NX:
> 
> 	X86_64_FMT_XD = BIT_ULL(63),
> 
> Which should comes out for ATS replies.
> 
> The existing drivers didn't wire it up, so I left it alone as well,

The VT-d driver once had such support, but it was removed by commit
e995fcde6070 as the VT-d architecture doesn't support it anymore.

commit e995fcde6070f0981e083c1e2e17e401e6c17ad9
Author: Lu Baolu <baolu.lu@linux.intel.com>
Date:   Tue Jul 2 21:08:35 2024 +0800

     iommu/vt-d: Remove control over Execute-Requested requests

     The VT-d specification has removed architectural support of the 
requests
     with pasid with a value of 1 for Execute-Requested (ER). And the 
NXE bit
     in the pasid table entry and XD bit in the first-stage paging 
Entries are
     deprecated accordingly.

     Remove the programming of these bits to make it consistent with the 
spec.

     Suggested-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
     Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
     Reviewed-by: Kevin Tian <kevin.tian@intel.com>
     Link: 
https://lore.kernel.org/r/20240624032351.249858-1-baolu.lu@linux.intel.com
     Link: 
https://lore.kernel.org/r/20240702130839.108139-4-baolu.lu@linux.intel.com
     Signed-off-by: Will Deacon <will@kernel.org>


> but the XD should be linked to IOMMU_NOEXEC. There are some little
> things like this we can evaluate after. The idea here is to try hard
> to make no change to the drivers existing behavior.

Yeah, we can carve out that bit for now and evaluate it later, given
that we already have enough sw bits.

Thanks,
baolu

  reply	other threads:[~2025-07-30  2:38 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-16 19:57 [PATCH 0/9] Convert Intel VT-D to use the generic iommu page table Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 1/9] iommu/pages: Add support for a incoherent IOMMU page walker Jason Gunthorpe
2025-07-21  8:41   ` Baolu Lu
2025-07-29 22:32     ` Jason Gunthorpe
2025-07-30  1:49       ` Baolu Lu
2025-08-11 21:21         ` Jason Gunthorpe
2025-08-15 11:28   ` Tian, Kevin
2025-08-22 21:13     ` Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 2/9] iommupt: Add basic support for SW bits in the page table Jason Gunthorpe
2025-08-15 11:29   ` Tian, Kevin
2025-08-18 23:35     ` Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 3/9] iommupt: Use the incoherent start/stop functions for PT_FEAT_DMA_INCOHERENT Jason Gunthorpe
2025-08-15 11:35   ` Tian, Kevin
2025-08-22 20:45     ` Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 4/9] iommupt: Flush the CPU cache after any writes to the page table Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 5/9] iommupt: Add the Intel VT-D second stage page table format Jason Gunthorpe
2025-07-22  3:11   ` Baolu Lu
2025-07-29 23:05     ` Jason Gunthorpe
2025-07-30  2:00       ` Baolu Lu
2025-08-22  9:14   ` Tian, Kevin
2025-08-22 14:53     ` Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 6/9] iommupt/x86: Set the dirty bit only for writable PTEs Jason Gunthorpe
2025-07-21 10:02   ` Baolu Lu
2025-07-16 19:57 ` [PATCH 7/9] iommupt/x86: Support SW bits and permit PT_FEAT_DMA_INCOHERENT Jason Gunthorpe
2025-07-22  5:17   ` Baolu Lu
2025-07-29 23:13     ` Jason Gunthorpe
2025-07-30  2:35       ` Baolu Lu [this message]
2025-08-22  9:17   ` Tian, Kevin
2025-08-22 14:55     ` Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 8/9] iommu/vt-d: Use the generic iommu page table Jason Gunthorpe
2025-07-22  6:44   ` Baolu Lu
2025-07-29 23:39     ` Jason Gunthorpe
2025-08-22  9:35   ` Tian, Kevin
2025-08-22 20:43     ` Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 9/9] iommupt: Add a kunit test for the SW bits Jason Gunthorpe

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