Re: [PATCH v2 0/8] iommu: Domain allocation enhancements

[Baolu Lu <baolu.lu@linux.intel.com>]

On 2024/10/2 13:30, Vasant Hegde wrote:
> On 9/11/2024 3:49 PM, Vasant Hegde wrote:
>> This series adds iommu_paging_domain_alloc_flags() which takes flags to
>> pass additional details for domain allocation (like domain with PASID
>> support).
>>
>> Also updates AMD IOMMU driver domain allocation code. With this by
>> default it will allocate domain with V2 page table for PASID capable
>> device and v1 page table for rest of the devices.
>>
>> @Baolu,
>>    With this changes (patch 1), to allocate PASID capable device core
>>    will call domain_alloc_user() interface. Do we need any changes to
>>    intel driver?
> @Baolu,
>    Looks like intel driver works fine with this change. Is that correct -OR- do
> we need any changes to intel_iommu_domain_alloc_user() ?

I still have a question about the following change:

https://lore.kernel.org/linux-iommu/a3e09a90-0b63-4332-9e25-a5832d5ec8b2@linux.intel.com/

This change might cause a functional regression when it comes to nested
translation. In nested translation mode, the user page table (e.g.,
created and managed by a guest VM for guest kernel DMA) must be in the
first-stage page table format. Then, it can be nested on a second-stage
page table managed by the host kernel.

Currently, the kernel automatically selects the page table formats. For
example, the Intel IOMMU driver always uses the first-stage page table
for guest kernel DMA. After this change, this assumption no longer holds
true. This means the kernel might use a second-stage page table for
guest kernel DMA, breaking nested translation.

Thanks,
baolu