Re: [PATCH v2 04/10] iommu/amd: Introduce per-device GCR3 table

[Jason Gunthorpe <jgg@ziepe.ca>]

On Wed, Aug 16, 2023 at 05:40:25PM +0000, Vasant Hegde wrote:
> From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
> 
> AMD IOMMU GCR3 table is indexed by PASID. Each entry stores guest CR3
> register value, which is an address to the root of guest IO page table.
> The GCR3 table can be programmed per-device. However, Linux AMD IOMMU
> driver currently managing the table on a per-domain basis.
> 
> PASID is a device feature. When SVA is enabled it will bind PASID to
> device, not domain. Hence it makes sense to have per device GCR3 table.
> 
> Introduce struct iommu_dev_data.gcr3_tbl_info to keep track of GCR3 table
> configuration. This will eventually replaces gcr3 related variables in
> protection_domain structure.
> 
> Suggested-by: Jason Gunthorpe <jgg@ziepe.ca>
> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
> Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
> ---
>  drivers/iommu/amd/amd_iommu_types.h | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
> index eb32df5371c4..1c4672ed90f4 100644
> --- a/drivers/iommu/amd/amd_iommu_types.h
> +++ b/drivers/iommu/amd/amd_iommu_types.h
> @@ -530,6 +530,13 @@ struct amd_irte_ops;
>  #define io_pgtable_cfg_to_data(x) \
>  	container_of((x), struct amd_io_pgtable, pgtbl_cfg)
>  
> +struct gcr3_tbl_info {
> +	u64	*gcr3_tbl;	/* Guest CR3 table */
> +	int	glx;		/* Number of levels for GCR3 table */
> +	int	pasid_cnt;	/* Track attached PASIDs */

These should be unsigned values since they can't be negative

Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>

Jason