From: <gerg@snapgear.com>
To: linux-m68k@vger.kernel.org, uclinux-dev@uclinux.org
Cc: Greg Ungerer <gerg@uclinux.org>
Subject: [PATCH 13/36] m68k: add cache support for V4e ColdFire cores running with MMU enabled
Date: Tue, 25 Oct 2011 17:19:05 +1000 [thread overview]
Message-ID: <1319527168-11166-14-git-send-email-gerg@snapgear.com> (raw)
In-Reply-To: <1319527168-11166-1-git-send-email-gerg@snapgear.com>
From: Greg Ungerer <gerg@uclinux.org>
Add code to deal with instruction, data and branch caches of the V4e
ColdFire cores when they are running with the MMU enabled.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
arch/m68k/include/asm/cacheflush_mm.h | 88 +++++++++++++++++++++++++++++++--
arch/m68k/mm/cache.c | 57 +++++++++++++---------
2 files changed, 117 insertions(+), 28 deletions(-)
diff --git a/arch/m68k/include/asm/cacheflush_mm.h b/arch/m68k/include/asm/cacheflush_mm.h
index 73de7c8..8104bd8 100644
--- a/arch/m68k/include/asm/cacheflush_mm.h
+++ b/arch/m68k/include/asm/cacheflush_mm.h
@@ -2,23 +2,89 @@
#define _M68K_CACHEFLUSH_H
#include <linux/mm.h>
+#ifdef CONFIG_COLDFIRE
+#include <asm/mcfsim.h>
+#endif
/* cache code */
#define FLUSH_I_AND_D (0x00000808)
#define FLUSH_I (0x00000008)
+#ifndef ICACHE_MAX_ADDR
+#define ICACHE_MAX_ADDR 0
+#define ICACHE_SET_MASK 0
+#define DCACHE_MAX_ADDR 0
+#define DCACHE_SETMASK 0
+#endif
+
+static inline void flush_cf_icache(unsigned long start, unsigned long end)
+{
+ unsigned long set;
+
+ for (set = start; set <= end; set += (0x10 - 3)) {
+ __asm__ __volatile__ (
+ "cpushl %%ic,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%ic,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%ic,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%ic,(%0)"
+ : "=a" (set)
+ : "a" (set));
+ }
+}
+
+static inline void flush_cf_dcache(unsigned long start, unsigned long end)
+{
+ unsigned long set;
+
+ for (set = start; set <= end; set += (0x10 - 3)) {
+ __asm__ __volatile__ (
+ "cpushl %%dc,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%dc,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%dc,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%dc,(%0)"
+ : "=a" (set)
+ : "a" (set));
+ }
+}
+
+static inline void flush_cf_bcache(unsigned long start, unsigned long end)
+{
+ unsigned long set;
+
+ for (set = start; set <= end; set += (0x10 - 3)) {
+ __asm__ __volatile__ (
+ "cpushl %%bc,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%bc,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%bc,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%bc,(%0)"
+ : "=a" (set)
+ : "a" (set));
+ }
+}
+
/*
* Cache handling functions
*/
static inline void flush_icache(void)
{
- if (CPU_IS_040_OR_060)
+ if (CPU_IS_COLDFIRE) {
+ flush_cf_icache(0, ICACHE_MAX_ADDR);
+ } else if (CPU_IS_040_OR_060) {
asm volatile ( "nop\n"
" .chip 68040\n"
" cpusha %bc\n"
" .chip 68k");
- else {
+ } else {
unsigned long tmp;
asm volatile ( "movec %%cacr,%0\n"
" or.w %1,%0\n"
@@ -51,12 +117,14 @@ extern void cache_push_v(unsigned long vaddr, int len);
process changes. */
#define __flush_cache_all() \
({ \
- if (CPU_IS_040_OR_060) \
+ if (CPU_IS_COLDFIRE) { \
+ flush_cf_dcache(0, DCACHE_MAX_ADDR); \
+ } else if (CPU_IS_040_OR_060) { \
__asm__ __volatile__("nop\n\t" \
".chip 68040\n\t" \
"cpusha %dc\n\t" \
".chip 68k"); \
- else { \
+ } else { \
unsigned long _tmp; \
__asm__ __volatile__("movec %%cacr,%0\n\t" \
"orw %1,%0\n\t" \
@@ -112,7 +180,17 @@ static inline void flush_cache_page(struct vm_area_struct *vma, unsigned long vm
/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
static inline void __flush_page_to_ram(void *vaddr)
{
- if (CPU_IS_040_OR_060) {
+ if (CPU_IS_COLDFIRE) {
+ unsigned long addr, start, end;
+ addr = ((unsigned long) vaddr) & ~(PAGE_SIZE - 1);
+ start = addr & ICACHE_SET_MASK;
+ end = (addr + PAGE_SIZE - 1) & ICACHE_SET_MASK;
+ if (start > end) {
+ flush_cf_bcache(0, end);
+ end = ICACHE_MAX_ADDR;
+ }
+ flush_cf_bcache(start, end);
+ } else if (CPU_IS_040_OR_060) {
__asm__ __volatile__("nop\n\t"
".chip 68040\n\t"
"cpushp %%bc,(%0)\n\t"
diff --git a/arch/m68k/mm/cache.c b/arch/m68k/mm/cache.c
index 5437fff..a34e5bb 100644
--- a/arch/m68k/mm/cache.c
+++ b/arch/m68k/mm/cache.c
@@ -10,10 +10,11 @@
#include <asm/pgalloc.h>
#include <asm/traps.h>
-
static unsigned long virt_to_phys_slow(unsigned long vaddr)
{
- if (CPU_IS_060) {
+ if (CPU_IS_COLDFIRE) {
+ /* FIXME */
+ } else if (CPU_IS_060) {
unsigned long paddr;
/* The PLPAR instruction causes an access error if the translation
@@ -70,12 +71,41 @@ static unsigned long virt_to_phys_slow(unsigned long vaddr)
return 0;
}
+void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
+ unsigned long addr, int len)
+{
+ if (CPU_IS_COLDFIRE) {
+ /* FIXME */
+ } else if (CPU_IS_040_OR_060) {
+ asm volatile ("nop\n\t"
+ ".chip 68040\n\t"
+ "cpushp %%bc,(%0)\n\t"
+ ".chip 68k"
+ : : "a" (page_to_phys(page)));
+ } else {
+ unsigned long tmp;
+ asm volatile ("movec %%cacr,%0\n\t"
+ "orw %1,%0\n\t"
+ "movec %0,%%cacr"
+ : "=&d" (tmp)
+ : "di" (FLUSH_I));
+ }
+}
+
/* Push n pages at kernel virtual address and clear the icache */
/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
void flush_icache_range(unsigned long address, unsigned long endaddr)
{
-
- if (CPU_IS_040_OR_060) {
+ if (CPU_IS_COLDFIRE) {
+ unsigned long start, end;
+ start = address & ICACHE_SET_MASK;
+ end = endaddr & ICACHE_SET_MASK;
+ if (start > end) {
+ flush_cf_icache(0, end);
+ end = ICACHE_MAX_ADDR;
+ }
+ flush_cf_icache(start, end);
+ } else if (CPU_IS_040_OR_060) {
address &= PAGE_MASK;
do {
@@ -97,22 +127,3 @@ void flush_icache_range(unsigned long address, unsigned long endaddr)
}
EXPORT_SYMBOL(flush_icache_range);
-void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
- unsigned long addr, int len)
-{
- if (CPU_IS_040_OR_060) {
- asm volatile ("nop\n\t"
- ".chip 68040\n\t"
- "cpushp %%bc,(%0)\n\t"
- ".chip 68k"
- : : "a" (page_to_phys(page)));
- } else {
- unsigned long tmp;
- asm volatile ("movec %%cacr,%0\n\t"
- "orw %1,%0\n\t"
- "movec %0,%%cacr"
- : "=&d" (tmp)
- : "di" (FLUSH_I));
- }
-}
-
--
1.7.0.4
next prev parent reply other threads:[~2011-10-25 7:21 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-10-25 7:18 [PATCH 00/36] m68k: ColdFire MMU support gerg
2011-10-25 7:18 ` [PATCH 01/36] m68k: add machine and CPU definitions for ColdFire cores gerg
2011-10-25 7:18 ` [PATCH 02/36] m68k: show ColdFire CPU/FPU/MMU type gerg
2011-10-25 7:18 ` [PATCH 03/36] m68k: definitions for the ColdFire V4e MMU hardware gerg
2011-10-25 7:18 ` [PATCH 04/36] m68k: make old interrupt code conditional on correct CPU types gerg
2011-10-25 7:18 ` [PATCH 05/36] m68k: add TASK definitions for ColdFires running with MMU gerg
2011-10-25 7:18 ` [PATCH 06/36] m68k: modify user space access functions to support ColdFire CPUs gerg
2011-10-30 13:02 ` Geert Uytterhoeven
2011-10-31 5:03 ` Greg Ungerer
2011-10-25 7:18 ` [PATCH 07/36] m68k: add ColdFire 54xx CPU MMU memory init code gerg
2011-10-25 7:19 ` [PATCH 08/36] m68k: init the MMU hardware for the 54xx ColdFire gerg
2011-10-25 7:19 ` [PATCH 09/36] m68k: set register a2 to current if MMU enabled on ColdFire gerg
2011-10-30 13:06 ` Geert Uytterhoeven
2011-10-31 4:19 ` Greg Ungerer
2011-10-25 7:19 ` [PATCH 10/36] m68k: page table support definitions and code for ColdFire MMU gerg
2011-10-30 13:07 ` Geert Uytterhoeven
2011-10-25 7:19 ` [PATCH 11/36] m68k: add page table size definitions for ColdFire V4e MMU gerg
2011-10-25 7:19 ` [PATCH 12/36] m68k: add ColdFire paging exception handling code gerg
2011-10-25 7:19 ` gerg [this message]
2011-10-25 7:19 ` [PATCH 14/36] m68k: modify ColdFire 54xx cache support for MMU enabled gerg
2011-10-25 7:19 ` [PATCH 15/36] m68k: add TLB flush support for the ColdFire V4e MMU hardware gerg
2011-10-30 13:26 ` Geert Uytterhoeven
2011-10-25 7:19 ` [PATCH 16/36] m68k: set ColdFire MMU page size gerg
2011-10-30 13:29 ` Geert Uytterhoeven
2011-10-31 4:41 ` Greg Ungerer
2011-10-25 7:19 ` [PATCH 17/36] m68k: ColdFire with MMU does not support separate address spaces gerg
2011-10-25 7:19 ` [PATCH 18/36] m68k: ColdFire V4e MMU context support code gerg
2011-10-25 7:19 ` [PATCH 19/36] m68k: use tracehook_report_syscall_entry/exit for ColdFire MMU ptrace path gerg
2011-10-25 7:19 ` [PATCH 20/36] m68k: ColdFire with MMU needs simpler lib checksum code gerg
2011-10-25 7:19 ` [PATCH 21/36] m68k: modify cache push and clear code for ColdFire with MMU enable gerg
2011-10-25 7:19 ` [PATCH 22/36] m68k: use ColdFire V4e MMU flags when ioremapping() gerg
2011-10-25 7:19 ` [PATCH 23/36] m68k: ColdFire V4e MMU paginit init code and miss handler gerg
2011-10-30 15:56 ` Finn Thain
2011-10-31 4:46 ` Greg Ungerer
2011-10-25 7:19 ` [PATCH 24/36] m68k: compile appropriate mm arch files for ColdFire V4e MMU support gerg
2011-10-30 13:46 ` Geert Uytterhoeven
2011-10-31 5:39 ` Greg Ungerer
2011-10-25 7:19 ` [PATCH 25/36] m68k: create ColdFire MMU pgalloc code gerg
2011-10-25 7:19 ` [PATCH 26/36] m68k: use non-MMU entry.S code when compiling for ColdFire CPU gerg
2011-10-25 7:19 ` [PATCH 27/36] m68k: add code to setup a ColdFire 54xx platform when MMU enabled gerg
2011-10-30 13:39 ` Geert Uytterhoeven
2011-10-31 4:59 ` Greg Ungerer
2011-10-25 7:19 ` [PATCH 28/36] m68k: ColdFire with MMU enabled uses same clocking code as non-MMU gerg
2011-10-25 7:19 ` [PATCH 29/36] m68k: use non-MMU linker script for ColdFire MMU builds gerg
2011-10-25 7:19 ` [PATCH 30/36] m68k: adjustments to stack frame for ColdFire with MMU enabled gerg
2011-10-25 7:19 ` [PATCH 31/36] m68k: completely disable FPU support for ColdFire gerg
2011-10-30 15:56 ` Finn Thain
2011-10-25 7:19 ` [PATCH 32/36] m68k: use new style interrupt handling for ColdFire with MMU enabled gerg
2011-10-25 7:19 ` [PATCH 33/36] m68k: define a ack_bad_irq() function for ColdFire with MMU gerg
2011-10-25 7:19 ` [PATCH 34/36] m68k: add ColdFire with MMU enabled support to the m68k mem init code gerg
2011-10-25 7:19 ` [PATCH 35/36] m68k: config option adjustments for configuring ColdFire with MMU gerg
2011-10-30 13:42 ` Geert Uytterhoeven
2011-10-25 7:19 ` [PATCH 36/36] m68k: allow ColdFire 547x and 548x CPUs to be built with MMU enabled gerg
2011-10-30 13:47 ` [PATCH 00/36] m68k: ColdFire MMU support Geert Uytterhoeven
2011-10-31 5:46 ` Greg Ungerer
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