From: Jayachandran C <jchandra@broadcom.com>
To: <linux-mips@linux-mips.org>
Cc: Jayachandran C <jchandra@broadcom.com>, <ralf@linux-mips.org>
Subject: [PATCH 03/18] MIPS: Netlogic: Some cleanups for assembly code
Date: Sat, 21 Dec 2013 16:52:15 +0530 [thread overview]
Message-ID: <1387624950-31297-4-git-send-email-jchandra@broadcom.com> (raw)
In-Reply-To: <1387624950-31297-1-git-send-email-jchandra@broadcom.com>
No change in logic, the changes are:
* cleanup some whitespace and comments
* remove confusing argument of SYS_CPU_COHERENT_BASE macro
* make the numerical labels in macros consistent
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
arch/mips/netlogic/common/reset.S | 29 +++++++++++++++--------------
arch/mips/netlogic/common/smpboot.S | 3 ++-
2 files changed, 17 insertions(+), 15 deletions(-)
diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S
index adb1828..06381e1 100644
--- a/arch/mips/netlogic/common/reset.S
+++ b/arch/mips/netlogic/common/reset.S
@@ -50,8 +50,8 @@
#include <asm/netlogic/xlp-hal/cpucontrol.h>
#define CP0_EBASE $15
-#define SYS_CPU_COHERENT_BASE(node) CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
- XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \
+#define SYS_CPU_COHERENT_BASE CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
+ XLP_IO_SYS_OFFSET(0) + XLP_IO_PCI_HDRSZ + \
SYS_CPU_NONCOHERENT_MODE * 4
/* Enable XLP features and workarounds in the LSU */
@@ -82,26 +82,26 @@
li t1, LSU_DEBUG_ADDR
li t2, 0 /* index */
li t3, 0x1000 /* loop count */
-1:
+11:
sll v0, t2, 5
mtcr zero, t0
ori v1, v0, 0x3 /* way0 | write_enable | write_active */
mtcr v1, t1
-2:
+12:
mfcr v1, t1
andi v1, 0x1 /* wait for write_active == 0 */
- bnez v1, 2b
+ bnez v1, 12b
nop
mtcr zero, t0
ori v1, v0, 0x7 /* way1 | write_enable | write_active */
mtcr v1, t1
-3:
+13:
mfcr v1, t1
andi v1, 0x1 /* wait for write_active == 0 */
- bnez v1, 3b
+ bnez v1, 13b
nop
addi t2, 1
- bne t3, t2, 1b
+ bne t3, t2, 11b
nop
.endm
@@ -149,7 +149,7 @@ FEXPORT(nlm_reset_entry)
li t1, 0x1
sll t0, t1, t0
nor t0, t0, zero /* t0 <- ~(1 << core) */
- li t2, SYS_CPU_COHERENT_BASE(0)
+ li t2, SYS_CPU_COHERENT_BASE
add t2, t2, t3 /* t2 <- SYS offset for node */
lw t1, 0(t2)
and t1, t1, t0
@@ -164,8 +164,7 @@ FEXPORT(nlm_reset_entry)
/* FALL THROUGH */
/*
- * Wake up sibling threads from the initial thread in
- * a core.
+ * Wake up sibling threads from the initial thread in a core.
*/
EXPORT(nlm_boot_siblings)
/* core L1D flush before enable threads */
@@ -181,8 +180,10 @@ EXPORT(nlm_boot_siblings)
/*
* The new hardware thread starts at the next instruction
* For all the cases other than core 0 thread 0, we will
- * jump to the secondary wait function.
- */
+ * jump to the secondary wait function.
+
+ * NOTE: All GPR contents are lost after the mtcr above!
+ */
mfc0 v0, CP0_EBASE, 1
andi v0, 0x3ff /* v0 <- node/core */
@@ -196,7 +197,7 @@ EXPORT(nlm_boot_siblings)
#endif
mtc0 t1, CP0_STATUS
- /* mark CPU ready, careful here, previous mtcr trashed registers */
+ /* mark CPU ready */
li t3, CKSEG1ADDR(RESET_DATA_PHYS)
ADDIU t1, t3, BOOT_CPU_READY
sll v1, v0, 2
diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S
index aa6cff0..db3b894 100644
--- a/arch/mips/netlogic/common/smpboot.S
+++ b/arch/mips/netlogic/common/smpboot.S
@@ -98,7 +98,7 @@ END(nlm_boot_secondary_cpus)
* In case of RMIboot bootloader which is used on XLR boards, the CPUs
* be already woken up and waiting in bootloader code.
* This will get them out of the bootloader code and into linux. Needed
- * because the bootloader area will be taken and initialized by linux.
+ * because the bootloader area will be taken and initialized by linux.
*/
NESTED(nlm_rmiboot_preboot, 16, sp)
mfc0 t0, $15, 1 /* read ebase */
@@ -133,6 +133,7 @@ NESTED(nlm_rmiboot_preboot, 16, sp)
or t1, t2, v1 /* put in new value */
mtcr t1, t0 /* update core control */
+ /* wait for NMI to hit */
1: wait
b 1b
nop
--
1.7.9.5
WARNING: multiple messages have this Message-ID (diff)
From: Jayachandran C <jchandra@broadcom.com>
To: linux-mips@linux-mips.org
Cc: Jayachandran C <jchandra@broadcom.com>, ralf@linux-mips.org
Subject: [PATCH 03/18] MIPS: Netlogic: Some cleanups for assembly code
Date: Sat, 21 Dec 2013 16:52:15 +0530 [thread overview]
Message-ID: <1387624950-31297-4-git-send-email-jchandra@broadcom.com> (raw)
Message-ID: <20131221112215.Ev_HfcXdDDl7zR29doO1aAqTlcRKDn9akP-nJK5rQZQ@z> (raw)
In-Reply-To: <1387624950-31297-1-git-send-email-jchandra@broadcom.com>
No change in logic, the changes are:
* cleanup some whitespace and comments
* remove confusing argument of SYS_CPU_COHERENT_BASE macro
* make the numerical labels in macros consistent
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
arch/mips/netlogic/common/reset.S | 29 +++++++++++++++--------------
arch/mips/netlogic/common/smpboot.S | 3 ++-
2 files changed, 17 insertions(+), 15 deletions(-)
diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S
index adb1828..06381e1 100644
--- a/arch/mips/netlogic/common/reset.S
+++ b/arch/mips/netlogic/common/reset.S
@@ -50,8 +50,8 @@
#include <asm/netlogic/xlp-hal/cpucontrol.h>
#define CP0_EBASE $15
-#define SYS_CPU_COHERENT_BASE(node) CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
- XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \
+#define SYS_CPU_COHERENT_BASE CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
+ XLP_IO_SYS_OFFSET(0) + XLP_IO_PCI_HDRSZ + \
SYS_CPU_NONCOHERENT_MODE * 4
/* Enable XLP features and workarounds in the LSU */
@@ -82,26 +82,26 @@
li t1, LSU_DEBUG_ADDR
li t2, 0 /* index */
li t3, 0x1000 /* loop count */
-1:
+11:
sll v0, t2, 5
mtcr zero, t0
ori v1, v0, 0x3 /* way0 | write_enable | write_active */
mtcr v1, t1
-2:
+12:
mfcr v1, t1
andi v1, 0x1 /* wait for write_active == 0 */
- bnez v1, 2b
+ bnez v1, 12b
nop
mtcr zero, t0
ori v1, v0, 0x7 /* way1 | write_enable | write_active */
mtcr v1, t1
-3:
+13:
mfcr v1, t1
andi v1, 0x1 /* wait for write_active == 0 */
- bnez v1, 3b
+ bnez v1, 13b
nop
addi t2, 1
- bne t3, t2, 1b
+ bne t3, t2, 11b
nop
.endm
@@ -149,7 +149,7 @@ FEXPORT(nlm_reset_entry)
li t1, 0x1
sll t0, t1, t0
nor t0, t0, zero /* t0 <- ~(1 << core) */
- li t2, SYS_CPU_COHERENT_BASE(0)
+ li t2, SYS_CPU_COHERENT_BASE
add t2, t2, t3 /* t2 <- SYS offset for node */
lw t1, 0(t2)
and t1, t1, t0
@@ -164,8 +164,7 @@ FEXPORT(nlm_reset_entry)
/* FALL THROUGH */
/*
- * Wake up sibling threads from the initial thread in
- * a core.
+ * Wake up sibling threads from the initial thread in a core.
*/
EXPORT(nlm_boot_siblings)
/* core L1D flush before enable threads */
@@ -181,8 +180,10 @@ EXPORT(nlm_boot_siblings)
/*
* The new hardware thread starts at the next instruction
* For all the cases other than core 0 thread 0, we will
- * jump to the secondary wait function.
- */
+ * jump to the secondary wait function.
+
+ * NOTE: All GPR contents are lost after the mtcr above!
+ */
mfc0 v0, CP0_EBASE, 1
andi v0, 0x3ff /* v0 <- node/core */
@@ -196,7 +197,7 @@ EXPORT(nlm_boot_siblings)
#endif
mtc0 t1, CP0_STATUS
- /* mark CPU ready, careful here, previous mtcr trashed registers */
+ /* mark CPU ready */
li t3, CKSEG1ADDR(RESET_DATA_PHYS)
ADDIU t1, t3, BOOT_CPU_READY
sll v1, v0, 2
diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S
index aa6cff0..db3b894 100644
--- a/arch/mips/netlogic/common/smpboot.S
+++ b/arch/mips/netlogic/common/smpboot.S
@@ -98,7 +98,7 @@ END(nlm_boot_secondary_cpus)
* In case of RMIboot bootloader which is used on XLR boards, the CPUs
* be already woken up and waiting in bootloader code.
* This will get them out of the bootloader code and into linux. Needed
- * because the bootloader area will be taken and initialized by linux.
+ * because the bootloader area will be taken and initialized by linux.
*/
NESTED(nlm_rmiboot_preboot, 16, sp)
mfc0 t0, $15, 1 /* read ebase */
@@ -133,6 +133,7 @@ NESTED(nlm_rmiboot_preboot, 16, sp)
or t1, t2, v1 /* put in new value */
mtcr t1, t0 /* update core control */
+ /* wait for NMI to hit */
1: wait
b 1b
nop
--
1.7.9.5
next prev parent reply other threads:[~2013-12-21 11:12 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-21 11:22 [PATCH 00/18] Broadcom XLP Updates for 3.14 Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 01/18] MIPS: Netlogic: Add MSI support for XLP Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 02/18] MIPS: Netlogic: Add topology.h for XLP family Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` Jayachandran C [this message]
2013-12-21 11:22 ` [PATCH 03/18] MIPS: Netlogic: Some cleanups for assembly code Jayachandran C
2013-12-21 11:22 ` [PATCH 04/18] MIPS: Netlogic: L1D cacheflush before thread enable on XLPII Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 05/18] MIPS: Netlogic: Add macro for node present Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 06/18] MIPS: Netlogic: Get coremask from FUSE register Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 07/18] MIPS: Netlogic: Core wakeup improvements Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 08/18] MIPS: Netlogic: Identify XLP 9XX chip Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 09/18] MIPS: Netlogic: update iomap.h for XLP9XX Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 10/18] MIPS: Netlogic: XLP9XX PIC updates Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 11/18] MIPS: Netlogic: SYS block updates of XLP9XX Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 12/18] MIPS: Netlogic: XLP9XX UART offset Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 17:35 ` John Crispin
2013-12-25 7:07 ` Jayachandran C.
2013-12-25 7:07 ` Jayachandran C.
2013-12-21 11:22 ` [PATCH 13/18] MIPS: Netlogic: XLP9XX bridge and DRAM code Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 14/18] MIPS: Netlogic: Add cpu to node mapping for XLP9XX Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 15/18] MIPS: PCI: Netlogic XLP9XX support Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 16/18] MIPS: Netlogic: XLP9XX USB support Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 17/18] MIPS: Netlogic: XLP9XX PIC OF support Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 18/18] MIPS: Netlogic: Add default DTB for XLP9XX SoC Jayachandran C
2013-12-21 11:22 ` Jayachandran C
-- strict thread matches above, loose matches on Subject: below --
2013-10-14 13:20 [PATCH 00/18] Broadcom XLP Updates Jayachandran C
2013-10-14 13:20 ` [PATCH 03/18] MIPS: Netlogic: Some cleanups for assembly code Jayachandran C
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