From: Jayachandran C <jchandra@broadcom.com>
To: <linux-mips@linux-mips.org>
Cc: Yonghong Song <ysong@broadcom.com>, <ralf@linux-mips.org>,
Jayachandran C <jchandra@broadcom.com>
Subject: [PATCH 04/18] MIPS: Netlogic: L1D cacheflush before thread enable on XLPII
Date: Sat, 21 Dec 2013 16:52:16 +0530 [thread overview]
Message-ID: <1387624950-31297-5-git-send-email-jchandra@broadcom.com> (raw)
In-Reply-To: <1387624950-31297-1-git-send-email-jchandra@broadcom.com>
From: Yonghong Song <ysong@broadcom.com>
On XLPII CPUs, the L1D cache has to be flushed with regular cache
operations before enabling threads in a core.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
arch/mips/netlogic/common/reset.S | 25 +++++++++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S
index 06381e1..57eb7a1 100644
--- a/arch/mips/netlogic/common/reset.S
+++ b/arch/mips/netlogic/common/reset.S
@@ -36,6 +36,7 @@
#include <asm/asm.h>
#include <asm/asm-offsets.h>
+#include <asm/cacheops.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/stackframe.h>
@@ -74,10 +75,18 @@
.endm
/*
- * Low level flush for L1D cache on XLP, the normal cache ops does
- * not do the complete and correct cache flush.
+ * L1D cache has to be flushed before enabling threads in XLP.
+ * On XLP8xx/XLP3xx, we do a low level flush using processor control
+ * registers. On XLPII CPUs, usual cache instructions work.
*/
.macro xlp_flush_l1_dcache
+ mfc0 t0, CP0_EBASE, 0
+ andi t0, t0, 0xff00
+ slt t1, t0, 0x1200
+ beqz t1, 15f
+ nop
+
+ /* XLP8xx low level cache flush */
li t0, LSU_DEBUG_DATA0
li t1, LSU_DEBUG_ADDR
li t2, 0 /* index */
@@ -103,6 +112,18 @@
addi t2, 1
bne t3, t2, 11b
nop
+ b 17f
+ nop
+
+ /* XLPII CPUs, Invalidate all 64k of L1 D-cache */
+15:
+ li t0, 0x80000000
+ li t1, 0x80010000
+16: cache Index_Writeback_Inv_D, 0(t0)
+ addiu t0, t0, 32
+ bne t0, t1, 16b
+ nop
+17:
.endm
/*
--
1.7.9.5
WARNING: multiple messages have this Message-ID (diff)
From: Jayachandran C <jchandra@broadcom.com>
To: linux-mips@linux-mips.org
Cc: Yonghong Song <ysong@broadcom.com>,
ralf@linux-mips.org, Jayachandran C <jchandra@broadcom.com>
Subject: [PATCH 04/18] MIPS: Netlogic: L1D cacheflush before thread enable on XLPII
Date: Sat, 21 Dec 2013 16:52:16 +0530 [thread overview]
Message-ID: <1387624950-31297-5-git-send-email-jchandra@broadcom.com> (raw)
Message-ID: <20131221112216.LDHiiS_lsm0gV0eQLu3R0GG57EBc3a2Z0RQ8dfXSmNg@z> (raw)
In-Reply-To: <1387624950-31297-1-git-send-email-jchandra@broadcom.com>
From: Yonghong Song <ysong@broadcom.com>
On XLPII CPUs, the L1D cache has to be flushed with regular cache
operations before enabling threads in a core.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
arch/mips/netlogic/common/reset.S | 25 +++++++++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S
index 06381e1..57eb7a1 100644
--- a/arch/mips/netlogic/common/reset.S
+++ b/arch/mips/netlogic/common/reset.S
@@ -36,6 +36,7 @@
#include <asm/asm.h>
#include <asm/asm-offsets.h>
+#include <asm/cacheops.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/stackframe.h>
@@ -74,10 +75,18 @@
.endm
/*
- * Low level flush for L1D cache on XLP, the normal cache ops does
- * not do the complete and correct cache flush.
+ * L1D cache has to be flushed before enabling threads in XLP.
+ * On XLP8xx/XLP3xx, we do a low level flush using processor control
+ * registers. On XLPII CPUs, usual cache instructions work.
*/
.macro xlp_flush_l1_dcache
+ mfc0 t0, CP0_EBASE, 0
+ andi t0, t0, 0xff00
+ slt t1, t0, 0x1200
+ beqz t1, 15f
+ nop
+
+ /* XLP8xx low level cache flush */
li t0, LSU_DEBUG_DATA0
li t1, LSU_DEBUG_ADDR
li t2, 0 /* index */
@@ -103,6 +112,18 @@
addi t2, 1
bne t3, t2, 11b
nop
+ b 17f
+ nop
+
+ /* XLPII CPUs, Invalidate all 64k of L1 D-cache */
+15:
+ li t0, 0x80000000
+ li t1, 0x80010000
+16: cache Index_Writeback_Inv_D, 0(t0)
+ addiu t0, t0, 32
+ bne t0, t1, 16b
+ nop
+17:
.endm
/*
--
1.7.9.5
next prev parent reply other threads:[~2013-12-21 11:13 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-21 11:22 [PATCH 00/18] Broadcom XLP Updates for 3.14 Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 01/18] MIPS: Netlogic: Add MSI support for XLP Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 02/18] MIPS: Netlogic: Add topology.h for XLP family Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 03/18] MIPS: Netlogic: Some cleanups for assembly code Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` Jayachandran C [this message]
2013-12-21 11:22 ` [PATCH 04/18] MIPS: Netlogic: L1D cacheflush before thread enable on XLPII Jayachandran C
2013-12-21 11:22 ` [PATCH 05/18] MIPS: Netlogic: Add macro for node present Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 06/18] MIPS: Netlogic: Get coremask from FUSE register Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 07/18] MIPS: Netlogic: Core wakeup improvements Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 08/18] MIPS: Netlogic: Identify XLP 9XX chip Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 09/18] MIPS: Netlogic: update iomap.h for XLP9XX Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 10/18] MIPS: Netlogic: XLP9XX PIC updates Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 11/18] MIPS: Netlogic: SYS block updates of XLP9XX Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 12/18] MIPS: Netlogic: XLP9XX UART offset Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 17:35 ` John Crispin
2013-12-25 7:07 ` Jayachandran C.
2013-12-25 7:07 ` Jayachandran C.
2013-12-21 11:22 ` [PATCH 13/18] MIPS: Netlogic: XLP9XX bridge and DRAM code Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 14/18] MIPS: Netlogic: Add cpu to node mapping for XLP9XX Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 15/18] MIPS: PCI: Netlogic XLP9XX support Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 16/18] MIPS: Netlogic: XLP9XX USB support Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 17/18] MIPS: Netlogic: XLP9XX PIC OF support Jayachandran C
2013-12-21 11:22 ` Jayachandran C
2013-12-21 11:22 ` [PATCH 18/18] MIPS: Netlogic: Add default DTB for XLP9XX SoC Jayachandran C
2013-12-21 11:22 ` Jayachandran C
-- strict thread matches above, loose matches on Subject: below --
2013-10-14 13:20 [PATCH 00/18] Broadcom XLP Updates Jayachandran C
2013-10-14 13:21 ` [PATCH 04/18] MIPS: Netlogic: L1D cacheflush before thread enable on XLPII Jayachandran C
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