Disabling lwl and lwr instruction generation

Disabling lwl and lwr instruction generation

[Ranjan Parthasarathy]

Is there a way to tell gcc to not generate the lwl, lwr instructions?

Thanks

Ranjan

Re: Disabling lwl and lwr instruction generation

[Ralf Baechle]

On Wed, Mar 12, 2003 at 10:05:20AM -0800, Ranjan Parthasarathy wrote:

> Is there a way to tell gcc to not generate the lwl, lwr instructions?

Gcc will only ever generate these instructions when __attribute__((unaligned))
is used.

  Ralf

Re: Disabling lwl and lwr instruction generation

[Richard Hodges]

On Thu, 13 Mar 2003, Ralf Baechle wrote:

> On Wed, Mar 12, 2003 at 10:05:20AM -0800, Ranjan Parthasarathy wrote:
>
> > Is there a way to tell gcc to not generate the lwl, lwr instructions?
>
> Gcc will only ever generate these instructions when __attribute__((unaligned))
> is used.

I got lwl and lwr from a memcpy() with two void pointers...

I quickly changed those to the (aligned) structure pointers instead, and
then memcpy() changed to ordinary word loads and stores.

So, is somebody starting a toolchain for that new Chinese CPU? :-)

-Richard

Re: Disabling lwl and lwr instruction generation

[Ralf Baechle]

On Wed, Mar 12, 2003 at 04:50:53PM -0800, Richard Hodges wrote:

> I got lwl and lwr from a memcpy() with two void pointers...
> 
> I quickly changed those to the (aligned) structure pointers instead, and
> then memcpy() changed to ordinary word loads and stores.
> 
> So, is somebody starting a toolchain for that new Chinese CPU? :-)

Wouldn't be the first processor without lwl/lwr instructions.  There have
been a few that didn't implement it for silly bean^Wgate counting issues
others have done it for patent and licensing reasons.

(Afair MIPS's patent is about to expire and IBM's prior art patent in the
same area is even way older but that legalese ...)

  Ralf

Re: Disabling lwl and lwr instruction generation

[Zhang Fuxin]

Richard Hodges wrote:

>On Thu, 13 Mar 2003, Ralf Baechle wrote:
>
>  
>
>>On Wed, Mar 12, 2003 at 10:05:20AM -0800, Ranjan Parthasarathy wrote:
>>
>>    
>>
>>>Is there a way to tell gcc to not generate the lwl, lwr instructions?
>>>      
>>>
>>Gcc will only ever generate these instructions when __attribute__((unaligned))
>>is used.
>>    
>>
>
>I got lwl and lwr from a memcpy() with two void pointers...
>
>I quickly changed those to the (aligned) structure pointers instead, and
>then memcpy() changed to ordinary word loads and stores.
>
>So, is somebody starting a toolchain for that new Chinese CPU? :-)
>  
>

I don't hear about it,but it will happen soon or later:)

We work around lwl/lwr problem by modifying toolchain from H.J. Lu's rh 
port.

it seems that gcc will explicitly output lwl/lwr for unaligned block 
copy,in other cases it will generate
ulW macros for gas to handle.





>-Richard
>
>
>
>  
>

Re: Disabling lwl and lwr instruction generation

[Thiemo Seufer]

Ralf Baechle wrote:
> On Wed, Mar 12, 2003 at 10:05:20AM -0800, Ranjan Parthasarathy wrote:
> 
> > Is there a way to tell gcc to not generate the lwl, lwr instructions?
> 
> Gcc will only ever generate these instructions when __attribute__((unaligned))
> is used.

Which might be not that obvious, e.g. __attribute__((packed)) can cause such
instructions, too.


Thiemo

Re: Disabling lwl and lwr instruction generation

[Ralf Baechle]

On Thu, Mar 13, 2003 at 01:52:03AM +0100, Thiemo Seufer wrote:

> > On Wed, Mar 12, 2003 at 10:05:20AM -0800, Ranjan Parthasarathy wrote:
> > 
> > > Is there a way to tell gcc to not generate the lwl, lwr instructions?
> > 
> > Gcc will only ever generate these instructions when __attribute__((unaligned))
> > is used.
> 
> Which might be not that obvious, e.g. __attribute__((packed)) can cause such
> instructions, too.

Typo - I meant __attribute__((packed)).  There is no such thing as
 __attribute__((unaligned)).

  Ralf

RE: Disabling lwl and lwr instruction generation

[Ranjan Parthasarathy]

Thanks for all your replies and no I am not working on the chinese processor :-). BTW it would be nice to have a mips option on override cpu options for disabling the lwl,lwr,swl,swr similar to "Cpu has ll/sc".

Thanks

Ranjan

-----Original Message-----
From: Ralf Baechle [mailto:ralf@linux-mips.org]
Sent: Wednesday, March 12, 2003 5:34 PM
To: Richard Hodges
Cc: Ranjan Parthasarathy; 'linux-mips@linux-mips.org'
Subject: Re: Disabling lwl and lwr instruction generation


On Wed, Mar 12, 2003 at 04:50:53PM -0800, Richard Hodges wrote:

> I got lwl and lwr from a memcpy() with two void pointers...
> 
> I quickly changed those to the (aligned) structure pointers instead, and
> then memcpy() changed to ordinary word loads and stores.
> 
> So, is somebody starting a toolchain for that new Chinese CPU? :-)

Wouldn't be the first processor without lwl/lwr instructions.  There have
been a few that didn't implement it for silly bean^Wgate counting issues
others have done it for patent and licensing reasons.

(Afair MIPS's patent is about to expire and IBM's prior art patent in the
same area is even way older but that legalese ...)

  Ralf

RE: Disabling lwl and lwr instruction generation

[Ranjan Parthasarathy]

Thanks for all your replies and no I am not working on the chinese processor :-). BTW it would be nice to have a mips option on override cpu options for disabling the lwl,lwr,swl,swr similar to "Cpu has ll/sc".

Thanks

Ranjan

-----Original Message-----
From: Ralf Baechle [mailto:ralf@linux-mips.org]
Sent: Wednesday, March 12, 2003 5:34 PM
To: Richard Hodges
Cc: Ranjan Parthasarathy; 'linux-mips@linux-mips.org'
Subject: Re: Disabling lwl and lwr instruction generation


On Wed, Mar 12, 2003 at 04:50:53PM -0800, Richard Hodges wrote:

> I got lwl and lwr from a memcpy() with two void pointers...
> 
> I quickly changed those to the (aligned) structure pointers instead, and
> then memcpy() changed to ordinary word loads and stores.
> 
> So, is somebody starting a toolchain for that new Chinese CPU? :-)

Wouldn't be the first processor without lwl/lwr instructions.  There have
been a few that didn't implement it for silly bean^Wgate counting issues
others have done it for patent and licensing reasons.

(Afair MIPS's patent is about to expire and IBM's prior art patent in the
same area is even way older but that legalese ...)

  Ralf

RE: Disabling lwl and lwr instruction generation

[Ranjan Parthasarathy]

From the gcc sources, the compiler generates the lwl,lwr etc. in the block move code in gcc/config/mips/mips.c ( output_block_move ). 

There is an option -mmemcpy which tells gcc to use a memcpy compiled in with the sources for this block move instead of gcc genetrating code. The problem however with this is that arch/mips/lib/memcpy.S is optimized using lwl,lwr,swl,swr. If this can be  modified so that lwl,lwr,swl,swr is used if enabled as a kernel option, it might work very well. 

Any ideas / suggestions?

Thanks

Ranjan

-----Original Message-----
From: Ralf Baechle [mailto:ralf@linux-mips.org]
Sent: Wednesday, March 12, 2003 5:34 PM
To: Richard Hodges
Cc: Ranjan Parthasarathy; 'linux-mips@linux-mips.org'
Subject: Re: Disabling lwl and lwr instruction generation


On Wed, Mar 12, 2003 at 04:50:53PM -0800, Richard Hodges wrote:

> I got lwl and lwr from a memcpy() with two void pointers...
> 
> I quickly changed those to the (aligned) structure pointers instead, and
> then memcpy() changed to ordinary word loads and stores.
> 
> So, is somebody starting a toolchain for that new Chinese CPU? :-)

Wouldn't be the first processor without lwl/lwr instructions.  There have
been a few that didn't implement it for silly bean^Wgate counting issues
others have done it for patent and licensing reasons.

(Afair MIPS's patent is about to expire and IBM's prior art patent in the
same area is even way older but that legalese ...)

  Ralf

RE: Disabling lwl and lwr instruction generation

[Ranjan Parthasarathy]

Re: Disabling lwl and lwr instruction generation

[Ralf Baechle]

On Thu, Mar 13, 2003 at 10:09:03AM -0800, Ranjan Parthasarathy wrote:

> From the gcc sources, the compiler generates the lwl,lwr etc. in the block
> move code in gcc/config/mips/mips.c ( output_block_move ). 
> 
> There is an option -mmemcpy which tells gcc to use a memcpy compiled in
> with the sources for this block move instead of gcc genetrating code. The
> problem however with this is that arch/mips/lib/memcpy.S is optimized
> using lwl,lwr,swl,swr. If this can be  modified so that lwl,lwr,swl,swr
> is used if enabled as a kernel option, it might work very well. 

Replace those unaligned copies with a word-wise or even bytewise copying.
Not good for performance but ...

  Ralf

Re: Disabling lwl and lwr instruction generation

[Alan Cox]

On Thu, 2003-03-13 at 21:35, Ralf Baechle wrote:
> Replace those unaligned copies with a word-wise or even bytewise copying.
> Not good for performance but ...

Depends on (src^dest) & 3. Glibc may have the code you need to get it
right, although it will also depend on how smart the cpu cache is - if
you have a write through cache then shift/mask/write in 32/64 chunks
may be fastest


Alan