exception priority for BCM1250

exception priority for BCM1250

[Lijun Chen]

Hi,

Does anybody know which mips family SB1 core on bcm1250 falls into?
It is a MIPS64 processor, does it belong to 5K family or 20Kc?

What about the exception priorities, such as cache error exception, bus 
error
exception, and so on? Are they maskable or non-maskable? It is not clear 
from
BCM1250 and sb1 core manuals.

Thanks a lot.

Lijun

Re: exception priority for BCM1250

[Lijun Chen]

Further to my last email, another question is if multiple simultaneous 
exceptions occur, or kernel is
handling an exception, another exception occurs, how linux handles this?

Thanks,
Lijun

Chen, Lijun [CAR:7Q28:EXCH] wrote:

> Hi,
>
> Does anybody know which mips family SB1 core on bcm1250 falls into?
> It is a MIPS64 processor, does it belong to 5K family or 20Kc?
>
> What about the exception priorities, such as cache error exception, 
> bus error
> exception, and so on? Are they maskable or non-maskable? It is not 
> clear from
> BCM1250 and sb1 core manuals.
>
> Thanks a lot.
>
> Lijun
>
>
>

Re: exception priority for BCM1250

[Ralf Baechle]

On Tue, Mar 30, 2004 at 06:38:02PM -0500, Lijun Chen wrote:

> Further to my last email, another question is if multiple simultaneous 
> exceptions occur, or kernel is
> handling an exception, another exception occurs, how linux handles this?

Not at all.  Exceptions have priorities and so simply the highest
priority will be taken and therefore handled.

  Ralf

Re: exception priority for BCM1250

[Ralf Baechle]

On Tue, Mar 30, 2004 at 05:47:41PM -0500, Lijun Chen wrote:

> Does anybody know which mips family SB1 core on bcm1250 falls into?
> It is a MIPS64 processor, does it belong to 5K family or 20Kc?

They're all MIPS64.

> What about the exception priorities, such as cache error exception, bus 
> error exception, and so on? Are they maskable or non-maskable? It is not
> clear from BCM1250 and sb1 core manuals.

This is explained in the MIPS64 spec.

  Ralf

Re: exception priority for BCM1250

[Dominic Sweetman]

Lijun,

> Does anybody know which mips family SB1 core on bcm1250 falls into?
> It is a MIPS64 processor

Yes, it complies to the MIPS64 Architecture specification...

> ... does it belong to 5K family or 20Kc?

Neither one.  5K and 20Kc are specific core CPUs licensed by MIPS
Technologies.  Broadcom have an "architecture license" and design
their own compatible MIPS64 CPUs, like the BCM1250.

> What about the exception priorities, such as cache error exception,
> bus error exception, and so on? Are they maskable or non-maskable? 

Other than interrupts, only a few obscure exception conditions are
maskable. 

Ralf was sensible to suggest you back off to the architecture manuals,
which talk about all MIPS CPUs.  You might also like to read a book
(like my "See MIPS Run").

> Further to my last email, another question is if multiple
> simultaneous exceptions occur, or kernel is handling an exception,
> another exception occurs, how linux handles this?

As always, that depends what you mean by "handling".

At the lowest level, the CPU:

o If ever confronted by multiple possible exceptions at the same time,
  picks the highest priority one which affects the oldest instruction
  in the pipeline...

o When it takes the exception and vectors into the kernel exception
  handler, it atomically sets the register bit SR[EXL] ("exception
  mode").  In this mode interrupts are disabled.  The kernel code
  should be careful not to cause an exception.

Read the book, is my advice.

Of course Linux goes on from the low-level exception handler to call
other kernel functions which you might regard as "handlers" too -
interrupt routines, for example.  In many cases these OS "handlers"
are run with SR[EXL] set to zero, making it possible to handle new
machine-level exceptions...  

But that's complicated.

--
Dominic Sweetman
MIPS Technologies

Re: exception priority for BCM1250

[Lijun Chen]

Thanks a lot, Dominic and Ralf.
So interrupts and a few exception conditions are maskable and preemptable.
The machine-level exceptions are non-maskable.If ever multiple 
exceptions occur
at the same time, cpu picks the highest priority one.

But in the MIPS64 spec, it says the EXL bit is set when any exception 
other than Reset,
Soft reset, NMI or Cache Error exception are taken. Does this mean Cache 
error can
preempt whatever else is going on except for Reset and NMI?

My intention is to write some information to a kernel buffer when cache 
and bus
error exceptions occur. If they use the common buffer and a spin_lock() 
is used before
writing, will this cause dead lock if kernel is handling bus error while 
a cache error
occurs?

Thanks again.
Lijun

Dominic Sweetman wrote:

>Lijun,
>
>  
>
>>Does anybody know which mips family SB1 core on bcm1250 falls into?
>>It is a MIPS64 processor
>>    
>>
>
>Yes, it complies to the MIPS64 Architecture specification...
>
>  
>
>>... does it belong to 5K family or 20Kc?
>>    
>>
>
>Neither one.  5K and 20Kc are specific core CPUs licensed by MIPS
>Technologies.  Broadcom have an "architecture license" and design
>their own compatible MIPS64 CPUs, like the BCM1250.
>
>  
>
>>What about the exception priorities, such as cache error exception,
>>bus error exception, and so on? Are they maskable or non-maskable? 
>>    
>>
>
>Other than interrupts, only a few obscure exception conditions are
>maskable. 
>
>Ralf was sensible to suggest you back off to the architecture manuals,
>which talk about all MIPS CPUs.  You might also like to read a book
>(like my "See MIPS Run").
>
>  
>
>>Further to my last email, another question is if multiple
>>simultaneous exceptions occur, or kernel is handling an exception,
>>another exception occurs, how linux handles this?
>>    
>>
>
>As always, that depends what you mean by "handling".
>
>At the lowest level, the CPU:
>
>o If ever confronted by multiple possible exceptions at the same time,
>  picks the highest priority one which affects the oldest instruction
>  in the pipeline...
>
>o When it takes the exception and vectors into the kernel exception
>  handler, it atomically sets the register bit SR[EXL] ("exception
>  mode").  In this mode interrupts are disabled.  The kernel code
>  should be careful not to cause an exception.
>
>Read the book, is my advice.
>
>Of course Linux goes on from the low-level exception handler to call
>other kernel functions which you might regard as "handlers" too -
>interrupt routines, for example.  In many cases these OS "handlers"
>are run with SR[EXL] set to zero, making it possible to handle new
>machine-level exceptions...  
>
>But that's complicated.
>
>--
>Dominic Sweetman
>MIPS Technologies
>
>
>  
>

Re: exception priority for BCM1250

[Jun Sun]

On Wed, Mar 31, 2004 at 10:39:19AM -0500, Lijun Chen wrote:
> Thanks a lot, Dominic and Ralf.
> So interrupts and a few exception conditions are maskable and preemptable.
> The machine-level exceptions are non-maskable.If ever multiple 
> exceptions occur
> at the same time, cpu picks the highest priority one.
> 
> But in the MIPS64 spec, it says the EXL bit is set when any exception 
> other than Reset,
> Soft reset, NMI or Cache Error exception are taken. Does this mean Cache 
> error can
> preempt whatever else is going on except for Reset and NMI?
> 

I think so.  Usually when cache error happens you are dead.  
For bcm1250 there is a cache error handler which works around a hw bug.
I believe the workaround code is in the linux-mips.org tree.
 
> My intention is to write some information to a kernel buffer when cache 
> and bus
> error exceptions occur. If they use the common buffer and a spin_lock() 
> is used before
> writing, will this cause dead lock if kernel is handling bus error while 
> a cache error
> occurs?
> 

It will be a deadlock only if another exception happens and you try
to acquire the lock while you are already in the middle of spin_lock()/spin_unlock(). 
You should use spin_lock() in a scope as small as possible.

BTW, you may my tiby tracing patch handy for something like this.

http://linux.junsun.net/patches/generic/experimental/040316.a-jstrace.patch

Jun

Re: exception priority for BCM1250

[Lijun Chen]

Jun, Thanks a lot for your reply. Your jtrace is interesting, i am going 
to give a try.
Lijun

Jun Sun wrote:

>On Wed, Mar 31, 2004 at 10:39:19AM -0500, Lijun Chen wrote:
>  
>
>>Thanks a lot, Dominic and Ralf.
>>So interrupts and a few exception conditions are maskable and preemptable.
>>The machine-level exceptions are non-maskable.If ever multiple 
>>exceptions occur
>>at the same time, cpu picks the highest priority one.
>>
>>But in the MIPS64 spec, it says the EXL bit is set when any exception 
>>other than Reset,
>>Soft reset, NMI or Cache Error exception are taken. Does this mean Cache 
>>error can
>>preempt whatever else is going on except for Reset and NMI?
>>
>>    
>>
>
>I think so.  Usually when cache error happens you are dead.  
>For bcm1250 there is a cache error handler which works around a hw bug.
>I believe the workaround code is in the linux-mips.org tree.
> 
>  
>
>>My intention is to write some information to a kernel buffer when cache 
>>and bus
>>error exceptions occur. If they use the common buffer and a spin_lock() 
>>is used before
>>writing, will this cause dead lock if kernel is handling bus error while 
>>a cache error
>>occurs?
>>
>>    
>>
>
>It will be a deadlock only if another exception happens and you try
>to acquire the lock while you are already in the middle of spin_lock()/spin_unlock(). 
>You should use spin_lock() in a scope as small as possible.
>
>BTW, you may my tiby tracing patch handy for something like this.
>
>http://linux.junsun.net/patches/generic/experimental/040316.a-jstrace.patch
>
>Jun
>
>  
>