From: Ralf Baechle <ralf@linux-mips.org>
To: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org, blogic@openwrt.org,
cernekee@gmail.com, jon.fraser@broadcom.com, pgynther@google.com,
paul.burton@imgtec.com, ddaney.cavm@gmail.com
Subject: Re: [PATCH 1/6] MIPS: BMIPS: Disable pref 30 for buggy CPUs
Date: Wed, 10 Feb 2016 10:20:33 +0100 [thread overview]
Message-ID: <20160210092033.GB10352@linux-mips.org> (raw)
In-Reply-To: <1455051354-6225-2-git-send-email-f.fainelli@gmail.com>
On Tue, Feb 09, 2016 at 12:55:49PM -0800, Florian Fainelli wrote:
> +static void bmips5000_pref30_quirk(void)
> +{
> + __asm__ __volatile__(
> + " .word 0x4008b008\n" /* mfc0 $8, $22, 8 */
> + " lui $9, 0x0100\n"
> + " or $8, $9\n"
> + /* disable "pref 30" on buggy CPUs */
> + " lui $9, 0x0800\n"
> + " or $8, $9\n"
> + " .word 0x4088b008\n" /* mtc0 $8, $22, 8 */
> + : : : "$8", "$9");
> +}
Simpler:
#define read_c0_horse_with_no_name(val) __read_32bit_c0_register($22, 8, val)
#define write_c0_horse_with_no_name(val) __write_32bit_c0_register($22, 8)
...
write_c0_horse_with_no_name(read_c0_horse_with_no_name() | 0x123);
And why do both MFC0 and MTC0 instructions above have the same opcode?
Also the selector number used above for both instructions is 8 - but the
architecture only allows for 8 selectors 0..7.
Ralf
next prev parent reply other threads:[~2016-02-10 9:20 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-09 20:55 [PATCH 0/6] MIPS: BMIPS: RIXI and workarounds support Florian Fainelli
2016-02-09 20:55 ` [PATCH 1/6] MIPS: BMIPS: Disable pref 30 for buggy CPUs Florian Fainelli
2016-02-09 21:01 ` Florian Fainelli
2016-02-09 23:42 ` Petri Gynther
2016-02-09 23:45 ` Florian Fainelli
2016-02-09 21:19 ` Maciej W. Rozycki
2016-02-09 21:19 ` Maciej W. Rozycki
2016-02-09 22:40 ` Florian Fainelli
2016-02-09 23:52 ` Maciej W. Rozycki
2016-02-09 23:52 ` Maciej W. Rozycki
2016-02-10 0:04 ` Florian Fainelli
2016-02-10 0:54 ` Maciej W. Rozycki
2016-02-10 0:54 ` Maciej W. Rozycki
2016-02-10 9:20 ` Ralf Baechle [this message]
2016-02-10 9:22 ` Ralf Baechle
2016-02-10 14:20 ` Maciej W. Rozycki
2016-02-10 14:20 ` Maciej W. Rozycki
2016-02-09 20:55 ` [PATCH 2/6] MIPS: BMIPS: Add early CPU initialization code Florian Fainelli
2016-02-09 20:55 ` [PATCH 3/6] MIPS: Allow RIXI to be used on non-R2 or R6 cores Florian Fainelli
2016-02-09 20:55 ` [PATCH 4/6] MIPS: Move RIXI exception enabling after vendor-specific cpu_probe Florian Fainelli
2016-02-09 20:55 ` [PATCH 5/6] MIPS: BMIPS: BMIPS4380 and BMIPS5000 support RIXI Florian Fainelli
2016-02-09 20:55 ` [PATCH 6/6] MIPS: Expose current_cpu_data.options through debugfs Florian Fainelli
2016-02-10 10:46 ` Ralf Baechle
2016-02-11 1:58 ` Florian Fainelli
2016-03-29 1:38 ` [PATCH 0/6] MIPS: BMIPS: RIXI and workarounds support Florian Fainelli
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