From: Paul Burton <paul.burton@imgtec.com>
To: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: <linux-mips@linux-mips.org>, Lars Persson <lars.persson@axis.com>,
"stable # v4 . 1+" <stable@vger.kernel.org>,
"Steven J. Hill" <Steven.Hill@imgtec.com>,
David Daney <david.daney@cavium.com>,
Huacai Chen <chenhc@lemote.com>,
Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>,
<linux-kernel@vger.kernel.org>,
Andrew Morton <akpm@linux-foundation.org>,
Jerome Marchand <jmarchan@redhat.com>,
"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
Ralf Baechle <ralf@linux-mips.org>
Subject: Re: [4/4] MIPS: Sync icache & dcache in set_pte_at
Date: Fri, 4 Mar 2016 10:37:14 +0000 [thread overview]
Message-ID: <20160304103714.GA5576@NP-P-BURTON> (raw)
In-Reply-To: <56D7A987.5040602@imgtec.com>
Hi Leonid,
On Wed, Mar 02, 2016 at 07:03:35PM -0800, Leonid Yegoshin wrote:
> Paul Burton wrote:
> >It is, however, used in such a way by others & seems to me like the only
> >correct way to implement the lazy cache flushing. The alternative would
> >be to adjust all generic code to ensure flush_icache_page gets called
> >before set_pte_at
>
> ... which is an exact case right now.
No, it isn't. I included call traces for 2 cases where this is not the
case right in the commit message.
> Both calls of flush_icache_page() are:
>
> 1) do_swap_page()
>
> flush_icache_page(vma, page);
> if (pte_swp_soft_dirty(orig_pte))
> pte = pte_mksoft_dirty(pte);
> set_pte_at(mm, address, page_table, pte);
> ...
>
> 2) do_set_pte()
>
> flush_icache_page(vma, page);
> entry = mk_pte(page, vma->vm_page_prot);
> if (write)
> entry = maybe_mkwrite(pte_mkdirty(entry), vma);
> if (anon) {
> inc_mm_counter_fast(vma->vm_mm, MM_ANONPAGES);
> page_add_new_anon_rmap(page, vma, address);
> } else {
> inc_mm_counter_fast(vma->vm_mm, MM_FILEPAGES);
> page_add_file_rmap(page);
> }
> set_pte_at(vma->vm_mm, address, pte, entry);
>
> /* no need to invalidate: a not-present page won't be cached */
> update_mmu_cache(vma, address, pte);
> ....
>
> You should only be sure that flush_icache_page() completes a lazy D-cache
> flush.
>
> - Leonid.
Well of course that's fine in those 2 cases. Of course both callers of
flush_icache_page call flush_icache_page - that's a meaningless
tautology. You're grepping for the wrong thing.
The problem is that there are other code paths which dirty pages (ie.
call flush_dcache_page), then get as far as set_pte_at *without* calling
flush_icache_page. Again - I included call traces from 2 paths that hit
this right in the commit message.
So:
- flush_icache_page isn't always called before we *need* to writeback
the page from the dcache. This is demonstrably the case (again, see
the commit message), and causes bugs when using UBIFS on boards
using the pistachio SoC at least.
- flush_icache_page is indicated as something that should go away in
Documentation/cachetlb.txt. Why do you feel we should make use of
it?
- Other architectures (at least arm, ia64 & powerpc which may not be
an exhaustive list) handle this in set_pte_at too. Doing it in the
same way can only be good for consistency.
So flush_icache_page is insufficient, apparently disliked & not the way
any other architectures solve the exact same problem (again, because it
does *not* cover all cases).
Thanks,
Paul
WARNING: multiple messages have this Message-ID (diff)
From: Paul Burton <paul.burton@imgtec.com>
To: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org, Lars Persson <lars.persson@axis.com>,
"stable # v4 . 1+" <stable@vger.kernel.org>,
"Steven J. Hill" <Steven.Hill@imgtec.com>,
David Daney <david.daney@cavium.com>,
Huacai Chen <chenhc@lemote.com>,
"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>,
linux-kernel@vger.kernel.org,
Andrew Morton <akpm@linux-foundation.org>,
Jerome Marchand <jmarchan@redhat.com>,
"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
Ralf Baechle <ralf@linux-mips.org>
Subject: Re: [4/4] MIPS: Sync icache & dcache in set_pte_at
Date: Fri, 4 Mar 2016 10:37:14 +0000 [thread overview]
Message-ID: <20160304103714.GA5576@NP-P-BURTON> (raw)
Message-ID: <20160304103714.cNsY8wXl_Ri_hTVb_bPsAjfcMOxEk1GUAWQrkkAmxTQ@z> (raw)
In-Reply-To: <56D7A987.5040602@imgtec.com>
Hi Leonid,
On Wed, Mar 02, 2016 at 07:03:35PM -0800, Leonid Yegoshin wrote:
> Paul Burton wrote:
> >It is, however, used in such a way by others & seems to me like the only
> >correct way to implement the lazy cache flushing. The alternative would
> >be to adjust all generic code to ensure flush_icache_page gets called
> >before set_pte_at
>
> ... which is an exact case right now.
No, it isn't. I included call traces for 2 cases where this is not the
case right in the commit message.
> Both calls of flush_icache_page() are:
>
> 1) do_swap_page()
>
> flush_icache_page(vma, page);
> if (pte_swp_soft_dirty(orig_pte))
> pte = pte_mksoft_dirty(pte);
> set_pte_at(mm, address, page_table, pte);
> ...
>
> 2) do_set_pte()
>
> flush_icache_page(vma, page);
> entry = mk_pte(page, vma->vm_page_prot);
> if (write)
> entry = maybe_mkwrite(pte_mkdirty(entry), vma);
> if (anon) {
> inc_mm_counter_fast(vma->vm_mm, MM_ANONPAGES);
> page_add_new_anon_rmap(page, vma, address);
> } else {
> inc_mm_counter_fast(vma->vm_mm, MM_FILEPAGES);
> page_add_file_rmap(page);
> }
> set_pte_at(vma->vm_mm, address, pte, entry);
>
> /* no need to invalidate: a not-present page won't be cached */
> update_mmu_cache(vma, address, pte);
> ....
>
> You should only be sure that flush_icache_page() completes a lazy D-cache
> flush.
>
> - Leonid.
Well of course that's fine in those 2 cases. Of course both callers of
flush_icache_page call flush_icache_page - that's a meaningless
tautology. You're grepping for the wrong thing.
The problem is that there are other code paths which dirty pages (ie.
call flush_dcache_page), then get as far as set_pte_at *without* calling
flush_icache_page. Again - I included call traces from 2 paths that hit
this right in the commit message.
So:
- flush_icache_page isn't always called before we *need* to writeback
the page from the dcache. This is demonstrably the case (again, see
the commit message), and causes bugs when using UBIFS on boards
using the pistachio SoC at least.
- flush_icache_page is indicated as something that should go away in
Documentation/cachetlb.txt. Why do you feel we should make use of
it?
- Other architectures (at least arm, ia64 & powerpc which may not be
an exhaustive list) handle this in set_pte_at too. Doing it in the
same way can only be good for consistency.
So flush_icache_page is insufficient, apparently disliked & not the way
any other architectures solve the exact same problem (again, because it
does *not* cover all cases).
Thanks,
Paul
next prev parent reply other threads:[~2016-03-04 10:37 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-01 2:37 [PATCH 0/4] MIPS cache & highmem fixes Paul Burton
2016-03-01 2:37 ` Paul Burton
2016-03-01 2:37 ` [PATCH 1/4] MIPS: Flush dcache for flush_kernel_dcache_page Paul Burton
2016-03-01 2:37 ` Paul Burton
2016-03-04 15:09 ` Lars Persson
2016-03-29 8:29 ` Ralf Baechle
2016-03-01 2:37 ` [PATCH 2/4] MIPS: Flush highmem pages in __flush_dcache_page Paul Burton
2016-03-01 2:37 ` Paul Burton
2016-03-29 8:35 ` Ralf Baechle
2016-03-29 8:55 ` Paul Burton
2016-03-29 8:55 ` Paul Burton
2016-03-01 2:37 ` [PATCH 3/4] MIPS: Handle highmem pages in __update_cache Paul Burton
2016-03-01 2:37 ` Paul Burton
2016-03-29 8:39 ` Ralf Baechle
2016-03-01 2:37 ` [PATCH 4/4] MIPS: Sync icache & dcache in set_pte_at Paul Burton
2016-03-01 2:37 ` Paul Burton
2016-03-01 9:44 ` Lars Persson
2016-03-01 9:44 ` Lars Persson
2016-03-01 17:13 ` David Daney
2016-03-01 17:13 ` David Daney
2016-03-01 17:19 ` Paul Burton
2016-03-01 17:19 ` Paul Burton
2016-03-02 14:12 ` Ralf Baechle
2016-03-02 14:24 ` Paul Burton
2016-03-02 14:24 ` Paul Burton
2016-03-04 17:43 ` David Daney
2016-03-04 17:43 ` David Daney
2016-03-04 17:47 ` Paul Burton
2016-03-04 17:47 ` Paul Burton
2016-03-03 3:03 ` [4/4] " Leonid Yegoshin
2016-03-03 3:03 ` Leonid Yegoshin
2016-03-04 10:37 ` Paul Burton [this message]
2016-03-04 10:37 ` Paul Burton
2016-03-04 15:20 ` Lars Persson
2016-03-04 21:01 ` Leonid Yegoshin
2016-03-04 21:01 ` Leonid Yegoshin
2016-03-04 21:21 ` Leonid Yegoshin
2016-03-04 21:21 ` Leonid Yegoshin
2016-03-05 1:06 ` Leonid Yegoshin
2016-03-05 1:06 ` Leonid Yegoshin
2016-03-04 19:02 ` [PATCH 4/4] " Lars Persson
2016-03-05 0:21 ` Paul Burton
2016-03-05 0:27 ` Paul Burton
2016-03-02 11:39 ` [PATCH 0/4] MIPS cache & highmem fixes Harvey Hunt
2016-03-02 11:39 ` Harvey Hunt
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